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Diffstat (limited to 'include/linux/tegra_vgpu.h')
-rw-r--r--include/linux/tegra_vgpu.h16
1 files changed, 13 insertions, 3 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h
index 2b3ab64e..04bb65b3 100644
--- a/include/linux/tegra_vgpu.h
+++ b/include/linux/tegra_vgpu.h
@@ -96,6 +96,7 @@ enum {
96 TEGRA_VGPU_CMD_READ_PTIMER = 59, 96 TEGRA_VGPU_CMD_READ_PTIMER = 59,
97 TEGRA_VGPU_CMD_SET_POWERGATE = 60, 97 TEGRA_VGPU_CMD_SET_POWERGATE = 60,
98 TEGRA_VGPU_CMD_SET_GPU_CLK_RATE = 61, 98 TEGRA_VGPU_CMD_SET_GPU_CLK_RATE = 61,
99 TEGRA_VGPU_CMD_GET_CONSTANTS = 62,
99}; 100};
100 101
101struct tegra_vgpu_connect_params { 102struct tegra_vgpu_connect_params {
@@ -110,14 +111,14 @@ struct tegra_vgpu_channel_hwctx_params {
110}; 111};
111 112
112enum { 113enum {
113 TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0, 114 TEGRA_VGPU_ATTRIB_NUM_CHANNELS = 0, /*deprecated */
114 TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE = 1, 115 TEGRA_VGPU_ATTRIB_GOLDEN_CTX_SIZE = 1,
115 TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE = 2, 116 TEGRA_VGPU_ATTRIB_ZCULL_CTX_SIZE = 2,
116 TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3, 117 TEGRA_VGPU_ATTRIB_COMPTAG_LINES = 3,
117 TEGRA_VGPU_ATTRIB_GPC_COUNT = 4, 118 TEGRA_VGPU_ATTRIB_GPC_COUNT = 4,
118 TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5, 119 TEGRA_VGPU_ATTRIB_MAX_TPC_PER_GPC_COUNT = 5,
119 TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6, 120 TEGRA_VGPU_ATTRIB_MAX_TPC_COUNT = 6,
120 TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, 121 TEGRA_VGPU_ATTRIB_PMC_BOOT_0 = 7, /* deprecated */
121 TEGRA_VGPU_ATTRIB_L2_SIZE = 8, 122 TEGRA_VGPU_ATTRIB_L2_SIZE = 8,
122 TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9, 123 TEGRA_VGPU_ATTRIB_GPC0_TPC0_SM_ARCH = 9,
123 TEGRA_VGPU_ATTRIB_NUM_FBPS = 10, 124 TEGRA_VGPU_ATTRIB_NUM_FBPS = 10,
@@ -131,7 +132,7 @@ enum {
131 TEGRA_VGPU_ATTRIB_LTC_COUNT = 18, 132 TEGRA_VGPU_ATTRIB_LTC_COUNT = 18,
132 TEGRA_VGPU_ATTRIB_TPC_COUNT = 19, 133 TEGRA_VGPU_ATTRIB_TPC_COUNT = 19,
133 TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20, 134 TEGRA_VGPU_ATTRIB_GPC0_TPC_COUNT = 20,
134 TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, 135 TEGRA_VGPU_ATTRIB_MAX_FREQ = 21, /* deprecated */
135}; 136};
136 137
137struct tegra_vgpu_attrib_params { 138struct tegra_vgpu_attrib_params {
@@ -402,6 +403,14 @@ struct tegra_vgpu_gpu_clk_rate_params {
402 u32 rate; /* in kHz */ 403 u32 rate; /* in kHz */
403}; 404};
404 405
406struct tegra_vgpu_constants_params {
407 u32 arch;
408 u32 impl;
409 u32 rev;
410 u32 max_freq;
411 u32 num_channels;
412};
413
405struct tegra_vgpu_cmd_msg { 414struct tegra_vgpu_cmd_msg {
406 u32 cmd; 415 u32 cmd;
407 int ret; 416 int ret;
@@ -445,6 +454,7 @@ struct tegra_vgpu_cmd_msg {
445 struct tegra_vgpu_read_ptimer_params read_ptimer; 454 struct tegra_vgpu_read_ptimer_params read_ptimer;
446 struct tegra_vgpu_set_powergate_params set_powergate; 455 struct tegra_vgpu_set_powergate_params set_powergate;
447 struct tegra_vgpu_gpu_clk_rate_params gpu_clk_rate; 456 struct tegra_vgpu_gpu_clk_rate_params gpu_clk_rate;
457 struct tegra_vgpu_constants_params constants;
448 char padding[192]; 458 char padding[192];
449 } params; 459 } params;
450}; 460};