diff options
Diffstat (limited to 'include/linux/tegra_vgpu.h')
-rw-r--r-- | include/linux/tegra_vgpu.h | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/include/linux/tegra_vgpu.h b/include/linux/tegra_vgpu.h index 280ca9c0..c4dd81dd 100644 --- a/include/linux/tegra_vgpu.h +++ b/include/linux/tegra_vgpu.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Tegra GPU Virtualization Interfaces to Server | 2 | * Tegra GPU Virtualization Interfaces to Server |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2015, NVIDIA Corporation. All rights reserved. | 4 | * Copyright (c) 2014-2016, NVIDIA Corporation. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -74,7 +74,9 @@ enum { | |||
74 | TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE, | 74 | TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE, |
75 | TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE, | 75 | TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE, |
76 | TEGRA_VGPU_CMD_REG_OPS, | 76 | TEGRA_VGPU_CMD_REG_OPS, |
77 | TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY | 77 | TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY, |
78 | TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE, | ||
79 | TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE | ||
78 | }; | 80 | }; |
79 | 81 | ||
80 | struct tegra_vgpu_connect_params { | 82 | struct tegra_vgpu_connect_params { |
@@ -84,6 +86,7 @@ struct tegra_vgpu_connect_params { | |||
84 | 86 | ||
85 | struct tegra_vgpu_channel_hwctx_params { | 87 | struct tegra_vgpu_channel_hwctx_params { |
86 | u32 id; | 88 | u32 id; |
89 | u64 pid; | ||
87 | u64 handle; | 90 | u64 handle; |
88 | }; | 91 | }; |
89 | 92 | ||
@@ -298,6 +301,17 @@ struct tegra_vgpu_channel_priority_params { | |||
298 | u32 priority; | 301 | u32 priority; |
299 | }; | 302 | }; |
300 | 303 | ||
304 | /* level follows nvgpu.h definitions */ | ||
305 | struct tegra_vgpu_channel_runlist_interleave_params { | ||
306 | u64 handle; | ||
307 | u32 level; | ||
308 | }; | ||
309 | |||
310 | struct tegra_vgpu_channel_timeslice_params { | ||
311 | u64 handle; | ||
312 | u32 timeslice_us; | ||
313 | }; | ||
314 | |||
301 | struct tegra_vgpu_cmd_msg { | 315 | struct tegra_vgpu_cmd_msg { |
302 | u32 cmd; | 316 | u32 cmd; |
303 | int ret; | 317 | int ret; |
@@ -326,6 +340,8 @@ struct tegra_vgpu_cmd_msg { | |||
326 | struct tegra_vgpu_sm_debug_mode sm_debug_mode; | 340 | struct tegra_vgpu_sm_debug_mode sm_debug_mode; |
327 | struct tegra_vgpu_reg_ops_params reg_ops; | 341 | struct tegra_vgpu_reg_ops_params reg_ops; |
328 | struct tegra_vgpu_channel_priority_params channel_priority; | 342 | struct tegra_vgpu_channel_priority_params channel_priority; |
343 | struct tegra_vgpu_channel_runlist_interleave_params channel_interleave; | ||
344 | struct tegra_vgpu_channel_timeslice_params channel_timeslice; | ||
329 | char padding[192]; | 345 | char padding[192]; |
330 | } params; | 346 | } params; |
331 | }; | 347 | }; |