diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | 85 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 4 |
5 files changed, 95 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c index e17e239b..3c668013 100644 --- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | |||
@@ -388,6 +388,26 @@ static int nvgpu_gpu_ioctl_set_debug_mode( | |||
388 | return err; | 388 | return err; |
389 | } | 389 | } |
390 | 390 | ||
391 | static int nvgpu_gpu_ioctl_trigger_suspend(struct gk20a *g) | ||
392 | { | ||
393 | int err = 0; | ||
394 | u32 dbgr_control0; | ||
395 | |||
396 | mutex_lock(&g->dbg_sessions_lock); | ||
397 | /* assert stop trigger. uniformity assumption: all SMs will have | ||
398 | * the same state in dbg_control0. */ | ||
399 | dbgr_control0 = | ||
400 | gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_control0_r()); | ||
401 | dbgr_control0 |= gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(); | ||
402 | |||
403 | /* broadcast write */ | ||
404 | gk20a_writel(g, | ||
405 | gr_gpcs_tpcs_sm_dbgr_control0_r(), dbgr_control0); | ||
406 | |||
407 | mutex_unlock(&g->dbg_sessions_lock); | ||
408 | return err; | ||
409 | } | ||
410 | |||
391 | static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g, | 411 | static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g, |
392 | struct nvgpu_gpu_wait_pause_args *args) | 412 | struct nvgpu_gpu_wait_pause_args *args) |
393 | { | 413 | { |
@@ -441,6 +461,57 @@ end: | |||
441 | return err; | 461 | return err; |
442 | } | 462 | } |
443 | 463 | ||
464 | static int nvgpu_gpu_ioctl_resume_from_pause(struct gk20a *g) | ||
465 | { | ||
466 | int err = 0; | ||
467 | |||
468 | mutex_lock(&g->dbg_sessions_lock); | ||
469 | |||
470 | /* Clear the pause mask to tell the GPU we want to resume everyone */ | ||
471 | gk20a_writel(g, | ||
472 | gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(), 0); | ||
473 | |||
474 | /* explicitly re-enable forwarding of SM interrupts upon any resume */ | ||
475 | gk20a_writel(g, gr_gpcs_tpcs_tpccs_tpc_exception_en_r(), | ||
476 | gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f()); | ||
477 | |||
478 | /* Now resume all sms, write a 0 to the stop trigger | ||
479 | * then a 1 to the run trigger */ | ||
480 | gk20a_resume_all_sms(g); | ||
481 | |||
482 | mutex_unlock(&g->dbg_sessions_lock); | ||
483 | return err; | ||
484 | } | ||
485 | |||
486 | static int nvgpu_gpu_ioctl_clear_sm_errors(struct gk20a *g) | ||
487 | { | ||
488 | int ret = 0; | ||
489 | u32 gpc_offset, tpc_offset, gpc, tpc; | ||
490 | struct gr_gk20a *gr = &g->gr; | ||
491 | u32 global_esr; | ||
492 | |||
493 | for (gpc = 0; gpc < gr->gpc_count; gpc++) { | ||
494 | |||
495 | gpc_offset = proj_gpc_stride_v() * gpc; | ||
496 | |||
497 | /* check if any tpc has an exception */ | ||
498 | for (tpc = 0; tpc < gr->tpc_count; tpc++) { | ||
499 | |||
500 | tpc_offset = proj_tpc_in_gpc_stride_v() * tpc; | ||
501 | |||
502 | global_esr = gk20a_readl(g, | ||
503 | gr_gpc0_tpc0_sm_hww_global_esr_r() + | ||
504 | gpc_offset + tpc_offset); | ||
505 | |||
506 | /* clear the hwws, also causes tpc and gpc | ||
507 | * exceptions to be cleared */ | ||
508 | gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr); | ||
509 | } | ||
510 | } | ||
511 | |||
512 | return ret; | ||
513 | } | ||
514 | |||
444 | static int nvgpu_gpu_ioctl_has_any_exception( | 515 | static int nvgpu_gpu_ioctl_has_any_exception( |
445 | struct gk20a *g, | 516 | struct gk20a *g, |
446 | struct nvgpu_gpu_tpc_exception_en_status_args *args) | 517 | struct nvgpu_gpu_tpc_exception_en_status_args *args) |
@@ -694,11 +765,23 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg | |||
694 | nvgpu_gpu_ioctl_set_debug_mode(g, (struct nvgpu_gpu_sm_debug_mode_args *)buf)); | 765 | nvgpu_gpu_ioctl_set_debug_mode(g, (struct nvgpu_gpu_sm_debug_mode_args *)buf)); |
695 | break; | 766 | break; |
696 | 767 | ||
768 | case NVGPU_GPU_IOCTL_TRIGGER_SUSPEND: | ||
769 | err = nvgpu_gpu_ioctl_trigger_suspend(g); | ||
770 | break; | ||
771 | |||
697 | case NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE: | 772 | case NVGPU_GPU_IOCTL_WAIT_FOR_PAUSE: |
698 | err = nvgpu_gpu_ioctl_wait_for_pause(g, | 773 | err = nvgpu_gpu_ioctl_wait_for_pause(g, |
699 | (struct nvgpu_gpu_wait_pause_args *)buf); | 774 | (struct nvgpu_gpu_wait_pause_args *)buf); |
700 | break; | 775 | break; |
701 | 776 | ||
777 | case NVGPU_GPU_IOCTL_RESUME_FROM_PAUSE: | ||
778 | err = nvgpu_gpu_ioctl_resume_from_pause(g); | ||
779 | break; | ||
780 | |||
781 | case NVGPU_GPU_IOCTL_CLEAR_SM_ERRORS: | ||
782 | err = nvgpu_gpu_ioctl_clear_sm_errors(g); | ||
783 | break; | ||
784 | |||
702 | case NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS: | 785 | case NVGPU_GPU_IOCTL_GET_TPC_EXCEPTION_EN_STATUS: |
703 | err = nvgpu_gpu_ioctl_has_any_exception(g, | 786 | err = nvgpu_gpu_ioctl_has_any_exception(g, |
704 | (struct nvgpu_gpu_tpc_exception_en_status_args *)buf); | 787 | (struct nvgpu_gpu_tpc_exception_en_status_args *)buf); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index ea6bca2f..30beb962 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -5159,7 +5159,7 @@ bool gk20a_gr_sm_debugger_attached(struct gk20a *g) | |||
5159 | return false; | 5159 | return false; |
5160 | } | 5160 | } |
5161 | 5161 | ||
5162 | static void gk20a_gr_clear_sm_hww(struct gk20a *g, | 5162 | void gk20a_gr_clear_sm_hww(struct gk20a *g, |
5163 | u32 gpc, u32 tpc, u32 global_esr) | 5163 | u32 gpc, u32 tpc, u32 global_esr) |
5164 | { | 5164 | { |
5165 | u32 offset = proj_gpc_stride_v() * gpc + | 5165 | u32 offset = proj_gpc_stride_v() * gpc + |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 55c5ceb7..51b87ac8 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -431,6 +431,8 @@ void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine); | |||
431 | 431 | ||
432 | /* sm */ | 432 | /* sm */ |
433 | bool gk20a_gr_sm_debugger_attached(struct gk20a *g); | 433 | bool gk20a_gr_sm_debugger_attached(struct gk20a *g); |
434 | void gk20a_gr_clear_sm_hww(struct gk20a *g, | ||
435 | u32 gpc, u32 tpc, u32 global_esr); | ||
434 | 436 | ||
435 | #define gr_gk20a_elpg_protected_call(g, func) \ | 437 | #define gr_gk20a_elpg_protected_call(g, func) \ |
436 | ({ \ | 438 | ({ \ |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index 726d0ad3..6a155ccc 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |||
@@ -3110,6 +3110,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) | |||
3110 | { | 3110 | { |
3111 | return 0x00504634; | 3111 | return 0x00504634; |
3112 | } | 3112 | } |
3113 | static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) | ||
3114 | { | ||
3115 | return 0x00419e24; | ||
3116 | } | ||
3113 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_warp_disable_v(void) | 3117 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_warp_disable_v(void) |
3114 | { | 3118 | { |
3115 | return 0x00000000; | 3119 | return 0x00000000; |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index 05f6cae5..41a7c885 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |||
@@ -3142,6 +3142,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_0_r(void) | |||
3142 | { | 3142 | { |
3143 | return 0x00504634; | 3143 | return 0x00504634; |
3144 | } | 3144 | } |
3145 | static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) | ||
3146 | { | ||
3147 | return 0x00419e24; | ||
3148 | } | ||
3145 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_warp_disable_v(void) | 3149 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_warp_disable_v(void) |
3146 | { | 3150 | { |
3147 | return 0x00000000; | 3151 | return 0x00000000; |