diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c | 33 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 113 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h | 29 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hal_gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_proj_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_proj_gm20b.h | 4 |
10 files changed, 206 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 03a698dc..41eb7eb7 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -100,6 +100,7 @@ enum nvgpu_litter_value { | |||
100 | GPU_LIT_TPC_IN_GPC_SHARED_BASE, | 100 | GPU_LIT_TPC_IN_GPC_SHARED_BASE, |
101 | GPU_LIT_PPC_IN_GPC_BASE, | 101 | GPU_LIT_PPC_IN_GPC_BASE, |
102 | GPU_LIT_PPC_IN_GPC_STRIDE, | 102 | GPU_LIT_PPC_IN_GPC_STRIDE, |
103 | GPU_LIT_PPC_IN_GPC_SHARED_BASE, | ||
103 | GPU_LIT_ROP_BASE, | 104 | GPU_LIT_ROP_BASE, |
104 | GPU_LIT_ROP_STRIDE, | 105 | GPU_LIT_ROP_STRIDE, |
105 | GPU_LIT_ROP_SHARED_BASE, | 106 | GPU_LIT_ROP_SHARED_BASE, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c index 5029db8d..81ac341f 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c | |||
@@ -336,6 +336,34 @@ static int gr_gk20a_init_ctx_vars_fw(struct gk20a *g, struct gr_gk20a *gr) | |||
336 | if (err) | 336 | if (err) |
337 | goto clean_up; | 337 | goto clean_up; |
338 | break; | 338 | break; |
339 | case NETLIST_REGIONID_NVPERF_SYS_ROUTER: | ||
340 | gk20a_dbg_info("NETLIST_REGIONID_NVPERF_SYS_ROUTER"); | ||
341 | err = gr_gk20a_alloc_load_netlist_aiv( | ||
342 | src, size, &g->gr.ctx_vars.ctxsw_regs.perf_sys_router); | ||
343 | if (err) | ||
344 | goto clean_up; | ||
345 | break; | ||
346 | case NETLIST_REGIONID_NVPERF_PMA: | ||
347 | gk20a_dbg_info("NETLIST_REGIONID_NVPERF_PMA"); | ||
348 | err = gr_gk20a_alloc_load_netlist_aiv( | ||
349 | src, size, &g->gr.ctx_vars.ctxsw_regs.perf_pma); | ||
350 | if (err) | ||
351 | goto clean_up; | ||
352 | break; | ||
353 | case NETLIST_REGIONID_CTXREG_PMROP: | ||
354 | gk20a_dbg_info("NETLIST_REGIONID_CTXREG_PMROP"); | ||
355 | err = gr_gk20a_alloc_load_netlist_aiv( | ||
356 | src, size, &g->gr.ctx_vars.ctxsw_regs.pm_rop); | ||
357 | if (err) | ||
358 | goto clean_up; | ||
359 | break; | ||
360 | case NETLIST_REGIONID_CTXREG_PMUCGPC: | ||
361 | gk20a_dbg_info("NETLIST_REGIONID_CTXREG_PMUCGPC"); | ||
362 | err = gr_gk20a_alloc_load_netlist_aiv( | ||
363 | src, size, &g->gr.ctx_vars.ctxsw_regs.pm_ucgpc); | ||
364 | if (err) | ||
365 | goto clean_up; | ||
366 | break; | ||
339 | default: | 367 | default: |
340 | gk20a_dbg_info("unrecognized region %d skipped", i); | 368 | gk20a_dbg_info("unrecognized region %d skipped", i); |
341 | break; | 369 | break; |
@@ -381,6 +409,11 @@ clean_up: | |||
381 | kfree(g->gr.ctx_vars.ctxsw_regs.gpc_router.l); | 409 | kfree(g->gr.ctx_vars.ctxsw_regs.gpc_router.l); |
382 | kfree(g->gr.ctx_vars.ctxsw_regs.pm_ltc.l); | 410 | kfree(g->gr.ctx_vars.ctxsw_regs.pm_ltc.l); |
383 | kfree(g->gr.ctx_vars.ctxsw_regs.pm_fbpa.l); | 411 | kfree(g->gr.ctx_vars.ctxsw_regs.pm_fbpa.l); |
412 | kfree(g->gr.ctx_vars.ctxsw_regs.pm_fbpa.l); | ||
413 | kfree(g->gr.ctx_vars.ctxsw_regs.perf_sys_router.l); | ||
414 | kfree(g->gr.ctx_vars.ctxsw_regs.perf_pma.l); | ||
415 | kfree(g->gr.ctx_vars.ctxsw_regs.pm_rop.l); | ||
416 | kfree(g->gr.ctx_vars.ctxsw_regs.pm_ucgpc.l); | ||
384 | release_firmware(netlist_fw); | 417 | release_firmware(netlist_fw); |
385 | err = -ENOENT; | 418 | err = -ENOENT; |
386 | } | 419 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h index b0e4c4c2..2b384993 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h | |||
@@ -93,6 +93,11 @@ union __max_name { | |||
93 | #define NETLIST_REGIONID_NVPERF_GPC_ROUTER 25 | 93 | #define NETLIST_REGIONID_NVPERF_GPC_ROUTER 25 |
94 | #define NETLIST_REGIONID_CTXREG_PMLTC 26 | 94 | #define NETLIST_REGIONID_CTXREG_PMLTC 26 |
95 | #define NETLIST_REGIONID_CTXREG_PMFBPA 27 | 95 | #define NETLIST_REGIONID_CTXREG_PMFBPA 27 |
96 | #define NETLIST_REGIONID_SWVEIDBUNDLEINIT 28 | ||
97 | #define NETLIST_REGIONID_NVPERF_SYS_ROUTER 29 | ||
98 | #define NETLIST_REGIONID_NVPERF_PMA 30 | ||
99 | #define NETLIST_REGIONID_CTXREG_PMROP 31 | ||
100 | #define NETLIST_REGIONID_CTXREG_PMUCGPC 32 | ||
96 | 101 | ||
97 | struct netlist_region { | 102 | struct netlist_region { |
98 | u32 region_id; | 103 | u32 region_id; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index c5b2ba5c..62d3b231 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -64,6 +64,8 @@ | |||
64 | #define NV_PERF_PMM_FBP_ROUTER_STRIDE 0x0200 | 64 | #define NV_PERF_PMM_FBP_ROUTER_STRIDE 0x0200 |
65 | #define NV_PERF_PMMGPC_CHIPLET_OFFSET 0x1000 | 65 | #define NV_PERF_PMMGPC_CHIPLET_OFFSET 0x1000 |
66 | #define NV_PERF_PMMGPCROUTER_STRIDE 0x0200 | 66 | #define NV_PERF_PMMGPCROUTER_STRIDE 0x0200 |
67 | #define NV_PCFG_BASE 0x00088000 | ||
68 | #define NV_XBAR_MXBAR_PRI_GPC_GNIC_STRIDE 0x0020 | ||
67 | #define FE_PWR_MODE_TIMEOUT_MAX 2000 | 69 | #define FE_PWR_MODE_TIMEOUT_MAX 2000 |
68 | #define FE_PWR_MODE_TIMEOUT_DEFAULT 10 | 70 | #define FE_PWR_MODE_TIMEOUT_DEFAULT 10 |
69 | #define CTXSW_MEM_SCRUBBING_TIMEOUT_MAX 1000 | 71 | #define CTXSW_MEM_SCRUBBING_TIMEOUT_MAX 1000 |
@@ -6446,6 +6448,13 @@ static int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr, | |||
6446 | } else | 6448 | } else |
6447 | *gpc_num = pri_get_gpc_num(g, addr); | 6449 | *gpc_num = pri_get_gpc_num(g, addr); |
6448 | 6450 | ||
6451 | if (pri_is_ppc_addr(g, gpc_addr)) { | ||
6452 | *addr_type = CTXSW_ADDR_TYPE_PPC; | ||
6453 | if (pri_is_ppc_addr_shared(g, gpc_addr)) { | ||
6454 | *broadcast_flags |= PRI_BROADCAST_FLAGS_PPC; | ||
6455 | return 0; | ||
6456 | } | ||
6457 | } | ||
6449 | if (g->ops.gr.is_tpc_addr(g, gpc_addr)) { | 6458 | if (g->ops.gr.is_tpc_addr(g, gpc_addr)) { |
6450 | *addr_type = CTXSW_ADDR_TYPE_TPC; | 6459 | *addr_type = CTXSW_ADDR_TYPE_TPC; |
6451 | if (pri_is_tpc_addr_shared(g, gpc_addr)) { | 6460 | if (pri_is_tpc_addr_shared(g, gpc_addr)) { |
@@ -7490,6 +7499,72 @@ static int map_cmp(const void *a, const void *b) | |||
7490 | return 0; | 7499 | return 0; |
7491 | } | 7500 | } |
7492 | 7501 | ||
7502 | static int add_ctxsw_buffer_map_entries_pmsys(struct ctxsw_buf_offset_map_entry *map, | ||
7503 | struct aiv_list_gk20a *regs, | ||
7504 | u32 *count, u32 *offset, | ||
7505 | u32 max_cnt, u32 base, u32 mask) | ||
7506 | { | ||
7507 | u32 idx; | ||
7508 | u32 cnt = *count; | ||
7509 | u32 off = *offset; | ||
7510 | |||
7511 | if ((cnt + regs->count) > max_cnt) | ||
7512 | return -EINVAL; | ||
7513 | |||
7514 | for (idx = 0; idx < regs->count; idx++) { | ||
7515 | if ((base + (regs->l[idx].addr & mask)) < 0xFFF) | ||
7516 | map[cnt].addr = base + (regs->l[idx].addr & mask) | ||
7517 | + NV_PCFG_BASE; | ||
7518 | else | ||
7519 | map[cnt].addr = base + (regs->l[idx].addr & mask); | ||
7520 | map[cnt++].offset = off; | ||
7521 | off += 4; | ||
7522 | } | ||
7523 | *count = cnt; | ||
7524 | *offset = off; | ||
7525 | return 0; | ||
7526 | } | ||
7527 | |||
7528 | static int add_ctxsw_buffer_map_entries_pmgpc(struct gk20a *g, | ||
7529 | struct ctxsw_buf_offset_map_entry *map, | ||
7530 | struct aiv_list_gk20a *regs, | ||
7531 | u32 *count, u32 *offset, | ||
7532 | u32 max_cnt, u32 base, u32 mask) | ||
7533 | { | ||
7534 | u32 idx; | ||
7535 | u32 cnt = *count; | ||
7536 | u32 off = *offset; | ||
7537 | |||
7538 | if ((cnt + regs->count) > max_cnt) | ||
7539 | return -EINVAL; | ||
7540 | |||
7541 | /* NOTE: The PPC offsets get added to the pm_gpc list if numPpc <= 1 | ||
7542 | * To handle the case of PPC registers getting added into GPC, the below | ||
7543 | * code specifically checks for any PPC offsets and adds them using | ||
7544 | * proper mask | ||
7545 | */ | ||
7546 | for (idx = 0; idx < regs->count; idx++) { | ||
7547 | /* Check if the address is PPC address */ | ||
7548 | if (pri_is_ppc_addr_shared(g, regs->l[idx].addr & mask)) { | ||
7549 | u32 ppc_in_gpc_base = nvgpu_get_litter_value(g, | ||
7550 | GPU_LIT_PPC_IN_GPC_BASE); | ||
7551 | u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g, | ||
7552 | GPU_LIT_PPC_IN_GPC_STRIDE); | ||
7553 | /* Use PPC mask instead of the GPC mask provided */ | ||
7554 | u32 ppcmask = ppc_in_gpc_stride - 1; | ||
7555 | |||
7556 | map[cnt].addr = base + ppc_in_gpc_base | ||
7557 | + (regs->l[idx].addr & ppcmask); | ||
7558 | } else | ||
7559 | map[cnt].addr = base + (regs->l[idx].addr & mask); | ||
7560 | map[cnt++].offset = off; | ||
7561 | off += 4; | ||
7562 | } | ||
7563 | *count = cnt; | ||
7564 | *offset = off; | ||
7565 | return 0; | ||
7566 | } | ||
7567 | |||
7493 | static int add_ctxsw_buffer_map_entries(struct ctxsw_buf_offset_map_entry *map, | 7568 | static int add_ctxsw_buffer_map_entries(struct ctxsw_buf_offset_map_entry *map, |
7494 | struct aiv_list_gk20a *regs, | 7569 | struct aiv_list_gk20a *regs, |
7495 | u32 *count, u32 *offset, | 7570 | u32 *count, u32 *offset, |
@@ -7577,12 +7652,18 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g, | |||
7577 | return -EINVAL; | 7652 | return -EINVAL; |
7578 | 7653 | ||
7579 | base = gpc_base + (gpc_stride * gpc_num); | 7654 | base = gpc_base + (gpc_stride * gpc_num); |
7580 | if (add_ctxsw_buffer_map_entries(map, | 7655 | if (add_ctxsw_buffer_map_entries_pmgpc(g, map, |
7581 | &g->gr.ctx_vars.ctxsw_regs.pm_gpc, | 7656 | &g->gr.ctx_vars.ctxsw_regs.pm_gpc, |
7582 | count, offset, max_cnt, base, | 7657 | count, offset, max_cnt, base, |
7583 | (gpc_stride - 1))) | 7658 | (gpc_stride - 1))) |
7584 | return -EINVAL; | 7659 | return -EINVAL; |
7585 | 7660 | ||
7661 | base = NV_XBAR_MXBAR_PRI_GPC_GNIC_STRIDE * gpc_num; | ||
7662 | if (add_ctxsw_buffer_map_entries(map, | ||
7663 | &g->gr.ctx_vars.ctxsw_regs.pm_ucgpc, | ||
7664 | count, offset, max_cnt, base, ~0)) | ||
7665 | return -EINVAL; | ||
7666 | |||
7586 | base = (NV_PERF_PMMGPC_CHIPLET_OFFSET * gpc_num); | 7667 | base = (NV_PERF_PMMGPC_CHIPLET_OFFSET * gpc_num); |
7587 | if (add_ctxsw_buffer_map_entries(map, | 7668 | if (add_ctxsw_buffer_map_entries(map, |
7588 | &g->gr.ctx_vars.ctxsw_regs.perf_gpc, | 7669 | &g->gr.ctx_vars.ctxsw_regs.perf_gpc, |
@@ -7609,6 +7690,12 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g, | |||
7609 | *| | | 7690 | *| | |
7610 | *| LIST_compressed_nv_perf_ctx_reg_SYS |Space allocated: numRegs words | 7691 | *| LIST_compressed_nv_perf_ctx_reg_SYS |Space allocated: numRegs words |
7611 | *|---------------------------------------------| | 7692 | *|---------------------------------------------| |
7693 | *| | | ||
7694 | *| LIST_compressed_nv_perf_ctx_reg_sysrouter|Space allocated: numRegs words | ||
7695 | *|---------------------------------------------| | ||
7696 | *| | | ||
7697 | *| LIST_compressed_nv_perf_ctx_reg_PMA |Space allocated: numRegs words | ||
7698 | *|---------------------------------------------| | ||
7612 | *| PADDING for 256 byte alignment | | 7699 | *| PADDING for 256 byte alignment | |
7613 | *|---------------------------------------------|<----256 byte aligned | 7700 | *|---------------------------------------------|<----256 byte aligned |
7614 | *| LIST_compressed_nv_perf_fbp_ctx_regs | | 7701 | *| LIST_compressed_nv_perf_fbp_ctx_regs | |
@@ -7620,6 +7707,8 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g, | |||
7620 | *| LIST_compressed_pm_fbpa_ctx_regs | | 7707 | *| LIST_compressed_pm_fbpa_ctx_regs | |
7621 | *| |Space allocated: numRegs * n words (for n FB units) | 7708 | *| |Space allocated: numRegs * n words (for n FB units) |
7622 | *|---------------------------------------------| | 7709 | *|---------------------------------------------| |
7710 | *| LIST_compressed_pm_rop_ctx_regs | | ||
7711 | *|---------------------------------------------| | ||
7623 | *| LIST_compressed_pm_ltc_ctx_regs | | 7712 | *| LIST_compressed_pm_ltc_ctx_regs | |
7624 | *| LTC0 LTS0 | | 7713 | *| LTC0 LTS0 | |
7625 | *| LTC1 LTS0 |Space allocated: numRegs * n words (for n LTC units) | 7714 | *| LTC1 LTS0 |Space allocated: numRegs * n words (for n LTC units) |
@@ -7641,7 +7730,8 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g, | |||
7641 | *| LIST_pm_ctx_reg_PPC REG1 TPCn | | 7730 | *| LIST_pm_ctx_reg_PPC REG1 TPCn | |
7642 | *| * numPpcs REGn TPC0 | | 7731 | *| * numPpcs REGn TPC0 | |
7643 | *| LIST_pm_ctx_reg_GPC REGn TPC1 | | 7732 | *| LIST_pm_ctx_reg_GPC REGn TPC1 | |
7644 | *| LIST_nv_perf_ctx_reg_GPC REGn TPCn | | 7733 | *| List_pm_ctx_reg_uc_GPC REGn TPCn | |
7734 | *| LIST_nv_perf_ctx_reg_GPC | | ||
7645 | *| ---- |-- | 7735 | *| ---- |-- |
7646 | *| GPC1 . | | 7736 | *| GPC1 . | |
7647 | *| . |<---- | 7737 | *| . |<---- |
@@ -7679,7 +7769,7 @@ static int gr_gk20a_create_hwpm_ctxsw_buffer_offset_map(struct gk20a *g) | |||
7679 | return -ENOMEM; | 7769 | return -ENOMEM; |
7680 | 7770 | ||
7681 | /* Add entries from _LIST_pm_ctx_reg_SYS */ | 7771 | /* Add entries from _LIST_pm_ctx_reg_SYS */ |
7682 | if (add_ctxsw_buffer_map_entries(map, &g->gr.ctx_vars.ctxsw_regs.pm_sys, | 7772 | if (add_ctxsw_buffer_map_entries_pmsys(map, &g->gr.ctx_vars.ctxsw_regs.pm_sys, |
7683 | &count, &offset, hwpm_ctxsw_reg_count_max, 0, ~0)) | 7773 | &count, &offset, hwpm_ctxsw_reg_count_max, 0, ~0)) |
7684 | goto cleanup; | 7774 | goto cleanup; |
7685 | 7775 | ||
@@ -7688,6 +7778,16 @@ static int gr_gk20a_create_hwpm_ctxsw_buffer_offset_map(struct gk20a *g) | |||
7688 | &count, &offset, hwpm_ctxsw_reg_count_max, 0, ~0)) | 7778 | &count, &offset, hwpm_ctxsw_reg_count_max, 0, ~0)) |
7689 | goto cleanup; | 7779 | goto cleanup; |
7690 | 7780 | ||
7781 | /* Add entries from _LIST_nv_perf_sysrouter_ctx_reg*/ | ||
7782 | if (add_ctxsw_buffer_map_entries(map, &g->gr.ctx_vars.ctxsw_regs.perf_sys_router, | ||
7783 | &count, &offset, hwpm_ctxsw_reg_count_max, 0, ~0)) | ||
7784 | goto cleanup; | ||
7785 | |||
7786 | /* Add entries from _LIST_nv_perf_pma_ctx_reg*/ | ||
7787 | if (add_ctxsw_buffer_map_entries(map, &g->gr.ctx_vars.ctxsw_regs.perf_pma, | ||
7788 | &count, &offset, hwpm_ctxsw_reg_count_max, 0, ~0)) | ||
7789 | goto cleanup; | ||
7790 | |||
7691 | offset = ALIGN(offset, 256); | 7791 | offset = ALIGN(offset, 256); |
7692 | 7792 | ||
7693 | /* Add entries from _LIST_nv_perf_fbp_ctx_regs */ | 7793 | /* Add entries from _LIST_nv_perf_fbp_ctx_regs */ |
@@ -7714,6 +7814,13 @@ static int gr_gk20a_create_hwpm_ctxsw_buffer_offset_map(struct gk20a *g) | |||
7714 | num_fbpas, fbpa_stride, ~0)) | 7814 | num_fbpas, fbpa_stride, ~0)) |
7715 | goto cleanup; | 7815 | goto cleanup; |
7716 | 7816 | ||
7817 | /* Add entries from _LIST_nv_pm_rop_ctx_regs */ | ||
7818 | if (add_ctxsw_buffer_map_entries(map, | ||
7819 | &g->gr.ctx_vars.ctxsw_regs.pm_rop, | ||
7820 | &count, &offset, | ||
7821 | hwpm_ctxsw_reg_count_max, 0, ~0)) | ||
7822 | goto cleanup; | ||
7823 | |||
7717 | /* Add entries from _LIST_compressed_nv_pm_ltc_ctx_regs */ | 7824 | /* Add entries from _LIST_compressed_nv_pm_ltc_ctx_regs */ |
7718 | if (add_ctxsw_buffer_map_entries_subunits(map, | 7825 | if (add_ctxsw_buffer_map_entries_subunits(map, |
7719 | &g->gr.ctx_vars.ctxsw_regs.pm_ltc, | 7826 | &g->gr.ctx_vars.ctxsw_regs.pm_ltc, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index aa83f85a..e1335b89 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -248,6 +248,10 @@ struct gr_gk20a { | |||
248 | struct aiv_list_gk20a gpc_router; | 248 | struct aiv_list_gk20a gpc_router; |
249 | struct aiv_list_gk20a pm_ltc; | 249 | struct aiv_list_gk20a pm_ltc; |
250 | struct aiv_list_gk20a pm_fbpa; | 250 | struct aiv_list_gk20a pm_fbpa; |
251 | struct aiv_list_gk20a perf_sys_router; | ||
252 | struct aiv_list_gk20a perf_pma; | ||
253 | struct aiv_list_gk20a pm_rop; | ||
254 | struct aiv_list_gk20a pm_ucgpc; | ||
251 | } ctxsw_regs; | 255 | } ctxsw_regs; |
252 | int regs_base_index; | 256 | int regs_base_index; |
253 | bool valid; | 257 | bool valid; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h index a7656d38..88521555 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h | |||
@@ -69,6 +69,35 @@ static inline u32 pri_get_gpc_num(struct gk20a *g, u32 addr) | |||
69 | } | 69 | } |
70 | return 0; | 70 | return 0; |
71 | } | 71 | } |
72 | |||
73 | /* | ||
74 | * PPC pri addressing | ||
75 | */ | ||
76 | static inline bool pri_is_ppc_addr_shared(struct gk20a *g, u32 addr) | ||
77 | { | ||
78 | u32 ppc_in_gpc_shared_base = nvgpu_get_litter_value(g, | ||
79 | GPU_LIT_PPC_IN_GPC_SHARED_BASE); | ||
80 | u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g, | ||
81 | GPU_LIT_PPC_IN_GPC_STRIDE); | ||
82 | |||
83 | return ((addr >= ppc_in_gpc_shared_base) && | ||
84 | (addr < (ppc_in_gpc_shared_base + ppc_in_gpc_stride))); | ||
85 | } | ||
86 | |||
87 | static inline bool pri_is_ppc_addr(struct gk20a *g, u32 addr) | ||
88 | { | ||
89 | u32 ppc_in_gpc_base = nvgpu_get_litter_value(g, | ||
90 | GPU_LIT_PPC_IN_GPC_BASE); | ||
91 | u32 num_pes_per_gpc = nvgpu_get_litter_value(g, | ||
92 | GPU_LIT_NUM_PES_PER_GPC); | ||
93 | u32 ppc_in_gpc_stride = nvgpu_get_litter_value(g, | ||
94 | GPU_LIT_PPC_IN_GPC_STRIDE); | ||
95 | |||
96 | return ((addr >= ppc_in_gpc_base) && | ||
97 | (addr < ppc_in_gpc_base + num_pes_per_gpc * ppc_in_gpc_stride)) | ||
98 | || pri_is_ppc_addr_shared(g, addr); | ||
99 | } | ||
100 | |||
72 | /* | 101 | /* |
73 | * TPC pri addressing | 102 | * TPC pri addressing |
74 | */ | 103 | */ |
diff --git a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c index 99c55992..e0479573 100644 --- a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c | |||
@@ -87,9 +87,15 @@ static int gk20a_get_litter_value(struct gk20a *g, | |||
87 | case GPU_LIT_TPC_IN_GPC_SHARED_BASE: | 87 | case GPU_LIT_TPC_IN_GPC_SHARED_BASE: |
88 | ret = proj_tpc_in_gpc_shared_base_v(); | 88 | ret = proj_tpc_in_gpc_shared_base_v(); |
89 | break; | 89 | break; |
90 | case GPU_LIT_PPC_IN_GPC_BASE: | ||
91 | ret = proj_ppc_in_gpc_base_v(); | ||
92 | break; | ||
90 | case GPU_LIT_PPC_IN_GPC_STRIDE: | 93 | case GPU_LIT_PPC_IN_GPC_STRIDE: |
91 | ret = proj_ppc_in_gpc_stride_v(); | 94 | ret = proj_ppc_in_gpc_stride_v(); |
92 | break; | 95 | break; |
96 | case GPU_LIT_PPC_IN_GPC_SHARED_BASE: | ||
97 | ret = proj_ppc_in_gpc_shared_base_v(); | ||
98 | break; | ||
93 | case GPU_LIT_ROP_BASE: | 99 | case GPU_LIT_ROP_BASE: |
94 | ret = proj_rop_base_v(); | 100 | ret = proj_rop_base_v(); |
95 | break; | 101 | break; |
@@ -118,6 +124,8 @@ static int gk20a_get_litter_value(struct gk20a *g, | |||
118 | ret = proj_fbpa_stride_v(); | 124 | ret = proj_fbpa_stride_v(); |
119 | break; | 125 | break; |
120 | default: | 126 | default: |
127 | gk20a_err(dev_from_gk20a(g), "Missing definition %d", value); | ||
128 | BUG(); | ||
121 | break; | 129 | break; |
122 | } | 130 | } |
123 | 131 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/hw_proj_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_proj_gk20a.h index 7dce9f91..047dc7d5 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_proj_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_proj_gk20a.h | |||
@@ -78,6 +78,10 @@ static inline u32 proj_ppc_in_gpc_base_v(void) | |||
78 | { | 78 | { |
79 | return 0x00003000; | 79 | return 0x00003000; |
80 | } | 80 | } |
81 | static inline u32 proj_ppc_in_gpc_shared_base_v(void) | ||
82 | { | ||
83 | return 0x00003e00; | ||
84 | } | ||
81 | static inline u32 proj_ppc_in_gpc_stride_v(void) | 85 | static inline u32 proj_ppc_in_gpc_stride_v(void) |
82 | { | 86 | { |
83 | return 0x00000200; | 87 | return 0x00000200; |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 4f2fffc8..57cafd38 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -128,9 +128,15 @@ static int gm20b_get_litter_value(struct gk20a *g, | |||
128 | case GPU_LIT_TPC_IN_GPC_SHARED_BASE: | 128 | case GPU_LIT_TPC_IN_GPC_SHARED_BASE: |
129 | ret = proj_tpc_in_gpc_shared_base_v(); | 129 | ret = proj_tpc_in_gpc_shared_base_v(); |
130 | break; | 130 | break; |
131 | case GPU_LIT_PPC_IN_GPC_BASE: | ||
132 | ret = proj_ppc_in_gpc_base_v(); | ||
133 | break; | ||
131 | case GPU_LIT_PPC_IN_GPC_STRIDE: | 134 | case GPU_LIT_PPC_IN_GPC_STRIDE: |
132 | ret = proj_ppc_in_gpc_stride_v(); | 135 | ret = proj_ppc_in_gpc_stride_v(); |
133 | break; | 136 | break; |
137 | case GPU_LIT_PPC_IN_GPC_SHARED_BASE: | ||
138 | ret = proj_ppc_in_gpc_shared_base_v(); | ||
139 | break; | ||
134 | case GPU_LIT_ROP_BASE: | 140 | case GPU_LIT_ROP_BASE: |
135 | ret = proj_rop_base_v(); | 141 | ret = proj_rop_base_v(); |
136 | break; | 142 | break; |
@@ -159,6 +165,8 @@ static int gm20b_get_litter_value(struct gk20a *g, | |||
159 | ret = proj_fbpa_stride_v(); | 165 | ret = proj_fbpa_stride_v(); |
160 | break; | 166 | break; |
161 | default: | 167 | default: |
168 | gk20a_err(dev_from_gk20a(g), "Missing definition %d", value); | ||
169 | BUG(); | ||
162 | break; | 170 | break; |
163 | } | 171 | } |
164 | 172 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_proj_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_proj_gm20b.h index d4d412e1..026c7848 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_proj_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_proj_gm20b.h | |||
@@ -78,6 +78,10 @@ static inline u32 proj_ppc_in_gpc_base_v(void) | |||
78 | { | 78 | { |
79 | return 0x00003000; | 79 | return 0x00003000; |
80 | } | 80 | } |
81 | static inline u32 proj_ppc_in_gpc_shared_base_v(void) | ||
82 | { | ||
83 | return 0x00003e00; | ||
84 | } | ||
81 | static inline u32 proj_ppc_in_gpc_stride_v(void) | 85 | static inline u32 proj_ppc_in_gpc_stride_v(void) |
82 | { | 86 | { |
83 | return 0x00000200; | 87 | return 0x00000200; |