diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c | 19 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 19 |
5 files changed, 0 insertions, 79 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c index 1a2d378a..b9d3f734 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c | |||
@@ -508,7 +508,6 @@ int vgpu_gm20b_init_hal(struct gk20a *g) | |||
508 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | 508 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
509 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 509 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
510 | 510 | ||
511 | #ifdef CONFIG_TEGRA_ACR | ||
512 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 511 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { |
513 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | 512 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
514 | } else { | 513 | } else { |
@@ -520,21 +519,6 @@ int vgpu_gm20b_init_hal(struct gk20a *g) | |||
520 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | 519 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
521 | } | 520 | } |
522 | } | 521 | } |
523 | #else | ||
524 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
525 | gk20a_dbg_info("running ASIM with PRIV security disabled"); | ||
526 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
527 | } else { | ||
528 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
529 | if (!val) { | ||
530 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
531 | } else { | ||
532 | gk20a_dbg_info("priv security is not supported but enabled"); | ||
533 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
534 | return -EPERM; | ||
535 | } | ||
536 | } | ||
537 | #endif | ||
538 | 522 | ||
539 | /* priv security dependent ops */ | 523 | /* priv security dependent ops */ |
540 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | 524 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c index 6806b318..78f88d4d 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -539,7 +539,6 @@ int vgpu_gp10b_init_hal(struct gk20a *g) | |||
539 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | 539 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); |
540 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 540 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
541 | 541 | ||
542 | #ifdef CONFIG_TEGRA_ACR | ||
543 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 542 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { |
544 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | 543 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); |
545 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | 544 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
@@ -557,24 +556,6 @@ int vgpu_gp10b_init_hal(struct gk20a *g) | |||
557 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | 556 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
558 | } | 557 | } |
559 | } | 558 | } |
560 | #else | ||
561 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
562 | gk20a_dbg_info("running simulator with PRIV security disabled"); | ||
563 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
564 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
565 | } else { | ||
566 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
567 | if (val) { | ||
568 | gk20a_dbg_info("priv security is not supported but enabled"); | ||
569 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
570 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
571 | return -EPERM; | ||
572 | } else { | ||
573 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
574 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
575 | } | ||
576 | } | ||
577 | #endif | ||
578 | 559 | ||
579 | /* priv security dependent ops */ | 560 | /* priv security dependent ops */ |
580 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | 561 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index ef46c1ee..0d032be0 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -737,7 +737,6 @@ u32 gr_gm20b_get_tpc_num(struct gk20a *g, u32 addr) | |||
737 | return 0; | 737 | return 0; |
738 | } | 738 | } |
739 | 739 | ||
740 | #ifdef CONFIG_TEGRA_ACR | ||
741 | static void gr_gm20b_load_gpccs_with_bootloader(struct gk20a *g) | 740 | static void gr_gm20b_load_gpccs_with_bootloader(struct gk20a *g) |
742 | { | 741 | { |
743 | struct gk20a_ctxsw_ucode_info *ucode_info = &g->ctxsw_ucode_info; | 742 | struct gk20a_ctxsw_ucode_info *ucode_info = &g->ctxsw_ucode_info; |
@@ -830,14 +829,6 @@ int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
830 | 829 | ||
831 | return 0; | 830 | return 0; |
832 | } | 831 | } |
833 | #else | ||
834 | |||
835 | int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | ||
836 | { | ||
837 | return -EPERM; | ||
838 | } | ||
839 | |||
840 | #endif | ||
841 | 832 | ||
842 | void gr_gm20b_detect_sm_arch(struct gk20a *g) | 833 | void gr_gm20b_detect_sm_arch(struct gk20a *g) |
843 | { | 834 | { |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 227b6b6c..bb18d2d7 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -634,7 +634,6 @@ int gm20b_init_hal(struct gk20a *g) | |||
634 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | 634 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
635 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 635 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
636 | 636 | ||
637 | #ifdef CONFIG_TEGRA_ACR | ||
638 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 637 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { |
639 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | 638 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
640 | } else { | 639 | } else { |
@@ -646,21 +645,6 @@ int gm20b_init_hal(struct gk20a *g) | |||
646 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | 645 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
647 | } | 646 | } |
648 | } | 647 | } |
649 | #else | ||
650 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
651 | gk20a_dbg_info("running ASIM with PRIV security disabled"); | ||
652 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
653 | } else { | ||
654 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
655 | if (!val) { | ||
656 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
657 | } else { | ||
658 | gk20a_dbg_info("priv security is not supported but enabled"); | ||
659 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
660 | return -EPERM; | ||
661 | } | ||
662 | } | ||
663 | #endif | ||
664 | 648 | ||
665 | /* priv security dependent ops */ | 649 | /* priv security dependent ops */ |
666 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | 650 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 9b3d1a2c..0b2a5712 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -662,7 +662,6 @@ int gp10b_init_hal(struct gk20a *g) | |||
662 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | 662 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); |
663 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 663 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
664 | 664 | ||
665 | #ifdef CONFIG_TEGRA_ACR | ||
666 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 665 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { |
667 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | 666 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); |
668 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | 667 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
@@ -680,24 +679,6 @@ int gp10b_init_hal(struct gk20a *g) | |||
680 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | 679 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
681 | } | 680 | } |
682 | } | 681 | } |
683 | #else | ||
684 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
685 | gk20a_dbg_info("running simulator with PRIV security disabled"); | ||
686 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
687 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
688 | } else { | ||
689 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
690 | if (val) { | ||
691 | gk20a_dbg_info("priv security is not supported but enabled"); | ||
692 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
693 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
694 | return -EPERM; | ||
695 | } else { | ||
696 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
697 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
698 | } | ||
699 | } | ||
700 | #endif | ||
701 | 682 | ||
702 | /* priv security dependent ops */ | 683 | /* priv security dependent ops */ |
703 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | 684 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |