diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 46 |
1 files changed, 26 insertions, 20 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 61ecddef..d2acba96 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -58,22 +58,28 @@ static int gr_gp10b_commit_global_cb_manager(struct gk20a *g, | |||
58 | struct channel_gk20a *c, bool patch) | 58 | struct channel_gk20a *c, bool patch) |
59 | { | 59 | { |
60 | struct gr_gk20a *gr = &g->gr; | 60 | struct gr_gk20a *gr = &g->gr; |
61 | struct channel_ctx_gk20a *ch_ctx = NULL; | 61 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; |
62 | struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; | ||
62 | u32 attrib_offset_in_chunk = 0; | 63 | u32 attrib_offset_in_chunk = 0; |
63 | u32 alpha_offset_in_chunk = 0; | 64 | u32 alpha_offset_in_chunk = 0; |
64 | u32 pd_ab_max_output; | 65 | u32 pd_ab_max_output; |
65 | u32 gpc_index, ppc_index; | 66 | u32 gpc_index, ppc_index; |
66 | u32 temp; | 67 | u32 temp, temp2; |
67 | u32 cbm_cfg_size1, cbm_cfg_size2; | 68 | u32 cbm_cfg_size_beta, cbm_cfg_size_alpha, cbm_cfg_size_steadystate; |
69 | u32 attrib_size_in_chunk, cb_attrib_cache_size_init; | ||
68 | 70 | ||
69 | gk20a_dbg_fn(""); | 71 | gk20a_dbg_fn(""); |
70 | 72 | ||
71 | if (patch) { | 73 | if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_GFXP) { |
72 | int err; | 74 | attrib_size_in_chunk = gr->attrib_cb_default_size + |
73 | ch_ctx = &c->ch_ctx; | 75 | (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - |
74 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); | 76 | gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); |
75 | if (err) | 77 | cb_attrib_cache_size_init = gr->attrib_cb_default_size + |
76 | return err; | 78 | (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - |
79 | gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); | ||
80 | } else { | ||
81 | attrib_size_in_chunk = gr->attrib_cb_size; | ||
82 | cb_attrib_cache_size_init = gr->attrib_cb_default_size; | ||
77 | } | 83 | } |
78 | 84 | ||
79 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_beta_r(), | 85 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_beta_r(), |
@@ -94,17 +100,20 @@ static int gr_gp10b_commit_global_cb_manager(struct gk20a *g, | |||
94 | 100 | ||
95 | for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { | 101 | for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { |
96 | temp = proj_gpc_stride_v() * gpc_index; | 102 | temp = proj_gpc_stride_v() * gpc_index; |
103 | temp2 = proj_scal_litter_num_pes_per_gpc_v() * gpc_index; | ||
97 | for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index]; | 104 | for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index]; |
98 | ppc_index++) { | 105 | ppc_index++) { |
99 | cbm_cfg_size1 = gr->attrib_cb_default_size * | 106 | cbm_cfg_size_beta = cb_attrib_cache_size_init * |
107 | gr->pes_tpc_count[ppc_index][gpc_index]; | ||
108 | cbm_cfg_size_alpha = gr->alpha_cb_default_size * | ||
100 | gr->pes_tpc_count[ppc_index][gpc_index]; | 109 | gr->pes_tpc_count[ppc_index][gpc_index]; |
101 | cbm_cfg_size2 = gr->alpha_cb_default_size * | 110 | cbm_cfg_size_steadystate = gr->attrib_cb_default_size * |
102 | gr->pes_tpc_count[ppc_index][gpc_index]; | 111 | gr->pes_tpc_count[ppc_index][gpc_index]; |
103 | 112 | ||
104 | gr_gk20a_ctx_patch_write(g, ch_ctx, | 113 | gr_gk20a_ctx_patch_write(g, ch_ctx, |
105 | gr_gpc0_ppc0_cbm_beta_cb_size_r() + temp + | 114 | gr_gpc0_ppc0_cbm_beta_cb_size_r() + temp + |
106 | proj_ppc_in_gpc_stride_v() * ppc_index, | 115 | proj_ppc_in_gpc_stride_v() * ppc_index, |
107 | cbm_cfg_size1, patch); | 116 | cbm_cfg_size_beta, patch); |
108 | 117 | ||
109 | gr_gk20a_ctx_patch_write(g, ch_ctx, | 118 | gr_gk20a_ctx_patch_write(g, ch_ctx, |
110 | gr_gpc0_ppc0_cbm_beta_cb_offset_r() + temp + | 119 | gr_gpc0_ppc0_cbm_beta_cb_offset_r() + temp + |
@@ -114,16 +123,16 @@ static int gr_gp10b_commit_global_cb_manager(struct gk20a *g, | |||
114 | gr_gk20a_ctx_patch_write(g, ch_ctx, | 123 | gr_gk20a_ctx_patch_write(g, ch_ctx, |
115 | gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp + | 124 | gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp + |
116 | proj_ppc_in_gpc_stride_v() * ppc_index, | 125 | proj_ppc_in_gpc_stride_v() * ppc_index, |
117 | gr->attrib_cb_default_size, | 126 | cbm_cfg_size_steadystate, |
118 | patch); | 127 | patch); |
119 | 128 | ||
120 | attrib_offset_in_chunk += gr->attrib_cb_size * | 129 | attrib_offset_in_chunk += attrib_size_in_chunk * |
121 | gr->pes_tpc_count[ppc_index][gpc_index]; | 130 | gr->pes_tpc_count[ppc_index][gpc_index]; |
122 | 131 | ||
123 | gr_gk20a_ctx_patch_write(g, ch_ctx, | 132 | gr_gk20a_ctx_patch_write(g, ch_ctx, |
124 | gr_gpc0_ppc0_cbm_alpha_cb_size_r() + temp + | 133 | gr_gpc0_ppc0_cbm_alpha_cb_size_r() + temp + |
125 | proj_ppc_in_gpc_stride_v() * ppc_index, | 134 | proj_ppc_in_gpc_stride_v() * ppc_index, |
126 | cbm_cfg_size2, patch); | 135 | cbm_cfg_size_alpha, patch); |
127 | 136 | ||
128 | gr_gk20a_ctx_patch_write(g, ch_ctx, | 137 | gr_gk20a_ctx_patch_write(g, ch_ctx, |
129 | gr_gpc0_ppc0_cbm_alpha_cb_offset_r() + temp + | 138 | gr_gpc0_ppc0_cbm_alpha_cb_offset_r() + temp + |
@@ -134,15 +143,12 @@ static int gr_gp10b_commit_global_cb_manager(struct gk20a *g, | |||
134 | gr->pes_tpc_count[ppc_index][gpc_index]; | 143 | gr->pes_tpc_count[ppc_index][gpc_index]; |
135 | 144 | ||
136 | gr_gk20a_ctx_patch_write(g, ch_ctx, | 145 | gr_gk20a_ctx_patch_write(g, ch_ctx, |
137 | gr_gpcs_swdx_tc_beta_cb_size_r(ppc_index + gpc_index), | 146 | gr_gpcs_swdx_tc_beta_cb_size_r(ppc_index + temp2), |
138 | gr_gpcs_swdx_tc_beta_cb_size_v_f(cbm_cfg_size1), | 147 | gr_gpcs_swdx_tc_beta_cb_size_v_f(cbm_cfg_size_steadystate), |
139 | patch); | 148 | patch); |
140 | } | 149 | } |
141 | } | 150 | } |
142 | 151 | ||
143 | if (patch) | ||
144 | gr_gk20a_ctx_patch_write_end(g, ch_ctx); | ||
145 | |||
146 | return 0; | 152 | return 0; |
147 | } | 153 | } |
148 | 154 | ||