diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 38 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 20 |
6 files changed, 85 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 0207588f..24c062d2 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -202,6 +202,10 @@ struct gpu_ops { | |||
202 | struct channel_gk20a *fault_ch, | 202 | struct channel_gk20a *fault_ch, |
203 | bool *early_exit, bool *ignore_debugger); | 203 | bool *early_exit, bool *ignore_debugger); |
204 | u32 (*mask_hww_warp_esr)(u32 hww_warp_esr); | 204 | u32 (*mask_hww_warp_esr)(u32 hww_warp_esr); |
205 | int (*handle_sm_exception)(struct gk20a *g, u32 gpc, u32 tpc, | ||
206 | bool *post_event, struct channel_gk20a *fault_ch); | ||
207 | int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc, | ||
208 | bool *post_event); | ||
205 | } gr; | 209 | } gr; |
206 | const char *name; | 210 | const char *name; |
207 | struct { | 211 | struct { |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 6e2ea548..542a6c02 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -3996,6 +3996,7 @@ static void gk20a_gr_enable_gpc_exceptions(struct gk20a *g) | |||
3996 | u32 tpc_mask; | 3996 | u32 tpc_mask; |
3997 | 3997 | ||
3998 | gk20a_writel(g, gr_gpcs_tpcs_tpccs_tpc_exception_en_r(), | 3998 | gk20a_writel(g, gr_gpcs_tpcs_tpccs_tpc_exception_en_r(), |
3999 | gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f() | | ||
3999 | gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f()); | 4000 | gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f()); |
4000 | 4001 | ||
4001 | tpc_mask = | 4002 | tpc_mask = |
@@ -5241,7 +5242,7 @@ u32 gk20a_mask_hww_warp_esr(u32 hww_warp_esr) | |||
5241 | return hww_warp_esr; | 5242 | return hww_warp_esr; |
5242 | } | 5243 | } |
5243 | 5244 | ||
5244 | static int gk20a_gr_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | 5245 | int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, |
5245 | bool *post_event, struct channel_gk20a *fault_ch) | 5246 | bool *post_event, struct channel_gk20a *fault_ch) |
5246 | { | 5247 | { |
5247 | int ret = 0; | 5248 | int ret = 0; |
@@ -5322,6 +5323,27 @@ static int gk20a_gr_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
5322 | return ret; | 5323 | return ret; |
5323 | } | 5324 | } |
5324 | 5325 | ||
5326 | int gr_gk20a_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | ||
5327 | bool *post_event) | ||
5328 | { | ||
5329 | int ret = 0; | ||
5330 | u32 offset = proj_gpc_stride_v() * gpc + | ||
5331 | proj_tpc_in_gpc_stride_v() * tpc; | ||
5332 | u32 esr; | ||
5333 | |||
5334 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, ""); | ||
5335 | |||
5336 | esr = gk20a_readl(g, | ||
5337 | gr_gpc0_tpc0_tex_m_hww_esr_r() + offset); | ||
5338 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "0x%08x", esr); | ||
5339 | |||
5340 | gk20a_writel(g, | ||
5341 | gr_gpc0_tpc0_tex_m_hww_esr_r() + offset, | ||
5342 | esr); | ||
5343 | |||
5344 | return ret; | ||
5345 | } | ||
5346 | |||
5325 | static int gk20a_gr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc, | 5347 | static int gk20a_gr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc, |
5326 | bool *post_event, struct channel_gk20a *fault_ch) | 5348 | bool *post_event, struct channel_gk20a *fault_ch) |
5327 | { | 5349 | { |
@@ -5338,8 +5360,16 @@ static int gk20a_gr_handle_tpc_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
5338 | gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v()) { | 5360 | gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v()) { |
5339 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, | 5361 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, |
5340 | "GPC%d TPC%d: SM exception pending", gpc, tpc); | 5362 | "GPC%d TPC%d: SM exception pending", gpc, tpc); |
5341 | ret = gk20a_gr_handle_sm_exception(g, gpc, tpc, | 5363 | ret = g->ops.gr.handle_sm_exception(g, gpc, tpc, |
5342 | post_event, fault_ch); | 5364 | post_event, fault_ch); |
5365 | } | ||
5366 | |||
5367 | /* check if a tex exeption is pending */ | ||
5368 | if (gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(tpc_exception) == | ||
5369 | gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v()) { | ||
5370 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, | ||
5371 | "GPC%d TPC%d: TEX exception pending", gpc, tpc); | ||
5372 | ret = g->ops.gr.handle_tex_exception(g, gpc, tpc, post_event); | ||
5343 | } | 5373 | } |
5344 | 5374 | ||
5345 | return ret; | 5375 | return ret; |
@@ -7595,4 +7625,6 @@ void gk20a_init_gr_ops(struct gpu_ops *gops) | |||
7595 | gops->gr.get_access_map = gr_gk20a_get_access_map; | 7625 | gops->gr.get_access_map = gr_gk20a_get_access_map; |
7596 | gops->gr.handle_fecs_error = gk20a_gr_handle_fecs_error; | 7626 | gops->gr.handle_fecs_error = gk20a_gr_handle_fecs_error; |
7597 | gops->gr.mask_hww_warp_esr = gk20a_mask_hww_warp_esr; | 7627 | gops->gr.mask_hww_warp_esr = gk20a_mask_hww_warp_esr; |
7628 | gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; | ||
7629 | gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception; | ||
7598 | } | 7630 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index ad197228..9c37fd02 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -528,6 +528,10 @@ int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, | |||
528 | struct zbc_entry *depth_val, u32 index); | 528 | struct zbc_entry *depth_val, u32 index); |
529 | int gr_gk20a_wait_idle(struct gk20a *g, unsigned long end_jiffies, | 529 | int gr_gk20a_wait_idle(struct gk20a *g, unsigned long end_jiffies, |
530 | u32 expect_delay); | 530 | u32 expect_delay); |
531 | int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | ||
532 | bool *post_event, struct channel_gk20a *fault_ch); | ||
533 | int gr_gk20a_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | ||
534 | bool *post_event); | ||
531 | int gr_gk20a_init_ctx_state(struct gk20a *g); | 535 | int gr_gk20a_init_ctx_state(struct gk20a *g); |
532 | int gr_gk20a_submit_fecs_method_op(struct gk20a *g, | 536 | int gr_gk20a_submit_fecs_method_op(struct gk20a *g, |
533 | struct fecs_method_op_gk20a op, | 537 | struct fecs_method_op_gk20a op, |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index 6a155ccc..a73209f2 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |||
@@ -2990,6 +2990,10 @@ static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) | |||
2990 | { | 2990 | { |
2991 | return 0x2; | 2991 | return 0x2; |
2992 | } | 2992 | } |
2993 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) | ||
2994 | { | ||
2995 | return 0x1; | ||
2996 | } | ||
2993 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) | 2997 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) |
2994 | { | 2998 | { |
2995 | return 0x0050450c; | 2999 | return 0x0050450c; |
@@ -3026,6 +3030,14 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) | |||
3026 | { | 3030 | { |
3027 | return 0x00504508; | 3031 | return 0x00504508; |
3028 | } | 3032 | } |
3033 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) | ||
3034 | { | ||
3035 | return (r >> 0) & 0x1; | ||
3036 | } | ||
3037 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) | ||
3038 | { | ||
3039 | return 0x00000001; | ||
3040 | } | ||
3029 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) | 3041 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) |
3030 | { | 3042 | { |
3031 | return (r >> 1) & 0x1; | 3043 | return (r >> 1) & 0x1; |
@@ -3170,6 +3182,14 @@ static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f( | |||
3170 | { | 3182 | { |
3171 | return 0x40; | 3183 | return 0x40; |
3172 | } | 3184 | } |
3185 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) | ||
3186 | { | ||
3187 | return 0x00504224; | ||
3188 | } | ||
3189 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void) | ||
3190 | { | ||
3191 | return 0x1; | ||
3192 | } | ||
3173 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) | 3193 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) |
3174 | { | 3194 | { |
3175 | return 0x00504648; | 3195 | return 0x00504648; |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index a80cef8f..ab1b166d 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1229,4 +1229,6 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
1229 | gops->gr.get_access_map = gr_gm20b_get_access_map; | 1229 | gops->gr.get_access_map = gr_gm20b_get_access_map; |
1230 | gops->gr.handle_fecs_error = gk20a_gr_handle_fecs_error; | 1230 | gops->gr.handle_fecs_error = gk20a_gr_handle_fecs_error; |
1231 | gops->gr.mask_hww_warp_esr = gk20a_mask_hww_warp_esr; | 1231 | gops->gr.mask_hww_warp_esr = gk20a_mask_hww_warp_esr; |
1232 | gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; | ||
1233 | gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception; | ||
1232 | } | 1234 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index 41a7c885..7a19e4ab 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |||
@@ -3022,6 +3022,10 @@ static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) | |||
3022 | { | 3022 | { |
3023 | return 0x2; | 3023 | return 0x2; |
3024 | } | 3024 | } |
3025 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) | ||
3026 | { | ||
3027 | return 0x1; | ||
3028 | } | ||
3025 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) | 3029 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) |
3026 | { | 3030 | { |
3027 | return 0x0050450c; | 3031 | return 0x0050450c; |
@@ -3058,6 +3062,14 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) | |||
3058 | { | 3062 | { |
3059 | return 0x00504508; | 3063 | return 0x00504508; |
3060 | } | 3064 | } |
3065 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) | ||
3066 | { | ||
3067 | return (r >> 0) & 0x1; | ||
3068 | } | ||
3069 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) | ||
3070 | { | ||
3071 | return 0x00000001; | ||
3072 | } | ||
3061 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) | 3073 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) |
3062 | { | 3074 | { |
3063 | return (r >> 1) & 0x1; | 3075 | return (r >> 1) & 0x1; |
@@ -3214,6 +3226,14 @@ static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f( | |||
3214 | { | 3226 | { |
3215 | return 0x40; | 3227 | return 0x40; |
3216 | } | 3228 | } |
3229 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) | ||
3230 | { | ||
3231 | return 0x00504224; | ||
3232 | } | ||
3233 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void) | ||
3234 | { | ||
3235 | return 0x1; | ||
3236 | } | ||
3217 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) | 3237 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) |
3218 | { | 3238 | { |
3219 | return 0x00504648; | 3239 | return 0x00504648; |