diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/common/bus/bus_gk20a.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/bus/bus_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 4 |
13 files changed, 31 insertions, 32 deletions
diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c index 46065579..62dd7450 100644 --- a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c +++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c | |||
@@ -31,9 +31,6 @@ | |||
31 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | 31 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> |
32 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> | 32 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> |
33 | #include <nvgpu/hw/gk20a/hw_timer_gk20a.h> | 33 | #include <nvgpu/hw/gk20a/hw_timer_gk20a.h> |
34 | #include <nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h> | ||
35 | #include <nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h> | ||
36 | #include <nvgpu/hw/gk20a/hw_pri_ringstation_fbp_gk20a.h> | ||
37 | 34 | ||
38 | void gk20a_bus_init_hw(struct gk20a *g) | 35 | void gk20a_bus_init_hw(struct gk20a *g) |
39 | { | 36 | { |
@@ -172,14 +169,3 @@ int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst) | |||
172 | 169 | ||
173 | return 0; | 170 | return 0; |
174 | } | 171 | } |
175 | |||
176 | void gk20a_bus_set_ppriv_timeout_settings(struct gk20a *g) | ||
177 | { | ||
178 | /* | ||
179 | * Bug 1340570: increase the clock timeout to avoid potential | ||
180 | * operation failure at high gpcclk rate. Default values are 0x400. | ||
181 | */ | ||
182 | nvgpu_writel(g, pri_ringstation_sys_master_config_r(0x15), 0x800); | ||
183 | nvgpu_writel(g, pri_ringstation_gpc_master_config_r(0xa), 0x800); | ||
184 | nvgpu_writel(g, pri_ringstation_fbp_master_config_r(0x8), 0x800); | ||
185 | } | ||
diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.h b/drivers/gpu/nvgpu/common/bus/bus_gk20a.h index 8c07d1fe..1f81a4b0 100644 --- a/drivers/gpu/nvgpu/common/bus/bus_gk20a.h +++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.h | |||
@@ -32,6 +32,5 @@ void gk20a_bus_isr(struct gk20a *g); | |||
32 | int gk20a_read_ptimer(struct gk20a *g, u64 *value); | 32 | int gk20a_read_ptimer(struct gk20a *g, u64 *value); |
33 | void gk20a_bus_init_hw(struct gk20a *g); | 33 | void gk20a_bus_init_hw(struct gk20a *g); |
34 | int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst); | 34 | int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst); |
35 | void gk20a_bus_set_ppriv_timeout_settings(struct gk20a *g); | ||
36 | 35 | ||
37 | #endif /* GK20A_H */ | 36 | #endif /* GK20A_H */ |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 77e6e759..2d304cff 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1128,7 +1128,6 @@ struct gpu_ops { | |||
1128 | u32 source_id, u32 count, | 1128 | u32 source_id, u32 count, |
1129 | struct nvgpu_cpu_time_correlation_sample *); | 1129 | struct nvgpu_cpu_time_correlation_sample *); |
1130 | int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst); | 1130 | int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst); |
1131 | void (*set_ppriv_timeout_settings)(struct gk20a *g); | ||
1132 | } bus; | 1131 | } bus; |
1133 | 1132 | ||
1134 | struct { | 1133 | struct { |
@@ -1179,6 +1178,7 @@ struct gpu_ops { | |||
1179 | struct { | 1178 | struct { |
1180 | void (*isr)(struct gk20a *g); | 1179 | void (*isr)(struct gk20a *g); |
1181 | void (*decode_error_code)(struct gk20a *g, u32 error_code); | 1180 | void (*decode_error_code)(struct gk20a *g, u32 error_code); |
1181 | void (*set_ppriv_timeout_settings)(struct gk20a *g); | ||
1182 | } priv_ring; | 1182 | } priv_ring; |
1183 | struct { | 1183 | struct { |
1184 | int (*check_priv_security)(struct gk20a *g); | 1184 | int (*check_priv_security)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 52346541..42e96715 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -4502,8 +4502,8 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4502 | 4502 | ||
4503 | gr_gk20a_zcull_init_hw(g, gr); | 4503 | gr_gk20a_zcull_init_hw(g, gr); |
4504 | 4504 | ||
4505 | if (g->ops.bus.set_ppriv_timeout_settings) | 4505 | if (g->ops.priv_ring.set_ppriv_timeout_settings) |
4506 | g->ops.bus.set_ppriv_timeout_settings(g); | 4506 | g->ops.priv_ring.set_ppriv_timeout_settings(g); |
4507 | 4507 | ||
4508 | /* enable fifo access */ | 4508 | /* enable fifo access */ |
4509 | gk20a_writel(g, gr_gpfifo_ctl_r(), | 4509 | gk20a_writel(g, gr_gpfifo_ctl_r(), |
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c index dea42b55..adbaf94f 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | |||
@@ -32,6 +32,7 @@ | |||
32 | #include <nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h> | 32 | #include <nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h> |
33 | #include <nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h> | 33 | #include <nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h> |
34 | #include <nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h> | 34 | #include <nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h> |
35 | #include <nvgpu/hw/gk20a/hw_pri_ringstation_fbp_gk20a.h> | ||
35 | 36 | ||
36 | void gk20a_enable_priv_ring(struct gk20a *g) | 37 | void gk20a_enable_priv_ring(struct gk20a *g) |
37 | { | 38 | { |
@@ -103,3 +104,14 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
103 | if (retry == 0 && cmd != pri_ringmaster_command_cmd_no_cmd_v()) | 104 | if (retry == 0 && cmd != pri_ringmaster_command_cmd_no_cmd_v()) |
104 | nvgpu_warn(g, "priv ringmaster intr ack too many retries"); | 105 | nvgpu_warn(g, "priv ringmaster intr ack too many retries"); |
105 | } | 106 | } |
107 | |||
108 | void gk20a_priv_set_timeout_settings(struct gk20a *g) | ||
109 | { | ||
110 | /* | ||
111 | * Bug 1340570: increase the clock timeout to avoid potential | ||
112 | * operation failure at high gpcclk rate. Default values are 0x400. | ||
113 | */ | ||
114 | nvgpu_writel(g, pri_ringstation_sys_master_config_r(0x15), 0x800); | ||
115 | nvgpu_writel(g, pri_ringstation_gpc_master_config_r(0xa), 0x800); | ||
116 | nvgpu_writel(g, pri_ringstation_fbp_master_config_r(0x8), 0x800); | ||
117 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h index ef564eeb..98040624 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h | |||
@@ -28,5 +28,6 @@ struct gpu_ops; | |||
28 | 28 | ||
29 | void gk20a_priv_ring_isr(struct gk20a *g); | 29 | void gk20a_priv_ring_isr(struct gk20a *g); |
30 | void gk20a_enable_priv_ring(struct gk20a *g); | 30 | void gk20a_enable_priv_ring(struct gk20a *g); |
31 | void gk20a_priv_set_timeout_settings(struct gk20a *g); | ||
31 | 32 | ||
32 | #endif /*__PRIV_RING_GK20A_H__*/ | 33 | #endif /*__PRIV_RING_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index ccceab03..970d2d27 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -608,8 +608,6 @@ static const struct gpu_ops gm20b_ops = { | |||
608 | .read_ptimer = gk20a_read_ptimer, | 608 | .read_ptimer = gk20a_read_ptimer, |
609 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, | 609 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, |
610 | .bar1_bind = gm20b_bus_bar1_bind, | 610 | .bar1_bind = gm20b_bus_bar1_bind, |
611 | .set_ppriv_timeout_settings = | ||
612 | gk20a_bus_set_ppriv_timeout_settings, | ||
613 | }, | 611 | }, |
614 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 612 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
615 | .css = { | 613 | .css = { |
@@ -626,6 +624,8 @@ static const struct gpu_ops gm20b_ops = { | |||
626 | }, | 624 | }, |
627 | .priv_ring = { | 625 | .priv_ring = { |
628 | .isr = gk20a_priv_ring_isr, | 626 | .isr = gk20a_priv_ring_isr, |
627 | .set_ppriv_timeout_settings = | ||
628 | gk20a_priv_set_timeout_settings, | ||
629 | }, | 629 | }, |
630 | .fuse = { | 630 | .fuse = { |
631 | .check_priv_security = gm20b_fuse_check_priv_security, | 631 | .check_priv_security = gm20b_fuse_check_priv_security, |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 7cfe4d76..6749dba7 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -726,8 +726,7 @@ static const struct gpu_ops gp106_ops = { | |||
726 | .read_ptimer = gk20a_read_ptimer, | 726 | .read_ptimer = gk20a_read_ptimer, |
727 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, | 727 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, |
728 | .bar1_bind = gk20a_bus_bar1_bind, | 728 | .bar1_bind = gk20a_bus_bar1_bind, |
729 | .set_ppriv_timeout_settings = | 729 | |
730 | gk20a_bus_set_ppriv_timeout_settings, | ||
731 | }, | 730 | }, |
732 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 731 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
733 | .css = { | 732 | .css = { |
@@ -760,6 +759,8 @@ static const struct gpu_ops gp106_ops = { | |||
760 | .priv_ring = { | 759 | .priv_ring = { |
761 | .isr = gp10b_priv_ring_isr, | 760 | .isr = gp10b_priv_ring_isr, |
762 | .decode_error_code = gp10b_priv_ring_decode_error_code, | 761 | .decode_error_code = gp10b_priv_ring_decode_error_code, |
762 | .set_ppriv_timeout_settings = | ||
763 | gk20a_priv_set_timeout_settings, | ||
763 | }, | 764 | }, |
764 | .fuse = { | 765 | .fuse = { |
765 | .check_priv_security = gp106_fuse_check_priv_security, | 766 | .check_priv_security = gp106_fuse_check_priv_security, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 2d6479fc..47986f1b 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -656,8 +656,6 @@ static const struct gpu_ops gp10b_ops = { | |||
656 | .read_ptimer = gk20a_read_ptimer, | 656 | .read_ptimer = gk20a_read_ptimer, |
657 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, | 657 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, |
658 | .bar1_bind = gk20a_bus_bar1_bind, | 658 | .bar1_bind = gk20a_bus_bar1_bind, |
659 | .set_ppriv_timeout_settings = | ||
660 | gk20a_bus_set_ppriv_timeout_settings, | ||
661 | }, | 659 | }, |
662 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 660 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
663 | .css = { | 661 | .css = { |
@@ -675,6 +673,8 @@ static const struct gpu_ops gp10b_ops = { | |||
675 | .priv_ring = { | 673 | .priv_ring = { |
676 | .isr = gp10b_priv_ring_isr, | 674 | .isr = gp10b_priv_ring_isr, |
677 | .decode_error_code = gp10b_priv_ring_decode_error_code, | 675 | .decode_error_code = gp10b_priv_ring_decode_error_code, |
676 | .set_ppriv_timeout_settings = | ||
677 | gk20a_priv_set_timeout_settings, | ||
678 | }, | 678 | }, |
679 | .fuse = { | 679 | .fuse = { |
680 | .check_priv_security = gp10b_fuse_check_priv_security, | 680 | .check_priv_security = gp10b_fuse_check_priv_security, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 961129c6..00c992bc 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -796,8 +796,6 @@ static const struct gpu_ops gv100_ops = { | |||
796 | .read_ptimer = gk20a_read_ptimer, | 796 | .read_ptimer = gk20a_read_ptimer, |
797 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, | 797 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, |
798 | .bar1_bind = NULL, | 798 | .bar1_bind = NULL, |
799 | .set_ppriv_timeout_settings = | ||
800 | gk20a_bus_set_ppriv_timeout_settings, | ||
801 | }, | 799 | }, |
802 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 800 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
803 | .css = { | 801 | .css = { |
@@ -827,6 +825,8 @@ static const struct gpu_ops gv100_ops = { | |||
827 | .priv_ring = { | 825 | .priv_ring = { |
828 | .isr = gp10b_priv_ring_isr, | 826 | .isr = gp10b_priv_ring_isr, |
829 | .decode_error_code = gp10b_priv_ring_decode_error_code, | 827 | .decode_error_code = gp10b_priv_ring_decode_error_code, |
828 | .set_ppriv_timeout_settings = | ||
829 | gk20a_priv_set_timeout_settings, | ||
830 | }, | 830 | }, |
831 | #if defined(CONFIG_TEGRA_NVLINK) | 831 | #if defined(CONFIG_TEGRA_NVLINK) |
832 | .nvlink = { | 832 | .nvlink = { |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 2379c17b..a191c3fc 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -725,8 +725,6 @@ static const struct gpu_ops gv11b_ops = { | |||
725 | .read_ptimer = gk20a_read_ptimer, | 725 | .read_ptimer = gk20a_read_ptimer, |
726 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, | 726 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, |
727 | .bar1_bind = NULL, | 727 | .bar1_bind = NULL, |
728 | .set_ppriv_timeout_settings = | ||
729 | gk20a_bus_set_ppriv_timeout_settings, | ||
730 | }, | 728 | }, |
731 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 729 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
732 | .css = { | 730 | .css = { |
@@ -744,6 +742,8 @@ static const struct gpu_ops gv11b_ops = { | |||
744 | .priv_ring = { | 742 | .priv_ring = { |
745 | .isr = gp10b_priv_ring_isr, | 743 | .isr = gp10b_priv_ring_isr, |
746 | .decode_error_code = gp10b_priv_ring_decode_error_code, | 744 | .decode_error_code = gp10b_priv_ring_decode_error_code, |
745 | .set_ppriv_timeout_settings = | ||
746 | gk20a_priv_set_timeout_settings, | ||
747 | }, | 747 | }, |
748 | .fuse = { | 748 | .fuse = { |
749 | .check_priv_security = gp10b_fuse_check_priv_security, | 749 | .check_priv_security = gp10b_fuse_check_priv_security, |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 3f6d4e0f..f4a87a74 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -529,8 +529,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
529 | .read_ptimer = vgpu_read_ptimer, | 529 | .read_ptimer = vgpu_read_ptimer, |
530 | .get_timestamps_zipper = vgpu_get_timestamps_zipper, | 530 | .get_timestamps_zipper = vgpu_get_timestamps_zipper, |
531 | .bar1_bind = gk20a_bus_bar1_bind, | 531 | .bar1_bind = gk20a_bus_bar1_bind, |
532 | .set_ppriv_timeout_settings = | ||
533 | gk20a_bus_set_ppriv_timeout_settings, | ||
534 | }, | 532 | }, |
535 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 533 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
536 | .css = { | 534 | .css = { |
@@ -548,6 +546,8 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
548 | }, | 546 | }, |
549 | .priv_ring = { | 547 | .priv_ring = { |
550 | .isr = gp10b_priv_ring_isr, | 548 | .isr = gp10b_priv_ring_isr, |
549 | .set_ppriv_timeout_settings = | ||
550 | gk20a_priv_set_timeout_settings, | ||
551 | }, | 551 | }, |
552 | .fuse = { | 552 | .fuse = { |
553 | .check_priv_security = vgpu_gp10b_fuse_check_priv_security, | 553 | .check_priv_security = vgpu_gp10b_fuse_check_priv_security, |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 0a48e1ae..deecc0d8 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -577,8 +577,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
577 | .read_ptimer = vgpu_read_ptimer, | 577 | .read_ptimer = vgpu_read_ptimer, |
578 | .get_timestamps_zipper = vgpu_get_timestamps_zipper, | 578 | .get_timestamps_zipper = vgpu_get_timestamps_zipper, |
579 | .bar1_bind = NULL, | 579 | .bar1_bind = NULL, |
580 | .set_ppriv_timeout_settings = | ||
581 | gk20a_bus_set_ppriv_timeout_settings, | ||
582 | }, | 580 | }, |
583 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 581 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
584 | .css = { | 582 | .css = { |
@@ -596,6 +594,8 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
596 | }, | 594 | }, |
597 | .priv_ring = { | 595 | .priv_ring = { |
598 | .isr = gp10b_priv_ring_isr, | 596 | .isr = gp10b_priv_ring_isr, |
597 | .set_ppriv_timeout_settings = | ||
598 | gk20a_priv_set_timeout_settings, | ||
599 | }, | 599 | }, |
600 | .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics, | 600 | .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics, |
601 | .get_litter_value = gv11b_get_litter_value, | 601 | .get_litter_value = gv11b_get_litter_value, |