diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h | 22 |
3 files changed, 25 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h b/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h index 7338fa3a..5b757cbf 100644 --- a/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h +++ b/drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h | |||
@@ -59,7 +59,7 @@ | |||
59 | BIT(CTRL_CLK_VIN_ID_GPC3) | \ | 59 | BIT(CTRL_CLK_VIN_ID_GPC3) | \ |
60 | BIT(CTRL_CLK_VIN_ID_GPC4) | \ | 60 | BIT(CTRL_CLK_VIN_ID_GPC4) | \ |
61 | BIT(CTRL_CLK_VIN_ID_GPC5)) | 61 | BIT(CTRL_CLK_VIN_ID_GPC5)) |
62 | #define CTRL_CLK_LUT_NUM_ENTRIES 0x50 | 62 | #define CTRL_CLK_LUT_NUM_ENTRIES (100) |
63 | #define CTRL_CLK_VIN_STEP_SIZE_UV (10000) | 63 | #define CTRL_CLK_VIN_STEP_SIZE_UV (10000) |
64 | #define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000) | 64 | #define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000) |
65 | #define CTRL_CLK_FLL_TYPE_DISABLED 0 | 65 | #define CTRL_CLK_FLL_TYPE_DISABLED 0 |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h index cf39658f..342ca199 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h | |||
@@ -50,12 +50,13 @@ struct nv_pmu_super_surface { | |||
50 | struct nv_pmu_clk_clk_vin_device_boardobj_grp_set clk_vin_device_grp_set; | 50 | struct nv_pmu_clk_clk_vin_device_boardobj_grp_set clk_vin_device_grp_set; |
51 | struct nv_pmu_clk_clk_domain_boardobj_grp_set clk_domain_grp_set; | 51 | struct nv_pmu_clk_clk_domain_boardobj_grp_set clk_domain_grp_set; |
52 | struct nv_pmu_clk_clk_freq_controller_boardobj_grp_set clk_freq_controller_grp_set; | 52 | struct nv_pmu_clk_clk_freq_controller_boardobj_grp_set clk_freq_controller_grp_set; |
53 | u8 clk_rsvd2[0x200]; | ||
53 | struct nv_pmu_clk_clk_fll_device_boardobj_grp_set clk_fll_device_grp_set; | 54 | struct nv_pmu_clk_clk_fll_device_boardobj_grp_set clk_fll_device_grp_set; |
54 | struct nv_pmu_clk_clk_prog_boardobj_grp_set clk_prog_grp_set; | 55 | struct nv_pmu_clk_clk_prog_boardobj_grp_set clk_prog_grp_set; |
55 | struct nv_pmu_clk_clk_vf_point_boardobj_grp_set clk_vf_point_grp_set; | 56 | struct nv_pmu_clk_clk_vf_point_boardobj_grp_set clk_vf_point_grp_set; |
56 | |||
57 | struct nv_pmu_clk_clk_vin_device_boardobj_grp_get_status clk_vin_device_grp_get_status; | 57 | struct nv_pmu_clk_clk_vin_device_boardobj_grp_get_status clk_vin_device_grp_get_status; |
58 | struct nv_pmu_clk_clk_fll_device_boardobj_grp_get_status clk_fll_device_grp_get_status; | 58 | struct nv_pmu_clk_clk_fll_device_boardobj_grp_get_status clk_fll_device_grp_get_status; |
59 | u8 clk_rsvd1[0x800]; | ||
59 | struct nv_pmu_clk_clk_vf_point_boardobj_grp_get_status clk_vf_point_grp_get_status; | 60 | struct nv_pmu_clk_clk_vf_point_boardobj_grp_get_status clk_vf_point_grp_get_status; |
60 | u8 clk_rsvd[0x4660]; | 61 | u8 clk_rsvd[0x4660]; |
61 | } clk; | 62 | } clk; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h index dde85435..471892ca 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h | |||
@@ -128,12 +128,30 @@ struct nv_pmu_clk_clk_domain_3x_master_boardobj_set { | |||
128 | u32 slave_idxs_mask; | 128 | u32 slave_idxs_mask; |
129 | }; | 129 | }; |
130 | 130 | ||
131 | struct nv_pmu_clk_clk_domain_35_prog_boardobj_set { | ||
132 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; | ||
133 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | ||
134 | u8 dummy; | ||
135 | }; | ||
136 | |||
137 | struct nv_pmu_clk_clk_domain_35_master_boardobj_set { | ||
138 | struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super; | ||
139 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | ||
140 | u32 master_slave_domains_grp_mask; | ||
141 | }; | ||
142 | |||
143 | |||
131 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set { | 144 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set { |
132 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; | 145 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; |
133 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | 146 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ |
134 | u8 master_idx; | 147 | u8 master_idx; |
135 | }; | 148 | }; |
136 | 149 | ||
150 | struct nv_pmu_clk_clk_domain_35_slave_boardobj_set { | ||
151 | struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super; | ||
152 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | ||
153 | u8 master_idx; | ||
154 | }; | ||
137 | union nv_pmu_clk_clk_domain_boardobj_set_union { | 155 | union nv_pmu_clk_clk_domain_boardobj_set_union { |
138 | struct nv_pmu_boardobj board_obj; | 156 | struct nv_pmu_boardobj board_obj; |
139 | struct nv_pmu_clk_clk_domain_boardobj_set super; | 157 | struct nv_pmu_clk_clk_domain_boardobj_set super; |
@@ -142,6 +160,9 @@ union nv_pmu_clk_clk_domain_boardobj_set_union { | |||
142 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog; | 160 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog; |
143 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set v3x_master; | 161 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set v3x_master; |
144 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set v3x_slave; | 162 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set v3x_slave; |
163 | struct nv_pmu_clk_clk_domain_35_prog_boardobj_set v35_prog; | ||
164 | struct nv_pmu_clk_clk_domain_35_master_boardobj_set v35_master; | ||
165 | struct nv_pmu_clk_clk_domain_35_slave_boardobj_set v35_slave; | ||
145 | }; | 166 | }; |
146 | 167 | ||
147 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_domain); | 168 | NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_domain); |
@@ -504,6 +525,7 @@ struct nv_pmu_clk_clk_fll_device_boardobjgrp_get_status_header { | |||
504 | struct nv_pmu_clk_clk_fll_device_boardobj_get_status { | 525 | struct nv_pmu_clk_clk_fll_device_boardobj_get_status { |
505 | struct nv_pmu_boardobj_query super; | 526 | struct nv_pmu_boardobj_query super; |
506 | u8 current_regime_id; | 527 | u8 current_regime_id; |
528 | bool b_dvco_min_reached; | ||
507 | u16 min_freq_mhz; | 529 | u16 min_freq_mhz; |
508 | struct nv_pmu_clk_lut_vf_entry lut_vf_curve[NV_UNSIGNED_ROUNDED_DIV(CTRL_CLK_LUT_NUM_ENTRIES, 2)]; | 530 | struct nv_pmu_clk_lut_vf_entry lut_vf_curve[NV_UNSIGNED_ROUNDED_DIV(CTRL_CLK_LUT_NUM_ENTRIES, 2)]; |
509 | }; | 531 | }; |