diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 42 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 1 |
9 files changed, 56 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 636d5714..7bcf5281 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -541,17 +541,12 @@ int gr_gk20a_ctx_wait_ucode(struct gk20a *g, u32 mailbox_id, | |||
541 | return 0; | 541 | return 0; |
542 | } | 542 | } |
543 | 543 | ||
544 | /* The following is a less brittle way to call gr_gk20a_submit_fecs_method(...) | 544 | int gr_gk20a_submit_fecs_method_op_locked(struct gk20a *g, |
545 | * We should replace most, if not all, fecs method calls to this instead. */ | ||
546 | int gr_gk20a_submit_fecs_method_op(struct gk20a *g, | ||
547 | struct fecs_method_op_gk20a op, | 545 | struct fecs_method_op_gk20a op, |
548 | bool sleepduringwait) | 546 | bool sleepduringwait) |
549 | { | 547 | { |
550 | struct gr_gk20a *gr = &g->gr; | ||
551 | int ret; | 548 | int ret; |
552 | 549 | ||
553 | nvgpu_mutex_acquire(&gr->fecs_mutex); | ||
554 | |||
555 | if (op.mailbox.id != 0) { | 550 | if (op.mailbox.id != 0) { |
556 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(op.mailbox.id), | 551 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(op.mailbox.id), |
557 | op.mailbox.data); | 552 | op.mailbox.data); |
@@ -579,6 +574,22 @@ int gr_gk20a_submit_fecs_method_op(struct gk20a *g, | |||
579 | op.method.data, op.method.addr); | 574 | op.method.data, op.method.addr); |
580 | } | 575 | } |
581 | 576 | ||
577 | return ret; | ||
578 | } | ||
579 | |||
580 | /* The following is a less brittle way to call gr_gk20a_submit_fecs_method(...) | ||
581 | * We should replace most, if not all, fecs method calls to this instead. */ | ||
582 | int gr_gk20a_submit_fecs_method_op(struct gk20a *g, | ||
583 | struct fecs_method_op_gk20a op, | ||
584 | bool sleepduringwait) | ||
585 | { | ||
586 | struct gr_gk20a *gr = &g->gr; | ||
587 | int ret; | ||
588 | |||
589 | nvgpu_mutex_acquire(&gr->fecs_mutex); | ||
590 | |||
591 | ret = gr_gk20a_submit_fecs_method_op_locked(g, op, sleepduringwait); | ||
592 | |||
582 | nvgpu_mutex_release(&gr->fecs_mutex); | 593 | nvgpu_mutex_release(&gr->fecs_mutex); |
583 | 594 | ||
584 | return ret; | 595 | return ret; |
@@ -2486,6 +2497,16 @@ int gr_gk20a_load_ctxsw_ucode(struct gk20a *g) | |||
2486 | return 0; | 2497 | return 0; |
2487 | } | 2498 | } |
2488 | 2499 | ||
2500 | int gr_gk20a_set_fecs_watchdog_timeout(struct gk20a *g) | ||
2501 | { | ||
2502 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0), 0xffffffff); | ||
2503 | gk20a_writel(g, gr_fecs_method_data_r(), 0x7fffffff); | ||
2504 | gk20a_writel(g, gr_fecs_method_push_r(), | ||
2505 | gr_fecs_method_push_adr_set_watchdog_timeout_f()); | ||
2506 | |||
2507 | return 0; | ||
2508 | } | ||
2509 | |||
2489 | static int gr_gk20a_wait_ctxsw_ready(struct gk20a *g) | 2510 | static int gr_gk20a_wait_ctxsw_ready(struct gk20a *g) |
2490 | { | 2511 | { |
2491 | u32 ret; | 2512 | u32 ret; |
@@ -2507,10 +2528,11 @@ static int gr_gk20a_wait_ctxsw_ready(struct gk20a *g) | |||
2507 | gr_fecs_current_ctx_valid_false_f()); | 2528 | gr_fecs_current_ctx_valid_false_f()); |
2508 | } | 2529 | } |
2509 | 2530 | ||
2510 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0), 0xffffffff); | 2531 | ret = g->ops.gr.set_fecs_watchdog_timeout(g); |
2511 | gk20a_writel(g, gr_fecs_method_data_r(), 0x7fffffff); | 2532 | if (ret) { |
2512 | gk20a_writel(g, gr_fecs_method_push_r(), | 2533 | nvgpu_err(g, "fail to set watchdog timeout"); |
2513 | gr_fecs_method_push_adr_set_watchdog_timeout_f()); | 2534 | return ret; |
2535 | } | ||
2514 | 2536 | ||
2515 | nvgpu_log_fn(g, "done"); | 2537 | nvgpu_log_fn(g, "done"); |
2516 | return 0; | 2538 | return 0; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 8ff2cfd4..08b81e86 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -702,6 +702,9 @@ int gr_gk20a_init_ctx_state(struct gk20a *g); | |||
702 | int gr_gk20a_submit_fecs_method_op(struct gk20a *g, | 702 | int gr_gk20a_submit_fecs_method_op(struct gk20a *g, |
703 | struct fecs_method_op_gk20a op, | 703 | struct fecs_method_op_gk20a op, |
704 | bool sleepduringwait); | 704 | bool sleepduringwait); |
705 | int gr_gk20a_submit_fecs_method_op_locked(struct gk20a *g, | ||
706 | struct fecs_method_op_gk20a op, | ||
707 | bool sleepduringwait); | ||
705 | int gr_gk20a_submit_fecs_sideband_method_op(struct gk20a *g, | 708 | int gr_gk20a_submit_fecs_sideband_method_op(struct gk20a *g, |
706 | struct fecs_method_op_gk20a op); | 709 | struct fecs_method_op_gk20a op); |
707 | int gr_gk20a_alloc_gr_ctx(struct gk20a *g, | 710 | int gr_gk20a_alloc_gr_ctx(struct gk20a *g, |
@@ -844,4 +847,5 @@ void gk20a_gr_destroy_ctx_buffer(struct gk20a *g, | |||
844 | int gk20a_gr_alloc_ctx_buffer(struct gk20a *g, | 847 | int gk20a_gr_alloc_ctx_buffer(struct gk20a *g, |
845 | struct gr_ctx_buffer_desc *desc, size_t size); | 848 | struct gr_ctx_buffer_desc *desc, size_t size); |
846 | void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr); | 849 | void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr); |
850 | int gr_gk20a_set_fecs_watchdog_timeout(struct gk20a *g); | ||
847 | #endif /*__GR_GK20A_H__*/ | 851 | #endif /*__GR_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index c470f520..31edf69f 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -332,6 +332,7 @@ static const struct gpu_ops gm20b_ops = { | |||
332 | .get_offset_in_gpccs_segment = | 332 | .get_offset_in_gpccs_segment = |
333 | gr_gk20a_get_offset_in_gpccs_segment, | 333 | gr_gk20a_get_offset_in_gpccs_segment, |
334 | .set_debug_mode = gm20b_gr_set_debug_mode, | 334 | .set_debug_mode = gm20b_gr_set_debug_mode, |
335 | .set_fecs_watchdog_timeout = gr_gk20a_set_fecs_watchdog_timeout, | ||
335 | }, | 336 | }, |
336 | .fb = { | 337 | .fb = { |
337 | .init_hw = gm20b_fb_init_hw, | 338 | .init_hw = gm20b_fb_init_hw, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index d3409b09..6498f8c9 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -366,6 +366,7 @@ static const struct gpu_ops gp10b_ops = { | |||
366 | .get_offset_in_gpccs_segment = | 366 | .get_offset_in_gpccs_segment = |
367 | gr_gk20a_get_offset_in_gpccs_segment, | 367 | gr_gk20a_get_offset_in_gpccs_segment, |
368 | .set_debug_mode = gm20b_gr_set_debug_mode, | 368 | .set_debug_mode = gm20b_gr_set_debug_mode, |
369 | .set_fecs_watchdog_timeout = gr_gk20a_set_fecs_watchdog_timeout, | ||
369 | }, | 370 | }, |
370 | .fb = { | 371 | .fb = { |
371 | .init_hw = gm20b_fb_init_hw, | 372 | .init_hw = gm20b_fb_init_hw, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 696316f5..3982006e 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -490,6 +490,7 @@ static const struct gpu_ops gv100_ops = { | |||
490 | .get_offset_in_gpccs_segment = | 490 | .get_offset_in_gpccs_segment = |
491 | gr_gk20a_get_offset_in_gpccs_segment, | 491 | gr_gk20a_get_offset_in_gpccs_segment, |
492 | .set_debug_mode = gm20b_gr_set_debug_mode, | 492 | .set_debug_mode = gm20b_gr_set_debug_mode, |
493 | .set_fecs_watchdog_timeout = gr_gv11b_set_fecs_watchdog_timeout, | ||
493 | }, | 494 | }, |
494 | .fb = { | 495 | .fb = { |
495 | .init_hw = gv11b_fb_init_hw, | 496 | .init_hw = gv11b_fb_init_hw, |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 5820a695..a7a804d2 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -5074,3 +5074,17 @@ fail: | |||
5074 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 5074 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
5075 | return err; | 5075 | return err; |
5076 | } | 5076 | } |
5077 | |||
5078 | int gr_gv11b_set_fecs_watchdog_timeout(struct gk20a *g) | ||
5079 | { | ||
5080 | return gr_gk20a_submit_fecs_method_op_locked(g, | ||
5081 | (struct fecs_method_op_gk20a) { | ||
5082 | .method.addr = gr_fecs_method_push_adr_set_watchdog_timeout_f(), | ||
5083 | .method.data = 0x7fffffff, | ||
5084 | .mailbox = { .id = 0, | ||
5085 | .data = ~0, .clr = ~0, .ret = NULL, | ||
5086 | .ok = gr_fecs_ctxsw_mailbox_value_pass_v(), | ||
5087 | .fail = 0, }, | ||
5088 | .cond.ok = GR_IS_UCODE_OP_EQUAL, | ||
5089 | .cond.fail = GR_IS_UCODE_OP_SKIP}, false); | ||
5090 | } | ||
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 2f765336..5d617a94 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -257,4 +257,5 @@ void gr_gv11b_set_skedcheck(struct gk20a *g, u32 data); | |||
257 | void gr_gv11b_set_go_idle_timeout(struct gk20a *g, u32 data); | 257 | void gr_gv11b_set_go_idle_timeout(struct gk20a *g, u32 data); |
258 | void gr_gv11b_set_coalesce_buffer_size(struct gk20a *g, u32 data); | 258 | void gr_gv11b_set_coalesce_buffer_size(struct gk20a *g, u32 data); |
259 | void gr_gv11b_set_tex_in_dbg(struct gk20a *g, u32 data); | 259 | void gr_gv11b_set_tex_in_dbg(struct gk20a *g, u32 data); |
260 | int gr_gv11b_set_fecs_watchdog_timeout(struct gk20a *g); | ||
260 | #endif /* NVGPU_GR_GV11B_H */ | 261 | #endif /* NVGPU_GR_GV11B_H */ |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index a2384fc8..c0f7e4e3 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -452,6 +452,7 @@ static const struct gpu_ops gv11b_ops = { | |||
452 | .get_offset_in_gpccs_segment = | 452 | .get_offset_in_gpccs_segment = |
453 | gr_gk20a_get_offset_in_gpccs_segment, | 453 | gr_gk20a_get_offset_in_gpccs_segment, |
454 | .set_debug_mode = gm20b_gr_set_debug_mode, | 454 | .set_debug_mode = gm20b_gr_set_debug_mode, |
455 | .set_fecs_watchdog_timeout = gr_gv11b_set_fecs_watchdog_timeout, | ||
455 | }, | 456 | }, |
456 | .fb = { | 457 | .fb = { |
457 | .init_hw = gv11b_fb_init_hw, | 458 | .init_hw = gv11b_fb_init_hw, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 61fe4fb5..9ec4ab6b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h | |||
@@ -531,6 +531,7 @@ struct gpu_ops { | |||
531 | void (*set_debug_mode)(struct gk20a *g, bool enable); | 531 | void (*set_debug_mode)(struct gk20a *g, bool enable); |
532 | int (*set_mmu_debug_mode)(struct gk20a *g, | 532 | int (*set_mmu_debug_mode)(struct gk20a *g, |
533 | struct channel_gk20a *ch, bool enable); | 533 | struct channel_gk20a *ch, bool enable); |
534 | int (*set_fecs_watchdog_timeout)(struct gk20a *g); | ||
534 | } gr; | 535 | } gr; |
535 | struct { | 536 | struct { |
536 | void (*init_hw)(struct gk20a *g); | 537 | void (*init_hw)(struct gk20a *g); |