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-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h82
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h52
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h14
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h206
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fb_gm20b.h146
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h256
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_flush_gm20b.h64
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h42
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h574
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h1904
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h234
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_mc_gm20b.h114
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h252
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h76
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pram_gm20b.h2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h54
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h10
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h16
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_proj_gm20b.h54
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h384
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ram_gm20b.h200
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_therm_gm20b.h148
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h28
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_top_gm20b.h88
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_trim_gm20b.h222
25 files changed, 2611 insertions, 2611 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h
index 2f22c2f9..15cddae2 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_bus_gm20b.h
@@ -58,166 +58,166 @@
58 58
59static inline u32 bus_bar0_window_r(void) 59static inline u32 bus_bar0_window_r(void)
60{ 60{
61 return 0x00001700; 61 return 0x00001700U;
62} 62}
63static inline u32 bus_bar0_window_base_f(u32 v) 63static inline u32 bus_bar0_window_base_f(u32 v)
64{ 64{
65 return (v & 0xffffff) << 0; 65 return (v & 0xffffffU) << 0U;
66} 66}
67static inline u32 bus_bar0_window_target_vid_mem_f(void) 67static inline u32 bus_bar0_window_target_vid_mem_f(void)
68{ 68{
69 return 0x0; 69 return 0x0U;
70} 70}
71static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) 71static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
72{ 72{
73 return 0x2000000; 73 return 0x2000000U;
74} 74}
75static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) 75static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
76{ 76{
77 return 0x3000000; 77 return 0x3000000U;
78} 78}
79static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) 79static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
80{ 80{
81 return 0x00000010; 81 return 0x00000010U;
82} 82}
83static inline u32 bus_bar1_block_r(void) 83static inline u32 bus_bar1_block_r(void)
84{ 84{
85 return 0x00001704; 85 return 0x00001704U;
86} 86}
87static inline u32 bus_bar1_block_ptr_f(u32 v) 87static inline u32 bus_bar1_block_ptr_f(u32 v)
88{ 88{
89 return (v & 0xfffffff) << 0; 89 return (v & 0xfffffffU) << 0U;
90} 90}
91static inline u32 bus_bar1_block_target_vid_mem_f(void) 91static inline u32 bus_bar1_block_target_vid_mem_f(void)
92{ 92{
93 return 0x0; 93 return 0x0U;
94} 94}
95static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) 95static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
96{ 96{
97 return 0x20000000; 97 return 0x20000000U;
98} 98}
99static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) 99static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
100{ 100{
101 return 0x30000000; 101 return 0x30000000U;
102} 102}
103static inline u32 bus_bar1_block_mode_virtual_f(void) 103static inline u32 bus_bar1_block_mode_virtual_f(void)
104{ 104{
105 return 0x80000000; 105 return 0x80000000U;
106} 106}
107static inline u32 bus_bar2_block_r(void) 107static inline u32 bus_bar2_block_r(void)
108{ 108{
109 return 0x00001714; 109 return 0x00001714U;
110} 110}
111static inline u32 bus_bar2_block_ptr_f(u32 v) 111static inline u32 bus_bar2_block_ptr_f(u32 v)
112{ 112{
113 return (v & 0xfffffff) << 0; 113 return (v & 0xfffffffU) << 0U;
114} 114}
115static inline u32 bus_bar2_block_target_vid_mem_f(void) 115static inline u32 bus_bar2_block_target_vid_mem_f(void)
116{ 116{
117 return 0x0; 117 return 0x0U;
118} 118}
119static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) 119static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
120{ 120{
121 return 0x20000000; 121 return 0x20000000U;
122} 122}
123static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) 123static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
124{ 124{
125 return 0x30000000; 125 return 0x30000000U;
126} 126}
127static inline u32 bus_bar2_block_mode_virtual_f(void) 127static inline u32 bus_bar2_block_mode_virtual_f(void)
128{ 128{
129 return 0x80000000; 129 return 0x80000000U;
130} 130}
131static inline u32 bus_bar1_block_ptr_shift_v(void) 131static inline u32 bus_bar1_block_ptr_shift_v(void)
132{ 132{
133 return 0x0000000c; 133 return 0x0000000cU;
134} 134}
135static inline u32 bus_bar2_block_ptr_shift_v(void) 135static inline u32 bus_bar2_block_ptr_shift_v(void)
136{ 136{
137 return 0x0000000c; 137 return 0x0000000cU;
138} 138}
139static inline u32 bus_bind_status_r(void) 139static inline u32 bus_bind_status_r(void)
140{ 140{
141 return 0x00001710; 141 return 0x00001710U;
142} 142}
143static inline u32 bus_bind_status_bar1_pending_v(u32 r) 143static inline u32 bus_bind_status_bar1_pending_v(u32 r)
144{ 144{
145 return (r >> 0) & 0x1; 145 return (r >> 0U) & 0x1U;
146} 146}
147static inline u32 bus_bind_status_bar1_pending_empty_f(void) 147static inline u32 bus_bind_status_bar1_pending_empty_f(void)
148{ 148{
149 return 0x0; 149 return 0x0U;
150} 150}
151static inline u32 bus_bind_status_bar1_pending_busy_f(void) 151static inline u32 bus_bind_status_bar1_pending_busy_f(void)
152{ 152{
153 return 0x1; 153 return 0x1U;
154} 154}
155static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) 155static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
156{ 156{
157 return (r >> 1) & 0x1; 157 return (r >> 1U) & 0x1U;
158} 158}
159static inline u32 bus_bind_status_bar1_outstanding_false_f(void) 159static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
160{ 160{
161 return 0x0; 161 return 0x0U;
162} 162}
163static inline u32 bus_bind_status_bar1_outstanding_true_f(void) 163static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
164{ 164{
165 return 0x2; 165 return 0x2U;
166} 166}
167static inline u32 bus_bind_status_bar2_pending_v(u32 r) 167static inline u32 bus_bind_status_bar2_pending_v(u32 r)
168{ 168{
169 return (r >> 2) & 0x1; 169 return (r >> 2U) & 0x1U;
170} 170}
171static inline u32 bus_bind_status_bar2_pending_empty_f(void) 171static inline u32 bus_bind_status_bar2_pending_empty_f(void)
172{ 172{
173 return 0x0; 173 return 0x0U;
174} 174}
175static inline u32 bus_bind_status_bar2_pending_busy_f(void) 175static inline u32 bus_bind_status_bar2_pending_busy_f(void)
176{ 176{
177 return 0x4; 177 return 0x4U;
178} 178}
179static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) 179static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
180{ 180{
181 return (r >> 3) & 0x1; 181 return (r >> 3U) & 0x1U;
182} 182}
183static inline u32 bus_bind_status_bar2_outstanding_false_f(void) 183static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
184{ 184{
185 return 0x0; 185 return 0x0U;
186} 186}
187static inline u32 bus_bind_status_bar2_outstanding_true_f(void) 187static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
188{ 188{
189 return 0x8; 189 return 0x8U;
190} 190}
191static inline u32 bus_intr_0_r(void) 191static inline u32 bus_intr_0_r(void)
192{ 192{
193 return 0x00001100; 193 return 0x00001100U;
194} 194}
195static inline u32 bus_intr_0_pri_squash_m(void) 195static inline u32 bus_intr_0_pri_squash_m(void)
196{ 196{
197 return 0x1 << 1; 197 return 0x1U << 1U;
198} 198}
199static inline u32 bus_intr_0_pri_fecserr_m(void) 199static inline u32 bus_intr_0_pri_fecserr_m(void)
200{ 200{
201 return 0x1 << 2; 201 return 0x1U << 2U;
202} 202}
203static inline u32 bus_intr_0_pri_timeout_m(void) 203static inline u32 bus_intr_0_pri_timeout_m(void)
204{ 204{
205 return 0x1 << 3; 205 return 0x1U << 3U;
206} 206}
207static inline u32 bus_intr_en_0_r(void) 207static inline u32 bus_intr_en_0_r(void)
208{ 208{
209 return 0x00001140; 209 return 0x00001140U;
210} 210}
211static inline u32 bus_intr_en_0_pri_squash_m(void) 211static inline u32 bus_intr_en_0_pri_squash_m(void)
212{ 212{
213 return 0x1 << 1; 213 return 0x1U << 1U;
214} 214}
215static inline u32 bus_intr_en_0_pri_fecserr_m(void) 215static inline u32 bus_intr_en_0_pri_fecserr_m(void)
216{ 216{
217 return 0x1 << 2; 217 return 0x1U << 2U;
218} 218}
219static inline u32 bus_intr_en_0_pri_timeout_m(void) 219static inline u32 bus_intr_en_0_pri_timeout_m(void)
220{ 220{
221 return 0x1 << 3; 221 return 0x1U << 3U;
222} 222}
223#endif 223#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h
index 97a031a0..adfce723 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ccsr_gm20b.h
@@ -58,106 +58,106 @@
58 58
59static inline u32 ccsr_channel_inst_r(u32 i) 59static inline u32 ccsr_channel_inst_r(u32 i)
60{ 60{
61 return 0x00800000 + i*8; 61 return 0x00800000U + i*8U;
62} 62}
63static inline u32 ccsr_channel_inst__size_1_v(void) 63static inline u32 ccsr_channel_inst__size_1_v(void)
64{ 64{
65 return 0x00000200; 65 return 0x00000200U;
66} 66}
67static inline u32 ccsr_channel_inst_ptr_f(u32 v) 67static inline u32 ccsr_channel_inst_ptr_f(u32 v)
68{ 68{
69 return (v & 0xfffffff) << 0; 69 return (v & 0xfffffffU) << 0U;
70} 70}
71static inline u32 ccsr_channel_inst_target_vid_mem_f(void) 71static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
72{ 72{
73 return 0x0; 73 return 0x0U;
74} 74}
75static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) 75static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
76{ 76{
77 return 0x20000000; 77 return 0x20000000U;
78} 78}
79static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) 79static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
80{ 80{
81 return 0x30000000; 81 return 0x30000000U;
82} 82}
83static inline u32 ccsr_channel_inst_bind_false_f(void) 83static inline u32 ccsr_channel_inst_bind_false_f(void)
84{ 84{
85 return 0x0; 85 return 0x0U;
86} 86}
87static inline u32 ccsr_channel_inst_bind_true_f(void) 87static inline u32 ccsr_channel_inst_bind_true_f(void)
88{ 88{
89 return 0x80000000; 89 return 0x80000000U;
90} 90}
91static inline u32 ccsr_channel_r(u32 i) 91static inline u32 ccsr_channel_r(u32 i)
92{ 92{
93 return 0x00800004 + i*8; 93 return 0x00800004U + i*8U;
94} 94}
95static inline u32 ccsr_channel__size_1_v(void) 95static inline u32 ccsr_channel__size_1_v(void)
96{ 96{
97 return 0x00000200; 97 return 0x00000200U;
98} 98}
99static inline u32 ccsr_channel_enable_v(u32 r) 99static inline u32 ccsr_channel_enable_v(u32 r)
100{ 100{
101 return (r >> 0) & 0x1; 101 return (r >> 0U) & 0x1U;
102} 102}
103static inline u32 ccsr_channel_enable_set_f(u32 v) 103static inline u32 ccsr_channel_enable_set_f(u32 v)
104{ 104{
105 return (v & 0x1) << 10; 105 return (v & 0x1U) << 10U;
106} 106}
107static inline u32 ccsr_channel_enable_set_true_f(void) 107static inline u32 ccsr_channel_enable_set_true_f(void)
108{ 108{
109 return 0x400; 109 return 0x400U;
110} 110}
111static inline u32 ccsr_channel_enable_clr_true_f(void) 111static inline u32 ccsr_channel_enable_clr_true_f(void)
112{ 112{
113 return 0x800; 113 return 0x800U;
114} 114}
115static inline u32 ccsr_channel_status_v(u32 r) 115static inline u32 ccsr_channel_status_v(u32 r)
116{ 116{
117 return (r >> 24) & 0xf; 117 return (r >> 24U) & 0xfU;
118} 118}
119static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) 119static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
120{ 120{
121 return 0x00000002; 121 return 0x00000002U;
122} 122}
123static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) 123static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
124{ 124{
125 return 0x00000004; 125 return 0x00000004U;
126} 126}
127static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) 127static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
128{ 128{
129 return 0x0000000a; 129 return 0x0000000aU;
130} 130}
131static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) 131static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
132{ 132{
133 return 0x0000000b; 133 return 0x0000000bU;
134} 134}
135static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) 135static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
136{ 136{
137 return 0x0000000c; 137 return 0x0000000cU;
138} 138}
139static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) 139static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
140{ 140{
141 return 0x0000000d; 141 return 0x0000000dU;
142} 142}
143static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) 143static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
144{ 144{
145 return 0x0000000e; 145 return 0x0000000eU;
146} 146}
147static inline u32 ccsr_channel_next_v(u32 r) 147static inline u32 ccsr_channel_next_v(u32 r)
148{ 148{
149 return (r >> 1) & 0x1; 149 return (r >> 1U) & 0x1U;
150} 150}
151static inline u32 ccsr_channel_next_true_v(void) 151static inline u32 ccsr_channel_next_true_v(void)
152{ 152{
153 return 0x00000001; 153 return 0x00000001U;
154} 154}
155static inline u32 ccsr_channel_force_ctx_reload_true_f(void) 155static inline u32 ccsr_channel_force_ctx_reload_true_f(void)
156{ 156{
157 return 0x100; 157 return 0x100U;
158} 158}
159static inline u32 ccsr_channel_busy_v(u32 r) 159static inline u32 ccsr_channel_busy_v(u32 r)
160{ 160{
161 return (r >> 28) & 0x1; 161 return (r >> 28U) & 0x1U;
162} 162}
163#endif 163#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h
index 5ba42d68..fb741a77 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ce2_gm20b.h
@@ -58,30 +58,30 @@
58 58
59static inline u32 ce2_intr_status_r(void) 59static inline u32 ce2_intr_status_r(void)
60{ 60{
61 return 0x00106908; 61 return 0x00106908U;
62} 62}
63static inline u32 ce2_intr_status_blockpipe_pending_f(void) 63static inline u32 ce2_intr_status_blockpipe_pending_f(void)
64{ 64{
65 return 0x1; 65 return 0x1U;
66} 66}
67static inline u32 ce2_intr_status_blockpipe_reset_f(void) 67static inline u32 ce2_intr_status_blockpipe_reset_f(void)
68{ 68{
69 return 0x1; 69 return 0x1U;
70} 70}
71static inline u32 ce2_intr_status_nonblockpipe_pending_f(void) 71static inline u32 ce2_intr_status_nonblockpipe_pending_f(void)
72{ 72{
73 return 0x2; 73 return 0x2U;
74} 74}
75static inline u32 ce2_intr_status_nonblockpipe_reset_f(void) 75static inline u32 ce2_intr_status_nonblockpipe_reset_f(void)
76{ 76{
77 return 0x2; 77 return 0x2U;
78} 78}
79static inline u32 ce2_intr_status_launcherr_pending_f(void) 79static inline u32 ce2_intr_status_launcherr_pending_f(void)
80{ 80{
81 return 0x4; 81 return 0x4U;
82} 82}
83static inline u32 ce2_intr_status_launcherr_reset_f(void) 83static inline u32 ce2_intr_status_launcherr_reset_f(void)
84{ 84{
85 return 0x4; 85 return 0x4U;
86} 86}
87#endif 87#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h
index 92e81915..b60dfc36 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h
@@ -58,414 +58,414 @@
58 58
59static inline u32 ctxsw_prog_fecs_header_v(void) 59static inline u32 ctxsw_prog_fecs_header_v(void)
60{ 60{
61 return 0x00000100; 61 return 0x00000100U;
62} 62}
63static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) 63static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
64{ 64{
65 return 0x00000008; 65 return 0x00000008U;
66} 66}
67static inline u32 ctxsw_prog_main_image_ctl_o(void) 67static inline u32 ctxsw_prog_main_image_ctl_o(void)
68{ 68{
69 return 0x0000000c; 69 return 0x0000000cU;
70} 70}
71static inline u32 ctxsw_prog_main_image_ctl_cde_enabled_f(void) 71static inline u32 ctxsw_prog_main_image_ctl_cde_enabled_f(void)
72{ 72{
73 return 0x400; 73 return 0x400U;
74} 74}
75static inline u32 ctxsw_prog_main_image_ctl_cde_disabled_f(void) 75static inline u32 ctxsw_prog_main_image_ctl_cde_disabled_f(void)
76{ 76{
77 return 0x0; 77 return 0x0U;
78} 78}
79static inline u32 ctxsw_prog_main_image_patch_count_o(void) 79static inline u32 ctxsw_prog_main_image_patch_count_o(void)
80{ 80{
81 return 0x00000010; 81 return 0x00000010U;
82} 82}
83static inline u32 ctxsw_prog_main_image_context_id_o(void) 83static inline u32 ctxsw_prog_main_image_context_id_o(void)
84{ 84{
85 return 0x000000f0; 85 return 0x000000f0U;
86} 86}
87static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) 87static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
88{ 88{
89 return 0x00000014; 89 return 0x00000014U;
90} 90}
91static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) 91static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
92{ 92{
93 return 0x00000018; 93 return 0x00000018U;
94} 94}
95static inline u32 ctxsw_prog_main_image_zcull_o(void) 95static inline u32 ctxsw_prog_main_image_zcull_o(void)
96{ 96{
97 return 0x0000001c; 97 return 0x0000001cU;
98} 98}
99static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) 99static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
100{ 100{
101 return 0x00000001; 101 return 0x00000001U;
102} 102}
103static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) 103static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
104{ 104{
105 return 0x00000002; 105 return 0x00000002U;
106} 106}
107static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) 107static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
108{ 108{
109 return 0x00000020; 109 return 0x00000020U;
110} 110}
111static inline u32 ctxsw_prog_main_image_pm_o(void) 111static inline u32 ctxsw_prog_main_image_pm_o(void)
112{ 112{
113 return 0x00000028; 113 return 0x00000028U;
114} 114}
115static inline u32 ctxsw_prog_main_image_pm_mode_m(void) 115static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
116{ 116{
117 return 0x7 << 0; 117 return 0x7U << 0U;
118} 118}
119static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) 119static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
120{ 120{
121 return 0x0; 121 return 0x0U;
122} 122}
123static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) 123static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
124{ 124{
125 return 0x7 << 3; 125 return 0x7U << 3U;
126} 126}
127static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) 127static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
128{ 128{
129 return 0x8; 129 return 0x8U;
130} 130}
131static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) 131static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
132{ 132{
133 return 0x0; 133 return 0x0U;
134} 134}
135static inline u32 ctxsw_prog_main_image_pm_pc_sampling_f(u32 v) 135static inline u32 ctxsw_prog_main_image_pm_pc_sampling_f(u32 v)
136{ 136{
137 return (v & 0x1) << 6; 137 return (v & 0x1U) << 6U;
138} 138}
139static inline u32 ctxsw_prog_main_image_pm_pc_sampling_m(void) 139static inline u32 ctxsw_prog_main_image_pm_pc_sampling_m(void)
140{ 140{
141 return 0x1 << 6; 141 return 0x1U << 6U;
142} 142}
143static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) 143static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
144{ 144{
145 return 0x0000002c; 145 return 0x0000002cU;
146} 146}
147static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) 147static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
148{ 148{
149 return 0x000000f4; 149 return 0x000000f4U;
150} 150}
151static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) 151static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
152{ 152{
153 return 0x000000f8; 153 return 0x000000f8U;
154} 154}
155static inline u32 ctxsw_prog_main_image_magic_value_o(void) 155static inline u32 ctxsw_prog_main_image_magic_value_o(void)
156{ 156{
157 return 0x000000fc; 157 return 0x000000fcU;
158} 158}
159static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) 159static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
160{ 160{
161 return 0x600dc0de; 161 return 0x600dc0deU;
162} 162}
163static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) 163static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
164{ 164{
165 return 0x0000000c; 165 return 0x0000000cU;
166} 166}
167static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) 167static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
168{ 168{
169 return (r >> 0) & 0xffff; 169 return (r >> 0U) & 0xffffU;
170} 170}
171static inline u32 ctxsw_prog_local_image_ppc_info_o(void) 171static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
172{ 172{
173 return 0x000000f4; 173 return 0x000000f4U;
174} 174}
175static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) 175static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
176{ 176{
177 return (r >> 0) & 0xffff; 177 return (r >> 0U) & 0xffffU;
178} 178}
179static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) 179static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
180{ 180{
181 return (r >> 16) & 0xffff; 181 return (r >> 16U) & 0xffffU;
182} 182}
183static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) 183static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
184{ 184{
185 return 0x000000f8; 185 return 0x000000f8U;
186} 186}
187static inline u32 ctxsw_prog_local_magic_value_o(void) 187static inline u32 ctxsw_prog_local_magic_value_o(void)
188{ 188{
189 return 0x000000fc; 189 return 0x000000fcU;
190} 190}
191static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) 191static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
192{ 192{
193 return 0xad0becab; 193 return 0xad0becabU;
194} 194}
195static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) 195static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
196{ 196{
197 return 0x000000ec; 197 return 0x000000ecU;
198} 198}
199static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) 199static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
200{ 200{
201 return (r >> 0) & 0xffff; 201 return (r >> 0U) & 0xffffU;
202} 202}
203static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) 203static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
204{ 204{
205 return (r >> 16) & 0xff; 205 return (r >> 16U) & 0xffU;
206} 206}
207static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) 207static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
208{ 208{
209 return 0x00000100; 209 return 0x00000100U;
210} 210}
211static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) 211static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
212{ 212{
213 return 0x00000004; 213 return 0x00000004U;
214} 214}
215static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) 215static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
216{ 216{
217 return 0x00000000; 217 return 0x00000000U;
218} 218}
219static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) 219static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
220{ 220{
221 return 0x00000002; 221 return 0x00000002U;
222} 222}
223static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) 223static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
224{ 224{
225 return 0x000000a0; 225 return 0x000000a0U;
226} 226}
227static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) 227static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
228{ 228{
229 return 2; 229 return 2U;
230} 230}
231static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) 231static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
232{ 232{
233 return (v & 0x3) << 0; 233 return (v & 0x3U) << 0U;
234} 234}
235static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) 235static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
236{ 236{
237 return 0x3 << 0; 237 return 0x3U << 0U;
238} 238}
239static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) 239static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
240{ 240{
241 return (r >> 0) & 0x3; 241 return (r >> 0U) & 0x3U;
242} 242}
243static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) 243static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
244{ 244{
245 return 0x0; 245 return 0x0U;
246} 246}
247static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) 247static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
248{ 248{
249 return 0x2; 249 return 0x2U;
250} 250}
251static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) 251static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
252{ 252{
253 return 0x000000a4; 253 return 0x000000a4U;
254} 254}
255static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) 255static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
256{ 256{
257 return 0x000000a8; 257 return 0x000000a8U;
258} 258}
259static inline u32 ctxsw_prog_main_image_misc_options_o(void) 259static inline u32 ctxsw_prog_main_image_misc_options_o(void)
260{ 260{
261 return 0x0000003c; 261 return 0x0000003cU;
262} 262}
263static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) 263static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
264{ 264{
265 return 0x1 << 3; 265 return 0x1U << 3U;
266} 266}
267static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) 267static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
268{ 268{
269 return 0x0; 269 return 0x0U;
270} 270}
271static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void) 271static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void)
272{ 272{
273 return 0x000000ac; 273 return 0x000000acU;
274} 274}
275static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v) 275static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v)
276{ 276{
277 return (v & 0xffff) << 0; 277 return (v & 0xffffU) << 0U;
278} 278}
279static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void) 279static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void)
280{ 280{
281 return 0x000000b0; 281 return 0x000000b0U;
282} 282}
283static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void) 283static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void)
284{ 284{
285 return 0xfffffff << 0; 285 return 0xfffffffU << 0U;
286} 286}
287static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void) 287static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void)
288{ 288{
289 return 0x3 << 28; 289 return 0x3U << 28U;
290} 290}
291static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void) 291static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void)
292{ 292{
293 return 0x0; 293 return 0x0U;
294} 294}
295static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void) 295static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void)
296{ 296{
297 return 0x20000000; 297 return 0x20000000U;
298} 298}
299static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void) 299static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void)
300{ 300{
301 return 0x30000000; 301 return 0x30000000U;
302} 302}
303static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void) 303static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void)
304{ 304{
305 return 0x000000b4; 305 return 0x000000b4U;
306} 306}
307static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v) 307static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v)
308{ 308{
309 return (v & 0xffffffff) << 0; 309 return (v & 0xffffffffU) << 0U;
310} 310}
311static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void) 311static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void)
312{ 312{
313 return 0x00000080; 313 return 0x00000080U;
314} 314}
315static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void) 315static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void)
316{ 316{
317 return 0x00000020; 317 return 0x00000020U;
318} 318}
319static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void) 319static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void)
320{ 320{
321 return 0x00000000; 321 return 0x00000000U;
322} 322}
323static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void) 323static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void)
324{ 324{
325 return 0x00000000; 325 return 0x00000000U;
326} 326}
327static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void) 327static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void)
328{ 328{
329 return 0x00000004; 329 return 0x00000004U;
330} 330}
331static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void) 331static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void)
332{ 332{
333 return 0x600dbeef; 333 return 0x600dbeefU;
334} 334}
335static inline u32 ctxsw_prog_record_timestamp_context_id_o(void) 335static inline u32 ctxsw_prog_record_timestamp_context_id_o(void)
336{ 336{
337 return 0x00000008; 337 return 0x00000008U;
338} 338}
339static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void) 339static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void)
340{ 340{
341 return 0x0000000c; 341 return 0x0000000cU;
342} 342}
343static inline u32 ctxsw_prog_record_timestamp_new_context_id_o(void) 343static inline u32 ctxsw_prog_record_timestamp_new_context_id_o(void)
344{ 344{
345 return 0x00000010; 345 return 0x00000010U;
346} 346}
347static inline u32 ctxsw_prog_record_timestamp_new_context_ptr_o(void) 347static inline u32 ctxsw_prog_record_timestamp_new_context_ptr_o(void)
348{ 348{
349 return 0x00000014; 349 return 0x00000014U;
350} 350}
351static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void) 351static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void)
352{ 352{
353 return 0x00000018; 353 return 0x00000018U;
354} 354}
355static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void) 355static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void)
356{ 356{
357 return 0x0000001c; 357 return 0x0000001cU;
358} 358}
359static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v) 359static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v)
360{ 360{
361 return (v & 0xffffff) << 0; 361 return (v & 0xffffffU) << 0U;
362} 362}
363static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r) 363static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r)
364{ 364{
365 return (r >> 0) & 0xffffff; 365 return (r >> 0U) & 0xffffffU;
366} 366}
367static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v) 367static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v)
368{ 368{
369 return (v & 0xff) << 24; 369 return (v & 0xffU) << 24U;
370} 370}
371static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void) 371static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void)
372{ 372{
373 return 0xff << 24; 373 return 0xffU << 24U;
374} 374}
375static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r) 375static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r)
376{ 376{
377 return (r >> 24) & 0xff; 377 return (r >> 24U) & 0xffU;
378} 378}
379static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void) 379static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void)
380{ 380{
381 return 0x00000001; 381 return 0x00000001U;
382} 382}
383static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void) 383static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void)
384{ 384{
385 return 0x1000000; 385 return 0x1000000U;
386} 386}
387static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void) 387static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void)
388{ 388{
389 return 0x00000002; 389 return 0x00000002U;
390} 390}
391static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void) 391static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void)
392{ 392{
393 return 0x2000000; 393 return 0x2000000U;
394} 394}
395static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void) 395static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void)
396{ 396{
397 return 0x0000000a; 397 return 0x0000000aU;
398} 398}
399static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void) 399static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void)
400{ 400{
401 return 0xa000000; 401 return 0xa000000U;
402} 402}
403static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void) 403static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void)
404{ 404{
405 return 0x0000000b; 405 return 0x0000000bU;
406} 406}
407static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void) 407static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void)
408{ 408{
409 return 0xb000000; 409 return 0xb000000U;
410} 410}
411static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void) 411static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void)
412{ 412{
413 return 0x0000000c; 413 return 0x0000000cU;
414} 414}
415static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void) 415static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void)
416{ 416{
417 return 0xc000000; 417 return 0xc000000U;
418} 418}
419static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void) 419static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void)
420{ 420{
421 return 0x0000000d; 421 return 0x0000000dU;
422} 422}
423static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void) 423static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void)
424{ 424{
425 return 0xd000000; 425 return 0xd000000U;
426} 426}
427static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void) 427static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void)
428{ 428{
429 return 0x00000003; 429 return 0x00000003U;
430} 430}
431static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void) 431static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void)
432{ 432{
433 return 0x3000000; 433 return 0x3000000U;
434} 434}
435static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void) 435static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void)
436{ 436{
437 return 0x00000004; 437 return 0x00000004U;
438} 438}
439static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void) 439static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void)
440{ 440{
441 return 0x4000000; 441 return 0x4000000U;
442} 442}
443static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void) 443static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void)
444{ 444{
445 return 0x00000005; 445 return 0x00000005U;
446} 446}
447static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void) 447static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void)
448{ 448{
449 return 0x5000000; 449 return 0x5000000U;
450} 450}
451static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void) 451static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void)
452{ 452{
453 return 0x000000ff; 453 return 0x000000ffU;
454} 454}
455static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void) 455static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void)
456{ 456{
457 return 0xff000000; 457 return 0xff000000U;
458} 458}
459static inline u32 ctxsw_prog_main_image_preemption_options_o(void) 459static inline u32 ctxsw_prog_main_image_preemption_options_o(void)
460{ 460{
461 return 0x00000060; 461 return 0x00000060U;
462} 462}
463static inline u32 ctxsw_prog_main_image_preemption_options_control_f(u32 v) 463static inline u32 ctxsw_prog_main_image_preemption_options_control_f(u32 v)
464{ 464{
465 return (v & 0x3) << 0; 465 return (v & 0x3U) << 0U;
466} 466}
467static inline u32 ctxsw_prog_main_image_preemption_options_control_cta_enabled_f(void) 467static inline u32 ctxsw_prog_main_image_preemption_options_control_cta_enabled_f(void)
468{ 468{
469 return 0x1; 469 return 0x1U;
470} 470}
471#endif 471#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fb_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fb_gm20b.h
index d80dc59d..531d0400 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fb_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fb_gm20b.h
@@ -58,294 +58,294 @@
58 58
59static inline u32 fb_fbhub_num_active_ltcs_r(void) 59static inline u32 fb_fbhub_num_active_ltcs_r(void)
60{ 60{
61 return 0x00100800; 61 return 0x00100800U;
62} 62}
63static inline u32 fb_mmu_ctrl_r(void) 63static inline u32 fb_mmu_ctrl_r(void)
64{ 64{
65 return 0x00100c80; 65 return 0x00100c80U;
66} 66}
67static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) 67static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
68{ 68{
69 return (v & 0x1) << 0; 69 return (v & 0x1U) << 0U;
70} 70}
71static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) 71static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
72{ 72{
73 return 0x0; 73 return 0x0U;
74} 74}
75static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) 75static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
76{ 76{
77 return 0x1; 77 return 0x1U;
78} 78}
79static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) 79static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
80{ 80{
81 return (r >> 15) & 0x1; 81 return (r >> 15U) & 0x1U;
82} 82}
83static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) 83static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
84{ 84{
85 return 0x0; 85 return 0x0U;
86} 86}
87static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) 87static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
88{ 88{
89 return (r >> 16) & 0xff; 89 return (r >> 16U) & 0xffU;
90} 90}
91static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) 91static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
92{ 92{
93 return (r >> 11) & 0x1; 93 return (r >> 11U) & 0x1U;
94} 94}
95static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) 95static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
96{ 96{
97 return 0x800; 97 return 0x800U;
98} 98}
99static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) 99static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
100{ 100{
101 return 0x0; 101 return 0x0U;
102} 102}
103static inline u32 fb_mmu_ctrl_use_full_comp_tag_line_v(u32 r) 103static inline u32 fb_mmu_ctrl_use_full_comp_tag_line_v(u32 r)
104{ 104{
105 return (r >> 12) & 0x1; 105 return (r >> 12U) & 0x1U;
106} 106}
107static inline u32 fb_mmu_ctrl_use_full_comp_tag_line_true_f(void) 107static inline u32 fb_mmu_ctrl_use_full_comp_tag_line_true_f(void)
108{ 108{
109 return 0x1000; 109 return 0x1000U;
110} 110}
111static inline u32 fb_priv_mmu_phy_secure_r(void) 111static inline u32 fb_priv_mmu_phy_secure_r(void)
112{ 112{
113 return 0x00100ce4; 113 return 0x00100ce4U;
114} 114}
115static inline u32 fb_mmu_invalidate_pdb_r(void) 115static inline u32 fb_mmu_invalidate_pdb_r(void)
116{ 116{
117 return 0x00100cb8; 117 return 0x00100cb8U;
118} 118}
119static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) 119static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
120{ 120{
121 return 0x0; 121 return 0x0U;
122} 122}
123static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) 123static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
124{ 124{
125 return 0x2; 125 return 0x2U;
126} 126}
127static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) 127static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
128{ 128{
129 return (v & 0xfffffff) << 4; 129 return (v & 0xfffffffU) << 4U;
130} 130}
131static inline u32 fb_mmu_invalidate_r(void) 131static inline u32 fb_mmu_invalidate_r(void)
132{ 132{
133 return 0x00100cbc; 133 return 0x00100cbcU;
134} 134}
135static inline u32 fb_mmu_invalidate_all_va_true_f(void) 135static inline u32 fb_mmu_invalidate_all_va_true_f(void)
136{ 136{
137 return 0x1; 137 return 0x1U;
138} 138}
139static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) 139static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
140{ 140{
141 return 0x2; 141 return 0x2U;
142} 142}
143static inline u32 fb_mmu_invalidate_trigger_s(void) 143static inline u32 fb_mmu_invalidate_trigger_s(void)
144{ 144{
145 return 1; 145 return 1U;
146} 146}
147static inline u32 fb_mmu_invalidate_trigger_f(u32 v) 147static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
148{ 148{
149 return (v & 0x1) << 31; 149 return (v & 0x1U) << 31U;
150} 150}
151static inline u32 fb_mmu_invalidate_trigger_m(void) 151static inline u32 fb_mmu_invalidate_trigger_m(void)
152{ 152{
153 return 0x1 << 31; 153 return 0x1U << 31U;
154} 154}
155static inline u32 fb_mmu_invalidate_trigger_v(u32 r) 155static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
156{ 156{
157 return (r >> 31) & 0x1; 157 return (r >> 31U) & 0x1U;
158} 158}
159static inline u32 fb_mmu_invalidate_trigger_true_f(void) 159static inline u32 fb_mmu_invalidate_trigger_true_f(void)
160{ 160{
161 return 0x80000000; 161 return 0x80000000U;
162} 162}
163static inline u32 fb_mmu_debug_wr_r(void) 163static inline u32 fb_mmu_debug_wr_r(void)
164{ 164{
165 return 0x00100cc8; 165 return 0x00100cc8U;
166} 166}
167static inline u32 fb_mmu_debug_wr_aperture_s(void) 167static inline u32 fb_mmu_debug_wr_aperture_s(void)
168{ 168{
169 return 2; 169 return 2U;
170} 170}
171static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) 171static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
172{ 172{
173 return (v & 0x3) << 0; 173 return (v & 0x3U) << 0U;
174} 174}
175static inline u32 fb_mmu_debug_wr_aperture_m(void) 175static inline u32 fb_mmu_debug_wr_aperture_m(void)
176{ 176{
177 return 0x3 << 0; 177 return 0x3U << 0U;
178} 178}
179static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) 179static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
180{ 180{
181 return (r >> 0) & 0x3; 181 return (r >> 0U) & 0x3U;
182} 182}
183static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) 183static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
184{ 184{
185 return 0x0; 185 return 0x0U;
186} 186}
187static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) 187static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
188{ 188{
189 return 0x2; 189 return 0x2U;
190} 190}
191static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) 191static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
192{ 192{
193 return 0x3; 193 return 0x3U;
194} 194}
195static inline u32 fb_mmu_debug_wr_vol_false_f(void) 195static inline u32 fb_mmu_debug_wr_vol_false_f(void)
196{ 196{
197 return 0x0; 197 return 0x0U;
198} 198}
199static inline u32 fb_mmu_debug_wr_vol_true_v(void) 199static inline u32 fb_mmu_debug_wr_vol_true_v(void)
200{ 200{
201 return 0x00000001; 201 return 0x00000001U;
202} 202}
203static inline u32 fb_mmu_debug_wr_vol_true_f(void) 203static inline u32 fb_mmu_debug_wr_vol_true_f(void)
204{ 204{
205 return 0x4; 205 return 0x4U;
206} 206}
207static inline u32 fb_mmu_debug_wr_addr_f(u32 v) 207static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
208{ 208{
209 return (v & 0xfffffff) << 4; 209 return (v & 0xfffffffU) << 4U;
210} 210}
211static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) 211static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
212{ 212{
213 return 0x0000000c; 213 return 0x0000000cU;
214} 214}
215static inline u32 fb_mmu_debug_rd_r(void) 215static inline u32 fb_mmu_debug_rd_r(void)
216{ 216{
217 return 0x00100ccc; 217 return 0x00100cccU;
218} 218}
219static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) 219static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
220{ 220{
221 return 0x0; 221 return 0x0U;
222} 222}
223static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) 223static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
224{ 224{
225 return 0x2; 225 return 0x2U;
226} 226}
227static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) 227static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
228{ 228{
229 return 0x3; 229 return 0x3U;
230} 230}
231static inline u32 fb_mmu_debug_rd_vol_false_f(void) 231static inline u32 fb_mmu_debug_rd_vol_false_f(void)
232{ 232{
233 return 0x0; 233 return 0x0U;
234} 234}
235static inline u32 fb_mmu_debug_rd_addr_f(u32 v) 235static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
236{ 236{
237 return (v & 0xfffffff) << 4; 237 return (v & 0xfffffffU) << 4U;
238} 238}
239static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) 239static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
240{ 240{
241 return 0x0000000c; 241 return 0x0000000cU;
242} 242}
243static inline u32 fb_mmu_debug_ctrl_r(void) 243static inline u32 fb_mmu_debug_ctrl_r(void)
244{ 244{
245 return 0x00100cc4; 245 return 0x00100cc4U;
246} 246}
247static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) 247static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
248{ 248{
249 return (r >> 16) & 0x1; 249 return (r >> 16U) & 0x1U;
250} 250}
251static inline u32 fb_mmu_debug_ctrl_debug_m(void) 251static inline u32 fb_mmu_debug_ctrl_debug_m(void)
252{ 252{
253 return 0x1 << 16; 253 return 0x1U << 16U;
254} 254}
255static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) 255static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
256{ 256{
257 return 0x00000001; 257 return 0x00000001U;
258} 258}
259static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void) 259static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void)
260{ 260{
261 return 0x10000; 261 return 0x10000U;
262} 262}
263static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) 263static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
264{ 264{
265 return 0x00000000; 265 return 0x00000000U;
266} 266}
267static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void) 267static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void)
268{ 268{
269 return 0x0; 269 return 0x0U;
270} 270}
271static inline u32 fb_mmu_vpr_info_r(void) 271static inline u32 fb_mmu_vpr_info_r(void)
272{ 272{
273 return 0x00100cd0; 273 return 0x00100cd0U;
274} 274}
275static inline u32 fb_mmu_vpr_info_index_f(u32 v) 275static inline u32 fb_mmu_vpr_info_index_f(u32 v)
276{ 276{
277 return (v & 0x3) << 0; 277 return (v & 0x3U) << 0U;
278} 278}
279static inline u32 fb_mmu_vpr_info_index_v(u32 r) 279static inline u32 fb_mmu_vpr_info_index_v(u32 r)
280{ 280{
281 return (r >> 0) & 0x3; 281 return (r >> 0U) & 0x3U;
282} 282}
283static inline u32 fb_mmu_vpr_info_index_addr_lo_v(void) 283static inline u32 fb_mmu_vpr_info_index_addr_lo_v(void)
284{ 284{
285 return 0x00000000; 285 return 0x00000000U;
286} 286}
287static inline u32 fb_mmu_vpr_info_index_addr_hi_v(void) 287static inline u32 fb_mmu_vpr_info_index_addr_hi_v(void)
288{ 288{
289 return 0x00000001; 289 return 0x00000001U;
290} 290}
291static inline u32 fb_mmu_vpr_info_index_cya_lo_v(void) 291static inline u32 fb_mmu_vpr_info_index_cya_lo_v(void)
292{ 292{
293 return 0x00000002; 293 return 0x00000002U;
294} 294}
295static inline u32 fb_mmu_vpr_info_index_cya_hi_v(void) 295static inline u32 fb_mmu_vpr_info_index_cya_hi_v(void)
296{ 296{
297 return 0x00000003; 297 return 0x00000003U;
298} 298}
299static inline u32 fb_mmu_vpr_info_fetch_f(u32 v) 299static inline u32 fb_mmu_vpr_info_fetch_f(u32 v)
300{ 300{
301 return (v & 0x1) << 2; 301 return (v & 0x1U) << 2U;
302} 302}
303static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) 303static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
304{ 304{
305 return (r >> 2) & 0x1; 305 return (r >> 2U) & 0x1U;
306} 306}
307static inline u32 fb_mmu_vpr_info_fetch_false_v(void) 307static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
308{ 308{
309 return 0x00000000; 309 return 0x00000000U;
310} 310}
311static inline u32 fb_mmu_vpr_info_fetch_true_v(void) 311static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
312{ 312{
313 return 0x00000001; 313 return 0x00000001U;
314} 314}
315static inline u32 fb_mmu_wpr_info_r(void) 315static inline u32 fb_mmu_wpr_info_r(void)
316{ 316{
317 return 0x00100cd4; 317 return 0x00100cd4U;
318} 318}
319static inline u32 fb_mmu_wpr_info_index_f(u32 v) 319static inline u32 fb_mmu_wpr_info_index_f(u32 v)
320{ 320{
321 return (v & 0xf) << 0; 321 return (v & 0xfU) << 0U;
322} 322}
323static inline u32 fb_mmu_wpr_info_index_allow_read_v(void) 323static inline u32 fb_mmu_wpr_info_index_allow_read_v(void)
324{ 324{
325 return 0x00000000; 325 return 0x00000000U;
326} 326}
327static inline u32 fb_mmu_wpr_info_index_allow_write_v(void) 327static inline u32 fb_mmu_wpr_info_index_allow_write_v(void)
328{ 328{
329 return 0x00000001; 329 return 0x00000001U;
330} 330}
331static inline u32 fb_mmu_wpr_info_index_wpr1_addr_lo_v(void) 331static inline u32 fb_mmu_wpr_info_index_wpr1_addr_lo_v(void)
332{ 332{
333 return 0x00000002; 333 return 0x00000002U;
334} 334}
335static inline u32 fb_mmu_wpr_info_index_wpr1_addr_hi_v(void) 335static inline u32 fb_mmu_wpr_info_index_wpr1_addr_hi_v(void)
336{ 336{
337 return 0x00000003; 337 return 0x00000003U;
338} 338}
339static inline u32 fb_mmu_wpr_info_index_wpr2_addr_lo_v(void) 339static inline u32 fb_mmu_wpr_info_index_wpr2_addr_lo_v(void)
340{ 340{
341 return 0x00000004; 341 return 0x00000004U;
342} 342}
343static inline u32 fb_mmu_wpr_info_index_wpr2_addr_hi_v(void) 343static inline u32 fb_mmu_wpr_info_index_wpr2_addr_hi_v(void)
344{ 344{
345 return 0x00000005; 345 return 0x00000005U;
346} 346}
347static inline u32 fb_niso_flush_sysmem_addr_r(void) 347static inline u32 fb_niso_flush_sysmem_addr_r(void)
348{ 348{
349 return 0x00100c10; 349 return 0x00100c10U;
350} 350}
351#endif 351#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h
index bfa9cc5b..d32506dd 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fifo_gm20b.h
@@ -58,514 +58,514 @@
58 58
59static inline u32 fifo_bar1_base_r(void) 59static inline u32 fifo_bar1_base_r(void)
60{ 60{
61 return 0x00002254; 61 return 0x00002254U;
62} 62}
63static inline u32 fifo_bar1_base_ptr_f(u32 v) 63static inline u32 fifo_bar1_base_ptr_f(u32 v)
64{ 64{
65 return (v & 0xfffffff) << 0; 65 return (v & 0xfffffffU) << 0U;
66} 66}
67static inline u32 fifo_bar1_base_ptr_align_shift_v(void) 67static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
68{ 68{
69 return 0x0000000c; 69 return 0x0000000cU;
70} 70}
71static inline u32 fifo_bar1_base_valid_false_f(void) 71static inline u32 fifo_bar1_base_valid_false_f(void)
72{ 72{
73 return 0x0; 73 return 0x0U;
74} 74}
75static inline u32 fifo_bar1_base_valid_true_f(void) 75static inline u32 fifo_bar1_base_valid_true_f(void)
76{ 76{
77 return 0x10000000; 77 return 0x10000000U;
78} 78}
79static inline u32 fifo_runlist_base_r(void) 79static inline u32 fifo_runlist_base_r(void)
80{ 80{
81 return 0x00002270; 81 return 0x00002270U;
82} 82}
83static inline u32 fifo_runlist_base_ptr_f(u32 v) 83static inline u32 fifo_runlist_base_ptr_f(u32 v)
84{ 84{
85 return (v & 0xfffffff) << 0; 85 return (v & 0xfffffffU) << 0U;
86} 86}
87static inline u32 fifo_runlist_base_target_vid_mem_f(void) 87static inline u32 fifo_runlist_base_target_vid_mem_f(void)
88{ 88{
89 return 0x0; 89 return 0x0U;
90} 90}
91static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) 91static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
92{ 92{
93 return 0x20000000; 93 return 0x20000000U;
94} 94}
95static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) 95static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
96{ 96{
97 return 0x30000000; 97 return 0x30000000U;
98} 98}
99static inline u32 fifo_runlist_r(void) 99static inline u32 fifo_runlist_r(void)
100{ 100{
101 return 0x00002274; 101 return 0x00002274U;
102} 102}
103static inline u32 fifo_runlist_engine_f(u32 v) 103static inline u32 fifo_runlist_engine_f(u32 v)
104{ 104{
105 return (v & 0xf) << 20; 105 return (v & 0xfU) << 20U;
106} 106}
107static inline u32 fifo_eng_runlist_base_r(u32 i) 107static inline u32 fifo_eng_runlist_base_r(u32 i)
108{ 108{
109 return 0x00002280 + i*8; 109 return 0x00002280U + i*8U;
110} 110}
111static inline u32 fifo_eng_runlist_base__size_1_v(void) 111static inline u32 fifo_eng_runlist_base__size_1_v(void)
112{ 112{
113 return 0x00000001; 113 return 0x00000001U;
114} 114}
115static inline u32 fifo_eng_runlist_r(u32 i) 115static inline u32 fifo_eng_runlist_r(u32 i)
116{ 116{
117 return 0x00002284 + i*8; 117 return 0x00002284U + i*8U;
118} 118}
119static inline u32 fifo_eng_runlist__size_1_v(void) 119static inline u32 fifo_eng_runlist__size_1_v(void)
120{ 120{
121 return 0x00000001; 121 return 0x00000001U;
122} 122}
123static inline u32 fifo_eng_runlist_length_f(u32 v) 123static inline u32 fifo_eng_runlist_length_f(u32 v)
124{ 124{
125 return (v & 0xffff) << 0; 125 return (v & 0xffffU) << 0U;
126} 126}
127static inline u32 fifo_eng_runlist_length_max_v(void) 127static inline u32 fifo_eng_runlist_length_max_v(void)
128{ 128{
129 return 0x0000ffff; 129 return 0x0000ffffU;
130} 130}
131static inline u32 fifo_eng_runlist_pending_true_f(void) 131static inline u32 fifo_eng_runlist_pending_true_f(void)
132{ 132{
133 return 0x100000; 133 return 0x100000U;
134} 134}
135static inline u32 fifo_pb_timeslice_r(u32 i) 135static inline u32 fifo_pb_timeslice_r(u32 i)
136{ 136{
137 return 0x00002350 + i*4; 137 return 0x00002350U + i*4U;
138} 138}
139static inline u32 fifo_pb_timeslice_timeout_16_f(void) 139static inline u32 fifo_pb_timeslice_timeout_16_f(void)
140{ 140{
141 return 0x10; 141 return 0x10U;
142} 142}
143static inline u32 fifo_pb_timeslice_timescale_0_f(void) 143static inline u32 fifo_pb_timeslice_timescale_0_f(void)
144{ 144{
145 return 0x0; 145 return 0x0U;
146} 146}
147static inline u32 fifo_pb_timeslice_enable_true_f(void) 147static inline u32 fifo_pb_timeslice_enable_true_f(void)
148{ 148{
149 return 0x10000000; 149 return 0x10000000U;
150} 150}
151static inline u32 fifo_pbdma_map_r(u32 i) 151static inline u32 fifo_pbdma_map_r(u32 i)
152{ 152{
153 return 0x00002390 + i*4; 153 return 0x00002390U + i*4U;
154} 154}
155static inline u32 fifo_intr_0_r(void) 155static inline u32 fifo_intr_0_r(void)
156{ 156{
157 return 0x00002100; 157 return 0x00002100U;
158} 158}
159static inline u32 fifo_intr_0_bind_error_pending_f(void) 159static inline u32 fifo_intr_0_bind_error_pending_f(void)
160{ 160{
161 return 0x1; 161 return 0x1U;
162} 162}
163static inline u32 fifo_intr_0_bind_error_reset_f(void) 163static inline u32 fifo_intr_0_bind_error_reset_f(void)
164{ 164{
165 return 0x1; 165 return 0x1U;
166} 166}
167static inline u32 fifo_intr_0_sched_error_pending_f(void) 167static inline u32 fifo_intr_0_sched_error_pending_f(void)
168{ 168{
169 return 0x100; 169 return 0x100U;
170} 170}
171static inline u32 fifo_intr_0_sched_error_reset_f(void) 171static inline u32 fifo_intr_0_sched_error_reset_f(void)
172{ 172{
173 return 0x100; 173 return 0x100U;
174} 174}
175static inline u32 fifo_intr_0_chsw_error_pending_f(void) 175static inline u32 fifo_intr_0_chsw_error_pending_f(void)
176{ 176{
177 return 0x10000; 177 return 0x10000U;
178} 178}
179static inline u32 fifo_intr_0_chsw_error_reset_f(void) 179static inline u32 fifo_intr_0_chsw_error_reset_f(void)
180{ 180{
181 return 0x10000; 181 return 0x10000U;
182} 182}
183static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) 183static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
184{ 184{
185 return 0x800000; 185 return 0x800000U;
186} 186}
187static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) 187static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
188{ 188{
189 return 0x800000; 189 return 0x800000U;
190} 190}
191static inline u32 fifo_intr_0_lb_error_pending_f(void) 191static inline u32 fifo_intr_0_lb_error_pending_f(void)
192{ 192{
193 return 0x1000000; 193 return 0x1000000U;
194} 194}
195static inline u32 fifo_intr_0_lb_error_reset_f(void) 195static inline u32 fifo_intr_0_lb_error_reset_f(void)
196{ 196{
197 return 0x1000000; 197 return 0x1000000U;
198} 198}
199static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void) 199static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void)
200{ 200{
201 return 0x8000000; 201 return 0x8000000U;
202} 202}
203static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void) 203static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void)
204{ 204{
205 return 0x8000000; 205 return 0x8000000U;
206} 206}
207static inline u32 fifo_intr_0_mmu_fault_pending_f(void) 207static inline u32 fifo_intr_0_mmu_fault_pending_f(void)
208{ 208{
209 return 0x10000000; 209 return 0x10000000U;
210} 210}
211static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) 211static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
212{ 212{
213 return 0x20000000; 213 return 0x20000000U;
214} 214}
215static inline u32 fifo_intr_0_runlist_event_pending_f(void) 215static inline u32 fifo_intr_0_runlist_event_pending_f(void)
216{ 216{
217 return 0x40000000; 217 return 0x40000000U;
218} 218}
219static inline u32 fifo_intr_0_channel_intr_pending_f(void) 219static inline u32 fifo_intr_0_channel_intr_pending_f(void)
220{ 220{
221 return 0x80000000; 221 return 0x80000000U;
222} 222}
223static inline u32 fifo_intr_en_0_r(void) 223static inline u32 fifo_intr_en_0_r(void)
224{ 224{
225 return 0x00002140; 225 return 0x00002140U;
226} 226}
227static inline u32 fifo_intr_en_0_sched_error_f(u32 v) 227static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
228{ 228{
229 return (v & 0x1) << 8; 229 return (v & 0x1U) << 8U;
230} 230}
231static inline u32 fifo_intr_en_0_sched_error_m(void) 231static inline u32 fifo_intr_en_0_sched_error_m(void)
232{ 232{
233 return 0x1 << 8; 233 return 0x1U << 8U;
234} 234}
235static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v) 235static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v)
236{ 236{
237 return (v & 0x1) << 28; 237 return (v & 0x1U) << 28U;
238} 238}
239static inline u32 fifo_intr_en_0_mmu_fault_m(void) 239static inline u32 fifo_intr_en_0_mmu_fault_m(void)
240{ 240{
241 return 0x1 << 28; 241 return 0x1U << 28U;
242} 242}
243static inline u32 fifo_intr_en_1_r(void) 243static inline u32 fifo_intr_en_1_r(void)
244{ 244{
245 return 0x00002528; 245 return 0x00002528U;
246} 246}
247static inline u32 fifo_intr_bind_error_r(void) 247static inline u32 fifo_intr_bind_error_r(void)
248{ 248{
249 return 0x0000252c; 249 return 0x0000252cU;
250} 250}
251static inline u32 fifo_intr_sched_error_r(void) 251static inline u32 fifo_intr_sched_error_r(void)
252{ 252{
253 return 0x0000254c; 253 return 0x0000254cU;
254} 254}
255static inline u32 fifo_intr_sched_error_code_f(u32 v) 255static inline u32 fifo_intr_sched_error_code_f(u32 v)
256{ 256{
257 return (v & 0xff) << 0; 257 return (v & 0xffU) << 0U;
258} 258}
259static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) 259static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void)
260{ 260{
261 return 0x0000000a; 261 return 0x0000000aU;
262} 262}
263static inline u32 fifo_intr_chsw_error_r(void) 263static inline u32 fifo_intr_chsw_error_r(void)
264{ 264{
265 return 0x0000256c; 265 return 0x0000256cU;
266} 266}
267static inline u32 fifo_intr_mmu_fault_id_r(void) 267static inline u32 fifo_intr_mmu_fault_id_r(void)
268{ 268{
269 return 0x0000259c; 269 return 0x0000259cU;
270} 270}
271static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) 271static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
272{ 272{
273 return 0x00000000; 273 return 0x00000000U;
274} 274}
275static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) 275static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
276{ 276{
277 return 0x0; 277 return 0x0U;
278} 278}
279static inline u32 fifo_intr_mmu_fault_inst_r(u32 i) 279static inline u32 fifo_intr_mmu_fault_inst_r(u32 i)
280{ 280{
281 return 0x00002800 + i*16; 281 return 0x00002800U + i*16U;
282} 282}
283static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r) 283static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r)
284{ 284{
285 return (r >> 0) & 0xfffffff; 285 return (r >> 0U) & 0xfffffffU;
286} 286}
287static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void) 287static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void)
288{ 288{
289 return 0x0000000c; 289 return 0x0000000cU;
290} 290}
291static inline u32 fifo_intr_mmu_fault_lo_r(u32 i) 291static inline u32 fifo_intr_mmu_fault_lo_r(u32 i)
292{ 292{
293 return 0x00002804 + i*16; 293 return 0x00002804U + i*16U;
294} 294}
295static inline u32 fifo_intr_mmu_fault_hi_r(u32 i) 295static inline u32 fifo_intr_mmu_fault_hi_r(u32 i)
296{ 296{
297 return 0x00002808 + i*16; 297 return 0x00002808U + i*16U;
298} 298}
299static inline u32 fifo_intr_mmu_fault_info_r(u32 i) 299static inline u32 fifo_intr_mmu_fault_info_r(u32 i)
300{ 300{
301 return 0x0000280c + i*16; 301 return 0x0000280cU + i*16U;
302} 302}
303static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) 303static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r)
304{ 304{
305 return (r >> 0) & 0xf; 305 return (r >> 0U) & 0xfU;
306} 306}
307static inline u32 fifo_intr_mmu_fault_info_write_v(u32 r) 307static inline u32 fifo_intr_mmu_fault_info_write_v(u32 r)
308{ 308{
309 return (r >> 7) & 0x1; 309 return (r >> 7U) & 0x1U;
310} 310}
311static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r) 311static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r)
312{ 312{
313 return (r >> 6) & 0x1; 313 return (r >> 6U) & 0x1U;
314} 314}
315static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void) 315static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void)
316{ 316{
317 return 0x00000000; 317 return 0x00000000U;
318} 318}
319static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void) 319static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void)
320{ 320{
321 return 0x00000001; 321 return 0x00000001U;
322} 322}
323static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) 323static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r)
324{ 324{
325 return (r >> 8) & 0x3f; 325 return (r >> 8U) & 0x3fU;
326} 326}
327static inline u32 fifo_intr_pbdma_id_r(void) 327static inline u32 fifo_intr_pbdma_id_r(void)
328{ 328{
329 return 0x000025a0; 329 return 0x000025a0U;
330} 330}
331static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) 331static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
332{ 332{
333 return (v & 0x1) << (0 + i*1); 333 return (v & 0x1U) << (0U + i*1U);
334} 334}
335static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) 335static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
336{ 336{
337 return (r >> (0 + i*1)) & 0x1; 337 return (r >> (0U + i*1U)) & 0x1U;
338} 338}
339static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) 339static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
340{ 340{
341 return 0x00000001; 341 return 0x00000001U;
342} 342}
343static inline u32 fifo_intr_runlist_r(void) 343static inline u32 fifo_intr_runlist_r(void)
344{ 344{
345 return 0x00002a00; 345 return 0x00002a00U;
346} 346}
347static inline u32 fifo_fb_timeout_r(void) 347static inline u32 fifo_fb_timeout_r(void)
348{ 348{
349 return 0x00002a04; 349 return 0x00002a04U;
350} 350}
351static inline u32 fifo_fb_timeout_period_m(void) 351static inline u32 fifo_fb_timeout_period_m(void)
352{ 352{
353 return 0x3fffffff << 0; 353 return 0x3fffffffU << 0U;
354} 354}
355static inline u32 fifo_fb_timeout_period_max_f(void) 355static inline u32 fifo_fb_timeout_period_max_f(void)
356{ 356{
357 return 0x3fffffff; 357 return 0x3fffffffU;
358} 358}
359static inline u32 fifo_error_sched_disable_r(void) 359static inline u32 fifo_error_sched_disable_r(void)
360{ 360{
361 return 0x0000262c; 361 return 0x0000262cU;
362} 362}
363static inline u32 fifo_sched_disable_r(void) 363static inline u32 fifo_sched_disable_r(void)
364{ 364{
365 return 0x00002630; 365 return 0x00002630U;
366} 366}
367static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) 367static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
368{ 368{
369 return (v & 0x1) << (0 + i*1); 369 return (v & 0x1U) << (0U + i*1U);
370} 370}
371static inline u32 fifo_sched_disable_runlist_m(u32 i) 371static inline u32 fifo_sched_disable_runlist_m(u32 i)
372{ 372{
373 return 0x1 << (0 + i*1); 373 return 0x1U << (0U + i*1U);
374} 374}
375static inline u32 fifo_sched_disable_true_v(void) 375static inline u32 fifo_sched_disable_true_v(void)
376{ 376{
377 return 0x00000001; 377 return 0x00000001U;
378} 378}
379static inline u32 fifo_preempt_r(void) 379static inline u32 fifo_preempt_r(void)
380{ 380{
381 return 0x00002634; 381 return 0x00002634U;
382} 382}
383static inline u32 fifo_preempt_pending_true_f(void) 383static inline u32 fifo_preempt_pending_true_f(void)
384{ 384{
385 return 0x100000; 385 return 0x100000U;
386} 386}
387static inline u32 fifo_preempt_type_channel_f(void) 387static inline u32 fifo_preempt_type_channel_f(void)
388{ 388{
389 return 0x0; 389 return 0x0U;
390} 390}
391static inline u32 fifo_preempt_type_tsg_f(void) 391static inline u32 fifo_preempt_type_tsg_f(void)
392{ 392{
393 return 0x1000000; 393 return 0x1000000U;
394} 394}
395static inline u32 fifo_preempt_chid_f(u32 v) 395static inline u32 fifo_preempt_chid_f(u32 v)
396{ 396{
397 return (v & 0xfff) << 0; 397 return (v & 0xfffU) << 0U;
398} 398}
399static inline u32 fifo_preempt_id_f(u32 v) 399static inline u32 fifo_preempt_id_f(u32 v)
400{ 400{
401 return (v & 0xfff) << 0; 401 return (v & 0xfffU) << 0U;
402} 402}
403static inline u32 fifo_trigger_mmu_fault_r(u32 i) 403static inline u32 fifo_trigger_mmu_fault_r(u32 i)
404{ 404{
405 return 0x00002a30 + i*4; 405 return 0x00002a30U + i*4U;
406} 406}
407static inline u32 fifo_trigger_mmu_fault_id_f(u32 v) 407static inline u32 fifo_trigger_mmu_fault_id_f(u32 v)
408{ 408{
409 return (v & 0x1f) << 0; 409 return (v & 0x1fU) << 0U;
410} 410}
411static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v) 411static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v)
412{ 412{
413 return (v & 0x1) << 8; 413 return (v & 0x1U) << 8U;
414} 414}
415static inline u32 fifo_engine_status_r(u32 i) 415static inline u32 fifo_engine_status_r(u32 i)
416{ 416{
417 return 0x00002640 + i*8; 417 return 0x00002640U + i*8U;
418} 418}
419static inline u32 fifo_engine_status__size_1_v(void) 419static inline u32 fifo_engine_status__size_1_v(void)
420{ 420{
421 return 0x00000002; 421 return 0x00000002U;
422} 422}
423static inline u32 fifo_engine_status_id_v(u32 r) 423static inline u32 fifo_engine_status_id_v(u32 r)
424{ 424{
425 return (r >> 0) & 0xfff; 425 return (r >> 0U) & 0xfffU;
426} 426}
427static inline u32 fifo_engine_status_id_type_v(u32 r) 427static inline u32 fifo_engine_status_id_type_v(u32 r)
428{ 428{
429 return (r >> 12) & 0x1; 429 return (r >> 12U) & 0x1U;
430} 430}
431static inline u32 fifo_engine_status_id_type_chid_v(void) 431static inline u32 fifo_engine_status_id_type_chid_v(void)
432{ 432{
433 return 0x00000000; 433 return 0x00000000U;
434} 434}
435static inline u32 fifo_engine_status_id_type_tsgid_v(void) 435static inline u32 fifo_engine_status_id_type_tsgid_v(void)
436{ 436{
437 return 0x00000001; 437 return 0x00000001U;
438} 438}
439static inline u32 fifo_engine_status_ctx_status_v(u32 r) 439static inline u32 fifo_engine_status_ctx_status_v(u32 r)
440{ 440{
441 return (r >> 13) & 0x7; 441 return (r >> 13U) & 0x7U;
442} 442}
443static inline u32 fifo_engine_status_ctx_status_invalid_v(void) 443static inline u32 fifo_engine_status_ctx_status_invalid_v(void)
444{ 444{
445 return 0x00000000; 445 return 0x00000000U;
446} 446}
447static inline u32 fifo_engine_status_ctx_status_valid_v(void) 447static inline u32 fifo_engine_status_ctx_status_valid_v(void)
448{ 448{
449 return 0x00000001; 449 return 0x00000001U;
450} 450}
451static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) 451static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
452{ 452{
453 return 0x00000005; 453 return 0x00000005U;
454} 454}
455static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) 455static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
456{ 456{
457 return 0x00000006; 457 return 0x00000006U;
458} 458}
459static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) 459static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
460{ 460{
461 return 0x00000007; 461 return 0x00000007U;
462} 462}
463static inline u32 fifo_engine_status_next_id_v(u32 r) 463static inline u32 fifo_engine_status_next_id_v(u32 r)
464{ 464{
465 return (r >> 16) & 0xfff; 465 return (r >> 16U) & 0xfffU;
466} 466}
467static inline u32 fifo_engine_status_next_id_type_v(u32 r) 467static inline u32 fifo_engine_status_next_id_type_v(u32 r)
468{ 468{
469 return (r >> 28) & 0x1; 469 return (r >> 28U) & 0x1U;
470} 470}
471static inline u32 fifo_engine_status_next_id_type_chid_v(void) 471static inline u32 fifo_engine_status_next_id_type_chid_v(void)
472{ 472{
473 return 0x00000000; 473 return 0x00000000U;
474} 474}
475static inline u32 fifo_engine_status_faulted_v(u32 r) 475static inline u32 fifo_engine_status_faulted_v(u32 r)
476{ 476{
477 return (r >> 30) & 0x1; 477 return (r >> 30U) & 0x1U;
478} 478}
479static inline u32 fifo_engine_status_faulted_true_v(void) 479static inline u32 fifo_engine_status_faulted_true_v(void)
480{ 480{
481 return 0x00000001; 481 return 0x00000001U;
482} 482}
483static inline u32 fifo_engine_status_engine_v(u32 r) 483static inline u32 fifo_engine_status_engine_v(u32 r)
484{ 484{
485 return (r >> 31) & 0x1; 485 return (r >> 31U) & 0x1U;
486} 486}
487static inline u32 fifo_engine_status_engine_idle_v(void) 487static inline u32 fifo_engine_status_engine_idle_v(void)
488{ 488{
489 return 0x00000000; 489 return 0x00000000U;
490} 490}
491static inline u32 fifo_engine_status_engine_busy_v(void) 491static inline u32 fifo_engine_status_engine_busy_v(void)
492{ 492{
493 return 0x00000001; 493 return 0x00000001U;
494} 494}
495static inline u32 fifo_engine_status_ctxsw_v(u32 r) 495static inline u32 fifo_engine_status_ctxsw_v(u32 r)
496{ 496{
497 return (r >> 15) & 0x1; 497 return (r >> 15U) & 0x1U;
498} 498}
499static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) 499static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
500{ 500{
501 return 0x00000001; 501 return 0x00000001U;
502} 502}
503static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) 503static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
504{ 504{
505 return 0x8000; 505 return 0x8000U;
506} 506}
507static inline u32 fifo_pbdma_status_r(u32 i) 507static inline u32 fifo_pbdma_status_r(u32 i)
508{ 508{
509 return 0x00003080 + i*4; 509 return 0x00003080U + i*4U;
510} 510}
511static inline u32 fifo_pbdma_status__size_1_v(void) 511static inline u32 fifo_pbdma_status__size_1_v(void)
512{ 512{
513 return 0x00000001; 513 return 0x00000001U;
514} 514}
515static inline u32 fifo_pbdma_status_id_v(u32 r) 515static inline u32 fifo_pbdma_status_id_v(u32 r)
516{ 516{
517 return (r >> 0) & 0xfff; 517 return (r >> 0U) & 0xfffU;
518} 518}
519static inline u32 fifo_pbdma_status_id_type_v(u32 r) 519static inline u32 fifo_pbdma_status_id_type_v(u32 r)
520{ 520{
521 return (r >> 12) & 0x1; 521 return (r >> 12U) & 0x1U;
522} 522}
523static inline u32 fifo_pbdma_status_id_type_chid_v(void) 523static inline u32 fifo_pbdma_status_id_type_chid_v(void)
524{ 524{
525 return 0x00000000; 525 return 0x00000000U;
526} 526}
527static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) 527static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
528{ 528{
529 return 0x00000001; 529 return 0x00000001U;
530} 530}
531static inline u32 fifo_pbdma_status_chan_status_v(u32 r) 531static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
532{ 532{
533 return (r >> 13) & 0x7; 533 return (r >> 13U) & 0x7U;
534} 534}
535static inline u32 fifo_pbdma_status_chan_status_valid_v(void) 535static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
536{ 536{
537 return 0x00000001; 537 return 0x00000001U;
538} 538}
539static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) 539static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
540{ 540{
541 return 0x00000005; 541 return 0x00000005U;
542} 542}
543static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) 543static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
544{ 544{
545 return 0x00000006; 545 return 0x00000006U;
546} 546}
547static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) 547static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
548{ 548{
549 return 0x00000007; 549 return 0x00000007U;
550} 550}
551static inline u32 fifo_pbdma_status_next_id_v(u32 r) 551static inline u32 fifo_pbdma_status_next_id_v(u32 r)
552{ 552{
553 return (r >> 16) & 0xfff; 553 return (r >> 16U) & 0xfffU;
554} 554}
555static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) 555static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
556{ 556{
557 return (r >> 28) & 0x1; 557 return (r >> 28U) & 0x1U;
558} 558}
559static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) 559static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
560{ 560{
561 return 0x00000000; 561 return 0x00000000U;
562} 562}
563static inline u32 fifo_pbdma_status_chsw_v(u32 r) 563static inline u32 fifo_pbdma_status_chsw_v(u32 r)
564{ 564{
565 return (r >> 15) & 0x1; 565 return (r >> 15U) & 0x1U;
566} 566}
567static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) 567static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
568{ 568{
569 return 0x00000001; 569 return 0x00000001U;
570} 570}
571#endif 571#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_flush_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_flush_gm20b.h
index 3c24a803..3b5801b6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_flush_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_flush_gm20b.h
@@ -58,130 +58,130 @@
58 58
59static inline u32 flush_l2_system_invalidate_r(void) 59static inline u32 flush_l2_system_invalidate_r(void)
60{ 60{
61 return 0x00070004; 61 return 0x00070004U;
62} 62}
63static inline u32 flush_l2_system_invalidate_pending_v(u32 r) 63static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
64{ 64{
65 return (r >> 0) & 0x1; 65 return (r >> 0U) & 0x1U;
66} 66}
67static inline u32 flush_l2_system_invalidate_pending_busy_v(void) 67static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
68{ 68{
69 return 0x00000001; 69 return 0x00000001U;
70} 70}
71static inline u32 flush_l2_system_invalidate_pending_busy_f(void) 71static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
72{ 72{
73 return 0x1; 73 return 0x1U;
74} 74}
75static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) 75static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
76{ 76{
77 return (r >> 1) & 0x1; 77 return (r >> 1U) & 0x1U;
78} 78}
79static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) 79static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
80{ 80{
81 return 0x00000001; 81 return 0x00000001U;
82} 82}
83static inline u32 flush_l2_flush_dirty_r(void) 83static inline u32 flush_l2_flush_dirty_r(void)
84{ 84{
85 return 0x00070010; 85 return 0x00070010U;
86} 86}
87static inline u32 flush_l2_flush_dirty_pending_v(u32 r) 87static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
88{ 88{
89 return (r >> 0) & 0x1; 89 return (r >> 0U) & 0x1U;
90} 90}
91static inline u32 flush_l2_flush_dirty_pending_empty_v(void) 91static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
92{ 92{
93 return 0x00000000; 93 return 0x00000000U;
94} 94}
95static inline u32 flush_l2_flush_dirty_pending_empty_f(void) 95static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
96{ 96{
97 return 0x0; 97 return 0x0U;
98} 98}
99static inline u32 flush_l2_flush_dirty_pending_busy_v(void) 99static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
100{ 100{
101 return 0x00000001; 101 return 0x00000001U;
102} 102}
103static inline u32 flush_l2_flush_dirty_pending_busy_f(void) 103static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
104{ 104{
105 return 0x1; 105 return 0x1U;
106} 106}
107static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) 107static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
108{ 108{
109 return (r >> 1) & 0x1; 109 return (r >> 1U) & 0x1U;
110} 110}
111static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) 111static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
112{ 112{
113 return 0x00000000; 113 return 0x00000000U;
114} 114}
115static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) 115static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
116{ 116{
117 return 0x0; 117 return 0x0U;
118} 118}
119static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) 119static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
120{ 120{
121 return 0x00000001; 121 return 0x00000001U;
122} 122}
123static inline u32 flush_l2_clean_comptags_r(void) 123static inline u32 flush_l2_clean_comptags_r(void)
124{ 124{
125 return 0x0007000c; 125 return 0x0007000cU;
126} 126}
127static inline u32 flush_l2_clean_comptags_pending_v(u32 r) 127static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
128{ 128{
129 return (r >> 0) & 0x1; 129 return (r >> 0U) & 0x1U;
130} 130}
131static inline u32 flush_l2_clean_comptags_pending_empty_v(void) 131static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
132{ 132{
133 return 0x00000000; 133 return 0x00000000U;
134} 134}
135static inline u32 flush_l2_clean_comptags_pending_empty_f(void) 135static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
136{ 136{
137 return 0x0; 137 return 0x0U;
138} 138}
139static inline u32 flush_l2_clean_comptags_pending_busy_v(void) 139static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
140{ 140{
141 return 0x00000001; 141 return 0x00000001U;
142} 142}
143static inline u32 flush_l2_clean_comptags_pending_busy_f(void) 143static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
144{ 144{
145 return 0x1; 145 return 0x1U;
146} 146}
147static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) 147static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
148{ 148{
149 return (r >> 1) & 0x1; 149 return (r >> 1U) & 0x1U;
150} 150}
151static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) 151static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
152{ 152{
153 return 0x00000000; 153 return 0x00000000U;
154} 154}
155static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) 155static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
156{ 156{
157 return 0x0; 157 return 0x0U;
158} 158}
159static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) 159static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
160{ 160{
161 return 0x00000001; 161 return 0x00000001U;
162} 162}
163static inline u32 flush_fb_flush_r(void) 163static inline u32 flush_fb_flush_r(void)
164{ 164{
165 return 0x00070000; 165 return 0x00070000U;
166} 166}
167static inline u32 flush_fb_flush_pending_v(u32 r) 167static inline u32 flush_fb_flush_pending_v(u32 r)
168{ 168{
169 return (r >> 0) & 0x1; 169 return (r >> 0U) & 0x1U;
170} 170}
171static inline u32 flush_fb_flush_pending_busy_v(void) 171static inline u32 flush_fb_flush_pending_busy_v(void)
172{ 172{
173 return 0x00000001; 173 return 0x00000001U;
174} 174}
175static inline u32 flush_fb_flush_pending_busy_f(void) 175static inline u32 flush_fb_flush_pending_busy_f(void)
176{ 176{
177 return 0x1; 177 return 0x1U;
178} 178}
179static inline u32 flush_fb_flush_outstanding_v(u32 r) 179static inline u32 flush_fb_flush_outstanding_v(u32 r)
180{ 180{
181 return (r >> 1) & 0x1; 181 return (r >> 1U) & 0x1U;
182} 182}
183static inline u32 flush_fb_flush_outstanding_true_v(void) 183static inline u32 flush_fb_flush_outstanding_true_v(void)
184{ 184{
185 return 0x00000001; 185 return 0x00000001U;
186} 186}
187#endif 187#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h
index eea44046..99b4b3f3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h
@@ -58,86 +58,86 @@
58 58
59static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) 59static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
60{ 60{
61 return 0x00021c38 + i*4; 61 return 0x00021c38U + i*4U;
62} 62}
63static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) 63static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i)
64{ 64{
65 return 0x00021838 + i*4; 65 return 0x00021838U + i*4U;
66} 66}
67static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) 67static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void)
68{ 68{
69 return 0x00021944; 69 return 0x00021944U;
70} 70}
71static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) 71static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
72{ 72{
73 return (v & 0x3) << 0; 73 return (v & 0x3U) << 0U;
74} 74}
75static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) 75static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
76{ 76{
77 return 0x3 << 0; 77 return 0x3U << 0U;
78} 78}
79static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) 79static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
80{ 80{
81 return (r >> 0) & 0x3; 81 return (r >> 0U) & 0x3U;
82} 82}
83static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) 83static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void)
84{ 84{
85 return 0x00021948; 85 return 0x00021948U;
86} 86}
87static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) 87static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
88{ 88{
89 return (v & 0x1) << 0; 89 return (v & 0x1U) << 0U;
90} 90}
91static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) 91static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
92{ 92{
93 return 0x1 << 0; 93 return 0x1U << 0U;
94} 94}
95static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) 95static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
96{ 96{
97 return (r >> 0) & 0x1; 97 return (r >> 0U) & 0x1U;
98} 98}
99static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) 99static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void)
100{ 100{
101 return 0x1; 101 return 0x1U;
102} 102}
103static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) 103static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void)
104{ 104{
105 return 0x0; 105 return 0x0U;
106} 106}
107static inline u32 fuse_status_opt_fbio_r(void) 107static inline u32 fuse_status_opt_fbio_r(void)
108{ 108{
109 return 0x00021c14; 109 return 0x00021c14U;
110} 110}
111static inline u32 fuse_status_opt_fbio_data_f(u32 v) 111static inline u32 fuse_status_opt_fbio_data_f(u32 v)
112{ 112{
113 return (v & 0xffff) << 0; 113 return (v & 0xffffU) << 0U;
114} 114}
115static inline u32 fuse_status_opt_fbio_data_m(void) 115static inline u32 fuse_status_opt_fbio_data_m(void)
116{ 116{
117 return 0xffff << 0; 117 return 0xffffU << 0U;
118} 118}
119static inline u32 fuse_status_opt_fbio_data_v(u32 r) 119static inline u32 fuse_status_opt_fbio_data_v(u32 r)
120{ 120{
121 return (r >> 0) & 0xffff; 121 return (r >> 0U) & 0xffffU;
122} 122}
123static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) 123static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i)
124{ 124{
125 return 0x00021d70 + i*4; 125 return 0x00021d70U + i*4U;
126} 126}
127static inline u32 fuse_status_opt_fbp_r(void) 127static inline u32 fuse_status_opt_fbp_r(void)
128{ 128{
129 return 0x00021d38; 129 return 0x00021d38U;
130} 130}
131static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) 131static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
132{ 132{
133 return (r >> (0 + i*1)) & 0x1; 133 return (r >> (0U + i*1U)) & 0x1U;
134} 134}
135static inline u32 fuse_opt_sec_debug_en_r(void) 135static inline u32 fuse_opt_sec_debug_en_r(void)
136{ 136{
137 return 0x00021218; 137 return 0x00021218U;
138} 138}
139static inline u32 fuse_opt_priv_sec_en_r(void) 139static inline u32 fuse_opt_priv_sec_en_r(void)
140{ 140{
141 return 0x00021434; 141 return 0x00021434U;
142} 142}
143#endif 143#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h
index 7cbecaca..e11ac246 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gmmu_gm20b.h
@@ -58,1150 +58,1150 @@
58 58
59static inline u32 gmmu_pde_aperture_big_w(void) 59static inline u32 gmmu_pde_aperture_big_w(void)
60{ 60{
61 return 0; 61 return 0U;
62} 62}
63static inline u32 gmmu_pde_aperture_big_invalid_f(void) 63static inline u32 gmmu_pde_aperture_big_invalid_f(void)
64{ 64{
65 return 0x0; 65 return 0x0U;
66} 66}
67static inline u32 gmmu_pde_aperture_big_video_memory_f(void) 67static inline u32 gmmu_pde_aperture_big_video_memory_f(void)
68{ 68{
69 return 0x1; 69 return 0x1U;
70} 70}
71static inline u32 gmmu_pde_aperture_big_sys_mem_coh_f(void) 71static inline u32 gmmu_pde_aperture_big_sys_mem_coh_f(void)
72{ 72{
73 return 0x2; 73 return 0x2U;
74} 74}
75static inline u32 gmmu_pde_aperture_big_sys_mem_ncoh_f(void) 75static inline u32 gmmu_pde_aperture_big_sys_mem_ncoh_f(void)
76{ 76{
77 return 0x3; 77 return 0x3U;
78} 78}
79static inline u32 gmmu_pde_size_w(void) 79static inline u32 gmmu_pde_size_w(void)
80{ 80{
81 return 0; 81 return 0U;
82} 82}
83static inline u32 gmmu_pde_size_full_f(void) 83static inline u32 gmmu_pde_size_full_f(void)
84{ 84{
85 return 0x0; 85 return 0x0U;
86} 86}
87static inline u32 gmmu_pde_address_big_sys_f(u32 v) 87static inline u32 gmmu_pde_address_big_sys_f(u32 v)
88{ 88{
89 return (v & 0xfffffff) << 4; 89 return (v & 0xfffffffU) << 4U;
90} 90}
91static inline u32 gmmu_pde_address_big_sys_w(void) 91static inline u32 gmmu_pde_address_big_sys_w(void)
92{ 92{
93 return 0; 93 return 0U;
94} 94}
95static inline u32 gmmu_pde_aperture_small_w(void) 95static inline u32 gmmu_pde_aperture_small_w(void)
96{ 96{
97 return 1; 97 return 1U;
98} 98}
99static inline u32 gmmu_pde_aperture_small_invalid_f(void) 99static inline u32 gmmu_pde_aperture_small_invalid_f(void)
100{ 100{
101 return 0x0; 101 return 0x0U;
102} 102}
103static inline u32 gmmu_pde_aperture_small_video_memory_f(void) 103static inline u32 gmmu_pde_aperture_small_video_memory_f(void)
104{ 104{
105 return 0x1; 105 return 0x1U;
106} 106}
107static inline u32 gmmu_pde_aperture_small_sys_mem_coh_f(void) 107static inline u32 gmmu_pde_aperture_small_sys_mem_coh_f(void)
108{ 108{
109 return 0x2; 109 return 0x2U;
110} 110}
111static inline u32 gmmu_pde_aperture_small_sys_mem_ncoh_f(void) 111static inline u32 gmmu_pde_aperture_small_sys_mem_ncoh_f(void)
112{ 112{
113 return 0x3; 113 return 0x3U;
114} 114}
115static inline u32 gmmu_pde_vol_small_w(void) 115static inline u32 gmmu_pde_vol_small_w(void)
116{ 116{
117 return 1; 117 return 1U;
118} 118}
119static inline u32 gmmu_pde_vol_small_true_f(void) 119static inline u32 gmmu_pde_vol_small_true_f(void)
120{ 120{
121 return 0x4; 121 return 0x4U;
122} 122}
123static inline u32 gmmu_pde_vol_small_false_f(void) 123static inline u32 gmmu_pde_vol_small_false_f(void)
124{ 124{
125 return 0x0; 125 return 0x0U;
126} 126}
127static inline u32 gmmu_pde_vol_big_w(void) 127static inline u32 gmmu_pde_vol_big_w(void)
128{ 128{
129 return 1; 129 return 1U;
130} 130}
131static inline u32 gmmu_pde_vol_big_true_f(void) 131static inline u32 gmmu_pde_vol_big_true_f(void)
132{ 132{
133 return 0x8; 133 return 0x8U;
134} 134}
135static inline u32 gmmu_pde_vol_big_false_f(void) 135static inline u32 gmmu_pde_vol_big_false_f(void)
136{ 136{
137 return 0x0; 137 return 0x0U;
138} 138}
139static inline u32 gmmu_pde_address_small_sys_f(u32 v) 139static inline u32 gmmu_pde_address_small_sys_f(u32 v)
140{ 140{
141 return (v & 0xfffffff) << 4; 141 return (v & 0xfffffffU) << 4U;
142} 142}
143static inline u32 gmmu_pde_address_small_sys_w(void) 143static inline u32 gmmu_pde_address_small_sys_w(void)
144{ 144{
145 return 1; 145 return 1U;
146} 146}
147static inline u32 gmmu_pde_address_shift_v(void) 147static inline u32 gmmu_pde_address_shift_v(void)
148{ 148{
149 return 0x0000000c; 149 return 0x0000000cU;
150} 150}
151static inline u32 gmmu_pde__size_v(void) 151static inline u32 gmmu_pde__size_v(void)
152{ 152{
153 return 0x00000008; 153 return 0x00000008U;
154} 154}
155static inline u32 gmmu_pte__size_v(void) 155static inline u32 gmmu_pte__size_v(void)
156{ 156{
157 return 0x00000008; 157 return 0x00000008U;
158} 158}
159static inline u32 gmmu_pte_valid_w(void) 159static inline u32 gmmu_pte_valid_w(void)
160{ 160{
161 return 0; 161 return 0U;
162} 162}
163static inline u32 gmmu_pte_valid_true_f(void) 163static inline u32 gmmu_pte_valid_true_f(void)
164{ 164{
165 return 0x1; 165 return 0x1U;
166} 166}
167static inline u32 gmmu_pte_valid_false_f(void) 167static inline u32 gmmu_pte_valid_false_f(void)
168{ 168{
169 return 0x0; 169 return 0x0U;
170} 170}
171static inline u32 gmmu_pte_privilege_w(void) 171static inline u32 gmmu_pte_privilege_w(void)
172{ 172{
173 return 0; 173 return 0U;
174} 174}
175static inline u32 gmmu_pte_privilege_true_f(void) 175static inline u32 gmmu_pte_privilege_true_f(void)
176{ 176{
177 return 0x2; 177 return 0x2U;
178} 178}
179static inline u32 gmmu_pte_privilege_false_f(void) 179static inline u32 gmmu_pte_privilege_false_f(void)
180{ 180{
181 return 0x0; 181 return 0x0U;
182} 182}
183static inline u32 gmmu_pte_address_sys_f(u32 v) 183static inline u32 gmmu_pte_address_sys_f(u32 v)
184{ 184{
185 return (v & 0xfffffff) << 4; 185 return (v & 0xfffffffU) << 4U;
186} 186}
187static inline u32 gmmu_pte_address_sys_w(void) 187static inline u32 gmmu_pte_address_sys_w(void)
188{ 188{
189 return 0; 189 return 0U;
190} 190}
191static inline u32 gmmu_pte_address_vid_f(u32 v) 191static inline u32 gmmu_pte_address_vid_f(u32 v)
192{ 192{
193 return (v & 0x1ffffff) << 4; 193 return (v & 0x1ffffffU) << 4U;
194} 194}
195static inline u32 gmmu_pte_address_vid_w(void) 195static inline u32 gmmu_pte_address_vid_w(void)
196{ 196{
197 return 0; 197 return 0U;
198} 198}
199static inline u32 gmmu_pte_vol_w(void) 199static inline u32 gmmu_pte_vol_w(void)
200{ 200{
201 return 1; 201 return 1U;
202} 202}
203static inline u32 gmmu_pte_vol_true_f(void) 203static inline u32 gmmu_pte_vol_true_f(void)
204{ 204{
205 return 0x1; 205 return 0x1U;
206} 206}
207static inline u32 gmmu_pte_vol_false_f(void) 207static inline u32 gmmu_pte_vol_false_f(void)
208{ 208{
209 return 0x0; 209 return 0x0U;
210} 210}
211static inline u32 gmmu_pte_aperture_w(void) 211static inline u32 gmmu_pte_aperture_w(void)
212{ 212{
213 return 1; 213 return 1U;
214} 214}
215static inline u32 gmmu_pte_aperture_video_memory_f(void) 215static inline u32 gmmu_pte_aperture_video_memory_f(void)
216{ 216{
217 return 0x0; 217 return 0x0U;
218} 218}
219static inline u32 gmmu_pte_aperture_sys_mem_coh_f(void) 219static inline u32 gmmu_pte_aperture_sys_mem_coh_f(void)
220{ 220{
221 return 0x4; 221 return 0x4U;
222} 222}
223static inline u32 gmmu_pte_aperture_sys_mem_ncoh_f(void) 223static inline u32 gmmu_pte_aperture_sys_mem_ncoh_f(void)
224{ 224{
225 return 0x6; 225 return 0x6U;
226} 226}
227static inline u32 gmmu_pte_read_only_w(void) 227static inline u32 gmmu_pte_read_only_w(void)
228{ 228{
229 return 0; 229 return 0U;
230} 230}
231static inline u32 gmmu_pte_read_only_true_f(void) 231static inline u32 gmmu_pte_read_only_true_f(void)
232{ 232{
233 return 0x4; 233 return 0x4U;
234} 234}
235static inline u32 gmmu_pte_write_disable_w(void) 235static inline u32 gmmu_pte_write_disable_w(void)
236{ 236{
237 return 1; 237 return 1U;
238} 238}
239static inline u32 gmmu_pte_write_disable_true_f(void) 239static inline u32 gmmu_pte_write_disable_true_f(void)
240{ 240{
241 return 0x80000000; 241 return 0x80000000U;
242} 242}
243static inline u32 gmmu_pte_read_disable_w(void) 243static inline u32 gmmu_pte_read_disable_w(void)
244{ 244{
245 return 1; 245 return 1U;
246} 246}
247static inline u32 gmmu_pte_read_disable_true_f(void) 247static inline u32 gmmu_pte_read_disable_true_f(void)
248{ 248{
249 return 0x40000000; 249 return 0x40000000U;
250} 250}
251static inline u32 gmmu_pte_comptagline_s(void) 251static inline u32 gmmu_pte_comptagline_s(void)
252{ 252{
253 return 17; 253 return 17U;
254} 254}
255static inline u32 gmmu_pte_comptagline_f(u32 v) 255static inline u32 gmmu_pte_comptagline_f(u32 v)
256{ 256{
257 return (v & 0x1ffff) << 12; 257 return (v & 0x1ffffU) << 12U;
258} 258}
259static inline u32 gmmu_pte_comptagline_w(void) 259static inline u32 gmmu_pte_comptagline_w(void)
260{ 260{
261 return 1; 261 return 1U;
262} 262}
263static inline u32 gmmu_pte_address_shift_v(void) 263static inline u32 gmmu_pte_address_shift_v(void)
264{ 264{
265 return 0x0000000c; 265 return 0x0000000cU;
266} 266}
267static inline u32 gmmu_pte_kind_f(u32 v) 267static inline u32 gmmu_pte_kind_f(u32 v)
268{ 268{
269 return (v & 0xff) << 4; 269 return (v & 0xffU) << 4U;
270} 270}
271static inline u32 gmmu_pte_kind_w(void) 271static inline u32 gmmu_pte_kind_w(void)
272{ 272{
273 return 1; 273 return 1U;
274} 274}
275static inline u32 gmmu_pte_kind_invalid_v(void) 275static inline u32 gmmu_pte_kind_invalid_v(void)
276{ 276{
277 return 0x000000ff; 277 return 0x000000ffU;
278} 278}
279static inline u32 gmmu_pte_kind_pitch_v(void) 279static inline u32 gmmu_pte_kind_pitch_v(void)
280{ 280{
281 return 0x00000000; 281 return 0x00000000U;
282} 282}
283static inline u32 gmmu_pte_kind_z16_v(void) 283static inline u32 gmmu_pte_kind_z16_v(void)
284{ 284{
285 return 0x00000001; 285 return 0x00000001U;
286} 286}
287static inline u32 gmmu_pte_kind_z16_2c_v(void) 287static inline u32 gmmu_pte_kind_z16_2c_v(void)
288{ 288{
289 return 0x00000002; 289 return 0x00000002U;
290} 290}
291static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) 291static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void)
292{ 292{
293 return 0x00000003; 293 return 0x00000003U;
294} 294}
295static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) 295static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void)
296{ 296{
297 return 0x00000004; 297 return 0x00000004U;
298} 298}
299static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) 299static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void)
300{ 300{
301 return 0x00000005; 301 return 0x00000005U;
302} 302}
303static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) 303static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void)
304{ 304{
305 return 0x00000006; 305 return 0x00000006U;
306} 306}
307static inline u32 gmmu_pte_kind_z16_2z_v(void) 307static inline u32 gmmu_pte_kind_z16_2z_v(void)
308{ 308{
309 return 0x00000007; 309 return 0x00000007U;
310} 310}
311static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) 311static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void)
312{ 312{
313 return 0x00000008; 313 return 0x00000008U;
314} 314}
315static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) 315static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void)
316{ 316{
317 return 0x00000009; 317 return 0x00000009U;
318} 318}
319static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) 319static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void)
320{ 320{
321 return 0x0000000a; 321 return 0x0000000aU;
322} 322}
323static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) 323static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void)
324{ 324{
325 return 0x0000000b; 325 return 0x0000000bU;
326} 326}
327static inline u32 gmmu_pte_kind_z16_4cz_v(void) 327static inline u32 gmmu_pte_kind_z16_4cz_v(void)
328{ 328{
329 return 0x0000000c; 329 return 0x0000000cU;
330} 330}
331static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void) 331static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void)
332{ 332{
333 return 0x0000000d; 333 return 0x0000000dU;
334} 334}
335static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void) 335static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void)
336{ 336{
337 return 0x0000000e; 337 return 0x0000000eU;
338} 338}
339static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void) 339static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void)
340{ 340{
341 return 0x0000000f; 341 return 0x0000000fU;
342} 342}
343static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void) 343static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void)
344{ 344{
345 return 0x00000010; 345 return 0x00000010U;
346} 346}
347static inline u32 gmmu_pte_kind_s8z24_v(void) 347static inline u32 gmmu_pte_kind_s8z24_v(void)
348{ 348{
349 return 0x00000011; 349 return 0x00000011U;
350} 350}
351static inline u32 gmmu_pte_kind_s8z24_1z_v(void) 351static inline u32 gmmu_pte_kind_s8z24_1z_v(void)
352{ 352{
353 return 0x00000012; 353 return 0x00000012U;
354} 354}
355static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) 355static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void)
356{ 356{
357 return 0x00000013; 357 return 0x00000013U;
358} 358}
359static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) 359static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void)
360{ 360{
361 return 0x00000014; 361 return 0x00000014U;
362} 362}
363static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) 363static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void)
364{ 364{
365 return 0x00000015; 365 return 0x00000015U;
366} 366}
367static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) 367static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void)
368{ 368{
369 return 0x00000016; 369 return 0x00000016U;
370} 370}
371static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) 371static inline u32 gmmu_pte_kind_s8z24_2cz_v(void)
372{ 372{
373 return 0x00000017; 373 return 0x00000017U;
374} 374}
375static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) 375static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void)
376{ 376{
377 return 0x00000018; 377 return 0x00000018U;
378} 378}
379static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) 379static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void)
380{ 380{
381 return 0x00000019; 381 return 0x00000019U;
382} 382}
383static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) 383static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void)
384{ 384{
385 return 0x0000001a; 385 return 0x0000001aU;
386} 386}
387static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) 387static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void)
388{ 388{
389 return 0x0000001b; 389 return 0x0000001bU;
390} 390}
391static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) 391static inline u32 gmmu_pte_kind_s8z24_2cs_v(void)
392{ 392{
393 return 0x0000001c; 393 return 0x0000001cU;
394} 394}
395static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) 395static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void)
396{ 396{
397 return 0x0000001d; 397 return 0x0000001dU;
398} 398}
399static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) 399static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void)
400{ 400{
401 return 0x0000001e; 401 return 0x0000001eU;
402} 402}
403static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) 403static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void)
404{ 404{
405 return 0x0000001f; 405 return 0x0000001fU;
406} 406}
407static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) 407static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void)
408{ 408{
409 return 0x00000020; 409 return 0x00000020U;
410} 410}
411static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) 411static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void)
412{ 412{
413 return 0x00000021; 413 return 0x00000021U;
414} 414}
415static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) 415static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void)
416{ 416{
417 return 0x00000022; 417 return 0x00000022U;
418} 418}
419static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) 419static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void)
420{ 420{
421 return 0x00000023; 421 return 0x00000023U;
422} 422}
423static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) 423static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void)
424{ 424{
425 return 0x00000024; 425 return 0x00000024U;
426} 426}
427static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) 427static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void)
428{ 428{
429 return 0x00000025; 429 return 0x00000025U;
430} 430}
431static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) 431static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void)
432{ 432{
433 return 0x00000026; 433 return 0x00000026U;
434} 434}
435static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) 435static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void)
436{ 436{
437 return 0x00000027; 437 return 0x00000027U;
438} 438}
439static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) 439static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void)
440{ 440{
441 return 0x00000028; 441 return 0x00000028U;
442} 442}
443static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) 443static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void)
444{ 444{
445 return 0x00000029; 445 return 0x00000029U;
446} 446}
447static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) 447static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void)
448{ 448{
449 return 0x0000002e; 449 return 0x0000002eU;
450} 450}
451static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) 451static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void)
452{ 452{
453 return 0x0000002f; 453 return 0x0000002fU;
454} 454}
455static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) 455static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void)
456{ 456{
457 return 0x00000030; 457 return 0x00000030U;
458} 458}
459static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) 459static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void)
460{ 460{
461 return 0x00000031; 461 return 0x00000031U;
462} 462}
463static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) 463static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void)
464{ 464{
465 return 0x00000032; 465 return 0x00000032U;
466} 466}
467static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) 467static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void)
468{ 468{
469 return 0x00000033; 469 return 0x00000033U;
470} 470}
471static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) 471static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void)
472{ 472{
473 return 0x00000034; 473 return 0x00000034U;
474} 474}
475static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) 475static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void)
476{ 476{
477 return 0x00000035; 477 return 0x00000035U;
478} 478}
479static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) 479static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void)
480{ 480{
481 return 0x0000003a; 481 return 0x0000003aU;
482} 482}
483static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) 483static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void)
484{ 484{
485 return 0x0000003b; 485 return 0x0000003bU;
486} 486}
487static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) 487static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void)
488{ 488{
489 return 0x0000003c; 489 return 0x0000003cU;
490} 490}
491static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) 491static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void)
492{ 492{
493 return 0x0000003d; 493 return 0x0000003dU;
494} 494}
495static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) 495static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void)
496{ 496{
497 return 0x0000003e; 497 return 0x0000003eU;
498} 498}
499static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) 499static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void)
500{ 500{
501 return 0x0000003f; 501 return 0x0000003fU;
502} 502}
503static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) 503static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void)
504{ 504{
505 return 0x00000040; 505 return 0x00000040U;
506} 506}
507static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) 507static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void)
508{ 508{
509 return 0x00000041; 509 return 0x00000041U;
510} 510}
511static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) 511static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void)
512{ 512{
513 return 0x00000042; 513 return 0x00000042U;
514} 514}
515static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) 515static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void)
516{ 516{
517 return 0x00000043; 517 return 0x00000043U;
518} 518}
519static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) 519static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void)
520{ 520{
521 return 0x00000044; 521 return 0x00000044U;
522} 522}
523static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) 523static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void)
524{ 524{
525 return 0x00000045; 525 return 0x00000045U;
526} 526}
527static inline u32 gmmu_pte_kind_z24s8_v(void) 527static inline u32 gmmu_pte_kind_z24s8_v(void)
528{ 528{
529 return 0x00000046; 529 return 0x00000046U;
530} 530}
531static inline u32 gmmu_pte_kind_z24s8_1z_v(void) 531static inline u32 gmmu_pte_kind_z24s8_1z_v(void)
532{ 532{
533 return 0x00000047; 533 return 0x00000047U;
534} 534}
535static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) 535static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void)
536{ 536{
537 return 0x00000048; 537 return 0x00000048U;
538} 538}
539static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) 539static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void)
540{ 540{
541 return 0x00000049; 541 return 0x00000049U;
542} 542}
543static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) 543static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void)
544{ 544{
545 return 0x0000004a; 545 return 0x0000004aU;
546} 546}
547static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) 547static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void)
548{ 548{
549 return 0x0000004b; 549 return 0x0000004bU;
550} 550}
551static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) 551static inline u32 gmmu_pte_kind_z24s8_2cs_v(void)
552{ 552{
553 return 0x0000004c; 553 return 0x0000004cU;
554} 554}
555static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) 555static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void)
556{ 556{
557 return 0x0000004d; 557 return 0x0000004dU;
558} 558}
559static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) 559static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void)
560{ 560{
561 return 0x0000004e; 561 return 0x0000004eU;
562} 562}
563static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) 563static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void)
564{ 564{
565 return 0x0000004f; 565 return 0x0000004fU;
566} 566}
567static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) 567static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void)
568{ 568{
569 return 0x00000050; 569 return 0x00000050U;
570} 570}
571static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) 571static inline u32 gmmu_pte_kind_z24s8_2cz_v(void)
572{ 572{
573 return 0x00000051; 573 return 0x00000051U;
574} 574}
575static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) 575static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void)
576{ 576{
577 return 0x00000052; 577 return 0x00000052U;
578} 578}
579static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) 579static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void)
580{ 580{
581 return 0x00000053; 581 return 0x00000053U;
582} 582}
583static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) 583static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void)
584{ 584{
585 return 0x00000054; 585 return 0x00000054U;
586} 586}
587static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) 587static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void)
588{ 588{
589 return 0x00000055; 589 return 0x00000055U;
590} 590}
591static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) 591static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void)
592{ 592{
593 return 0x00000056; 593 return 0x00000056U;
594} 594}
595static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) 595static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void)
596{ 596{
597 return 0x00000057; 597 return 0x00000057U;
598} 598}
599static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) 599static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void)
600{ 600{
601 return 0x00000058; 601 return 0x00000058U;
602} 602}
603static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) 603static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void)
604{ 604{
605 return 0x00000059; 605 return 0x00000059U;
606} 606}
607static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) 607static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void)
608{ 608{
609 return 0x0000005a; 609 return 0x0000005aU;
610} 610}
611static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) 611static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void)
612{ 612{
613 return 0x0000005b; 613 return 0x0000005bU;
614} 614}
615static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) 615static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void)
616{ 616{
617 return 0x0000005c; 617 return 0x0000005cU;
618} 618}
619static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) 619static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void)
620{ 620{
621 return 0x0000005d; 621 return 0x0000005dU;
622} 622}
623static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) 623static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void)
624{ 624{
625 return 0x0000005e; 625 return 0x0000005eU;
626} 626}
627static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) 627static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void)
628{ 628{
629 return 0x00000063; 629 return 0x00000063U;
630} 630}
631static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) 631static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void)
632{ 632{
633 return 0x00000064; 633 return 0x00000064U;
634} 634}
635static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) 635static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void)
636{ 636{
637 return 0x00000065; 637 return 0x00000065U;
638} 638}
639static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) 639static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void)
640{ 640{
641 return 0x00000066; 641 return 0x00000066U;
642} 642}
643static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) 643static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void)
644{ 644{
645 return 0x00000067; 645 return 0x00000067U;
646} 646}
647static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) 647static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void)
648{ 648{
649 return 0x00000068; 649 return 0x00000068U;
650} 650}
651static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) 651static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void)
652{ 652{
653 return 0x00000069; 653 return 0x00000069U;
654} 654}
655static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) 655static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void)
656{ 656{
657 return 0x0000006a; 657 return 0x0000006aU;
658} 658}
659static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) 659static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void)
660{ 660{
661 return 0x0000006f; 661 return 0x0000006fU;
662} 662}
663static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) 663static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void)
664{ 664{
665 return 0x00000070; 665 return 0x00000070U;
666} 666}
667static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) 667static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void)
668{ 668{
669 return 0x00000071; 669 return 0x00000071U;
670} 670}
671static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) 671static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void)
672{ 672{
673 return 0x00000072; 673 return 0x00000072U;
674} 674}
675static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) 675static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void)
676{ 676{
677 return 0x00000073; 677 return 0x00000073U;
678} 678}
679static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) 679static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void)
680{ 680{
681 return 0x00000074; 681 return 0x00000074U;
682} 682}
683static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) 683static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void)
684{ 684{
685 return 0x00000075; 685 return 0x00000075U;
686} 686}
687static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) 687static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void)
688{ 688{
689 return 0x00000076; 689 return 0x00000076U;
690} 690}
691static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) 691static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void)
692{ 692{
693 return 0x00000077; 693 return 0x00000077U;
694} 694}
695static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) 695static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void)
696{ 696{
697 return 0x00000078; 697 return 0x00000078U;
698} 698}
699static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) 699static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void)
700{ 700{
701 return 0x00000079; 701 return 0x00000079U;
702} 702}
703static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) 703static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void)
704{ 704{
705 return 0x0000007a; 705 return 0x0000007aU;
706} 706}
707static inline u32 gmmu_pte_kind_zf32_v(void) 707static inline u32 gmmu_pte_kind_zf32_v(void)
708{ 708{
709 return 0x0000007b; 709 return 0x0000007bU;
710} 710}
711static inline u32 gmmu_pte_kind_zf32_1z_v(void) 711static inline u32 gmmu_pte_kind_zf32_1z_v(void)
712{ 712{
713 return 0x0000007c; 713 return 0x0000007cU;
714} 714}
715static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) 715static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void)
716{ 716{
717 return 0x0000007d; 717 return 0x0000007dU;
718} 718}
719static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) 719static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void)
720{ 720{
721 return 0x0000007e; 721 return 0x0000007eU;
722} 722}
723static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) 723static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void)
724{ 724{
725 return 0x0000007f; 725 return 0x0000007fU;
726} 726}
727static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) 727static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void)
728{ 728{
729 return 0x00000080; 729 return 0x00000080U;
730} 730}
731static inline u32 gmmu_pte_kind_zf32_2cs_v(void) 731static inline u32 gmmu_pte_kind_zf32_2cs_v(void)
732{ 732{
733 return 0x00000081; 733 return 0x00000081U;
734} 734}
735static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) 735static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void)
736{ 736{
737 return 0x00000082; 737 return 0x00000082U;
738} 738}
739static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) 739static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void)
740{ 740{
741 return 0x00000083; 741 return 0x00000083U;
742} 742}
743static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) 743static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void)
744{ 744{
745 return 0x00000084; 745 return 0x00000084U;
746} 746}
747static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) 747static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void)
748{ 748{
749 return 0x00000085; 749 return 0x00000085U;
750} 750}
751static inline u32 gmmu_pte_kind_zf32_2cz_v(void) 751static inline u32 gmmu_pte_kind_zf32_2cz_v(void)
752{ 752{
753 return 0x00000086; 753 return 0x00000086U;
754} 754}
755static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) 755static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void)
756{ 756{
757 return 0x00000087; 757 return 0x00000087U;
758} 758}
759static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) 759static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void)
760{ 760{
761 return 0x00000088; 761 return 0x00000088U;
762} 762}
763static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) 763static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void)
764{ 764{
765 return 0x00000089; 765 return 0x00000089U;
766} 766}
767static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) 767static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void)
768{ 768{
769 return 0x0000008a; 769 return 0x0000008aU;
770} 770}
771static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) 771static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void)
772{ 772{
773 return 0x0000008b; 773 return 0x0000008bU;
774} 774}
775static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) 775static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void)
776{ 776{
777 return 0x0000008c; 777 return 0x0000008cU;
778} 778}
779static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) 779static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void)
780{ 780{
781 return 0x0000008d; 781 return 0x0000008dU;
782} 782}
783static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) 783static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void)
784{ 784{
785 return 0x0000008e; 785 return 0x0000008eU;
786} 786}
787static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) 787static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void)
788{ 788{
789 return 0x0000008f; 789 return 0x0000008fU;
790} 790}
791static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) 791static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void)
792{ 792{
793 return 0x00000090; 793 return 0x00000090U;
794} 794}
795static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) 795static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void)
796{ 796{
797 return 0x00000091; 797 return 0x00000091U;
798} 798}
799static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) 799static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void)
800{ 800{
801 return 0x00000092; 801 return 0x00000092U;
802} 802}
803static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) 803static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void)
804{ 804{
805 return 0x00000097; 805 return 0x00000097U;
806} 806}
807static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) 807static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void)
808{ 808{
809 return 0x00000098; 809 return 0x00000098U;
810} 810}
811static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) 811static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void)
812{ 812{
813 return 0x00000099; 813 return 0x00000099U;
814} 814}
815static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) 815static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void)
816{ 816{
817 return 0x0000009a; 817 return 0x0000009aU;
818} 818}
819static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) 819static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void)
820{ 820{
821 return 0x0000009b; 821 return 0x0000009bU;
822} 822}
823static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) 823static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void)
824{ 824{
825 return 0x0000009c; 825 return 0x0000009cU;
826} 826}
827static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) 827static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void)
828{ 828{
829 return 0x0000009d; 829 return 0x0000009dU;
830} 830}
831static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) 831static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void)
832{ 832{
833 return 0x0000009e; 833 return 0x0000009eU;
834} 834}
835static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) 835static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void)
836{ 836{
837 return 0x0000009f; 837 return 0x0000009fU;
838} 838}
839static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) 839static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void)
840{ 840{
841 return 0x000000a0; 841 return 0x000000a0U;
842} 842}
843static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) 843static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void)
844{ 844{
845 return 0x000000a1; 845 return 0x000000a1U;
846} 846}
847static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) 847static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void)
848{ 848{
849 return 0x000000a2; 849 return 0x000000a2U;
850} 850}
851static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) 851static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void)
852{ 852{
853 return 0x000000a3; 853 return 0x000000a3U;
854} 854}
855static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) 855static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void)
856{ 856{
857 return 0x000000a4; 857 return 0x000000a4U;
858} 858}
859static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) 859static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void)
860{ 860{
861 return 0x000000a5; 861 return 0x000000a5U;
862} 862}
863static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) 863static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void)
864{ 864{
865 return 0x000000a6; 865 return 0x000000a6U;
866} 866}
867static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) 867static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void)
868{ 868{
869 return 0x000000a7; 869 return 0x000000a7U;
870} 870}
871static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) 871static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void)
872{ 872{
873 return 0x000000a8; 873 return 0x000000a8U;
874} 874}
875static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) 875static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void)
876{ 876{
877 return 0x000000a9; 877 return 0x000000a9U;
878} 878}
879static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) 879static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void)
880{ 880{
881 return 0x000000aa; 881 return 0x000000aaU;
882} 882}
883static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) 883static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void)
884{ 884{
885 return 0x000000ab; 885 return 0x000000abU;
886} 886}
887static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) 887static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void)
888{ 888{
889 return 0x000000ac; 889 return 0x000000acU;
890} 890}
891static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) 891static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void)
892{ 892{
893 return 0x000000ad; 893 return 0x000000adU;
894} 894}
895static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) 895static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void)
896{ 896{
897 return 0x000000ae; 897 return 0x000000aeU;
898} 898}
899static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) 899static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void)
900{ 900{
901 return 0x000000b3; 901 return 0x000000b3U;
902} 902}
903static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) 903static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void)
904{ 904{
905 return 0x000000b4; 905 return 0x000000b4U;
906} 906}
907static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) 907static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void)
908{ 908{
909 return 0x000000b5; 909 return 0x000000b5U;
910} 910}
911static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) 911static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void)
912{ 912{
913 return 0x000000b6; 913 return 0x000000b6U;
914} 914}
915static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) 915static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void)
916{ 916{
917 return 0x000000b7; 917 return 0x000000b7U;
918} 918}
919static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) 919static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void)
920{ 920{
921 return 0x000000b8; 921 return 0x000000b8U;
922} 922}
923static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) 923static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void)
924{ 924{
925 return 0x000000b9; 925 return 0x000000b9U;
926} 926}
927static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) 927static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void)
928{ 928{
929 return 0x000000ba; 929 return 0x000000baU;
930} 930}
931static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) 931static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void)
932{ 932{
933 return 0x000000bb; 933 return 0x000000bbU;
934} 934}
935static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) 935static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void)
936{ 936{
937 return 0x000000bc; 937 return 0x000000bcU;
938} 938}
939static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) 939static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void)
940{ 940{
941 return 0x000000bd; 941 return 0x000000bdU;
942} 942}
943static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) 943static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void)
944{ 944{
945 return 0x000000be; 945 return 0x000000beU;
946} 946}
947static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) 947static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void)
948{ 948{
949 return 0x000000bf; 949 return 0x000000bfU;
950} 950}
951static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) 951static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void)
952{ 952{
953 return 0x000000c0; 953 return 0x000000c0U;
954} 954}
955static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) 955static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void)
956{ 956{
957 return 0x000000c1; 957 return 0x000000c1U;
958} 958}
959static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) 959static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void)
960{ 960{
961 return 0x000000c2; 961 return 0x000000c2U;
962} 962}
963static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) 963static inline u32 gmmu_pte_kind_zf32_x24s8_v(void)
964{ 964{
965 return 0x000000c3; 965 return 0x000000c3U;
966} 966}
967static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) 967static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void)
968{ 968{
969 return 0x000000c4; 969 return 0x000000c4U;
970} 970}
971static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) 971static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void)
972{ 972{
973 return 0x000000c5; 973 return 0x000000c5U;
974} 974}
975static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) 975static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void)
976{ 976{
977 return 0x000000c6; 977 return 0x000000c6U;
978} 978}
979static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) 979static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void)
980{ 980{
981 return 0x000000c7; 981 return 0x000000c7U;
982} 982}
983static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) 983static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void)
984{ 984{
985 return 0x000000c8; 985 return 0x000000c8U;
986} 986}
987static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) 987static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void)
988{ 988{
989 return 0x000000ce; 989 return 0x000000ceU;
990} 990}
991static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) 991static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void)
992{ 992{
993 return 0x000000cf; 993 return 0x000000cfU;
994} 994}
995static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) 995static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void)
996{ 996{
997 return 0x000000d0; 997 return 0x000000d0U;
998} 998}
999static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) 999static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void)
1000{ 1000{
1001 return 0x000000d1; 1001 return 0x000000d1U;
1002} 1002}
1003static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) 1003static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void)
1004{ 1004{
1005 return 0x000000d2; 1005 return 0x000000d2U;
1006} 1006}
1007static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) 1007static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void)
1008{ 1008{
1009 return 0x000000d3; 1009 return 0x000000d3U;
1010} 1010}
1011static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) 1011static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void)
1012{ 1012{
1013 return 0x000000d4; 1013 return 0x000000d4U;
1014} 1014}
1015static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) 1015static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void)
1016{ 1016{
1017 return 0x000000d5; 1017 return 0x000000d5U;
1018} 1018}
1019static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) 1019static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void)
1020{ 1020{
1021 return 0x000000d6; 1021 return 0x000000d6U;
1022} 1022}
1023static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) 1023static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void)
1024{ 1024{
1025 return 0x000000d7; 1025 return 0x000000d7U;
1026} 1026}
1027static inline u32 gmmu_pte_kind_generic_16bx2_v(void) 1027static inline u32 gmmu_pte_kind_generic_16bx2_v(void)
1028{ 1028{
1029 return 0x000000fe; 1029 return 0x000000feU;
1030} 1030}
1031static inline u32 gmmu_pte_kind_c32_2c_v(void) 1031static inline u32 gmmu_pte_kind_c32_2c_v(void)
1032{ 1032{
1033 return 0x000000d8; 1033 return 0x000000d8U;
1034} 1034}
1035static inline u32 gmmu_pte_kind_c32_2cbr_v(void) 1035static inline u32 gmmu_pte_kind_c32_2cbr_v(void)
1036{ 1036{
1037 return 0x000000d9; 1037 return 0x000000d9U;
1038} 1038}
1039static inline u32 gmmu_pte_kind_c32_2cba_v(void) 1039static inline u32 gmmu_pte_kind_c32_2cba_v(void)
1040{ 1040{
1041 return 0x000000da; 1041 return 0x000000daU;
1042} 1042}
1043static inline u32 gmmu_pte_kind_c32_2cra_v(void) 1043static inline u32 gmmu_pte_kind_c32_2cra_v(void)
1044{ 1044{
1045 return 0x000000db; 1045 return 0x000000dbU;
1046} 1046}
1047static inline u32 gmmu_pte_kind_c32_2bra_v(void) 1047static inline u32 gmmu_pte_kind_c32_2bra_v(void)
1048{ 1048{
1049 return 0x000000dc; 1049 return 0x000000dcU;
1050} 1050}
1051static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) 1051static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void)
1052{ 1052{
1053 return 0x000000dd; 1053 return 0x000000ddU;
1054} 1054}
1055static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) 1055static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void)
1056{ 1056{
1057 return 0x000000de; 1057 return 0x000000deU;
1058} 1058}
1059static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void) 1059static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void)
1060{ 1060{
1061 return 0x000000cc; 1061 return 0x000000ccU;
1062} 1062}
1063static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) 1063static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void)
1064{ 1064{
1065 return 0x000000df; 1065 return 0x000000dfU;
1066} 1066}
1067static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) 1067static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void)
1068{ 1068{
1069 return 0x000000e0; 1069 return 0x000000e0U;
1070} 1070}
1071static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) 1071static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void)
1072{ 1072{
1073 return 0x000000e1; 1073 return 0x000000e1U;
1074} 1074}
1075static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) 1075static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void)
1076{ 1076{
1077 return 0x000000e2; 1077 return 0x000000e2U;
1078} 1078}
1079static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) 1079static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void)
1080{ 1080{
1081 return 0x000000e3; 1081 return 0x000000e3U;
1082} 1082}
1083static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) 1083static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void)
1084{ 1084{
1085 return 0x000000e4; 1085 return 0x000000e4U;
1086} 1086}
1087static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) 1087static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void)
1088{ 1088{
1089 return 0x000000e5; 1089 return 0x000000e5U;
1090} 1090}
1091static inline u32 gmmu_pte_kind_c64_2c_v(void) 1091static inline u32 gmmu_pte_kind_c64_2c_v(void)
1092{ 1092{
1093 return 0x000000e6; 1093 return 0x000000e6U;
1094} 1094}
1095static inline u32 gmmu_pte_kind_c64_2cbr_v(void) 1095static inline u32 gmmu_pte_kind_c64_2cbr_v(void)
1096{ 1096{
1097 return 0x000000e7; 1097 return 0x000000e7U;
1098} 1098}
1099static inline u32 gmmu_pte_kind_c64_2cba_v(void) 1099static inline u32 gmmu_pte_kind_c64_2cba_v(void)
1100{ 1100{
1101 return 0x000000e8; 1101 return 0x000000e8U;
1102} 1102}
1103static inline u32 gmmu_pte_kind_c64_2cra_v(void) 1103static inline u32 gmmu_pte_kind_c64_2cra_v(void)
1104{ 1104{
1105 return 0x000000e9; 1105 return 0x000000e9U;
1106} 1106}
1107static inline u32 gmmu_pte_kind_c64_2bra_v(void) 1107static inline u32 gmmu_pte_kind_c64_2bra_v(void)
1108{ 1108{
1109 return 0x000000ea; 1109 return 0x000000eaU;
1110} 1110}
1111static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) 1111static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void)
1112{ 1112{
1113 return 0x000000eb; 1113 return 0x000000ebU;
1114} 1114}
1115static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) 1115static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void)
1116{ 1116{
1117 return 0x000000ec; 1117 return 0x000000ecU;
1118} 1118}
1119static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void) 1119static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void)
1120{ 1120{
1121 return 0x000000cd; 1121 return 0x000000cdU;
1122} 1122}
1123static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) 1123static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void)
1124{ 1124{
1125 return 0x000000ed; 1125 return 0x000000edU;
1126} 1126}
1127static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) 1127static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void)
1128{ 1128{
1129 return 0x000000ee; 1129 return 0x000000eeU;
1130} 1130}
1131static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) 1131static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void)
1132{ 1132{
1133 return 0x000000ef; 1133 return 0x000000efU;
1134} 1134}
1135static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) 1135static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void)
1136{ 1136{
1137 return 0x000000f0; 1137 return 0x000000f0U;
1138} 1138}
1139static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) 1139static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void)
1140{ 1140{
1141 return 0x000000f1; 1141 return 0x000000f1U;
1142} 1142}
1143static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) 1143static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void)
1144{ 1144{
1145 return 0x000000f2; 1145 return 0x000000f2U;
1146} 1146}
1147static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) 1147static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void)
1148{ 1148{
1149 return 0x000000f3; 1149 return 0x000000f3U;
1150} 1150}
1151static inline u32 gmmu_pte_kind_c128_2c_v(void) 1151static inline u32 gmmu_pte_kind_c128_2c_v(void)
1152{ 1152{
1153 return 0x000000f4; 1153 return 0x000000f4U;
1154} 1154}
1155static inline u32 gmmu_pte_kind_c128_2cr_v(void) 1155static inline u32 gmmu_pte_kind_c128_2cr_v(void)
1156{ 1156{
1157 return 0x000000f5; 1157 return 0x000000f5U;
1158} 1158}
1159static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) 1159static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void)
1160{ 1160{
1161 return 0x000000f6; 1161 return 0x000000f6U;
1162} 1162}
1163static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) 1163static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void)
1164{ 1164{
1165 return 0x000000f7; 1165 return 0x000000f7U;
1166} 1166}
1167static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) 1167static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void)
1168{ 1168{
1169 return 0x000000f8; 1169 return 0x000000f8U;
1170} 1170}
1171static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) 1171static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void)
1172{ 1172{
1173 return 0x000000f9; 1173 return 0x000000f9U;
1174} 1174}
1175static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) 1175static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void)
1176{ 1176{
1177 return 0x000000fa; 1177 return 0x000000faU;
1178} 1178}
1179static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) 1179static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void)
1180{ 1180{
1181 return 0x000000fb; 1181 return 0x000000fbU;
1182} 1182}
1183static inline u32 gmmu_pte_kind_x8c24_v(void) 1183static inline u32 gmmu_pte_kind_x8c24_v(void)
1184{ 1184{
1185 return 0x000000fc; 1185 return 0x000000fcU;
1186} 1186}
1187static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) 1187static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void)
1188{ 1188{
1189 return 0x000000fd; 1189 return 0x000000fdU;
1190} 1190}
1191static inline u32 gmmu_pte_kind_smsked_message_v(void) 1191static inline u32 gmmu_pte_kind_smsked_message_v(void)
1192{ 1192{
1193 return 0x000000ca; 1193 return 0x000000caU;
1194} 1194}
1195static inline u32 gmmu_pte_kind_smhost_message_v(void) 1195static inline u32 gmmu_pte_kind_smhost_message_v(void)
1196{ 1196{
1197 return 0x000000cb; 1197 return 0x000000cbU;
1198} 1198}
1199static inline u32 gmmu_pte_kind_s8_v(void) 1199static inline u32 gmmu_pte_kind_s8_v(void)
1200{ 1200{
1201 return 0x0000002a; 1201 return 0x0000002aU;
1202} 1202}
1203static inline u32 gmmu_pte_kind_s8_2s_v(void) 1203static inline u32 gmmu_pte_kind_s8_2s_v(void)
1204{ 1204{
1205 return 0x0000002b; 1205 return 0x0000002bU;
1206} 1206}
1207#endif 1207#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
index 763e04e3..e2877566 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h
@@ -58,3810 +58,3810 @@
58 58
59static inline u32 gr_intr_r(void) 59static inline u32 gr_intr_r(void)
60{ 60{
61 return 0x00400100; 61 return 0x00400100U;
62} 62}
63static inline u32 gr_intr_notify_pending_f(void) 63static inline u32 gr_intr_notify_pending_f(void)
64{ 64{
65 return 0x1; 65 return 0x1U;
66} 66}
67static inline u32 gr_intr_notify_reset_f(void) 67static inline u32 gr_intr_notify_reset_f(void)
68{ 68{
69 return 0x1; 69 return 0x1U;
70} 70}
71static inline u32 gr_intr_semaphore_pending_f(void) 71static inline u32 gr_intr_semaphore_pending_f(void)
72{ 72{
73 return 0x2; 73 return 0x2U;
74} 74}
75static inline u32 gr_intr_semaphore_reset_f(void) 75static inline u32 gr_intr_semaphore_reset_f(void)
76{ 76{
77 return 0x2; 77 return 0x2U;
78} 78}
79static inline u32 gr_intr_illegal_method_pending_f(void) 79static inline u32 gr_intr_illegal_method_pending_f(void)
80{ 80{
81 return 0x10; 81 return 0x10U;
82} 82}
83static inline u32 gr_intr_illegal_method_reset_f(void) 83static inline u32 gr_intr_illegal_method_reset_f(void)
84{ 84{
85 return 0x10; 85 return 0x10U;
86} 86}
87static inline u32 gr_intr_illegal_notify_pending_f(void) 87static inline u32 gr_intr_illegal_notify_pending_f(void)
88{ 88{
89 return 0x40; 89 return 0x40U;
90} 90}
91static inline u32 gr_intr_illegal_notify_reset_f(void) 91static inline u32 gr_intr_illegal_notify_reset_f(void)
92{ 92{
93 return 0x40; 93 return 0x40U;
94} 94}
95static inline u32 gr_intr_firmware_method_f(u32 v) 95static inline u32 gr_intr_firmware_method_f(u32 v)
96{ 96{
97 return (v & 0x1) << 8; 97 return (v & 0x1U) << 8U;
98} 98}
99static inline u32 gr_intr_firmware_method_pending_f(void) 99static inline u32 gr_intr_firmware_method_pending_f(void)
100{ 100{
101 return 0x100; 101 return 0x100U;
102} 102}
103static inline u32 gr_intr_firmware_method_reset_f(void) 103static inline u32 gr_intr_firmware_method_reset_f(void)
104{ 104{
105 return 0x100; 105 return 0x100U;
106} 106}
107static inline u32 gr_intr_illegal_class_pending_f(void) 107static inline u32 gr_intr_illegal_class_pending_f(void)
108{ 108{
109 return 0x20; 109 return 0x20U;
110} 110}
111static inline u32 gr_intr_illegal_class_reset_f(void) 111static inline u32 gr_intr_illegal_class_reset_f(void)
112{ 112{
113 return 0x20; 113 return 0x20U;
114} 114}
115static inline u32 gr_intr_fecs_error_pending_f(void) 115static inline u32 gr_intr_fecs_error_pending_f(void)
116{ 116{
117 return 0x80000; 117 return 0x80000U;
118} 118}
119static inline u32 gr_intr_fecs_error_reset_f(void) 119static inline u32 gr_intr_fecs_error_reset_f(void)
120{ 120{
121 return 0x80000; 121 return 0x80000U;
122} 122}
123static inline u32 gr_intr_class_error_pending_f(void) 123static inline u32 gr_intr_class_error_pending_f(void)
124{ 124{
125 return 0x100000; 125 return 0x100000U;
126} 126}
127static inline u32 gr_intr_class_error_reset_f(void) 127static inline u32 gr_intr_class_error_reset_f(void)
128{ 128{
129 return 0x100000; 129 return 0x100000U;
130} 130}
131static inline u32 gr_intr_exception_pending_f(void) 131static inline u32 gr_intr_exception_pending_f(void)
132{ 132{
133 return 0x200000; 133 return 0x200000U;
134} 134}
135static inline u32 gr_intr_exception_reset_f(void) 135static inline u32 gr_intr_exception_reset_f(void)
136{ 136{
137 return 0x200000; 137 return 0x200000U;
138} 138}
139static inline u32 gr_fecs_intr_r(void) 139static inline u32 gr_fecs_intr_r(void)
140{ 140{
141 return 0x00400144; 141 return 0x00400144U;
142} 142}
143static inline u32 gr_class_error_r(void) 143static inline u32 gr_class_error_r(void)
144{ 144{
145 return 0x00400110; 145 return 0x00400110U;
146} 146}
147static inline u32 gr_class_error_code_v(u32 r) 147static inline u32 gr_class_error_code_v(u32 r)
148{ 148{
149 return (r >> 0) & 0xffff; 149 return (r >> 0U) & 0xffffU;
150} 150}
151static inline u32 gr_intr_nonstall_r(void) 151static inline u32 gr_intr_nonstall_r(void)
152{ 152{
153 return 0x00400120; 153 return 0x00400120U;
154} 154}
155static inline u32 gr_intr_nonstall_trap_pending_f(void) 155static inline u32 gr_intr_nonstall_trap_pending_f(void)
156{ 156{
157 return 0x2; 157 return 0x2U;
158} 158}
159static inline u32 gr_intr_en_r(void) 159static inline u32 gr_intr_en_r(void)
160{ 160{
161 return 0x0040013c; 161 return 0x0040013cU;
162} 162}
163static inline u32 gr_exception_r(void) 163static inline u32 gr_exception_r(void)
164{ 164{
165 return 0x00400108; 165 return 0x00400108U;
166} 166}
167static inline u32 gr_exception_fe_m(void) 167static inline u32 gr_exception_fe_m(void)
168{ 168{
169 return 0x1 << 0; 169 return 0x1U << 0U;
170} 170}
171static inline u32 gr_exception_gpc_m(void) 171static inline u32 gr_exception_gpc_m(void)
172{ 172{
173 return 0x1 << 24; 173 return 0x1U << 24U;
174} 174}
175static inline u32 gr_exception_memfmt_m(void) 175static inline u32 gr_exception_memfmt_m(void)
176{ 176{
177 return 0x1 << 1; 177 return 0x1U << 1U;
178} 178}
179static inline u32 gr_exception_ds_m(void) 179static inline u32 gr_exception_ds_m(void)
180{ 180{
181 return 0x1 << 4; 181 return 0x1U << 4U;
182} 182}
183static inline u32 gr_exception_sked_m(void) 183static inline u32 gr_exception_sked_m(void)
184{ 184{
185 return 0x1 << 8; 185 return 0x1U << 8U;
186} 186}
187static inline u32 gr_exception1_r(void) 187static inline u32 gr_exception1_r(void)
188{ 188{
189 return 0x00400118; 189 return 0x00400118U;
190} 190}
191static inline u32 gr_exception1_gpc_0_pending_f(void) 191static inline u32 gr_exception1_gpc_0_pending_f(void)
192{ 192{
193 return 0x1; 193 return 0x1U;
194} 194}
195static inline u32 gr_exception2_r(void) 195static inline u32 gr_exception2_r(void)
196{ 196{
197 return 0x0040011c; 197 return 0x0040011cU;
198} 198}
199static inline u32 gr_exception_en_r(void) 199static inline u32 gr_exception_en_r(void)
200{ 200{
201 return 0x00400138; 201 return 0x00400138U;
202} 202}
203static inline u32 gr_exception_en_fe_m(void) 203static inline u32 gr_exception_en_fe_m(void)
204{ 204{
205 return 0x1 << 0; 205 return 0x1U << 0U;
206} 206}
207static inline u32 gr_exception1_en_r(void) 207static inline u32 gr_exception1_en_r(void)
208{ 208{
209 return 0x00400130; 209 return 0x00400130U;
210} 210}
211static inline u32 gr_exception2_en_r(void) 211static inline u32 gr_exception2_en_r(void)
212{ 212{
213 return 0x00400134; 213 return 0x00400134U;
214} 214}
215static inline u32 gr_gpfifo_ctl_r(void) 215static inline u32 gr_gpfifo_ctl_r(void)
216{ 216{
217 return 0x00400500; 217 return 0x00400500U;
218} 218}
219static inline u32 gr_gpfifo_ctl_access_f(u32 v) 219static inline u32 gr_gpfifo_ctl_access_f(u32 v)
220{ 220{
221 return (v & 0x1) << 0; 221 return (v & 0x1U) << 0U;
222} 222}
223static inline u32 gr_gpfifo_ctl_access_disabled_f(void) 223static inline u32 gr_gpfifo_ctl_access_disabled_f(void)
224{ 224{
225 return 0x0; 225 return 0x0U;
226} 226}
227static inline u32 gr_gpfifo_ctl_access_enabled_f(void) 227static inline u32 gr_gpfifo_ctl_access_enabled_f(void)
228{ 228{
229 return 0x1; 229 return 0x1U;
230} 230}
231static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) 231static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v)
232{ 232{
233 return (v & 0x1) << 16; 233 return (v & 0x1U) << 16U;
234} 234}
235static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) 235static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void)
236{ 236{
237 return 0x00000001; 237 return 0x00000001U;
238} 238}
239static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) 239static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void)
240{ 240{
241 return 0x10000; 241 return 0x10000U;
242} 242}
243static inline u32 gr_gpfifo_status_r(void) 243static inline u32 gr_gpfifo_status_r(void)
244{ 244{
245 return 0x00400504; 245 return 0x00400504U;
246} 246}
247static inline u32 gr_trapped_addr_r(void) 247static inline u32 gr_trapped_addr_r(void)
248{ 248{
249 return 0x00400704; 249 return 0x00400704U;
250} 250}
251static inline u32 gr_trapped_addr_mthd_v(u32 r) 251static inline u32 gr_trapped_addr_mthd_v(u32 r)
252{ 252{
253 return (r >> 2) & 0xfff; 253 return (r >> 2U) & 0xfffU;
254} 254}
255static inline u32 gr_trapped_addr_subch_v(u32 r) 255static inline u32 gr_trapped_addr_subch_v(u32 r)
256{ 256{
257 return (r >> 16) & 0x7; 257 return (r >> 16U) & 0x7U;
258} 258}
259static inline u32 gr_trapped_data_lo_r(void) 259static inline u32 gr_trapped_data_lo_r(void)
260{ 260{
261 return 0x00400708; 261 return 0x00400708U;
262} 262}
263static inline u32 gr_trapped_data_hi_r(void) 263static inline u32 gr_trapped_data_hi_r(void)
264{ 264{
265 return 0x0040070c; 265 return 0x0040070cU;
266} 266}
267static inline u32 gr_status_r(void) 267static inline u32 gr_status_r(void)
268{ 268{
269 return 0x00400700; 269 return 0x00400700U;
270} 270}
271static inline u32 gr_status_fe_method_upper_v(u32 r) 271static inline u32 gr_status_fe_method_upper_v(u32 r)
272{ 272{
273 return (r >> 1) & 0x1; 273 return (r >> 1U) & 0x1U;
274} 274}
275static inline u32 gr_status_fe_method_lower_v(u32 r) 275static inline u32 gr_status_fe_method_lower_v(u32 r)
276{ 276{
277 return (r >> 2) & 0x1; 277 return (r >> 2U) & 0x1U;
278} 278}
279static inline u32 gr_status_fe_method_lower_idle_v(void) 279static inline u32 gr_status_fe_method_lower_idle_v(void)
280{ 280{
281 return 0x00000000; 281 return 0x00000000U;
282} 282}
283static inline u32 gr_status_fe_gi_v(u32 r) 283static inline u32 gr_status_fe_gi_v(u32 r)
284{ 284{
285 return (r >> 21) & 0x1; 285 return (r >> 21U) & 0x1U;
286} 286}
287static inline u32 gr_status_mask_r(void) 287static inline u32 gr_status_mask_r(void)
288{ 288{
289 return 0x00400610; 289 return 0x00400610U;
290} 290}
291static inline u32 gr_status_1_r(void) 291static inline u32 gr_status_1_r(void)
292{ 292{
293 return 0x00400604; 293 return 0x00400604U;
294} 294}
295static inline u32 gr_status_2_r(void) 295static inline u32 gr_status_2_r(void)
296{ 296{
297 return 0x00400608; 297 return 0x00400608U;
298} 298}
299static inline u32 gr_engine_status_r(void) 299static inline u32 gr_engine_status_r(void)
300{ 300{
301 return 0x0040060c; 301 return 0x0040060cU;
302} 302}
303static inline u32 gr_engine_status_value_busy_f(void) 303static inline u32 gr_engine_status_value_busy_f(void)
304{ 304{
305 return 0x1; 305 return 0x1U;
306} 306}
307static inline u32 gr_pri_be0_becs_be_exception_r(void) 307static inline u32 gr_pri_be0_becs_be_exception_r(void)
308{ 308{
309 return 0x00410204; 309 return 0x00410204U;
310} 310}
311static inline u32 gr_pri_be0_becs_be_exception_en_r(void) 311static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
312{ 312{
313 return 0x00410208; 313 return 0x00410208U;
314} 314}
315static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) 315static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
316{ 316{
317 return 0x00502c90; 317 return 0x00502c90U;
318} 318}
319static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) 319static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
320{ 320{
321 return 0x00502c94; 321 return 0x00502c94U;
322} 322}
323static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) 323static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
324{ 324{
325 return 0x00504508; 325 return 0x00504508U;
326} 326}
327static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) 327static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
328{ 328{
329 return 0x0050450c; 329 return 0x0050450cU;
330} 330}
331static inline u32 gr_activity_0_r(void) 331static inline u32 gr_activity_0_r(void)
332{ 332{
333 return 0x00400380; 333 return 0x00400380U;
334} 334}
335static inline u32 gr_activity_1_r(void) 335static inline u32 gr_activity_1_r(void)
336{ 336{
337 return 0x00400384; 337 return 0x00400384U;
338} 338}
339static inline u32 gr_activity_2_r(void) 339static inline u32 gr_activity_2_r(void)
340{ 340{
341 return 0x00400388; 341 return 0x00400388U;
342} 342}
343static inline u32 gr_activity_4_r(void) 343static inline u32 gr_activity_4_r(void)
344{ 344{
345 return 0x00400390; 345 return 0x00400390U;
346} 346}
347static inline u32 gr_pri_gpc0_gcc_dbg_r(void) 347static inline u32 gr_pri_gpc0_gcc_dbg_r(void)
348{ 348{
349 return 0x00501000; 349 return 0x00501000U;
350} 350}
351static inline u32 gr_pri_gpcs_gcc_dbg_r(void) 351static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
352{ 352{
353 return 0x00419000; 353 return 0x00419000U;
354} 354}
355static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) 355static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
356{ 356{
357 return 0x1 << 1; 357 return 0x1U << 1U;
358} 358}
359static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) 359static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
360{ 360{
361 return 0x005046a4; 361 return 0x005046a4U;
362} 362}
363static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) 363static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
364{ 364{
365 return 0x00419ea4; 365 return 0x00419ea4U;
366} 366}
367static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) 367static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
368{ 368{
369 return 0x1 << 0; 369 return 0x1U << 0U;
370} 370}
371static inline u32 gr_pri_sked_activity_r(void) 371static inline u32 gr_pri_sked_activity_r(void)
372{ 372{
373 return 0x00407054; 373 return 0x00407054U;
374} 374}
375static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) 375static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void)
376{ 376{
377 return 0x00502c80; 377 return 0x00502c80U;
378} 378}
379static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) 379static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void)
380{ 380{
381 return 0x00502c84; 381 return 0x00502c84U;
382} 382}
383static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) 383static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void)
384{ 384{
385 return 0x00502c88; 385 return 0x00502c88U;
386} 386}
387static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) 387static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void)
388{ 388{
389 return 0x00502c8c; 389 return 0x00502c8cU;
390} 390}
391static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) 391static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void)
392{ 392{
393 return 0x00504500; 393 return 0x00504500U;
394} 394}
395static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) 395static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void)
396{ 396{
397 return 0x00504d00; 397 return 0x00504d00U;
398} 398}
399static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) 399static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void)
400{ 400{
401 return 0x00501d00; 401 return 0x00501d00U;
402} 402}
403static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) 403static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void)
404{ 404{
405 return 0x0041ac80; 405 return 0x0041ac80U;
406} 406}
407static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) 407static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void)
408{ 408{
409 return 0x0041ac84; 409 return 0x0041ac84U;
410} 410}
411static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) 411static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void)
412{ 412{
413 return 0x0041ac88; 413 return 0x0041ac88U;
414} 414}
415static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) 415static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void)
416{ 416{
417 return 0x0041ac8c; 417 return 0x0041ac8cU;
418} 418}
419static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) 419static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void)
420{ 420{
421 return 0x0041c500; 421 return 0x0041c500U;
422} 422}
423static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) 423static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void)
424{ 424{
425 return 0x0041cd00; 425 return 0x0041cd00U;
426} 426}
427static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) 427static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void)
428{ 428{
429 return 0x00419d00; 429 return 0x00419d00U;
430} 430}
431static inline u32 gr_pri_be0_becs_be_activity0_r(void) 431static inline u32 gr_pri_be0_becs_be_activity0_r(void)
432{ 432{
433 return 0x00410200; 433 return 0x00410200U;
434} 434}
435static inline u32 gr_pri_be1_becs_be_activity0_r(void) 435static inline u32 gr_pri_be1_becs_be_activity0_r(void)
436{ 436{
437 return 0x00410600; 437 return 0x00410600U;
438} 438}
439static inline u32 gr_pri_bes_becs_be_activity0_r(void) 439static inline u32 gr_pri_bes_becs_be_activity0_r(void)
440{ 440{
441 return 0x00408a00; 441 return 0x00408a00U;
442} 442}
443static inline u32 gr_pri_ds_mpipe_status_r(void) 443static inline u32 gr_pri_ds_mpipe_status_r(void)
444{ 444{
445 return 0x00405858; 445 return 0x00405858U;
446} 446}
447static inline u32 gr_pri_fe_go_idle_on_status_r(void) 447static inline u32 gr_pri_fe_go_idle_on_status_r(void)
448{ 448{
449 return 0x00404150; 449 return 0x00404150U;
450} 450}
451static inline u32 gr_pri_fe_go_idle_check_r(void) 451static inline u32 gr_pri_fe_go_idle_check_r(void)
452{ 452{
453 return 0x00404158; 453 return 0x00404158U;
454} 454}
455static inline u32 gr_pri_fe_go_idle_info_r(void) 455static inline u32 gr_pri_fe_go_idle_info_r(void)
456{ 456{
457 return 0x00404194; 457 return 0x00404194U;
458} 458}
459static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) 459static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
460{ 460{
461 return 0x00504238; 461 return 0x00504238U;
462} 462}
463static inline u32 gr_pri_be0_crop_status1_r(void) 463static inline u32 gr_pri_be0_crop_status1_r(void)
464{ 464{
465 return 0x00410134; 465 return 0x00410134U;
466} 466}
467static inline u32 gr_pri_bes_crop_status1_r(void) 467static inline u32 gr_pri_bes_crop_status1_r(void)
468{ 468{
469 return 0x00408934; 469 return 0x00408934U;
470} 470}
471static inline u32 gr_pri_be0_zrop_status_r(void) 471static inline u32 gr_pri_be0_zrop_status_r(void)
472{ 472{
473 return 0x00410048; 473 return 0x00410048U;
474} 474}
475static inline u32 gr_pri_be0_zrop_status2_r(void) 475static inline u32 gr_pri_be0_zrop_status2_r(void)
476{ 476{
477 return 0x0041004c; 477 return 0x0041004cU;
478} 478}
479static inline u32 gr_pri_bes_zrop_status_r(void) 479static inline u32 gr_pri_bes_zrop_status_r(void)
480{ 480{
481 return 0x00408848; 481 return 0x00408848U;
482} 482}
483static inline u32 gr_pri_bes_zrop_status2_r(void) 483static inline u32 gr_pri_bes_zrop_status2_r(void)
484{ 484{
485 return 0x0040884c; 485 return 0x0040884cU;
486} 486}
487static inline u32 gr_pipe_bundle_address_r(void) 487static inline u32 gr_pipe_bundle_address_r(void)
488{ 488{
489 return 0x00400200; 489 return 0x00400200U;
490} 490}
491static inline u32 gr_pipe_bundle_address_value_v(u32 r) 491static inline u32 gr_pipe_bundle_address_value_v(u32 r)
492{ 492{
493 return (r >> 0) & 0xffff; 493 return (r >> 0U) & 0xffffU;
494} 494}
495static inline u32 gr_pipe_bundle_data_r(void) 495static inline u32 gr_pipe_bundle_data_r(void)
496{ 496{
497 return 0x00400204; 497 return 0x00400204U;
498} 498}
499static inline u32 gr_pipe_bundle_config_r(void) 499static inline u32 gr_pipe_bundle_config_r(void)
500{ 500{
501 return 0x00400208; 501 return 0x00400208U;
502} 502}
503static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) 503static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void)
504{ 504{
505 return 0x0; 505 return 0x0U;
506} 506}
507static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) 507static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void)
508{ 508{
509 return 0x80000000; 509 return 0x80000000U;
510} 510}
511static inline u32 gr_fe_hww_esr_r(void) 511static inline u32 gr_fe_hww_esr_r(void)
512{ 512{
513 return 0x00404000; 513 return 0x00404000U;
514} 514}
515static inline u32 gr_fe_hww_esr_reset_active_f(void) 515static inline u32 gr_fe_hww_esr_reset_active_f(void)
516{ 516{
517 return 0x40000000; 517 return 0x40000000U;
518} 518}
519static inline u32 gr_fe_hww_esr_en_enable_f(void) 519static inline u32 gr_fe_hww_esr_en_enable_f(void)
520{ 520{
521 return 0x80000000; 521 return 0x80000000U;
522} 522}
523static inline u32 gr_fe_go_idle_timeout_r(void) 523static inline u32 gr_fe_go_idle_timeout_r(void)
524{ 524{
525 return 0x00404154; 525 return 0x00404154U;
526} 526}
527static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) 527static inline u32 gr_fe_go_idle_timeout_count_f(u32 v)
528{ 528{
529 return (v & 0xffffffff) << 0; 529 return (v & 0xffffffffU) << 0U;
530} 530}
531static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) 531static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
532{ 532{
533 return 0x0; 533 return 0x0U;
534} 534}
535static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) 535static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
536{ 536{
537 return 0x800; 537 return 0x800U;
538} 538}
539static inline u32 gr_fe_object_table_r(u32 i) 539static inline u32 gr_fe_object_table_r(u32 i)
540{ 540{
541 return 0x00404200 + i*4; 541 return 0x00404200U + i*4U;
542} 542}
543static inline u32 gr_fe_object_table_nvclass_v(u32 r) 543static inline u32 gr_fe_object_table_nvclass_v(u32 r)
544{ 544{
545 return (r >> 0) & 0xffff; 545 return (r >> 0U) & 0xffffU;
546} 546}
547static inline u32 gr_fe_tpc_fs_r(void) 547static inline u32 gr_fe_tpc_fs_r(void)
548{ 548{
549 return 0x004041c4; 549 return 0x004041c4U;
550} 550}
551static inline u32 gr_pri_mme_shadow_raw_index_r(void) 551static inline u32 gr_pri_mme_shadow_raw_index_r(void)
552{ 552{
553 return 0x00404488; 553 return 0x00404488U;
554} 554}
555static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) 555static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void)
556{ 556{
557 return 0x80000000; 557 return 0x80000000U;
558} 558}
559static inline u32 gr_pri_mme_shadow_raw_data_r(void) 559static inline u32 gr_pri_mme_shadow_raw_data_r(void)
560{ 560{
561 return 0x0040448c; 561 return 0x0040448cU;
562} 562}
563static inline u32 gr_mme_hww_esr_r(void) 563static inline u32 gr_mme_hww_esr_r(void)
564{ 564{
565 return 0x00404490; 565 return 0x00404490U;
566} 566}
567static inline u32 gr_mme_hww_esr_reset_active_f(void) 567static inline u32 gr_mme_hww_esr_reset_active_f(void)
568{ 568{
569 return 0x40000000; 569 return 0x40000000U;
570} 570}
571static inline u32 gr_mme_hww_esr_en_enable_f(void) 571static inline u32 gr_mme_hww_esr_en_enable_f(void)
572{ 572{
573 return 0x80000000; 573 return 0x80000000U;
574} 574}
575static inline u32 gr_memfmt_hww_esr_r(void) 575static inline u32 gr_memfmt_hww_esr_r(void)
576{ 576{
577 return 0x00404600; 577 return 0x00404600U;
578} 578}
579static inline u32 gr_memfmt_hww_esr_reset_active_f(void) 579static inline u32 gr_memfmt_hww_esr_reset_active_f(void)
580{ 580{
581 return 0x40000000; 581 return 0x40000000U;
582} 582}
583static inline u32 gr_memfmt_hww_esr_en_enable_f(void) 583static inline u32 gr_memfmt_hww_esr_en_enable_f(void)
584{ 584{
585 return 0x80000000; 585 return 0x80000000U;
586} 586}
587static inline u32 gr_fecs_cpuctl_r(void) 587static inline u32 gr_fecs_cpuctl_r(void)
588{ 588{
589 return 0x00409100; 589 return 0x00409100U;
590} 590}
591static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) 591static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v)
592{ 592{
593 return (v & 0x1) << 1; 593 return (v & 0x1U) << 1U;
594} 594}
595static inline u32 gr_fecs_cpuctl_alias_r(void) 595static inline u32 gr_fecs_cpuctl_alias_r(void)
596{ 596{
597 return 0x00409130; 597 return 0x00409130U;
598} 598}
599static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) 599static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v)
600{ 600{
601 return (v & 0x1) << 1; 601 return (v & 0x1U) << 1U;
602} 602}
603static inline u32 gr_fecs_dmactl_r(void) 603static inline u32 gr_fecs_dmactl_r(void)
604{ 604{
605 return 0x0040910c; 605 return 0x0040910cU;
606} 606}
607static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) 607static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
608{ 608{
609 return (v & 0x1) << 0; 609 return (v & 0x1U) << 0U;
610} 610}
611static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) 611static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
612{ 612{
613 return 0x1 << 1; 613 return 0x1U << 1U;
614} 614}
615static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) 615static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
616{ 616{
617 return 0x1 << 2; 617 return 0x1U << 2U;
618} 618}
619static inline u32 gr_fecs_os_r(void) 619static inline u32 gr_fecs_os_r(void)
620{ 620{
621 return 0x00409080; 621 return 0x00409080U;
622} 622}
623static inline u32 gr_fecs_idlestate_r(void) 623static inline u32 gr_fecs_idlestate_r(void)
624{ 624{
625 return 0x0040904c; 625 return 0x0040904cU;
626} 626}
627static inline u32 gr_fecs_mailbox0_r(void) 627static inline u32 gr_fecs_mailbox0_r(void)
628{ 628{
629 return 0x00409040; 629 return 0x00409040U;
630} 630}
631static inline u32 gr_fecs_mailbox1_r(void) 631static inline u32 gr_fecs_mailbox1_r(void)
632{ 632{
633 return 0x00409044; 633 return 0x00409044U;
634} 634}
635static inline u32 gr_fecs_irqstat_r(void) 635static inline u32 gr_fecs_irqstat_r(void)
636{ 636{
637 return 0x00409008; 637 return 0x00409008U;
638} 638}
639static inline u32 gr_fecs_irqmode_r(void) 639static inline u32 gr_fecs_irqmode_r(void)
640{ 640{
641 return 0x0040900c; 641 return 0x0040900cU;
642} 642}
643static inline u32 gr_fecs_irqmask_r(void) 643static inline u32 gr_fecs_irqmask_r(void)
644{ 644{
645 return 0x00409018; 645 return 0x00409018U;
646} 646}
647static inline u32 gr_fecs_irqdest_r(void) 647static inline u32 gr_fecs_irqdest_r(void)
648{ 648{
649 return 0x0040901c; 649 return 0x0040901cU;
650} 650}
651static inline u32 gr_fecs_curctx_r(void) 651static inline u32 gr_fecs_curctx_r(void)
652{ 652{
653 return 0x00409050; 653 return 0x00409050U;
654} 654}
655static inline u32 gr_fecs_nxtctx_r(void) 655static inline u32 gr_fecs_nxtctx_r(void)
656{ 656{
657 return 0x00409054; 657 return 0x00409054U;
658} 658}
659static inline u32 gr_fecs_engctl_r(void) 659static inline u32 gr_fecs_engctl_r(void)
660{ 660{
661 return 0x004090a4; 661 return 0x004090a4U;
662} 662}
663static inline u32 gr_fecs_debug1_r(void) 663static inline u32 gr_fecs_debug1_r(void)
664{ 664{
665 return 0x00409090; 665 return 0x00409090U;
666} 666}
667static inline u32 gr_fecs_debuginfo_r(void) 667static inline u32 gr_fecs_debuginfo_r(void)
668{ 668{
669 return 0x00409094; 669 return 0x00409094U;
670} 670}
671static inline u32 gr_fecs_icd_cmd_r(void) 671static inline u32 gr_fecs_icd_cmd_r(void)
672{ 672{
673 return 0x00409200; 673 return 0x00409200U;
674} 674}
675static inline u32 gr_fecs_icd_cmd_opc_s(void) 675static inline u32 gr_fecs_icd_cmd_opc_s(void)
676{ 676{
677 return 4; 677 return 4U;
678} 678}
679static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) 679static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
680{ 680{
681 return (v & 0xf) << 0; 681 return (v & 0xfU) << 0U;
682} 682}
683static inline u32 gr_fecs_icd_cmd_opc_m(void) 683static inline u32 gr_fecs_icd_cmd_opc_m(void)
684{ 684{
685 return 0xf << 0; 685 return 0xfU << 0U;
686} 686}
687static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) 687static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
688{ 688{
689 return (r >> 0) & 0xf; 689 return (r >> 0U) & 0xfU;
690} 690}
691static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) 691static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void)
692{ 692{
693 return 0x8; 693 return 0x8U;
694} 694}
695static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) 695static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void)
696{ 696{
697 return 0xe; 697 return 0xeU;
698} 698}
699static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) 699static inline u32 gr_fecs_icd_cmd_idx_f(u32 v)
700{ 700{
701 return (v & 0x1f) << 8; 701 return (v & 0x1fU) << 8U;
702} 702}
703static inline u32 gr_fecs_icd_rdata_r(void) 703static inline u32 gr_fecs_icd_rdata_r(void)
704{ 704{
705 return 0x0040920c; 705 return 0x0040920cU;
706} 706}
707static inline u32 gr_fecs_imemc_r(u32 i) 707static inline u32 gr_fecs_imemc_r(u32 i)
708{ 708{
709 return 0x00409180 + i*16; 709 return 0x00409180U + i*16U;
710} 710}
711static inline u32 gr_fecs_imemc_offs_f(u32 v) 711static inline u32 gr_fecs_imemc_offs_f(u32 v)
712{ 712{
713 return (v & 0x3f) << 2; 713 return (v & 0x3fU) << 2U;
714} 714}
715static inline u32 gr_fecs_imemc_blk_f(u32 v) 715static inline u32 gr_fecs_imemc_blk_f(u32 v)
716{ 716{
717 return (v & 0xff) << 8; 717 return (v & 0xffU) << 8U;
718} 718}
719static inline u32 gr_fecs_imemc_aincw_f(u32 v) 719static inline u32 gr_fecs_imemc_aincw_f(u32 v)
720{ 720{
721 return (v & 0x1) << 24; 721 return (v & 0x1U) << 24U;
722} 722}
723static inline u32 gr_fecs_imemd_r(u32 i) 723static inline u32 gr_fecs_imemd_r(u32 i)
724{ 724{
725 return 0x00409184 + i*16; 725 return 0x00409184U + i*16U;
726} 726}
727static inline u32 gr_fecs_imemt_r(u32 i) 727static inline u32 gr_fecs_imemt_r(u32 i)
728{ 728{
729 return 0x00409188 + i*16; 729 return 0x00409188U + i*16U;
730} 730}
731static inline u32 gr_fecs_imemt_tag_f(u32 v) 731static inline u32 gr_fecs_imemt_tag_f(u32 v)
732{ 732{
733 return (v & 0xffff) << 0; 733 return (v & 0xffffU) << 0U;
734} 734}
735static inline u32 gr_fecs_dmemc_r(u32 i) 735static inline u32 gr_fecs_dmemc_r(u32 i)
736{ 736{
737 return 0x004091c0 + i*8; 737 return 0x004091c0U + i*8U;
738} 738}
739static inline u32 gr_fecs_dmemc_offs_s(void) 739static inline u32 gr_fecs_dmemc_offs_s(void)
740{ 740{
741 return 6; 741 return 6U;
742} 742}
743static inline u32 gr_fecs_dmemc_offs_f(u32 v) 743static inline u32 gr_fecs_dmemc_offs_f(u32 v)
744{ 744{
745 return (v & 0x3f) << 2; 745 return (v & 0x3fU) << 2U;
746} 746}
747static inline u32 gr_fecs_dmemc_offs_m(void) 747static inline u32 gr_fecs_dmemc_offs_m(void)
748{ 748{
749 return 0x3f << 2; 749 return 0x3fU << 2U;
750} 750}
751static inline u32 gr_fecs_dmemc_offs_v(u32 r) 751static inline u32 gr_fecs_dmemc_offs_v(u32 r)
752{ 752{
753 return (r >> 2) & 0x3f; 753 return (r >> 2U) & 0x3fU;
754} 754}
755static inline u32 gr_fecs_dmemc_blk_f(u32 v) 755static inline u32 gr_fecs_dmemc_blk_f(u32 v)
756{ 756{
757 return (v & 0xff) << 8; 757 return (v & 0xffU) << 8U;
758} 758}
759static inline u32 gr_fecs_dmemc_aincw_f(u32 v) 759static inline u32 gr_fecs_dmemc_aincw_f(u32 v)
760{ 760{
761 return (v & 0x1) << 24; 761 return (v & 0x1U) << 24U;
762} 762}
763static inline u32 gr_fecs_dmemd_r(u32 i) 763static inline u32 gr_fecs_dmemd_r(u32 i)
764{ 764{
765 return 0x004091c4 + i*8; 765 return 0x004091c4U + i*8U;
766} 766}
767static inline u32 gr_fecs_dmatrfbase_r(void) 767static inline u32 gr_fecs_dmatrfbase_r(void)
768{ 768{
769 return 0x00409110; 769 return 0x00409110U;
770} 770}
771static inline u32 gr_fecs_dmatrfmoffs_r(void) 771static inline u32 gr_fecs_dmatrfmoffs_r(void)
772{ 772{
773 return 0x00409114; 773 return 0x00409114U;
774} 774}
775static inline u32 gr_fecs_dmatrffboffs_r(void) 775static inline u32 gr_fecs_dmatrffboffs_r(void)
776{ 776{
777 return 0x0040911c; 777 return 0x0040911cU;
778} 778}
779static inline u32 gr_fecs_dmatrfcmd_r(void) 779static inline u32 gr_fecs_dmatrfcmd_r(void)
780{ 780{
781 return 0x00409118; 781 return 0x00409118U;
782} 782}
783static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) 783static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v)
784{ 784{
785 return (v & 0x1) << 4; 785 return (v & 0x1U) << 4U;
786} 786}
787static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) 787static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v)
788{ 788{
789 return (v & 0x1) << 5; 789 return (v & 0x1U) << 5U;
790} 790}
791static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) 791static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v)
792{ 792{
793 return (v & 0x7) << 8; 793 return (v & 0x7U) << 8U;
794} 794}
795static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) 795static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v)
796{ 796{
797 return (v & 0x7) << 12; 797 return (v & 0x7U) << 12U;
798} 798}
799static inline u32 gr_fecs_bootvec_r(void) 799static inline u32 gr_fecs_bootvec_r(void)
800{ 800{
801 return 0x00409104; 801 return 0x00409104U;
802} 802}
803static inline u32 gr_fecs_bootvec_vec_f(u32 v) 803static inline u32 gr_fecs_bootvec_vec_f(u32 v)
804{ 804{
805 return (v & 0xffffffff) << 0; 805 return (v & 0xffffffffU) << 0U;
806} 806}
807static inline u32 gr_fecs_falcon_hwcfg_r(void) 807static inline u32 gr_fecs_falcon_hwcfg_r(void)
808{ 808{
809 return 0x00409108; 809 return 0x00409108U;
810} 810}
811static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) 811static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
812{ 812{
813 return 0x0041a108; 813 return 0x0041a108U;
814} 814}
815static inline u32 gr_fecs_falcon_rm_r(void) 815static inline u32 gr_fecs_falcon_rm_r(void)
816{ 816{
817 return 0x00409084; 817 return 0x00409084U;
818} 818}
819static inline u32 gr_fecs_current_ctx_r(void) 819static inline u32 gr_fecs_current_ctx_r(void)
820{ 820{
821 return 0x00409b00; 821 return 0x00409b00U;
822} 822}
823static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) 823static inline u32 gr_fecs_current_ctx_ptr_f(u32 v)
824{ 824{
825 return (v & 0xfffffff) << 0; 825 return (v & 0xfffffffU) << 0U;
826} 826}
827static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) 827static inline u32 gr_fecs_current_ctx_ptr_v(u32 r)
828{ 828{
829 return (r >> 0) & 0xfffffff; 829 return (r >> 0U) & 0xfffffffU;
830} 830}
831static inline u32 gr_fecs_current_ctx_target_s(void) 831static inline u32 gr_fecs_current_ctx_target_s(void)
832{ 832{
833 return 2; 833 return 2U;
834} 834}
835static inline u32 gr_fecs_current_ctx_target_f(u32 v) 835static inline u32 gr_fecs_current_ctx_target_f(u32 v)
836{ 836{
837 return (v & 0x3) << 28; 837 return (v & 0x3U) << 28U;
838} 838}
839static inline u32 gr_fecs_current_ctx_target_m(void) 839static inline u32 gr_fecs_current_ctx_target_m(void)
840{ 840{
841 return 0x3 << 28; 841 return 0x3U << 28U;
842} 842}
843static inline u32 gr_fecs_current_ctx_target_v(u32 r) 843static inline u32 gr_fecs_current_ctx_target_v(u32 r)
844{ 844{
845 return (r >> 28) & 0x3; 845 return (r >> 28U) & 0x3U;
846} 846}
847static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) 847static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void)
848{ 848{
849 return 0x0; 849 return 0x0U;
850} 850}
851static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) 851static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void)
852{ 852{
853 return 0x20000000; 853 return 0x20000000U;
854} 854}
855static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) 855static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void)
856{ 856{
857 return 0x30000000; 857 return 0x30000000U;
858} 858}
859static inline u32 gr_fecs_current_ctx_valid_s(void) 859static inline u32 gr_fecs_current_ctx_valid_s(void)
860{ 860{
861 return 1; 861 return 1U;
862} 862}
863static inline u32 gr_fecs_current_ctx_valid_f(u32 v) 863static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
864{ 864{
865 return (v & 0x1) << 31; 865 return (v & 0x1U) << 31U;
866} 866}
867static inline u32 gr_fecs_current_ctx_valid_m(void) 867static inline u32 gr_fecs_current_ctx_valid_m(void)
868{ 868{
869 return 0x1 << 31; 869 return 0x1U << 31U;
870} 870}
871static inline u32 gr_fecs_current_ctx_valid_v(u32 r) 871static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
872{ 872{
873 return (r >> 31) & 0x1; 873 return (r >> 31U) & 0x1U;
874} 874}
875static inline u32 gr_fecs_current_ctx_valid_false_f(void) 875static inline u32 gr_fecs_current_ctx_valid_false_f(void)
876{ 876{
877 return 0x0; 877 return 0x0U;
878} 878}
879static inline u32 gr_fecs_method_data_r(void) 879static inline u32 gr_fecs_method_data_r(void)
880{ 880{
881 return 0x00409500; 881 return 0x00409500U;
882} 882}
883static inline u32 gr_fecs_method_push_r(void) 883static inline u32 gr_fecs_method_push_r(void)
884{ 884{
885 return 0x00409504; 885 return 0x00409504U;
886} 886}
887static inline u32 gr_fecs_method_push_adr_f(u32 v) 887static inline u32 gr_fecs_method_push_adr_f(u32 v)
888{ 888{
889 return (v & 0xfff) << 0; 889 return (v & 0xfffU) << 0U;
890} 890}
891static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) 891static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void)
892{ 892{
893 return 0x00000003; 893 return 0x00000003U;
894} 894}
895static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) 895static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void)
896{ 896{
897 return 0x3; 897 return 0x3U;
898} 898}
899static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) 899static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void)
900{ 900{
901 return 0x00000010; 901 return 0x00000010U;
902} 902}
903static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) 903static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void)
904{ 904{
905 return 0x00000009; 905 return 0x00000009U;
906} 906}
907static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) 907static inline u32 gr_fecs_method_push_adr_restore_golden_v(void)
908{ 908{
909 return 0x00000015; 909 return 0x00000015U;
910} 910}
911static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) 911static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void)
912{ 912{
913 return 0x00000016; 913 return 0x00000016U;
914} 914}
915static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) 915static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void)
916{ 916{
917 return 0x00000025; 917 return 0x00000025U;
918} 918}
919static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) 919static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void)
920{ 920{
921 return 0x00000030; 921 return 0x00000030U;
922} 922}
923static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) 923static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void)
924{ 924{
925 return 0x00000031; 925 return 0x00000031U;
926} 926}
927static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) 927static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void)
928{ 928{
929 return 0x00000032; 929 return 0x00000032U;
930} 930}
931static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) 931static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void)
932{ 932{
933 return 0x00000038; 933 return 0x00000038U;
934} 934}
935static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) 935static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void)
936{ 936{
937 return 0x00000039; 937 return 0x00000039U;
938} 938}
939static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) 939static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
940{ 940{
941 return 0x21; 941 return 0x21U;
942} 942}
943static inline u32 gr_fecs_method_push_adr_write_timestamp_record_v(void) 943static inline u32 gr_fecs_method_push_adr_write_timestamp_record_v(void)
944{ 944{
945 return 0x0000003d; 945 return 0x0000003dU;
946} 946}
947static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) 947static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
948{ 948{
949 return 0x00000004; 949 return 0x00000004U;
950} 950}
951static inline u32 gr_fecs_host_int_status_r(void) 951static inline u32 gr_fecs_host_int_status_r(void)
952{ 952{
953 return 0x00409c18; 953 return 0x00409c18U;
954} 954}
955static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) 955static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v)
956{ 956{
957 return (v & 0x1) << 16; 957 return (v & 0x1U) << 16U;
958} 958}
959static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) 959static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
960{ 960{
961 return (v & 0x1) << 17; 961 return (v & 0x1U) << 17U;
962} 962}
963static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) 963static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
964{ 964{
965 return (v & 0x1) << 18; 965 return (v & 0x1U) << 18U;
966} 966}
967static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) 967static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
968{ 968{
969 return (v & 0xffff) << 0; 969 return (v & 0xffffU) << 0U;
970} 970}
971static inline u32 gr_fecs_host_int_clear_r(void) 971static inline u32 gr_fecs_host_int_clear_r(void)
972{ 972{
973 return 0x00409c20; 973 return 0x00409c20U;
974} 974}
975static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) 975static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v)
976{ 976{
977 return (v & 0x1) << 1; 977 return (v & 0x1U) << 1U;
978} 978}
979static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) 979static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void)
980{ 980{
981 return 0x2; 981 return 0x2U;
982} 982}
983static inline u32 gr_fecs_host_int_enable_r(void) 983static inline u32 gr_fecs_host_int_enable_r(void)
984{ 984{
985 return 0x00409c24; 985 return 0x00409c24U;
986} 986}
987static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) 987static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void)
988{ 988{
989 return 0x2; 989 return 0x2U;
990} 990}
991static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) 991static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void)
992{ 992{
993 return 0x10000; 993 return 0x10000U;
994} 994}
995static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) 995static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void)
996{ 996{
997 return 0x20000; 997 return 0x20000U;
998} 998}
999static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) 999static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void)
1000{ 1000{
1001 return 0x40000; 1001 return 0x40000U;
1002} 1002}
1003static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) 1003static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void)
1004{ 1004{
1005 return 0x80000; 1005 return 0x80000U;
1006} 1006}
1007static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) 1007static inline u32 gr_fecs_ctxsw_reset_ctl_r(void)
1008{ 1008{
1009 return 0x00409614; 1009 return 0x00409614U;
1010} 1010}
1011static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) 1011static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void)
1012{ 1012{
1013 return 0x0; 1013 return 0x0U;
1014} 1014}
1015static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) 1015static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void)
1016{ 1016{
1017 return 0x0; 1017 return 0x0U;
1018} 1018}
1019static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) 1019static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void)
1020{ 1020{
1021 return 0x0; 1021 return 0x0U;
1022} 1022}
1023static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) 1023static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void)
1024{ 1024{
1025 return 0x10; 1025 return 0x10U;
1026} 1026}
1027static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) 1027static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void)
1028{ 1028{
1029 return 0x20; 1029 return 0x20U;
1030} 1030}
1031static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) 1031static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void)
1032{ 1032{
1033 return 0x40; 1033 return 0x40U;
1034} 1034}
1035static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) 1035static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void)
1036{ 1036{
1037 return 0x0; 1037 return 0x0U;
1038} 1038}
1039static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) 1039static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void)
1040{ 1040{
1041 return 0x100; 1041 return 0x100U;
1042} 1042}
1043static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) 1043static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void)
1044{ 1044{
1045 return 0x0; 1045 return 0x0U;
1046} 1046}
1047static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) 1047static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void)
1048{ 1048{
1049 return 0x200; 1049 return 0x200U;
1050} 1050}
1051static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) 1051static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void)
1052{ 1052{
1053 return 1; 1053 return 1U;
1054} 1054}
1055static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) 1055static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
1056{ 1056{
1057 return (v & 0x1) << 10; 1057 return (v & 0x1U) << 10U;
1058} 1058}
1059static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) 1059static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
1060{ 1060{
1061 return 0x1 << 10; 1061 return 0x1U << 10U;
1062} 1062}
1063static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) 1063static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
1064{ 1064{
1065 return (r >> 10) & 0x1; 1065 return (r >> 10U) & 0x1U;
1066} 1066}
1067static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) 1067static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void)
1068{ 1068{
1069 return 0x0; 1069 return 0x0U;
1070} 1070}
1071static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) 1071static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void)
1072{ 1072{
1073 return 0x400; 1073 return 0x400U;
1074} 1074}
1075static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) 1075static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void)
1076{ 1076{
1077 return 0x0040960c; 1077 return 0x0040960cU;
1078} 1078}
1079static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) 1079static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i)
1080{ 1080{
1081 return 0x00409800 + i*4; 1081 return 0x00409800U + i*4U;
1082} 1082}
1083static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) 1083static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void)
1084{ 1084{
1085 return 0x00000010; 1085 return 0x00000010U;
1086} 1086}
1087static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) 1087static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v)
1088{ 1088{
1089 return (v & 0xffffffff) << 0; 1089 return (v & 0xffffffffU) << 0U;
1090} 1090}
1091static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) 1091static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void)
1092{ 1092{
1093 return 0x00000001; 1093 return 0x00000001U;
1094} 1094}
1095static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) 1095static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void)
1096{ 1096{
1097 return 0x00000002; 1097 return 0x00000002U;
1098} 1098}
1099static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) 1099static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i)
1100{ 1100{
1101 return 0x004098c0 + i*4; 1101 return 0x004098c0U + i*4U;
1102} 1102}
1103static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) 1103static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v)
1104{ 1104{
1105 return (v & 0xffffffff) << 0; 1105 return (v & 0xffffffffU) << 0U;
1106} 1106}
1107static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) 1107static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i)
1108{ 1108{
1109 return 0x00409840 + i*4; 1109 return 0x00409840U + i*4U;
1110} 1110}
1111static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) 1111static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v)
1112{ 1112{
1113 return (v & 0xffffffff) << 0; 1113 return (v & 0xffffffffU) << 0U;
1114} 1114}
1115static inline u32 gr_fecs_fs_r(void) 1115static inline u32 gr_fecs_fs_r(void)
1116{ 1116{
1117 return 0x00409604; 1117 return 0x00409604U;
1118} 1118}
1119static inline u32 gr_fecs_fs_num_available_gpcs_s(void) 1119static inline u32 gr_fecs_fs_num_available_gpcs_s(void)
1120{ 1120{
1121 return 5; 1121 return 5U;
1122} 1122}
1123static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) 1123static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
1124{ 1124{
1125 return (v & 0x1f) << 0; 1125 return (v & 0x1fU) << 0U;
1126} 1126}
1127static inline u32 gr_fecs_fs_num_available_gpcs_m(void) 1127static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
1128{ 1128{
1129 return 0x1f << 0; 1129 return 0x1fU << 0U;
1130} 1130}
1131static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) 1131static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
1132{ 1132{
1133 return (r >> 0) & 0x1f; 1133 return (r >> 0U) & 0x1fU;
1134} 1134}
1135static inline u32 gr_fecs_fs_num_available_fbps_s(void) 1135static inline u32 gr_fecs_fs_num_available_fbps_s(void)
1136{ 1136{
1137 return 5; 1137 return 5U;
1138} 1138}
1139static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) 1139static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
1140{ 1140{
1141 return (v & 0x1f) << 16; 1141 return (v & 0x1fU) << 16U;
1142} 1142}
1143static inline u32 gr_fecs_fs_num_available_fbps_m(void) 1143static inline u32 gr_fecs_fs_num_available_fbps_m(void)
1144{ 1144{
1145 return 0x1f << 16; 1145 return 0x1fU << 16U;
1146} 1146}
1147static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) 1147static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
1148{ 1148{
1149 return (r >> 16) & 0x1f; 1149 return (r >> 16U) & 0x1fU;
1150} 1150}
1151static inline u32 gr_fecs_cfg_r(void) 1151static inline u32 gr_fecs_cfg_r(void)
1152{ 1152{
1153 return 0x00409620; 1153 return 0x00409620U;
1154} 1154}
1155static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) 1155static inline u32 gr_fecs_cfg_imem_sz_v(u32 r)
1156{ 1156{
1157 return (r >> 0) & 0xff; 1157 return (r >> 0U) & 0xffU;
1158} 1158}
1159static inline u32 gr_fecs_rc_lanes_r(void) 1159static inline u32 gr_fecs_rc_lanes_r(void)
1160{ 1160{
1161 return 0x00409880; 1161 return 0x00409880U;
1162} 1162}
1163static inline u32 gr_fecs_rc_lanes_num_chains_s(void) 1163static inline u32 gr_fecs_rc_lanes_num_chains_s(void)
1164{ 1164{
1165 return 6; 1165 return 6U;
1166} 1166}
1167static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) 1167static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
1168{ 1168{
1169 return (v & 0x3f) << 0; 1169 return (v & 0x3fU) << 0U;
1170} 1170}
1171static inline u32 gr_fecs_rc_lanes_num_chains_m(void) 1171static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
1172{ 1172{
1173 return 0x3f << 0; 1173 return 0x3fU << 0U;
1174} 1174}
1175static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) 1175static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
1176{ 1176{
1177 return (r >> 0) & 0x3f; 1177 return (r >> 0U) & 0x3fU;
1178} 1178}
1179static inline u32 gr_fecs_ctxsw_status_1_r(void) 1179static inline u32 gr_fecs_ctxsw_status_1_r(void)
1180{ 1180{
1181 return 0x00409400; 1181 return 0x00409400U;
1182} 1182}
1183static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) 1183static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void)
1184{ 1184{
1185 return 1; 1185 return 1U;
1186} 1186}
1187static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) 1187static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
1188{ 1188{
1189 return (v & 0x1) << 12; 1189 return (v & 0x1U) << 12U;
1190} 1190}
1191static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) 1191static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
1192{ 1192{
1193 return 0x1 << 12; 1193 return 0x1U << 12U;
1194} 1194}
1195static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) 1195static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
1196{ 1196{
1197 return (r >> 12) & 0x1; 1197 return (r >> 12U) & 0x1U;
1198} 1198}
1199static inline u32 gr_fecs_arb_ctx_adr_r(void) 1199static inline u32 gr_fecs_arb_ctx_adr_r(void)
1200{ 1200{
1201 return 0x00409a24; 1201 return 0x00409a24U;
1202} 1202}
1203static inline u32 gr_fecs_new_ctx_r(void) 1203static inline u32 gr_fecs_new_ctx_r(void)
1204{ 1204{
1205 return 0x00409b04; 1205 return 0x00409b04U;
1206} 1206}
1207static inline u32 gr_fecs_new_ctx_ptr_s(void) 1207static inline u32 gr_fecs_new_ctx_ptr_s(void)
1208{ 1208{
1209 return 28; 1209 return 28U;
1210} 1210}
1211static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) 1211static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
1212{ 1212{
1213 return (v & 0xfffffff) << 0; 1213 return (v & 0xfffffffU) << 0U;
1214} 1214}
1215static inline u32 gr_fecs_new_ctx_ptr_m(void) 1215static inline u32 gr_fecs_new_ctx_ptr_m(void)
1216{ 1216{
1217 return 0xfffffff << 0; 1217 return 0xfffffffU << 0U;
1218} 1218}
1219static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) 1219static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
1220{ 1220{
1221 return (r >> 0) & 0xfffffff; 1221 return (r >> 0U) & 0xfffffffU;
1222} 1222}
1223static inline u32 gr_fecs_new_ctx_target_s(void) 1223static inline u32 gr_fecs_new_ctx_target_s(void)
1224{ 1224{
1225 return 2; 1225 return 2U;
1226} 1226}
1227static inline u32 gr_fecs_new_ctx_target_f(u32 v) 1227static inline u32 gr_fecs_new_ctx_target_f(u32 v)
1228{ 1228{
1229 return (v & 0x3) << 28; 1229 return (v & 0x3U) << 28U;
1230} 1230}
1231static inline u32 gr_fecs_new_ctx_target_m(void) 1231static inline u32 gr_fecs_new_ctx_target_m(void)
1232{ 1232{
1233 return 0x3 << 28; 1233 return 0x3U << 28U;
1234} 1234}
1235static inline u32 gr_fecs_new_ctx_target_v(u32 r) 1235static inline u32 gr_fecs_new_ctx_target_v(u32 r)
1236{ 1236{
1237 return (r >> 28) & 0x3; 1237 return (r >> 28U) & 0x3U;
1238} 1238}
1239static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void) 1239static inline u32 gr_fecs_new_ctx_target_vid_mem_f(void)
1240{ 1240{
1241 return 0x0; 1241 return 0x0U;
1242} 1242}
1243static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void) 1243static inline u32 gr_fecs_new_ctx_target_sys_mem_ncoh_f(void)
1244{ 1244{
1245 return 0x30000000; 1245 return 0x30000000U;
1246} 1246}
1247static inline u32 gr_fecs_new_ctx_valid_s(void) 1247static inline u32 gr_fecs_new_ctx_valid_s(void)
1248{ 1248{
1249 return 1; 1249 return 1U;
1250} 1250}
1251static inline u32 gr_fecs_new_ctx_valid_f(u32 v) 1251static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
1252{ 1252{
1253 return (v & 0x1) << 31; 1253 return (v & 0x1U) << 31U;
1254} 1254}
1255static inline u32 gr_fecs_new_ctx_valid_m(void) 1255static inline u32 gr_fecs_new_ctx_valid_m(void)
1256{ 1256{
1257 return 0x1 << 31; 1257 return 0x1U << 31U;
1258} 1258}
1259static inline u32 gr_fecs_new_ctx_valid_v(u32 r) 1259static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
1260{ 1260{
1261 return (r >> 31) & 0x1; 1261 return (r >> 31U) & 0x1U;
1262} 1262}
1263static inline u32 gr_fecs_arb_ctx_ptr_r(void) 1263static inline u32 gr_fecs_arb_ctx_ptr_r(void)
1264{ 1264{
1265 return 0x00409a0c; 1265 return 0x00409a0cU;
1266} 1266}
1267static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) 1267static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void)
1268{ 1268{
1269 return 28; 1269 return 28U;
1270} 1270}
1271static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) 1271static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
1272{ 1272{
1273 return (v & 0xfffffff) << 0; 1273 return (v & 0xfffffffU) << 0U;
1274} 1274}
1275static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) 1275static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
1276{ 1276{
1277 return 0xfffffff << 0; 1277 return 0xfffffffU << 0U;
1278} 1278}
1279static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) 1279static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
1280{ 1280{
1281 return (r >> 0) & 0xfffffff; 1281 return (r >> 0U) & 0xfffffffU;
1282} 1282}
1283static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) 1283static inline u32 gr_fecs_arb_ctx_ptr_target_s(void)
1284{ 1284{
1285 return 2; 1285 return 2U;
1286} 1286}
1287static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) 1287static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
1288{ 1288{
1289 return (v & 0x3) << 28; 1289 return (v & 0x3U) << 28U;
1290} 1290}
1291static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) 1291static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
1292{ 1292{
1293 return 0x3 << 28; 1293 return 0x3U << 28U;
1294} 1294}
1295static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) 1295static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
1296{ 1296{
1297 return (r >> 28) & 0x3; 1297 return (r >> 28U) & 0x3U;
1298} 1298}
1299static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void) 1299static inline u32 gr_fecs_arb_ctx_ptr_target_vid_mem_f(void)
1300{ 1300{
1301 return 0x0; 1301 return 0x0U;
1302} 1302}
1303static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void) 1303static inline u32 gr_fecs_arb_ctx_ptr_target_sys_mem_ncoh_f(void)
1304{ 1304{
1305 return 0x30000000; 1305 return 0x30000000U;
1306} 1306}
1307static inline u32 gr_fecs_arb_ctx_cmd_r(void) 1307static inline u32 gr_fecs_arb_ctx_cmd_r(void)
1308{ 1308{
1309 return 0x00409a10; 1309 return 0x00409a10U;
1310} 1310}
1311static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) 1311static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void)
1312{ 1312{
1313 return 5; 1313 return 5U;
1314} 1314}
1315static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) 1315static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
1316{ 1316{
1317 return (v & 0x1f) << 0; 1317 return (v & 0x1fU) << 0U;
1318} 1318}
1319static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) 1319static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
1320{ 1320{
1321 return 0x1f << 0; 1321 return 0x1fU << 0U;
1322} 1322}
1323static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) 1323static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
1324{ 1324{
1325 return (r >> 0) & 0x1f; 1325 return (r >> 0U) & 0x1fU;
1326} 1326}
1327static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) 1327static inline u32 gr_fecs_ctxsw_status_fe_0_r(void)
1328{ 1328{
1329 return 0x00409c00; 1329 return 0x00409c00U;
1330} 1330}
1331static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) 1331static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void)
1332{ 1332{
1333 return 0x00502c04; 1333 return 0x00502c04U;
1334} 1334}
1335static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) 1335static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
1336{ 1336{
1337 return 0x00502400; 1337 return 0x00502400U;
1338} 1338}
1339static inline u32 gr_fecs_ctxsw_idlestate_r(void) 1339static inline u32 gr_fecs_ctxsw_idlestate_r(void)
1340{ 1340{
1341 return 0x00409420; 1341 return 0x00409420U;
1342} 1342}
1343static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) 1343static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
1344{ 1344{
1345 return 0x00502420; 1345 return 0x00502420U;
1346} 1346}
1347static inline u32 gr_rstr2d_gpc_map0_r(void) 1347static inline u32 gr_rstr2d_gpc_map0_r(void)
1348{ 1348{
1349 return 0x0040780c; 1349 return 0x0040780cU;
1350} 1350}
1351static inline u32 gr_rstr2d_gpc_map1_r(void) 1351static inline u32 gr_rstr2d_gpc_map1_r(void)
1352{ 1352{
1353 return 0x00407810; 1353 return 0x00407810U;
1354} 1354}
1355static inline u32 gr_rstr2d_gpc_map2_r(void) 1355static inline u32 gr_rstr2d_gpc_map2_r(void)
1356{ 1356{
1357 return 0x00407814; 1357 return 0x00407814U;
1358} 1358}
1359static inline u32 gr_rstr2d_gpc_map3_r(void) 1359static inline u32 gr_rstr2d_gpc_map3_r(void)
1360{ 1360{
1361 return 0x00407818; 1361 return 0x00407818U;
1362} 1362}
1363static inline u32 gr_rstr2d_gpc_map4_r(void) 1363static inline u32 gr_rstr2d_gpc_map4_r(void)
1364{ 1364{
1365 return 0x0040781c; 1365 return 0x0040781cU;
1366} 1366}
1367static inline u32 gr_rstr2d_gpc_map5_r(void) 1367static inline u32 gr_rstr2d_gpc_map5_r(void)
1368{ 1368{
1369 return 0x00407820; 1369 return 0x00407820U;
1370} 1370}
1371static inline u32 gr_rstr2d_map_table_cfg_r(void) 1371static inline u32 gr_rstr2d_map_table_cfg_r(void)
1372{ 1372{
1373 return 0x004078bc; 1373 return 0x004078bcU;
1374} 1374}
1375static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) 1375static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v)
1376{ 1376{
1377 return (v & 0xff) << 0; 1377 return (v & 0xffU) << 0U;
1378} 1378}
1379static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) 1379static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v)
1380{ 1380{
1381 return (v & 0xff) << 8; 1381 return (v & 0xffU) << 8U;
1382} 1382}
1383static inline u32 gr_pd_hww_esr_r(void) 1383static inline u32 gr_pd_hww_esr_r(void)
1384{ 1384{
1385 return 0x00406018; 1385 return 0x00406018U;
1386} 1386}
1387static inline u32 gr_pd_hww_esr_reset_active_f(void) 1387static inline u32 gr_pd_hww_esr_reset_active_f(void)
1388{ 1388{
1389 return 0x40000000; 1389 return 0x40000000U;
1390} 1390}
1391static inline u32 gr_pd_hww_esr_en_enable_f(void) 1391static inline u32 gr_pd_hww_esr_en_enable_f(void)
1392{ 1392{
1393 return 0x80000000; 1393 return 0x80000000U;
1394} 1394}
1395static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) 1395static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i)
1396{ 1396{
1397 return 0x00406028 + i*4; 1397 return 0x00406028U + i*4U;
1398} 1398}
1399static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) 1399static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void)
1400{ 1400{
1401 return 0x00000004; 1401 return 0x00000004U;
1402} 1402}
1403static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) 1403static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v)
1404{ 1404{
1405 return (v & 0xf) << 0; 1405 return (v & 0xfU) << 0U;
1406} 1406}
1407static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) 1407static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v)
1408{ 1408{
1409 return (v & 0xf) << 4; 1409 return (v & 0xfU) << 4U;
1410} 1410}
1411static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) 1411static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v)
1412{ 1412{
1413 return (v & 0xf) << 8; 1413 return (v & 0xfU) << 8U;
1414} 1414}
1415static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) 1415static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v)
1416{ 1416{
1417 return (v & 0xf) << 12; 1417 return (v & 0xfU) << 12U;
1418} 1418}
1419static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) 1419static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v)
1420{ 1420{
1421 return (v & 0xf) << 16; 1421 return (v & 0xfU) << 16U;
1422} 1422}
1423static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) 1423static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v)
1424{ 1424{
1425 return (v & 0xf) << 20; 1425 return (v & 0xfU) << 20U;
1426} 1426}
1427static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) 1427static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v)
1428{ 1428{
1429 return (v & 0xf) << 24; 1429 return (v & 0xfU) << 24U;
1430} 1430}
1431static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) 1431static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v)
1432{ 1432{
1433 return (v & 0xf) << 28; 1433 return (v & 0xfU) << 28U;
1434} 1434}
1435static inline u32 gr_pd_ab_dist_cfg0_r(void) 1435static inline u32 gr_pd_ab_dist_cfg0_r(void)
1436{ 1436{
1437 return 0x004064c0; 1437 return 0x004064c0U;
1438} 1438}
1439static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) 1439static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void)
1440{ 1440{
1441 return 0x80000000; 1441 return 0x80000000U;
1442} 1442}
1443static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) 1443static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void)
1444{ 1444{
1445 return 0x0; 1445 return 0x0U;
1446} 1446}
1447static inline u32 gr_pd_ab_dist_cfg1_r(void) 1447static inline u32 gr_pd_ab_dist_cfg1_r(void)
1448{ 1448{
1449 return 0x004064c4; 1449 return 0x004064c4U;
1450} 1450}
1451static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) 1451static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
1452{ 1452{
1453 return 0xffff; 1453 return 0xffffU;
1454} 1454}
1455static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) 1455static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v)
1456{ 1456{
1457 return (v & 0xffff) << 16; 1457 return (v & 0xffffU) << 16U;
1458} 1458}
1459static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) 1459static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void)
1460{ 1460{
1461 return 0x00000080; 1461 return 0x00000080U;
1462} 1462}
1463static inline u32 gr_pd_ab_dist_cfg2_r(void) 1463static inline u32 gr_pd_ab_dist_cfg2_r(void)
1464{ 1464{
1465 return 0x004064c8; 1465 return 0x004064c8U;
1466} 1466}
1467static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) 1467static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
1468{ 1468{
1469 return (v & 0xfff) << 0; 1469 return (v & 0xfffU) << 0U;
1470} 1470}
1471static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) 1471static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
1472{ 1472{
1473 return 0x000001c0; 1473 return 0x000001c0U;
1474} 1474}
1475static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) 1475static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
1476{ 1476{
1477 return (v & 0xfff) << 16; 1477 return (v & 0xfffU) << 16U;
1478} 1478}
1479static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) 1479static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
1480{ 1480{
1481 return 0x00000020; 1481 return 0x00000020U;
1482} 1482}
1483static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) 1483static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
1484{ 1484{
1485 return 0x00000182; 1485 return 0x00000182U;
1486} 1486}
1487static inline u32 gr_pd_pagepool_r(void) 1487static inline u32 gr_pd_pagepool_r(void)
1488{ 1488{
1489 return 0x004064cc; 1489 return 0x004064ccU;
1490} 1490}
1491static inline u32 gr_pd_pagepool_total_pages_f(u32 v) 1491static inline u32 gr_pd_pagepool_total_pages_f(u32 v)
1492{ 1492{
1493 return (v & 0xff) << 0; 1493 return (v & 0xffU) << 0U;
1494} 1494}
1495static inline u32 gr_pd_pagepool_valid_true_f(void) 1495static inline u32 gr_pd_pagepool_valid_true_f(void)
1496{ 1496{
1497 return 0x80000000; 1497 return 0x80000000U;
1498} 1498}
1499static inline u32 gr_pd_dist_skip_table_r(u32 i) 1499static inline u32 gr_pd_dist_skip_table_r(u32 i)
1500{ 1500{
1501 return 0x004064d0 + i*4; 1501 return 0x004064d0U + i*4U;
1502} 1502}
1503static inline u32 gr_pd_dist_skip_table__size_1_v(void) 1503static inline u32 gr_pd_dist_skip_table__size_1_v(void)
1504{ 1504{
1505 return 0x00000008; 1505 return 0x00000008U;
1506} 1506}
1507static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) 1507static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v)
1508{ 1508{
1509 return (v & 0xff) << 0; 1509 return (v & 0xffU) << 0U;
1510} 1510}
1511static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) 1511static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v)
1512{ 1512{
1513 return (v & 0xff) << 8; 1513 return (v & 0xffU) << 8U;
1514} 1514}
1515static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) 1515static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v)
1516{ 1516{
1517 return (v & 0xff) << 16; 1517 return (v & 0xffU) << 16U;
1518} 1518}
1519static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) 1519static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v)
1520{ 1520{
1521 return (v & 0xff) << 24; 1521 return (v & 0xffU) << 24U;
1522} 1522}
1523static inline u32 gr_ds_debug_r(void) 1523static inline u32 gr_ds_debug_r(void)
1524{ 1524{
1525 return 0x00405800; 1525 return 0x00405800U;
1526} 1526}
1527static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) 1527static inline u32 gr_ds_debug_timeslice_mode_disable_f(void)
1528{ 1528{
1529 return 0x0; 1529 return 0x0U;
1530} 1530}
1531static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) 1531static inline u32 gr_ds_debug_timeslice_mode_enable_f(void)
1532{ 1532{
1533 return 0x8000000; 1533 return 0x8000000U;
1534} 1534}
1535static inline u32 gr_ds_zbc_color_r_r(void) 1535static inline u32 gr_ds_zbc_color_r_r(void)
1536{ 1536{
1537 return 0x00405804; 1537 return 0x00405804U;
1538} 1538}
1539static inline u32 gr_ds_zbc_color_r_val_f(u32 v) 1539static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
1540{ 1540{
1541 return (v & 0xffffffff) << 0; 1541 return (v & 0xffffffffU) << 0U;
1542} 1542}
1543static inline u32 gr_ds_zbc_color_g_r(void) 1543static inline u32 gr_ds_zbc_color_g_r(void)
1544{ 1544{
1545 return 0x00405808; 1545 return 0x00405808U;
1546} 1546}
1547static inline u32 gr_ds_zbc_color_g_val_f(u32 v) 1547static inline u32 gr_ds_zbc_color_g_val_f(u32 v)
1548{ 1548{
1549 return (v & 0xffffffff) << 0; 1549 return (v & 0xffffffffU) << 0U;
1550} 1550}
1551static inline u32 gr_ds_zbc_color_b_r(void) 1551static inline u32 gr_ds_zbc_color_b_r(void)
1552{ 1552{
1553 return 0x0040580c; 1553 return 0x0040580cU;
1554} 1554}
1555static inline u32 gr_ds_zbc_color_b_val_f(u32 v) 1555static inline u32 gr_ds_zbc_color_b_val_f(u32 v)
1556{ 1556{
1557 return (v & 0xffffffff) << 0; 1557 return (v & 0xffffffffU) << 0U;
1558} 1558}
1559static inline u32 gr_ds_zbc_color_a_r(void) 1559static inline u32 gr_ds_zbc_color_a_r(void)
1560{ 1560{
1561 return 0x00405810; 1561 return 0x00405810U;
1562} 1562}
1563static inline u32 gr_ds_zbc_color_a_val_f(u32 v) 1563static inline u32 gr_ds_zbc_color_a_val_f(u32 v)
1564{ 1564{
1565 return (v & 0xffffffff) << 0; 1565 return (v & 0xffffffffU) << 0U;
1566} 1566}
1567static inline u32 gr_ds_zbc_color_fmt_r(void) 1567static inline u32 gr_ds_zbc_color_fmt_r(void)
1568{ 1568{
1569 return 0x00405814; 1569 return 0x00405814U;
1570} 1570}
1571static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) 1571static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v)
1572{ 1572{
1573 return (v & 0x7f) << 0; 1573 return (v & 0x7fU) << 0U;
1574} 1574}
1575static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) 1575static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void)
1576{ 1576{
1577 return 0x0; 1577 return 0x0U;
1578} 1578}
1579static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) 1579static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void)
1580{ 1580{
1581 return 0x00000001; 1581 return 0x00000001U;
1582} 1582}
1583static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) 1583static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void)
1584{ 1584{
1585 return 0x00000002; 1585 return 0x00000002U;
1586} 1586}
1587static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) 1587static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
1588{ 1588{
1589 return 0x00000004; 1589 return 0x00000004U;
1590} 1590}
1591static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) 1591static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
1592{ 1592{
1593 return 0x00000028; 1593 return 0x00000028U;
1594} 1594}
1595static inline u32 gr_ds_zbc_z_r(void) 1595static inline u32 gr_ds_zbc_z_r(void)
1596{ 1596{
1597 return 0x00405818; 1597 return 0x00405818U;
1598} 1598}
1599static inline u32 gr_ds_zbc_z_val_s(void) 1599static inline u32 gr_ds_zbc_z_val_s(void)
1600{ 1600{
1601 return 32; 1601 return 32U;
1602} 1602}
1603static inline u32 gr_ds_zbc_z_val_f(u32 v) 1603static inline u32 gr_ds_zbc_z_val_f(u32 v)
1604{ 1604{
1605 return (v & 0xffffffff) << 0; 1605 return (v & 0xffffffffU) << 0U;
1606} 1606}
1607static inline u32 gr_ds_zbc_z_val_m(void) 1607static inline u32 gr_ds_zbc_z_val_m(void)
1608{ 1608{
1609 return 0xffffffff << 0; 1609 return 0xffffffffU << 0U;
1610} 1610}
1611static inline u32 gr_ds_zbc_z_val_v(u32 r) 1611static inline u32 gr_ds_zbc_z_val_v(u32 r)
1612{ 1612{
1613 return (r >> 0) & 0xffffffff; 1613 return (r >> 0U) & 0xffffffffU;
1614} 1614}
1615static inline u32 gr_ds_zbc_z_val__init_v(void) 1615static inline u32 gr_ds_zbc_z_val__init_v(void)
1616{ 1616{
1617 return 0x00000000; 1617 return 0x00000000U;
1618} 1618}
1619static inline u32 gr_ds_zbc_z_val__init_f(void) 1619static inline u32 gr_ds_zbc_z_val__init_f(void)
1620{ 1620{
1621 return 0x0; 1621 return 0x0U;
1622} 1622}
1623static inline u32 gr_ds_zbc_z_fmt_r(void) 1623static inline u32 gr_ds_zbc_z_fmt_r(void)
1624{ 1624{
1625 return 0x0040581c; 1625 return 0x0040581cU;
1626} 1626}
1627static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) 1627static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v)
1628{ 1628{
1629 return (v & 0x1) << 0; 1629 return (v & 0x1U) << 0U;
1630} 1630}
1631static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) 1631static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void)
1632{ 1632{
1633 return 0x0; 1633 return 0x0U;
1634} 1634}
1635static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) 1635static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void)
1636{ 1636{
1637 return 0x00000001; 1637 return 0x00000001U;
1638} 1638}
1639static inline u32 gr_ds_zbc_tbl_index_r(void) 1639static inline u32 gr_ds_zbc_tbl_index_r(void)
1640{ 1640{
1641 return 0x00405820; 1641 return 0x00405820U;
1642} 1642}
1643static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) 1643static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v)
1644{ 1644{
1645 return (v & 0xf) << 0; 1645 return (v & 0xfU) << 0U;
1646} 1646}
1647static inline u32 gr_ds_zbc_tbl_ld_r(void) 1647static inline u32 gr_ds_zbc_tbl_ld_r(void)
1648{ 1648{
1649 return 0x00405824; 1649 return 0x00405824U;
1650} 1650}
1651static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) 1651static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void)
1652{ 1652{
1653 return 0x0; 1653 return 0x0U;
1654} 1654}
1655static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) 1655static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void)
1656{ 1656{
1657 return 0x1; 1657 return 0x1U;
1658} 1658}
1659static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) 1659static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void)
1660{ 1660{
1661 return 0x0; 1661 return 0x0U;
1662} 1662}
1663static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) 1663static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
1664{ 1664{
1665 return 0x4; 1665 return 0x4U;
1666} 1666}
1667static inline u32 gr_ds_tga_constraintlogic_r(void) 1667static inline u32 gr_ds_tga_constraintlogic_r(void)
1668{ 1668{
1669 return 0x00405830; 1669 return 0x00405830U;
1670} 1670}
1671static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) 1671static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
1672{ 1672{
1673 return (v & 0xffff) << 16; 1673 return (v & 0xffffU) << 16U;
1674} 1674}
1675static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) 1675static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v)
1676{ 1676{
1677 return (v & 0xffff) << 0; 1677 return (v & 0xffffU) << 0U;
1678} 1678}
1679static inline u32 gr_ds_hww_esr_r(void) 1679static inline u32 gr_ds_hww_esr_r(void)
1680{ 1680{
1681 return 0x00405840; 1681 return 0x00405840U;
1682} 1682}
1683static inline u32 gr_ds_hww_esr_reset_s(void) 1683static inline u32 gr_ds_hww_esr_reset_s(void)
1684{ 1684{
1685 return 1; 1685 return 1U;
1686} 1686}
1687static inline u32 gr_ds_hww_esr_reset_f(u32 v) 1687static inline u32 gr_ds_hww_esr_reset_f(u32 v)
1688{ 1688{
1689 return (v & 0x1) << 30; 1689 return (v & 0x1U) << 30U;
1690} 1690}
1691static inline u32 gr_ds_hww_esr_reset_m(void) 1691static inline u32 gr_ds_hww_esr_reset_m(void)
1692{ 1692{
1693 return 0x1 << 30; 1693 return 0x1U << 30U;
1694} 1694}
1695static inline u32 gr_ds_hww_esr_reset_v(u32 r) 1695static inline u32 gr_ds_hww_esr_reset_v(u32 r)
1696{ 1696{
1697 return (r >> 30) & 0x1; 1697 return (r >> 30U) & 0x1U;
1698} 1698}
1699static inline u32 gr_ds_hww_esr_reset_task_v(void) 1699static inline u32 gr_ds_hww_esr_reset_task_v(void)
1700{ 1700{
1701 return 0x00000001; 1701 return 0x00000001U;
1702} 1702}
1703static inline u32 gr_ds_hww_esr_reset_task_f(void) 1703static inline u32 gr_ds_hww_esr_reset_task_f(void)
1704{ 1704{
1705 return 0x40000000; 1705 return 0x40000000U;
1706} 1706}
1707static inline u32 gr_ds_hww_esr_en_enabled_f(void) 1707static inline u32 gr_ds_hww_esr_en_enabled_f(void)
1708{ 1708{
1709 return 0x80000000; 1709 return 0x80000000U;
1710} 1710}
1711static inline u32 gr_ds_hww_esr_2_r(void) 1711static inline u32 gr_ds_hww_esr_2_r(void)
1712{ 1712{
1713 return 0x00405848; 1713 return 0x00405848U;
1714} 1714}
1715static inline u32 gr_ds_hww_esr_2_reset_s(void) 1715static inline u32 gr_ds_hww_esr_2_reset_s(void)
1716{ 1716{
1717 return 1; 1717 return 1U;
1718} 1718}
1719static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) 1719static inline u32 gr_ds_hww_esr_2_reset_f(u32 v)
1720{ 1720{
1721 return (v & 0x1) << 30; 1721 return (v & 0x1U) << 30U;
1722} 1722}
1723static inline u32 gr_ds_hww_esr_2_reset_m(void) 1723static inline u32 gr_ds_hww_esr_2_reset_m(void)
1724{ 1724{
1725 return 0x1 << 30; 1725 return 0x1U << 30U;
1726} 1726}
1727static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) 1727static inline u32 gr_ds_hww_esr_2_reset_v(u32 r)
1728{ 1728{
1729 return (r >> 30) & 0x1; 1729 return (r >> 30U) & 0x1U;
1730} 1730}
1731static inline u32 gr_ds_hww_esr_2_reset_task_v(void) 1731static inline u32 gr_ds_hww_esr_2_reset_task_v(void)
1732{ 1732{
1733 return 0x00000001; 1733 return 0x00000001U;
1734} 1734}
1735static inline u32 gr_ds_hww_esr_2_reset_task_f(void) 1735static inline u32 gr_ds_hww_esr_2_reset_task_f(void)
1736{ 1736{
1737 return 0x40000000; 1737 return 0x40000000U;
1738} 1738}
1739static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) 1739static inline u32 gr_ds_hww_esr_2_en_enabled_f(void)
1740{ 1740{
1741 return 0x80000000; 1741 return 0x80000000U;
1742} 1742}
1743static inline u32 gr_ds_hww_report_mask_r(void) 1743static inline u32 gr_ds_hww_report_mask_r(void)
1744{ 1744{
1745 return 0x00405844; 1745 return 0x00405844U;
1746} 1746}
1747static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) 1747static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void)
1748{ 1748{
1749 return 0x1; 1749 return 0x1U;
1750} 1750}
1751static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) 1751static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void)
1752{ 1752{
1753 return 0x2; 1753 return 0x2U;
1754} 1754}
1755static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) 1755static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void)
1756{ 1756{
1757 return 0x4; 1757 return 0x4U;
1758} 1758}
1759static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) 1759static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void)
1760{ 1760{
1761 return 0x8; 1761 return 0x8U;
1762} 1762}
1763static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) 1763static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void)
1764{ 1764{
1765 return 0x10; 1765 return 0x10U;
1766} 1766}
1767static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) 1767static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void)
1768{ 1768{
1769 return 0x20; 1769 return 0x20U;
1770} 1770}
1771static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) 1771static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void)
1772{ 1772{
1773 return 0x40; 1773 return 0x40U;
1774} 1774}
1775static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) 1775static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void)
1776{ 1776{
1777 return 0x80; 1777 return 0x80U;
1778} 1778}
1779static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) 1779static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void)
1780{ 1780{
1781 return 0x100; 1781 return 0x100U;
1782} 1782}
1783static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) 1783static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void)
1784{ 1784{
1785 return 0x200; 1785 return 0x200U;
1786} 1786}
1787static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) 1787static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void)
1788{ 1788{
1789 return 0x400; 1789 return 0x400U;
1790} 1790}
1791static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) 1791static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void)
1792{ 1792{
1793 return 0x800; 1793 return 0x800U;
1794} 1794}
1795static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) 1795static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void)
1796{ 1796{
1797 return 0x1000; 1797 return 0x1000U;
1798} 1798}
1799static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) 1799static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void)
1800{ 1800{
1801 return 0x2000; 1801 return 0x2000U;
1802} 1802}
1803static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) 1803static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void)
1804{ 1804{
1805 return 0x4000; 1805 return 0x4000U;
1806} 1806}
1807static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) 1807static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void)
1808{ 1808{
1809 return 0x8000; 1809 return 0x8000U;
1810} 1810}
1811static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) 1811static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void)
1812{ 1812{
1813 return 0x10000; 1813 return 0x10000U;
1814} 1814}
1815static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) 1815static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void)
1816{ 1816{
1817 return 0x20000; 1817 return 0x20000U;
1818} 1818}
1819static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) 1819static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void)
1820{ 1820{
1821 return 0x40000; 1821 return 0x40000U;
1822} 1822}
1823static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) 1823static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void)
1824{ 1824{
1825 return 0x80000; 1825 return 0x80000U;
1826} 1826}
1827static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) 1827static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void)
1828{ 1828{
1829 return 0x100000; 1829 return 0x100000U;
1830} 1830}
1831static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) 1831static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void)
1832{ 1832{
1833 return 0x200000; 1833 return 0x200000U;
1834} 1834}
1835static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) 1835static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void)
1836{ 1836{
1837 return 0x400000; 1837 return 0x400000U;
1838} 1838}
1839static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) 1839static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void)
1840{ 1840{
1841 return 0x800000; 1841 return 0x800000U;
1842} 1842}
1843static inline u32 gr_ds_hww_report_mask_2_r(void) 1843static inline u32 gr_ds_hww_report_mask_2_r(void)
1844{ 1844{
1845 return 0x0040584c; 1845 return 0x0040584cU;
1846} 1846}
1847static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) 1847static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void)
1848{ 1848{
1849 return 0x1; 1849 return 0x1U;
1850} 1850}
1851static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) 1851static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i)
1852{ 1852{
1853 return 0x00405870 + i*4; 1853 return 0x00405870U + i*4U;
1854} 1854}
1855static inline u32 gr_scc_bundle_cb_base_r(void) 1855static inline u32 gr_scc_bundle_cb_base_r(void)
1856{ 1856{
1857 return 0x00408004; 1857 return 0x00408004U;
1858} 1858}
1859static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) 1859static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v)
1860{ 1860{
1861 return (v & 0xffffffff) << 0; 1861 return (v & 0xffffffffU) << 0U;
1862} 1862}
1863static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) 1863static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void)
1864{ 1864{
1865 return 0x00000008; 1865 return 0x00000008U;
1866} 1866}
1867static inline u32 gr_scc_bundle_cb_size_r(void) 1867static inline u32 gr_scc_bundle_cb_size_r(void)
1868{ 1868{
1869 return 0x00408008; 1869 return 0x00408008U;
1870} 1870}
1871static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) 1871static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
1872{ 1872{
1873 return (v & 0x7ff) << 0; 1873 return (v & 0x7ffU) << 0U;
1874} 1874}
1875static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) 1875static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
1876{ 1876{
1877 return 0x00000018; 1877 return 0x00000018U;
1878} 1878}
1879static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) 1879static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
1880{ 1880{
1881 return 0x00000100; 1881 return 0x00000100U;
1882} 1882}
1883static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) 1883static inline u32 gr_scc_bundle_cb_size_valid_false_v(void)
1884{ 1884{
1885 return 0x00000000; 1885 return 0x00000000U;
1886} 1886}
1887static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) 1887static inline u32 gr_scc_bundle_cb_size_valid_false_f(void)
1888{ 1888{
1889 return 0x0; 1889 return 0x0U;
1890} 1890}
1891static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) 1891static inline u32 gr_scc_bundle_cb_size_valid_true_f(void)
1892{ 1892{
1893 return 0x80000000; 1893 return 0x80000000U;
1894} 1894}
1895static inline u32 gr_scc_pagepool_base_r(void) 1895static inline u32 gr_scc_pagepool_base_r(void)
1896{ 1896{
1897 return 0x0040800c; 1897 return 0x0040800cU;
1898} 1898}
1899static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) 1899static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v)
1900{ 1900{
1901 return (v & 0xffffffff) << 0; 1901 return (v & 0xffffffffU) << 0U;
1902} 1902}
1903static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) 1903static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void)
1904{ 1904{
1905 return 0x00000008; 1905 return 0x00000008U;
1906} 1906}
1907static inline u32 gr_scc_pagepool_r(void) 1907static inline u32 gr_scc_pagepool_r(void)
1908{ 1908{
1909 return 0x00408010; 1909 return 0x00408010U;
1910} 1910}
1911static inline u32 gr_scc_pagepool_total_pages_f(u32 v) 1911static inline u32 gr_scc_pagepool_total_pages_f(u32 v)
1912{ 1912{
1913 return (v & 0xff) << 0; 1913 return (v & 0xffU) << 0U;
1914} 1914}
1915static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) 1915static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
1916{ 1916{
1917 return 0x00000000; 1917 return 0x00000000U;
1918} 1918}
1919static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) 1919static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void)
1920{ 1920{
1921 return 0x00000080; 1921 return 0x00000080U;
1922} 1922}
1923static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) 1923static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
1924{ 1924{
1925 return 0x00000100; 1925 return 0x00000100U;
1926} 1926}
1927static inline u32 gr_scc_pagepool_max_valid_pages_s(void) 1927static inline u32 gr_scc_pagepool_max_valid_pages_s(void)
1928{ 1928{
1929 return 8; 1929 return 8U;
1930} 1930}
1931static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) 1931static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
1932{ 1932{
1933 return (v & 0xff) << 8; 1933 return (v & 0xffU) << 8U;
1934} 1934}
1935static inline u32 gr_scc_pagepool_max_valid_pages_m(void) 1935static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
1936{ 1936{
1937 return 0xff << 8; 1937 return 0xffU << 8U;
1938} 1938}
1939static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) 1939static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
1940{ 1940{
1941 return (r >> 8) & 0xff; 1941 return (r >> 8U) & 0xffU;
1942} 1942}
1943static inline u32 gr_scc_pagepool_valid_true_f(void) 1943static inline u32 gr_scc_pagepool_valid_true_f(void)
1944{ 1944{
1945 return 0x80000000; 1945 return 0x80000000U;
1946} 1946}
1947static inline u32 gr_scc_init_r(void) 1947static inline u32 gr_scc_init_r(void)
1948{ 1948{
1949 return 0x0040802c; 1949 return 0x0040802cU;
1950} 1950}
1951static inline u32 gr_scc_init_ram_trigger_f(void) 1951static inline u32 gr_scc_init_ram_trigger_f(void)
1952{ 1952{
1953 return 0x1; 1953 return 0x1U;
1954} 1954}
1955static inline u32 gr_scc_hww_esr_r(void) 1955static inline u32 gr_scc_hww_esr_r(void)
1956{ 1956{
1957 return 0x00408030; 1957 return 0x00408030U;
1958} 1958}
1959static inline u32 gr_scc_hww_esr_reset_active_f(void) 1959static inline u32 gr_scc_hww_esr_reset_active_f(void)
1960{ 1960{
1961 return 0x40000000; 1961 return 0x40000000U;
1962} 1962}
1963static inline u32 gr_scc_hww_esr_en_enable_f(void) 1963static inline u32 gr_scc_hww_esr_en_enable_f(void)
1964{ 1964{
1965 return 0x80000000; 1965 return 0x80000000U;
1966} 1966}
1967static inline u32 gr_sked_hww_esr_r(void) 1967static inline u32 gr_sked_hww_esr_r(void)
1968{ 1968{
1969 return 0x00407020; 1969 return 0x00407020U;
1970} 1970}
1971static inline u32 gr_sked_hww_esr_reset_active_f(void) 1971static inline u32 gr_sked_hww_esr_reset_active_f(void)
1972{ 1972{
1973 return 0x40000000; 1973 return 0x40000000U;
1974} 1974}
1975static inline u32 gr_cwd_fs_r(void) 1975static inline u32 gr_cwd_fs_r(void)
1976{ 1976{
1977 return 0x00405b00; 1977 return 0x00405b00U;
1978} 1978}
1979static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) 1979static inline u32 gr_cwd_fs_num_gpcs_f(u32 v)
1980{ 1980{
1981 return (v & 0xff) << 0; 1981 return (v & 0xffU) << 0U;
1982} 1982}
1983static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) 1983static inline u32 gr_cwd_fs_num_tpcs_f(u32 v)
1984{ 1984{
1985 return (v & 0xff) << 8; 1985 return (v & 0xffU) << 8U;
1986} 1986}
1987static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) 1987static inline u32 gr_cwd_gpc_tpc_id_r(u32 i)
1988{ 1988{
1989 return 0x00405b60 + i*4; 1989 return 0x00405b60U + i*4U;
1990} 1990}
1991static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) 1991static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void)
1992{ 1992{
1993 return 4; 1993 return 4U;
1994} 1994}
1995static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) 1995static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v)
1996{ 1996{
1997 return (v & 0xf) << 0; 1997 return (v & 0xfU) << 0U;
1998} 1998}
1999static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) 1999static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void)
2000{ 2000{
2001 return 4; 2001 return 4U;
2002} 2002}
2003static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) 2003static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v)
2004{ 2004{
2005 return (v & 0xf) << 4; 2005 return (v & 0xfU) << 4U;
2006} 2006}
2007static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) 2007static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v)
2008{ 2008{
2009 return (v & 0xf) << 8; 2009 return (v & 0xfU) << 8U;
2010} 2010}
2011static inline u32 gr_cwd_sm_id_r(u32 i) 2011static inline u32 gr_cwd_sm_id_r(u32 i)
2012{ 2012{
2013 return 0x00405ba0 + i*4; 2013 return 0x00405ba0U + i*4U;
2014} 2014}
2015static inline u32 gr_cwd_sm_id__size_1_v(void) 2015static inline u32 gr_cwd_sm_id__size_1_v(void)
2016{ 2016{
2017 return 0x00000006; 2017 return 0x00000006U;
2018} 2018}
2019static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) 2019static inline u32 gr_cwd_sm_id_tpc0_f(u32 v)
2020{ 2020{
2021 return (v & 0xff) << 0; 2021 return (v & 0xffU) << 0U;
2022} 2022}
2023static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) 2023static inline u32 gr_cwd_sm_id_tpc1_f(u32 v)
2024{ 2024{
2025 return (v & 0xff) << 8; 2025 return (v & 0xffU) << 8U;
2026} 2026}
2027static inline u32 gr_gpc0_fs_gpc_r(void) 2027static inline u32 gr_gpc0_fs_gpc_r(void)
2028{ 2028{
2029 return 0x00502608; 2029 return 0x00502608U;
2030} 2030}
2031static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) 2031static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r)
2032{ 2032{
2033 return (r >> 0) & 0x1f; 2033 return (r >> 0U) & 0x1fU;
2034} 2034}
2035static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) 2035static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r)
2036{ 2036{
2037 return (r >> 16) & 0x1f; 2037 return (r >> 16U) & 0x1fU;
2038} 2038}
2039static inline u32 gr_gpc0_cfg_r(void) 2039static inline u32 gr_gpc0_cfg_r(void)
2040{ 2040{
2041 return 0x00502620; 2041 return 0x00502620U;
2042} 2042}
2043static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) 2043static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r)
2044{ 2044{
2045 return (r >> 0) & 0xff; 2045 return (r >> 0U) & 0xffU;
2046} 2046}
2047static inline u32 gr_gpccs_rc_lanes_r(void) 2047static inline u32 gr_gpccs_rc_lanes_r(void)
2048{ 2048{
2049 return 0x00502880; 2049 return 0x00502880U;
2050} 2050}
2051static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) 2051static inline u32 gr_gpccs_rc_lanes_num_chains_s(void)
2052{ 2052{
2053 return 6; 2053 return 6U;
2054} 2054}
2055static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) 2055static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
2056{ 2056{
2057 return (v & 0x3f) << 0; 2057 return (v & 0x3fU) << 0U;
2058} 2058}
2059static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) 2059static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
2060{ 2060{
2061 return 0x3f << 0; 2061 return 0x3fU << 0U;
2062} 2062}
2063static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) 2063static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
2064{ 2064{
2065 return (r >> 0) & 0x3f; 2065 return (r >> 0U) & 0x3fU;
2066} 2066}
2067static inline u32 gr_gpccs_rc_lane_size_r(u32 i) 2067static inline u32 gr_gpccs_rc_lane_size_r(u32 i)
2068{ 2068{
2069 return 0x00502910 + i*0; 2069 return 0x00502910U + i*0U;
2070} 2070}
2071static inline u32 gr_gpccs_rc_lane_size__size_1_v(void) 2071static inline u32 gr_gpccs_rc_lane_size__size_1_v(void)
2072{ 2072{
2073 return 0x00000010; 2073 return 0x00000010U;
2074} 2074}
2075static inline u32 gr_gpccs_rc_lane_size_v_s(void) 2075static inline u32 gr_gpccs_rc_lane_size_v_s(void)
2076{ 2076{
2077 return 24; 2077 return 24U;
2078} 2078}
2079static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) 2079static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
2080{ 2080{
2081 return (v & 0xffffff) << 0; 2081 return (v & 0xffffffU) << 0U;
2082} 2082}
2083static inline u32 gr_gpccs_rc_lane_size_v_m(void) 2083static inline u32 gr_gpccs_rc_lane_size_v_m(void)
2084{ 2084{
2085 return 0xffffff << 0; 2085 return 0xffffffU << 0U;
2086} 2086}
2087static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) 2087static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
2088{ 2088{
2089 return (r >> 0) & 0xffffff; 2089 return (r >> 0U) & 0xffffffU;
2090} 2090}
2091static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) 2091static inline u32 gr_gpccs_rc_lane_size_v_0_v(void)
2092{ 2092{
2093 return 0x00000000; 2093 return 0x00000000U;
2094} 2094}
2095static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) 2095static inline u32 gr_gpccs_rc_lane_size_v_0_f(void)
2096{ 2096{
2097 return 0x0; 2097 return 0x0U;
2098} 2098}
2099static inline u32 gr_gpc0_zcull_fs_r(void) 2099static inline u32 gr_gpc0_zcull_fs_r(void)
2100{ 2100{
2101 return 0x00500910; 2101 return 0x00500910U;
2102} 2102}
2103static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) 2103static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v)
2104{ 2104{
2105 return (v & 0x1ff) << 0; 2105 return (v & 0x1ffU) << 0U;
2106} 2106}
2107static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) 2107static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v)
2108{ 2108{
2109 return (v & 0xf) << 16; 2109 return (v & 0xfU) << 16U;
2110} 2110}
2111static inline u32 gr_gpc0_zcull_ram_addr_r(void) 2111static inline u32 gr_gpc0_zcull_ram_addr_r(void)
2112{ 2112{
2113 return 0x00500914; 2113 return 0x00500914U;
2114} 2114}
2115static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) 2115static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v)
2116{ 2116{
2117 return (v & 0xf) << 0; 2117 return (v & 0xfU) << 0U;
2118} 2118}
2119static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) 2119static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v)
2120{ 2120{
2121 return (v & 0xf) << 8; 2121 return (v & 0xfU) << 8U;
2122} 2122}
2123static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) 2123static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void)
2124{ 2124{
2125 return 0x00500918; 2125 return 0x00500918U;
2126} 2126}
2127static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) 2127static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v)
2128{ 2128{
2129 return (v & 0xffffff) << 0; 2129 return (v & 0xffffffU) << 0U;
2130} 2130}
2131static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) 2131static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void)
2132{ 2132{
2133 return 0x00800000; 2133 return 0x00800000U;
2134} 2134}
2135static inline u32 gr_gpc0_zcull_total_ram_size_r(void) 2135static inline u32 gr_gpc0_zcull_total_ram_size_r(void)
2136{ 2136{
2137 return 0x00500920; 2137 return 0x00500920U;
2138} 2138}
2139static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) 2139static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v)
2140{ 2140{
2141 return (v & 0xffff) << 0; 2141 return (v & 0xffffU) << 0U;
2142} 2142}
2143static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) 2143static inline u32 gr_gpc0_zcull_zcsize_r(u32 i)
2144{ 2144{
2145 return 0x00500a04 + i*32; 2145 return 0x00500a04U + i*32U;
2146} 2146}
2147static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) 2147static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void)
2148{ 2148{
2149 return 0x00000040; 2149 return 0x00000040U;
2150} 2150}
2151static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) 2151static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void)
2152{ 2152{
2153 return 0x00000010; 2153 return 0x00000010U;
2154} 2154}
2155static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) 2155static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i)
2156{ 2156{
2157 return 0x00500c10 + i*4; 2157 return 0x00500c10U + i*4U;
2158} 2158}
2159static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) 2159static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v)
2160{ 2160{
2161 return (v & 0xff) << 0; 2161 return (v & 0xffU) << 0U;
2162} 2162}
2163static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) 2163static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i)
2164{ 2164{
2165 return 0x00500c30 + i*4; 2165 return 0x00500c30U + i*4U;
2166} 2166}
2167static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) 2167static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r)
2168{ 2168{
2169 return (r >> 0) & 0xff; 2169 return (r >> 0U) & 0xffU;
2170} 2170}
2171static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) 2171static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void)
2172{ 2172{
2173 return 0x00504088; 2173 return 0x00504088U;
2174} 2174}
2175static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) 2175static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
2176{ 2176{
2177 return (v & 0xffff) << 0; 2177 return (v & 0xffffU) << 0U;
2178} 2178}
2179static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) 2179static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
2180{ 2180{
2181 return 0x00504698; 2181 return 0x00504698U;
2182} 2182}
2183static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) 2183static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v)
2184{ 2184{
2185 return (v & 0xffff) << 0; 2185 return (v & 0xffffU) << 0U;
2186} 2186}
2187static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r) 2187static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r)
2188{ 2188{
2189 return (r >> 0) & 0xffff; 2189 return (r >> 0U) & 0xffffU;
2190} 2190}
2191static inline u32 gr_gpc0_tpc0_sm_arch_r(void) 2191static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
2192{ 2192{
2193 return 0x0050469c; 2193 return 0x0050469cU;
2194} 2194}
2195static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) 2195static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
2196{ 2196{
2197 return (r >> 0) & 0xff; 2197 return (r >> 0U) & 0xffU;
2198} 2198}
2199static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) 2199static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r)
2200{ 2200{
2201 return (r >> 8) & 0xfff; 2201 return (r >> 8U) & 0xfffU;
2202} 2202}
2203static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) 2203static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r)
2204{ 2204{
2205 return (r >> 20) & 0xfff; 2205 return (r >> 20U) & 0xfffU;
2206} 2206}
2207static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) 2207static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
2208{ 2208{
2209 return 0x00503018; 2209 return 0x00503018U;
2210} 2210}
2211static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) 2211static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
2212{ 2212{
2213 return 0x1 << 0; 2213 return 0x1U << 0U;
2214} 2214}
2215static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) 2215static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
2216{ 2216{
2217 return 0x1; 2217 return 0x1U;
2218} 2218}
2219static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) 2219static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void)
2220{ 2220{
2221 return 0x005030c0; 2221 return 0x005030c0U;
2222} 2222}
2223static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) 2223static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v)
2224{ 2224{
2225 return (v & 0xffff) << 0; 2225 return (v & 0xffffU) << 0U;
2226} 2226}
2227static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) 2227static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
2228{ 2228{
2229 return 0xffff << 0; 2229 return 0xffffU << 0U;
2230} 2230}
2231static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) 2231static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
2232{ 2232{
2233 return 0x00000400; 2233 return 0x00000400U;
2234} 2234}
2235static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) 2235static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
2236{ 2236{
2237 return 0x00000020; 2237 return 0x00000020U;
2238} 2238}
2239static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) 2239static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void)
2240{ 2240{
2241 return 0x005030f4; 2241 return 0x005030f4U;
2242} 2242}
2243static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) 2243static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void)
2244{ 2244{
2245 return 0x005030e4; 2245 return 0x005030e4U;
2246} 2246}
2247static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) 2247static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v)
2248{ 2248{
2249 return (v & 0xffff) << 0; 2249 return (v & 0xffffU) << 0U;
2250} 2250}
2251static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) 2251static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void)
2252{ 2252{
2253 return 0xffff << 0; 2253 return 0xffffU << 0U;
2254} 2254}
2255static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) 2255static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void)
2256{ 2256{
2257 return 0x00000800; 2257 return 0x00000800U;
2258} 2258}
2259static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) 2259static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void)
2260{ 2260{
2261 return 0x00000020; 2261 return 0x00000020U;
2262} 2262}
2263static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) 2263static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void)
2264{ 2264{
2265 return 0x005030f8; 2265 return 0x005030f8U;
2266} 2266}
2267static inline u32 gr_gpcs_tpcs_tex_m_dbg2_r(void) 2267static inline u32 gr_gpcs_tpcs_tex_m_dbg2_r(void)
2268{ 2268{
2269 return 0x00419a3c; 2269 return 0x00419a3cU;
2270} 2270}
2271static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(u32 v) 2271static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(u32 v)
2272{ 2272{
2273 return (v & 0x1) << 2; 2273 return (v & 0x1U) << 2U;
2274} 2274}
2275static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void) 2275static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void)
2276{ 2276{
2277 return 0x1 << 2; 2277 return 0x1U << 2U;
2278} 2278}
2279static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v) 2279static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(u32 v)
2280{ 2280{
2281 return (v & 0x1) << 4; 2281 return (v & 0x1U) << 4U;
2282} 2282}
2283static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void) 2283static inline u32 gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(void)
2284{ 2284{
2285 return 0x1 << 4; 2285 return 0x1U << 4U;
2286} 2286}
2287static inline u32 gr_gpccs_falcon_addr_r(void) 2287static inline u32 gr_gpccs_falcon_addr_r(void)
2288{ 2288{
2289 return 0x0041a0ac; 2289 return 0x0041a0acU;
2290} 2290}
2291static inline u32 gr_gpccs_falcon_addr_lsb_s(void) 2291static inline u32 gr_gpccs_falcon_addr_lsb_s(void)
2292{ 2292{
2293 return 6; 2293 return 6U;
2294} 2294}
2295static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) 2295static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
2296{ 2296{
2297 return (v & 0x3f) << 0; 2297 return (v & 0x3fU) << 0U;
2298} 2298}
2299static inline u32 gr_gpccs_falcon_addr_lsb_m(void) 2299static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
2300{ 2300{
2301 return 0x3f << 0; 2301 return 0x3fU << 0U;
2302} 2302}
2303static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) 2303static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
2304{ 2304{
2305 return (r >> 0) & 0x3f; 2305 return (r >> 0U) & 0x3fU;
2306} 2306}
2307static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) 2307static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void)
2308{ 2308{
2309 return 0x00000000; 2309 return 0x00000000U;
2310} 2310}
2311static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) 2311static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void)
2312{ 2312{
2313 return 0x0; 2313 return 0x0U;
2314} 2314}
2315static inline u32 gr_gpccs_falcon_addr_msb_s(void) 2315static inline u32 gr_gpccs_falcon_addr_msb_s(void)
2316{ 2316{
2317 return 6; 2317 return 6U;
2318} 2318}
2319static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) 2319static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
2320{ 2320{
2321 return (v & 0x3f) << 6; 2321 return (v & 0x3fU) << 6U;
2322} 2322}
2323static inline u32 gr_gpccs_falcon_addr_msb_m(void) 2323static inline u32 gr_gpccs_falcon_addr_msb_m(void)
2324{ 2324{
2325 return 0x3f << 6; 2325 return 0x3fU << 6U;
2326} 2326}
2327static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) 2327static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
2328{ 2328{
2329 return (r >> 6) & 0x3f; 2329 return (r >> 6U) & 0x3fU;
2330} 2330}
2331static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) 2331static inline u32 gr_gpccs_falcon_addr_msb_init_v(void)
2332{ 2332{
2333 return 0x00000000; 2333 return 0x00000000U;
2334} 2334}
2335static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) 2335static inline u32 gr_gpccs_falcon_addr_msb_init_f(void)
2336{ 2336{
2337 return 0x0; 2337 return 0x0U;
2338} 2338}
2339static inline u32 gr_gpccs_falcon_addr_ext_s(void) 2339static inline u32 gr_gpccs_falcon_addr_ext_s(void)
2340{ 2340{
2341 return 12; 2341 return 12U;
2342} 2342}
2343static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) 2343static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
2344{ 2344{
2345 return (v & 0xfff) << 0; 2345 return (v & 0xfffU) << 0U;
2346} 2346}
2347static inline u32 gr_gpccs_falcon_addr_ext_m(void) 2347static inline u32 gr_gpccs_falcon_addr_ext_m(void)
2348{ 2348{
2349 return 0xfff << 0; 2349 return 0xfffU << 0U;
2350} 2350}
2351static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) 2351static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
2352{ 2352{
2353 return (r >> 0) & 0xfff; 2353 return (r >> 0U) & 0xfffU;
2354} 2354}
2355static inline u32 gr_gpccs_cpuctl_r(void) 2355static inline u32 gr_gpccs_cpuctl_r(void)
2356{ 2356{
2357 return 0x0041a100; 2357 return 0x0041a100U;
2358} 2358}
2359static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) 2359static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v)
2360{ 2360{
2361 return (v & 0x1) << 1; 2361 return (v & 0x1U) << 1U;
2362} 2362}
2363static inline u32 gr_gpccs_dmactl_r(void) 2363static inline u32 gr_gpccs_dmactl_r(void)
2364{ 2364{
2365 return 0x0041a10c; 2365 return 0x0041a10cU;
2366} 2366}
2367static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) 2367static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
2368{ 2368{
2369 return (v & 0x1) << 0; 2369 return (v & 0x1U) << 0U;
2370} 2370}
2371static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) 2371static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
2372{ 2372{
2373 return 0x1 << 1; 2373 return 0x1U << 1U;
2374} 2374}
2375static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) 2375static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
2376{ 2376{
2377 return 0x1 << 2; 2377 return 0x1U << 2U;
2378} 2378}
2379static inline u32 gr_gpccs_imemc_r(u32 i) 2379static inline u32 gr_gpccs_imemc_r(u32 i)
2380{ 2380{
2381 return 0x0041a180 + i*16; 2381 return 0x0041a180U + i*16U;
2382} 2382}
2383static inline u32 gr_gpccs_imemc_offs_f(u32 v) 2383static inline u32 gr_gpccs_imemc_offs_f(u32 v)
2384{ 2384{
2385 return (v & 0x3f) << 2; 2385 return (v & 0x3fU) << 2U;
2386} 2386}
2387static inline u32 gr_gpccs_imemc_blk_f(u32 v) 2387static inline u32 gr_gpccs_imemc_blk_f(u32 v)
2388{ 2388{
2389 return (v & 0xff) << 8; 2389 return (v & 0xffU) << 8U;
2390} 2390}
2391static inline u32 gr_gpccs_imemc_aincw_f(u32 v) 2391static inline u32 gr_gpccs_imemc_aincw_f(u32 v)
2392{ 2392{
2393 return (v & 0x1) << 24; 2393 return (v & 0x1U) << 24U;
2394} 2394}
2395static inline u32 gr_gpccs_imemd_r(u32 i) 2395static inline u32 gr_gpccs_imemd_r(u32 i)
2396{ 2396{
2397 return 0x0041a184 + i*16; 2397 return 0x0041a184U + i*16U;
2398} 2398}
2399static inline u32 gr_gpccs_imemt_r(u32 i) 2399static inline u32 gr_gpccs_imemt_r(u32 i)
2400{ 2400{
2401 return 0x0041a188 + i*16; 2401 return 0x0041a188U + i*16U;
2402} 2402}
2403static inline u32 gr_gpccs_imemt__size_1_v(void) 2403static inline u32 gr_gpccs_imemt__size_1_v(void)
2404{ 2404{
2405 return 0x00000004; 2405 return 0x00000004U;
2406} 2406}
2407static inline u32 gr_gpccs_imemt_tag_f(u32 v) 2407static inline u32 gr_gpccs_imemt_tag_f(u32 v)
2408{ 2408{
2409 return (v & 0xffff) << 0; 2409 return (v & 0xffffU) << 0U;
2410} 2410}
2411static inline u32 gr_gpccs_dmemc_r(u32 i) 2411static inline u32 gr_gpccs_dmemc_r(u32 i)
2412{ 2412{
2413 return 0x0041a1c0 + i*8; 2413 return 0x0041a1c0U + i*8U;
2414} 2414}
2415static inline u32 gr_gpccs_dmemc_offs_f(u32 v) 2415static inline u32 gr_gpccs_dmemc_offs_f(u32 v)
2416{ 2416{
2417 return (v & 0x3f) << 2; 2417 return (v & 0x3fU) << 2U;
2418} 2418}
2419static inline u32 gr_gpccs_dmemc_blk_f(u32 v) 2419static inline u32 gr_gpccs_dmemc_blk_f(u32 v)
2420{ 2420{
2421 return (v & 0xff) << 8; 2421 return (v & 0xffU) << 8U;
2422} 2422}
2423static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) 2423static inline u32 gr_gpccs_dmemc_aincw_f(u32 v)
2424{ 2424{
2425 return (v & 0x1) << 24; 2425 return (v & 0x1U) << 24U;
2426} 2426}
2427static inline u32 gr_gpccs_dmemd_r(u32 i) 2427static inline u32 gr_gpccs_dmemd_r(u32 i)
2428{ 2428{
2429 return 0x0041a1c4 + i*8; 2429 return 0x0041a1c4U + i*8U;
2430} 2430}
2431static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) 2431static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i)
2432{ 2432{
2433 return 0x0041a800 + i*4; 2433 return 0x0041a800U + i*4U;
2434} 2434}
2435static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) 2435static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v)
2436{ 2436{
2437 return (v & 0xffffffff) << 0; 2437 return (v & 0xffffffffU) << 0U;
2438} 2438}
2439static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) 2439static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void)
2440{ 2440{
2441 return 0x00418e24; 2441 return 0x00418e24U;
2442} 2442}
2443static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) 2443static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void)
2444{ 2444{
2445 return 32; 2445 return 32U;
2446} 2446}
2447static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) 2447static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v)
2448{ 2448{
2449 return (v & 0xffffffff) << 0; 2449 return (v & 0xffffffffU) << 0U;
2450} 2450}
2451static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) 2451static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void)
2452{ 2452{
2453 return 0xffffffff << 0; 2453 return 0xffffffffU << 0U;
2454} 2454}
2455static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) 2455static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r)
2456{ 2456{
2457 return (r >> 0) & 0xffffffff; 2457 return (r >> 0U) & 0xffffffffU;
2458} 2458}
2459static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) 2459static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void)
2460{ 2460{
2461 return 0x00000000; 2461 return 0x00000000U;
2462} 2462}
2463static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) 2463static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void)
2464{ 2464{
2465 return 0x0; 2465 return 0x0U;
2466} 2466}
2467static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) 2467static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void)
2468{ 2468{
2469 return 0x00418e28; 2469 return 0x00418e28U;
2470} 2470}
2471static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) 2471static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void)
2472{ 2472{
2473 return 11; 2473 return 11U;
2474} 2474}
2475static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) 2475static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v)
2476{ 2476{
2477 return (v & 0x7ff) << 0; 2477 return (v & 0x7ffU) << 0U;
2478} 2478}
2479static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) 2479static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void)
2480{ 2480{
2481 return 0x7ff << 0; 2481 return 0x7ffU << 0U;
2482} 2482}
2483static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) 2483static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
2484{ 2484{
2485 return (r >> 0) & 0x7ff; 2485 return (r >> 0U) & 0x7ffU;
2486} 2486}
2487static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) 2487static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void)
2488{ 2488{
2489 return 0x00000018; 2489 return 0x00000018U;
2490} 2490}
2491static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) 2491static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void)
2492{ 2492{
2493 return 0x18; 2493 return 0x18U;
2494} 2494}
2495static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) 2495static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void)
2496{ 2496{
2497 return 1; 2497 return 1U;
2498} 2498}
2499static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) 2499static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v)
2500{ 2500{
2501 return (v & 0x1) << 31; 2501 return (v & 0x1U) << 31U;
2502} 2502}
2503static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) 2503static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void)
2504{ 2504{
2505 return 0x1 << 31; 2505 return 0x1U << 31U;
2506} 2506}
2507static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) 2507static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r)
2508{ 2508{
2509 return (r >> 31) & 0x1; 2509 return (r >> 31U) & 0x1U;
2510} 2510}
2511static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) 2511static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void)
2512{ 2512{
2513 return 0x00000000; 2513 return 0x00000000U;
2514} 2514}
2515static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) 2515static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void)
2516{ 2516{
2517 return 0x0; 2517 return 0x0U;
2518} 2518}
2519static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) 2519static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void)
2520{ 2520{
2521 return 0x00000001; 2521 return 0x00000001U;
2522} 2522}
2523static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) 2523static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void)
2524{ 2524{
2525 return 0x80000000; 2525 return 0x80000000U;
2526} 2526}
2527static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) 2527static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i)
2528{ 2528{
2529 return 0x00418ea0 + i*4; 2529 return 0x00418ea0U + i*4U;
2530} 2530}
2531static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) 2531static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
2532{ 2532{
2533 return (v & 0xffff) << 0; 2533 return (v & 0xffffU) << 0U;
2534} 2534}
2535static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) 2535static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
2536{ 2536{
2537 return 0xffff << 0; 2537 return 0xffffU << 0U;
2538} 2538}
2539static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_f(u32 v) 2539static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_f(u32 v)
2540{ 2540{
2541 return (v & 0xffff) << 16; 2541 return (v & 0xffffU) << 16U;
2542} 2542}
2543static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_m(void) 2543static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_m(void)
2544{ 2544{
2545 return 0xffff << 16; 2545 return 0xffffU << 16U;
2546} 2546}
2547static inline u32 gr_gpcs_swdx_rm_pagepool_r(void) 2547static inline u32 gr_gpcs_swdx_rm_pagepool_r(void)
2548{ 2548{
2549 return 0x00418e30; 2549 return 0x00418e30U;
2550} 2550}
2551static inline u32 gr_gpcs_swdx_rm_pagepool_total_pages_f(u32 v) 2551static inline u32 gr_gpcs_swdx_rm_pagepool_total_pages_f(u32 v)
2552{ 2552{
2553 return (v & 0xff) << 0; 2553 return (v & 0xffU) << 0U;
2554} 2554}
2555static inline u32 gr_gpcs_swdx_rm_pagepool_valid_true_f(void) 2555static inline u32 gr_gpcs_swdx_rm_pagepool_valid_true_f(void)
2556{ 2556{
2557 return 0x80000000; 2557 return 0x80000000U;
2558} 2558}
2559static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) 2559static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
2560{ 2560{
2561 return 0x00418810; 2561 return 0x00418810U;
2562} 2562}
2563static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) 2563static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v)
2564{ 2564{
2565 return (v & 0xfffffff) << 0; 2565 return (v & 0xfffffffU) << 0U;
2566} 2566}
2567static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) 2567static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void)
2568{ 2568{
2569 return 0x0000000c; 2569 return 0x0000000cU;
2570} 2570}
2571static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) 2571static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
2572{ 2572{
2573 return 0x80000000; 2573 return 0x80000000U;
2574} 2574}
2575static inline u32 gr_crstr_gpc_map0_r(void) 2575static inline u32 gr_crstr_gpc_map0_r(void)
2576{ 2576{
2577 return 0x00418b08; 2577 return 0x00418b08U;
2578} 2578}
2579static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v) 2579static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v)
2580{ 2580{
2581 return (v & 0x7) << 0; 2581 return (v & 0x7U) << 0U;
2582} 2582}
2583static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v) 2583static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v)
2584{ 2584{
2585 return (v & 0x7) << 5; 2585 return (v & 0x7U) << 5U;
2586} 2586}
2587static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v) 2587static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v)
2588{ 2588{
2589 return (v & 0x7) << 10; 2589 return (v & 0x7U) << 10U;
2590} 2590}
2591static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v) 2591static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v)
2592{ 2592{
2593 return (v & 0x7) << 15; 2593 return (v & 0x7U) << 15U;
2594} 2594}
2595static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v) 2595static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v)
2596{ 2596{
2597 return (v & 0x7) << 20; 2597 return (v & 0x7U) << 20U;
2598} 2598}
2599static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v) 2599static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v)
2600{ 2600{
2601 return (v & 0x7) << 25; 2601 return (v & 0x7U) << 25U;
2602} 2602}
2603static inline u32 gr_crstr_gpc_map1_r(void) 2603static inline u32 gr_crstr_gpc_map1_r(void)
2604{ 2604{
2605 return 0x00418b0c; 2605 return 0x00418b0cU;
2606} 2606}
2607static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v) 2607static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v)
2608{ 2608{
2609 return (v & 0x7) << 0; 2609 return (v & 0x7U) << 0U;
2610} 2610}
2611static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v) 2611static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v)
2612{ 2612{
2613 return (v & 0x7) << 5; 2613 return (v & 0x7U) << 5U;
2614} 2614}
2615static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v) 2615static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v)
2616{ 2616{
2617 return (v & 0x7) << 10; 2617 return (v & 0x7U) << 10U;
2618} 2618}
2619static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v) 2619static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v)
2620{ 2620{
2621 return (v & 0x7) << 15; 2621 return (v & 0x7U) << 15U;
2622} 2622}
2623static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v) 2623static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v)
2624{ 2624{
2625 return (v & 0x7) << 20; 2625 return (v & 0x7U) << 20U;
2626} 2626}
2627static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v) 2627static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v)
2628{ 2628{
2629 return (v & 0x7) << 25; 2629 return (v & 0x7U) << 25U;
2630} 2630}
2631static inline u32 gr_crstr_gpc_map2_r(void) 2631static inline u32 gr_crstr_gpc_map2_r(void)
2632{ 2632{
2633 return 0x00418b10; 2633 return 0x00418b10U;
2634} 2634}
2635static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v) 2635static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v)
2636{ 2636{
2637 return (v & 0x7) << 0; 2637 return (v & 0x7U) << 0U;
2638} 2638}
2639static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v) 2639static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v)
2640{ 2640{
2641 return (v & 0x7) << 5; 2641 return (v & 0x7U) << 5U;
2642} 2642}
2643static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v) 2643static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v)
2644{ 2644{
2645 return (v & 0x7) << 10; 2645 return (v & 0x7U) << 10U;
2646} 2646}
2647static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v) 2647static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v)
2648{ 2648{
2649 return (v & 0x7) << 15; 2649 return (v & 0x7U) << 15U;
2650} 2650}
2651static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v) 2651static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v)
2652{ 2652{
2653 return (v & 0x7) << 20; 2653 return (v & 0x7U) << 20U;
2654} 2654}
2655static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v) 2655static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v)
2656{ 2656{
2657 return (v & 0x7) << 25; 2657 return (v & 0x7U) << 25U;
2658} 2658}
2659static inline u32 gr_crstr_gpc_map3_r(void) 2659static inline u32 gr_crstr_gpc_map3_r(void)
2660{ 2660{
2661 return 0x00418b14; 2661 return 0x00418b14U;
2662} 2662}
2663static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v) 2663static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v)
2664{ 2664{
2665 return (v & 0x7) << 0; 2665 return (v & 0x7U) << 0U;
2666} 2666}
2667static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v) 2667static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v)
2668{ 2668{
2669 return (v & 0x7) << 5; 2669 return (v & 0x7U) << 5U;
2670} 2670}
2671static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v) 2671static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v)
2672{ 2672{
2673 return (v & 0x7) << 10; 2673 return (v & 0x7U) << 10U;
2674} 2674}
2675static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v) 2675static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v)
2676{ 2676{
2677 return (v & 0x7) << 15; 2677 return (v & 0x7U) << 15U;
2678} 2678}
2679static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v) 2679static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v)
2680{ 2680{
2681 return (v & 0x7) << 20; 2681 return (v & 0x7U) << 20U;
2682} 2682}
2683static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v) 2683static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v)
2684{ 2684{
2685 return (v & 0x7) << 25; 2685 return (v & 0x7U) << 25U;
2686} 2686}
2687static inline u32 gr_crstr_gpc_map4_r(void) 2687static inline u32 gr_crstr_gpc_map4_r(void)
2688{ 2688{
2689 return 0x00418b18; 2689 return 0x00418b18U;
2690} 2690}
2691static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v) 2691static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v)
2692{ 2692{
2693 return (v & 0x7) << 0; 2693 return (v & 0x7U) << 0U;
2694} 2694}
2695static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v) 2695static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v)
2696{ 2696{
2697 return (v & 0x7) << 5; 2697 return (v & 0x7U) << 5U;
2698} 2698}
2699static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v) 2699static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v)
2700{ 2700{
2701 return (v & 0x7) << 10; 2701 return (v & 0x7U) << 10U;
2702} 2702}
2703static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v) 2703static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v)
2704{ 2704{
2705 return (v & 0x7) << 15; 2705 return (v & 0x7U) << 15U;
2706} 2706}
2707static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v) 2707static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v)
2708{ 2708{
2709 return (v & 0x7) << 20; 2709 return (v & 0x7U) << 20U;
2710} 2710}
2711static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v) 2711static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v)
2712{ 2712{
2713 return (v & 0x7) << 25; 2713 return (v & 0x7U) << 25U;
2714} 2714}
2715static inline u32 gr_crstr_gpc_map5_r(void) 2715static inline u32 gr_crstr_gpc_map5_r(void)
2716{ 2716{
2717 return 0x00418b1c; 2717 return 0x00418b1cU;
2718} 2718}
2719static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v) 2719static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v)
2720{ 2720{
2721 return (v & 0x7) << 0; 2721 return (v & 0x7U) << 0U;
2722} 2722}
2723static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v) 2723static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v)
2724{ 2724{
2725 return (v & 0x7) << 5; 2725 return (v & 0x7U) << 5U;
2726} 2726}
2727static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v) 2727static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v)
2728{ 2728{
2729 return (v & 0x7) << 10; 2729 return (v & 0x7U) << 10U;
2730} 2730}
2731static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v) 2731static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v)
2732{ 2732{
2733 return (v & 0x7) << 15; 2733 return (v & 0x7U) << 15U;
2734} 2734}
2735static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v) 2735static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v)
2736{ 2736{
2737 return (v & 0x7) << 20; 2737 return (v & 0x7U) << 20U;
2738} 2738}
2739static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v) 2739static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v)
2740{ 2740{
2741 return (v & 0x7) << 25; 2741 return (v & 0x7U) << 25U;
2742} 2742}
2743static inline u32 gr_crstr_map_table_cfg_r(void) 2743static inline u32 gr_crstr_map_table_cfg_r(void)
2744{ 2744{
2745 return 0x00418bb8; 2745 return 0x00418bb8U;
2746} 2746}
2747static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) 2747static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v)
2748{ 2748{
2749 return (v & 0xff) << 0; 2749 return (v & 0xffU) << 0U;
2750} 2750}
2751static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) 2751static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
2752{ 2752{
2753 return (v & 0xff) << 8; 2753 return (v & 0xffU) << 8U;
2754} 2754}
2755static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void) 2755static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void)
2756{ 2756{
2757 return 0x00418980; 2757 return 0x00418980U;
2758} 2758}
2759static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v) 2759static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v)
2760{ 2760{
2761 return (v & 0x7) << 0; 2761 return (v & 0x7U) << 0U;
2762} 2762}
2763static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v) 2763static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v)
2764{ 2764{
2765 return (v & 0x7) << 4; 2765 return (v & 0x7U) << 4U;
2766} 2766}
2767static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v) 2767static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v)
2768{ 2768{
2769 return (v & 0x7) << 8; 2769 return (v & 0x7U) << 8U;
2770} 2770}
2771static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v) 2771static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v)
2772{ 2772{
2773 return (v & 0x7) << 12; 2773 return (v & 0x7U) << 12U;
2774} 2774}
2775static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v) 2775static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v)
2776{ 2776{
2777 return (v & 0x7) << 16; 2777 return (v & 0x7U) << 16U;
2778} 2778}
2779static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v) 2779static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v)
2780{ 2780{
2781 return (v & 0x7) << 20; 2781 return (v & 0x7U) << 20U;
2782} 2782}
2783static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v) 2783static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v)
2784{ 2784{
2785 return (v & 0x7) << 24; 2785 return (v & 0x7U) << 24U;
2786} 2786}
2787static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v) 2787static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v)
2788{ 2788{
2789 return (v & 0x7) << 28; 2789 return (v & 0x7U) << 28U;
2790} 2790}
2791static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void) 2791static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void)
2792{ 2792{
2793 return 0x00418984; 2793 return 0x00418984U;
2794} 2794}
2795static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v) 2795static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v)
2796{ 2796{
2797 return (v & 0x7) << 0; 2797 return (v & 0x7U) << 0U;
2798} 2798}
2799static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v) 2799static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v)
2800{ 2800{
2801 return (v & 0x7) << 4; 2801 return (v & 0x7U) << 4U;
2802} 2802}
2803static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v) 2803static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v)
2804{ 2804{
2805 return (v & 0x7) << 8; 2805 return (v & 0x7U) << 8U;
2806} 2806}
2807static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v) 2807static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v)
2808{ 2808{
2809 return (v & 0x7) << 12; 2809 return (v & 0x7U) << 12U;
2810} 2810}
2811static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v) 2811static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v)
2812{ 2812{
2813 return (v & 0x7) << 16; 2813 return (v & 0x7U) << 16U;
2814} 2814}
2815static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v) 2815static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v)
2816{ 2816{
2817 return (v & 0x7) << 20; 2817 return (v & 0x7U) << 20U;
2818} 2818}
2819static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v) 2819static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v)
2820{ 2820{
2821 return (v & 0x7) << 24; 2821 return (v & 0x7U) << 24U;
2822} 2822}
2823static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v) 2823static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v)
2824{ 2824{
2825 return (v & 0x7) << 28; 2825 return (v & 0x7U) << 28U;
2826} 2826}
2827static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void) 2827static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void)
2828{ 2828{
2829 return 0x00418988; 2829 return 0x00418988U;
2830} 2830}
2831static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v) 2831static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v)
2832{ 2832{
2833 return (v & 0x7) << 0; 2833 return (v & 0x7U) << 0U;
2834} 2834}
2835static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v) 2835static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v)
2836{ 2836{
2837 return (v & 0x7) << 4; 2837 return (v & 0x7U) << 4U;
2838} 2838}
2839static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v) 2839static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v)
2840{ 2840{
2841 return (v & 0x7) << 8; 2841 return (v & 0x7U) << 8U;
2842} 2842}
2843static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v) 2843static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v)
2844{ 2844{
2845 return (v & 0x7) << 12; 2845 return (v & 0x7U) << 12U;
2846} 2846}
2847static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v) 2847static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v)
2848{ 2848{
2849 return (v & 0x7) << 16; 2849 return (v & 0x7U) << 16U;
2850} 2850}
2851static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v) 2851static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v)
2852{ 2852{
2853 return (v & 0x7) << 20; 2853 return (v & 0x7U) << 20U;
2854} 2854}
2855static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v) 2855static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v)
2856{ 2856{
2857 return (v & 0x7) << 24; 2857 return (v & 0x7U) << 24U;
2858} 2858}
2859static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void) 2859static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void)
2860{ 2860{
2861 return 3; 2861 return 3U;
2862} 2862}
2863static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v) 2863static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v)
2864{ 2864{
2865 return (v & 0x7) << 28; 2865 return (v & 0x7U) << 28U;
2866} 2866}
2867static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void) 2867static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void)
2868{ 2868{
2869 return 0x7 << 28; 2869 return 0x7U << 28U;
2870} 2870}
2871static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r) 2871static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r)
2872{ 2872{
2873 return (r >> 28) & 0x7; 2873 return (r >> 28U) & 0x7U;
2874} 2874}
2875static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void) 2875static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void)
2876{ 2876{
2877 return 0x0041898c; 2877 return 0x0041898cU;
2878} 2878}
2879static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v) 2879static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v)
2880{ 2880{
2881 return (v & 0x7) << 0; 2881 return (v & 0x7U) << 0U;
2882} 2882}
2883static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v) 2883static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v)
2884{ 2884{
2885 return (v & 0x7) << 4; 2885 return (v & 0x7U) << 4U;
2886} 2886}
2887static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v) 2887static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v)
2888{ 2888{
2889 return (v & 0x7) << 8; 2889 return (v & 0x7U) << 8U;
2890} 2890}
2891static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v) 2891static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v)
2892{ 2892{
2893 return (v & 0x7) << 12; 2893 return (v & 0x7U) << 12U;
2894} 2894}
2895static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v) 2895static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v)
2896{ 2896{
2897 return (v & 0x7) << 16; 2897 return (v & 0x7U) << 16U;
2898} 2898}
2899static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v) 2899static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v)
2900{ 2900{
2901 return (v & 0x7) << 20; 2901 return (v & 0x7U) << 20U;
2902} 2902}
2903static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v) 2903static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v)
2904{ 2904{
2905 return (v & 0x7) << 24; 2905 return (v & 0x7U) << 24U;
2906} 2906}
2907static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v) 2907static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v)
2908{ 2908{
2909 return (v & 0x7) << 28; 2909 return (v & 0x7U) << 28U;
2910} 2910}
2911static inline u32 gr_gpcs_gpm_pd_cfg_r(void) 2911static inline u32 gr_gpcs_gpm_pd_cfg_r(void)
2912{ 2912{
2913 return 0x00418c6c; 2913 return 0x00418c6cU;
2914} 2914}
2915static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void) 2915static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void)
2916{ 2916{
2917 return 0x0; 2917 return 0x0U;
2918} 2918}
2919static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void) 2919static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void)
2920{ 2920{
2921 return 0x1; 2921 return 0x1U;
2922} 2922}
2923static inline u32 gr_gpcs_gcc_pagepool_base_r(void) 2923static inline u32 gr_gpcs_gcc_pagepool_base_r(void)
2924{ 2924{
2925 return 0x00419004; 2925 return 0x00419004U;
2926} 2926}
2927static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) 2927static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v)
2928{ 2928{
2929 return (v & 0xffffffff) << 0; 2929 return (v & 0xffffffffU) << 0U;
2930} 2930}
2931static inline u32 gr_gpcs_gcc_pagepool_r(void) 2931static inline u32 gr_gpcs_gcc_pagepool_r(void)
2932{ 2932{
2933 return 0x00419008; 2933 return 0x00419008U;
2934} 2934}
2935static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) 2935static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v)
2936{ 2936{
2937 return (v & 0xff) << 0; 2937 return (v & 0xffU) << 0U;
2938} 2938}
2939static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) 2939static inline u32 gr_gpcs_tpcs_pe_vaf_r(void)
2940{ 2940{
2941 return 0x0041980c; 2941 return 0x0041980cU;
2942} 2942}
2943static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) 2943static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void)
2944{ 2944{
2945 return 0x10; 2945 return 0x10U;
2946} 2946}
2947static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) 2947static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void)
2948{ 2948{
2949 return 0x00419848; 2949 return 0x00419848U;
2950} 2950}
2951static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) 2951static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v)
2952{ 2952{
2953 return (v & 0xfffffff) << 0; 2953 return (v & 0xfffffffU) << 0U;
2954} 2954}
2955static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) 2955static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v)
2956{ 2956{
2957 return (v & 0x1) << 28; 2957 return (v & 0x1U) << 28U;
2958} 2958}
2959static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) 2959static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
2960{ 2960{
2961 return 0x10000000; 2961 return 0x10000000U;
2962} 2962}
2963static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) 2963static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
2964{ 2964{
2965 return 0x00419c00; 2965 return 0x00419c00U;
2966} 2966}
2967static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) 2967static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void)
2968{ 2968{
2969 return 0x0; 2969 return 0x0U;
2970} 2970}
2971static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) 2971static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
2972{ 2972{
2973 return 0x8; 2973 return 0x8U;
2974} 2974}
2975static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) 2975static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void)
2976{ 2976{
2977 return 0x00419c2c; 2977 return 0x00419c2cU;
2978} 2978}
2979static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) 2979static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v)
2980{ 2980{
2981 return (v & 0xfffffff) << 0; 2981 return (v & 0xfffffffU) << 0U;
2982} 2982}
2983static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) 2983static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v)
2984{ 2984{
2985 return (v & 0x1) << 28; 2985 return (v & 0x1U) << 28U;
2986} 2986}
2987static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) 2987static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void)
2988{ 2988{
2989 return 0x10000000; 2989 return 0x10000000U;
2990} 2990}
2991static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) 2991static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void)
2992{ 2992{
2993 return 0x00419e44; 2993 return 0x00419e44U;
2994} 2994}
2995static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void) 2995static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void)
2996{ 2996{
2997 return 0x2; 2997 return 0x2U;
2998} 2998}
2999static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void) 2999static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void)
3000{ 3000{
3001 return 0x4; 3001 return 0x4U;
3002} 3002}
3003static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void) 3003static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void)
3004{ 3004{
3005 return 0x8; 3005 return 0x8U;
3006} 3006}
3007static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void) 3007static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void)
3008{ 3008{
3009 return 0x10; 3009 return 0x10U;
3010} 3010}
3011static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void) 3011static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
3012{ 3012{
3013 return 0x20; 3013 return 0x20U;
3014} 3014}
3015static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void) 3015static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void)
3016{ 3016{
3017 return 0x40; 3017 return 0x40U;
3018} 3018}
3019static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void) 3019static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void)
3020{ 3020{
3021 return 0x80; 3021 return 0x80U;
3022} 3022}
3023static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void) 3023static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
3024{ 3024{
3025 return 0x100; 3025 return 0x100U;
3026} 3026}
3027static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) 3027static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
3028{ 3028{
3029 return 0x200; 3029 return 0x200U;
3030} 3030}
3031static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void) 3031static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void)
3032{ 3032{
3033 return 0x400; 3033 return 0x400U;
3034} 3034}
3035static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) 3035static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
3036{ 3036{
3037 return 0x800; 3037 return 0x800U;
3038} 3038}
3039static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void) 3039static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void)
3040{ 3040{
3041 return 0x1000; 3041 return 0x1000U;
3042} 3042}
3043static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void) 3043static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void)
3044{ 3044{
3045 return 0x2000; 3045 return 0x2000U;
3046} 3046}
3047static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void) 3047static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void)
3048{ 3048{
3049 return 0x4000; 3049 return 0x4000U;
3050} 3050}
3051static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void) 3051static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
3052{ 3052{
3053 return 0x8000; 3053 return 0x8000U;
3054} 3054}
3055static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) 3055static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
3056{ 3056{
3057 return 0x10000; 3057 return 0x10000U;
3058} 3058}
3059static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void) 3059static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void)
3060{ 3060{
3061 return 0x20000; 3061 return 0x20000U;
3062} 3062}
3063static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) 3063static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
3064{ 3064{
3065 return 0x40000; 3065 return 0x40000U;
3066} 3066}
3067static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void) 3067static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void)
3068{ 3068{
3069 return 0x800000; 3069 return 0x800000U;
3070} 3070}
3071static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void) 3071static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void)
3072{ 3072{
3073 return 0x400000; 3073 return 0x400000U;
3074} 3074}
3075static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void) 3075static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void)
3076{ 3076{
3077 return 0x80000; 3077 return 0x80000U;
3078} 3078}
3079static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void) 3079static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void)
3080{ 3080{
3081 return 0x100000; 3081 return 0x100000U;
3082} 3082}
3083static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r(void) 3083static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r(void)
3084{ 3084{
3085 return 0x00504644; 3085 return 0x00504644U;
3086} 3086}
3087static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) 3087static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void)
3088{ 3088{
3089 return 0x00419e4c; 3089 return 0x00419e4cU;
3090} 3090}
3091static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void) 3091static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void)
3092{ 3092{
3093 return 0x1; 3093 return 0x1U;
3094} 3094}
3095static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void) 3095static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void)
3096{ 3096{
3097 return 0x2; 3097 return 0x2U;
3098} 3098}
3099static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) 3099static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
3100{ 3100{
3101 return 0x4; 3101 return 0x4U;
3102} 3102}
3103static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void) 3103static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void)
3104{ 3104{
3105 return 0x8; 3105 return 0x8U;
3106} 3106}
3107static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void) 3107static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void)
3108{ 3108{
3109 return 0x10; 3109 return 0x10U;
3110} 3110}
3111static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void) 3111static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void)
3112{ 3112{
3113 return 0x20; 3113 return 0x20U;
3114} 3114}
3115static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void) 3115static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void)
3116{ 3116{
3117 return 0x40; 3117 return 0x40U;
3118} 3118}
3119static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r(void) 3119static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r(void)
3120{ 3120{
3121 return 0x0050464c; 3121 return 0x0050464cU;
3122} 3122}
3123static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) 3123static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
3124{ 3124{
3125 return 0x00419d0c; 3125 return 0x00419d0cU;
3126} 3126}
3127static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) 3127static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void)
3128{ 3128{
3129 return 0x2; 3129 return 0x2U;
3130} 3130}
3131static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) 3131static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void)
3132{ 3132{
3133 return 0x1; 3133 return 0x1U;
3134} 3134}
3135static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) 3135static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
3136{ 3136{
3137 return 0x0050450c; 3137 return 0x0050450cU;
3138} 3138}
3139static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) 3139static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
3140{ 3140{
3141 return 0x2; 3141 return 0x2U;
3142} 3142}
3143static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) 3143static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r)
3144{ 3144{
3145 return (r >> 1) & 0x1; 3145 return (r >> 1U) & 0x1U;
3146} 3146}
3147static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) 3147static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void)
3148{ 3148{
3149 return 0x0041ac94; 3149 return 0x0041ac94U;
3150} 3150}
3151static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) 3151static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v)
3152{ 3152{
3153 return (v & 0xff) << 16; 3153 return (v & 0xffU) << 16U;
3154} 3154}
3155static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) 3155static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
3156{ 3156{
3157 return 0x00502c90; 3157 return 0x00502c90U;
3158} 3158}
3159static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) 3159static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r)
3160{ 3160{
3161 return (r >> 2) & 0x1; 3161 return (r >> 2U) & 0x1U;
3162} 3162}
3163static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) 3163static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
3164{ 3164{
3165 return (r >> 16) & 0xff; 3165 return (r >> 16U) & 0xffU;
3166} 3166}
3167static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) 3167static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void)
3168{ 3168{
3169 return 0x00000001; 3169 return 0x00000001U;
3170} 3170}
3171static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) 3171static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void)
3172{ 3172{
3173 return 0x00504508; 3173 return 0x00504508U;
3174} 3174}
3175static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) 3175static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r)
3176{ 3176{
3177 return (r >> 0) & 0x1; 3177 return (r >> 0U) & 0x1U;
3178} 3178}
3179static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) 3179static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void)
3180{ 3180{
3181 return 0x00000001; 3181 return 0x00000001U;
3182} 3182}
3183static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) 3183static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r)
3184{ 3184{
3185 return (r >> 1) & 0x1; 3185 return (r >> 1U) & 0x1U;
3186} 3186}
3187static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) 3187static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
3188{ 3188{
3189 return 0x00000001; 3189 return 0x00000001U;
3190} 3190}
3191static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) 3191static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void)
3192{ 3192{
3193 return 0x00504610; 3193 return 0x00504610U;
3194} 3194}
3195static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void) 3195static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void)
3196{ 3196{
3197 return 0x1 << 0; 3197 return 0x1U << 0U;
3198} 3198}
3199static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) 3199static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r)
3200{ 3200{
3201 return (r >> 0) & 0x1; 3201 return (r >> 0U) & 0x1U;
3202} 3202}
3203static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) 3203static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void)
3204{ 3204{
3205 return 0x00000001; 3205 return 0x00000001U;
3206} 3206}
3207static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void) 3207static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void)
3208{ 3208{
3209 return 0x1; 3209 return 0x1U;
3210} 3210}
3211static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) 3211static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void)
3212{ 3212{
3213 return 0x00000000; 3213 return 0x00000000U;
3214} 3214}
3215static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void) 3215static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void)
3216{ 3216{
3217 return 0x0; 3217 return 0x0U;
3218} 3218}
3219static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) 3219static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void)
3220{ 3220{
3221 return 0x80000000; 3221 return 0x80000000U;
3222} 3222}
3223static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) 3223static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void)
3224{ 3224{
3225 return 0x0; 3225 return 0x0U;
3226} 3226}
3227static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void) 3227static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void)
3228{ 3228{
3229 return 0x8; 3229 return 0x8U;
3230} 3230}
3231static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void) 3231static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void)
3232{ 3232{
3233 return 0x0; 3233 return 0x0U;
3234} 3234}
3235static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) 3235static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void)
3236{ 3236{
3237 return 0x40000000; 3237 return 0x40000000U;
3238} 3238}
3239static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void) 3239static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void)
3240{ 3240{
3241 return 0x1 << 1; 3241 return 0x1U << 1U;
3242} 3242}
3243static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) 3243static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r)
3244{ 3244{
3245 return (r >> 1) & 0x1; 3245 return (r >> 1U) & 0x1U;
3246} 3246}
3247static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) 3247static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void)
3248{ 3248{
3249 return 0x0; 3249 return 0x0U;
3250} 3250}
3251static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void) 3251static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void)
3252{ 3252{
3253 return 0x1 << 2; 3253 return 0x1U << 2U;
3254} 3254}
3255static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) 3255static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r)
3256{ 3256{
3257 return (r >> 2) & 0x1; 3257 return (r >> 2U) & 0x1U;
3258} 3258}
3259static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) 3259static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
3260{ 3260{
3261 return 0x0; 3261 return 0x0U;
3262} 3262}
3263static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void) 3263static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void)
3264{ 3264{
3265 return 0x00000000; 3265 return 0x00000000U;
3266} 3266}
3267static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void) 3267static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void)
3268{ 3268{
3269 return 0x00000000; 3269 return 0x00000000U;
3270} 3270}
3271static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) 3271static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
3272{ 3272{
3273 return 0x00504614; 3273 return 0x00504614U;
3274} 3274}
3275static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void) 3275static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_1_r(void)
3276{ 3276{
3277 return 0x00504618; 3277 return 0x00504618U;
3278} 3278}
3279static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_2_r(void) 3279static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_2_r(void)
3280{ 3280{
3281 return 0x0050461c; 3281 return 0x0050461cU;
3282} 3282}
3283static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) 3283static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
3284{ 3284{
3285 return 0x00504624; 3285 return 0x00504624U;
3286} 3286}
3287static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void) 3287static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r(void)
3288{ 3288{
3289 return 0x00504628; 3289 return 0x00504628U;
3290} 3290}
3291static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_2_r(void) 3291static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_2_r(void)
3292{ 3292{
3293 return 0x00504750; 3293 return 0x00504750U;
3294} 3294}
3295static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) 3295static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
3296{ 3296{
3297 return 0x00504634; 3297 return 0x00504634U;
3298} 3298}
3299static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void) 3299static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r(void)
3300{ 3300{
3301 return 0x00504638; 3301 return 0x00504638U;
3302} 3302}
3303static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_2_r(void) 3303static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_2_r(void)
3304{ 3304{
3305 return 0x00504758; 3305 return 0x00504758U;
3306} 3306}
3307static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) 3307static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void)
3308{ 3308{
3309 return 0x00419e24; 3309 return 0x00419e24U;
3310} 3310}
3311static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) 3311static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
3312{ 3312{
3313 return 0x0050460c; 3313 return 0x0050460cU;
3314} 3314}
3315static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r) 3315static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r)
3316{ 3316{
3317 return (r >> 0) & 0x1; 3317 return (r >> 0U) & 0x1U;
3318} 3318}
3319static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) 3319static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r)
3320{ 3320{
3321 return (r >> 4) & 0x1; 3321 return (r >> 4U) & 0x1U;
3322} 3322}
3323static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) 3323static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void)
3324{ 3324{
3325 return 0x00000001; 3325 return 0x00000001U;
3326} 3326}
3327static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) 3327static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void)
3328{ 3328{
3329 return 0x00419e50; 3329 return 0x00419e50U;
3330} 3330}
3331static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void) 3331static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void)
3332{ 3332{
3333 return 0x10; 3333 return 0x10U;
3334} 3334}
3335static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void) 3335static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void)
3336{ 3336{
3337 return 0x20; 3337 return 0x20U;
3338} 3338}
3339static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void) 3339static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void)
3340{ 3340{
3341 return 0x40; 3341 return 0x40U;
3342} 3342}
3343static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) 3343static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
3344{ 3344{
3345 return 0x1; 3345 return 0x1U;
3346} 3346}
3347static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void) 3347static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void)
3348{ 3348{
3349 return 0x2; 3349 return 0x2U;
3350} 3350}
3351static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void) 3351static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
3352{ 3352{
3353 return 0x4; 3353 return 0x4U;
3354} 3354}
3355static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) 3355static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
3356{ 3356{
3357 return 0x8; 3357 return 0x8U;
3358} 3358}
3359static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void) 3359static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void)
3360{ 3360{
3361 return 0x80000000; 3361 return 0x80000000U;
3362} 3362}
3363static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) 3363static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void)
3364{ 3364{
3365 return 0x00504650; 3365 return 0x00504650U;
3366} 3366}
3367static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void) 3367static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void)
3368{ 3368{
3369 return 0x10; 3369 return 0x10U;
3370} 3370}
3371static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void) 3371static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void)
3372{ 3372{
3373 return 0x20; 3373 return 0x20U;
3374} 3374}
3375static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void) 3375static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void)
3376{ 3376{
3377 return 0x40; 3377 return 0x40U;
3378} 3378}
3379static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) 3379static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void)
3380{ 3380{
3381 return 0x1; 3381 return 0x1U;
3382} 3382}
3383static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void) 3383static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void)
3384{ 3384{
3385 return 0x2; 3385 return 0x2U;
3386} 3386}
3387static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void) 3387static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void)
3388{ 3388{
3389 return 0x4; 3389 return 0x4U;
3390} 3390}
3391static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) 3391static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void)
3392{ 3392{
3393 return 0x8; 3393 return 0x8U;
3394} 3394}
3395static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void) 3395static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void)
3396{ 3396{
3397 return 0x80000000; 3397 return 0x80000000U;
3398} 3398}
3399static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) 3399static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void)
3400{ 3400{
3401 return 0x00504224; 3401 return 0x00504224U;
3402} 3402}
3403static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void) 3403static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void)
3404{ 3404{
3405 return 0x1; 3405 return 0x1U;
3406} 3406}
3407static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) 3407static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
3408{ 3408{
3409 return 0x00504648; 3409 return 0x00504648U;
3410} 3410}
3411static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r) 3411static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r)
3412{ 3412{
3413 return (r >> 0) & 0xffff; 3413 return (r >> 0U) & 0xffffU;
3414} 3414}
3415static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void) 3415static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void)
3416{ 3416{
3417 return 0x00000000; 3417 return 0x00000000U;
3418} 3418}
3419static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void) 3419static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void)
3420{ 3420{
3421 return 0x0; 3421 return 0x0U;
3422} 3422}
3423static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void) 3423static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void)
3424{ 3424{
3425 return 0x00504654; 3425 return 0x00504654U;
3426} 3426}
3427static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) 3427static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
3428{ 3428{
3429 return 0x00504770; 3429 return 0x00504770U;
3430} 3430}
3431static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) 3431static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
3432{ 3432{
3433 return 0x00419f70; 3433 return 0x00419f70U;
3434} 3434}
3435static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) 3435static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
3436{ 3436{
3437 return 0x1 << 4; 3437 return 0x1U << 4U;
3438} 3438}
3439static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) 3439static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
3440{ 3440{
3441 return (v & 0x1) << 4; 3441 return (v & 0x1U) << 4U;
3442} 3442}
3443static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) 3443static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
3444{ 3444{
3445 return 0x0050477c; 3445 return 0x0050477cU;
3446} 3446}
3447static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) 3447static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
3448{ 3448{
3449 return 0x00419f7c; 3449 return 0x00419f7cU;
3450} 3450}
3451static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) 3451static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
3452{ 3452{
3453 return 0x1 << 0; 3453 return 0x1U << 0U;
3454} 3454}
3455static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) 3455static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
3456{ 3456{
3457 return (v & 0x1) << 0; 3457 return (v & 0x1U) << 0U;
3458} 3458}
3459static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) 3459static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
3460{ 3460{
3461 return 0x0041be08; 3461 return 0x0041be08U;
3462} 3462}
3463static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) 3463static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
3464{ 3464{
3465 return 0x4; 3465 return 0x4U;
3466} 3466}
3467static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void) 3467static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void)
3468{ 3468{
3469 return 0x0041bf00; 3469 return 0x0041bf00U;
3470} 3470}
3471static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void) 3471static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void)
3472{ 3472{
3473 return 0x0041bf04; 3473 return 0x0041bf04U;
3474} 3474}
3475static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void) 3475static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void)
3476{ 3476{
3477 return 0x0041bf08; 3477 return 0x0041bf08U;
3478} 3478}
3479static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void) 3479static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void)
3480{ 3480{
3481 return 0x0041bf0c; 3481 return 0x0041bf0cU;
3482} 3482}
3483static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void) 3483static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void)
3484{ 3484{
3485 return 0x0041bf10; 3485 return 0x0041bf10U;
3486} 3486}
3487static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void) 3487static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void)
3488{ 3488{
3489 return 0x0041bf14; 3489 return 0x0041bf14U;
3490} 3490}
3491static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) 3491static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
3492{ 3492{
3493 return 0x0041bfd0; 3493 return 0x0041bfd0U;
3494} 3494}
3495static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) 3495static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v)
3496{ 3496{
3497 return (v & 0xff) << 0; 3497 return (v & 0xffU) << 0U;
3498} 3498}
3499static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) 3499static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v)
3500{ 3500{
3501 return (v & 0xff) << 8; 3501 return (v & 0xffU) << 8U;
3502} 3502}
3503static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) 3503static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v)
3504{ 3504{
3505 return (v & 0x1f) << 16; 3505 return (v & 0x1fU) << 16U;
3506} 3506}
3507static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) 3507static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
3508{ 3508{
3509 return (v & 0x7) << 21; 3509 return (v & 0x7U) << 21U;
3510} 3510}
3511static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v) 3511static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v)
3512{ 3512{
3513 return (v & 0x1f) << 24; 3513 return (v & 0x1fU) << 24U;
3514} 3514}
3515static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) 3515static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
3516{ 3516{
3517 return 0x0041bfd4; 3517 return 0x0041bfd4U;
3518} 3518}
3519static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) 3519static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
3520{ 3520{
3521 return (v & 0xffffff) << 0; 3521 return (v & 0xffffffU) << 0U;
3522} 3522}
3523static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void) 3523static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void)
3524{ 3524{
3525 return 0x0041bfe4; 3525 return 0x0041bfe4U;
3526} 3526}
3527static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v) 3527static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v)
3528{ 3528{
3529 return (v & 0x1f) << 0; 3529 return (v & 0x1fU) << 0U;
3530} 3530}
3531static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v) 3531static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v)
3532{ 3532{
3533 return (v & 0x1f) << 5; 3533 return (v & 0x1fU) << 5U;
3534} 3534}
3535static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v) 3535static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v)
3536{ 3536{
3537 return (v & 0x1f) << 10; 3537 return (v & 0x1fU) << 10U;
3538} 3538}
3539static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v) 3539static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v)
3540{ 3540{
3541 return (v & 0x1f) << 15; 3541 return (v & 0x1fU) << 15U;
3542} 3542}
3543static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v) 3543static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v)
3544{ 3544{
3545 return (v & 0x1f) << 20; 3545 return (v & 0x1fU) << 20U;
3546} 3546}
3547static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v) 3547static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v)
3548{ 3548{
3549 return (v & 0x1f) << 25; 3549 return (v & 0x1fU) << 25U;
3550} 3550}
3551static inline u32 gr_bes_zrop_settings_r(void) 3551static inline u32 gr_bes_zrop_settings_r(void)
3552{ 3552{
3553 return 0x00408850; 3553 return 0x00408850U;
3554} 3554}
3555static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) 3555static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v)
3556{ 3556{
3557 return (v & 0xf) << 0; 3557 return (v & 0xfU) << 0U;
3558} 3558}
3559static inline u32 gr_be0_crop_debug3_r(void) 3559static inline u32 gr_be0_crop_debug3_r(void)
3560{ 3560{
3561 return 0x00410108; 3561 return 0x00410108U;
3562} 3562}
3563static inline u32 gr_bes_crop_debug3_r(void) 3563static inline u32 gr_bes_crop_debug3_r(void)
3564{ 3564{
3565 return 0x00408908; 3565 return 0x00408908U;
3566} 3566}
3567static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) 3567static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void)
3568{ 3568{
3569 return 0x1 << 31; 3569 return 0x1U << 31U;
3570} 3570}
3571static inline u32 gr_bes_crop_settings_r(void) 3571static inline u32 gr_bes_crop_settings_r(void)
3572{ 3572{
3573 return 0x00408958; 3573 return 0x00408958U;
3574} 3574}
3575static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) 3575static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v)
3576{ 3576{
3577 return (v & 0xf) << 0; 3577 return (v & 0xfU) << 0U;
3578} 3578}
3579static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) 3579static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void)
3580{ 3580{
3581 return 0x00000020; 3581 return 0x00000020U;
3582} 3582}
3583static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) 3583static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void)
3584{ 3584{
3585 return 0x00000020; 3585 return 0x00000020U;
3586} 3586}
3587static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) 3587static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void)
3588{ 3588{
3589 return 0x000000c0; 3589 return 0x000000c0U;
3590} 3590}
3591static inline u32 gr_zcull_subregion_qty_v(void) 3591static inline u32 gr_zcull_subregion_qty_v(void)
3592{ 3592{
3593 return 0x00000010; 3593 return 0x00000010U;
3594} 3594}
3595static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) 3595static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void)
3596{ 3596{
3597 return 0x00504604; 3597 return 0x00504604U;
3598} 3598}
3599static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) 3599static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void)
3600{ 3600{
3601 return 0x00504608; 3601 return 0x00504608U;
3602} 3602}
3603static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) 3603static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void)
3604{ 3604{
3605 return 0x0050465c; 3605 return 0x0050465cU;
3606} 3606}
3607static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) 3607static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void)
3608{ 3608{
3609 return 0x00504660; 3609 return 0x00504660U;
3610} 3610}
3611static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) 3611static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void)
3612{ 3612{
3613 return 0x00504664; 3613 return 0x00504664U;
3614} 3614}
3615static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) 3615static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void)
3616{ 3616{
3617 return 0x00504668; 3617 return 0x00504668U;
3618} 3618}
3619static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) 3619static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void)
3620{ 3620{
3621 return 0x0050466c; 3621 return 0x0050466cU;
3622} 3622}
3623static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) 3623static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void)
3624{ 3624{
3625 return 0x00504658; 3625 return 0x00504658U;
3626} 3626}
3627static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) 3627static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void)
3628{ 3628{
3629 return 0x00504730; 3629 return 0x00504730U;
3630} 3630}
3631static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) 3631static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void)
3632{ 3632{
3633 return 0x00504734; 3633 return 0x00504734U;
3634} 3634}
3635static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) 3635static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void)
3636{ 3636{
3637 return 0x00504738; 3637 return 0x00504738U;
3638} 3638}
3639static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) 3639static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void)
3640{ 3640{
3641 return 0x0050473c; 3641 return 0x0050473cU;
3642} 3642}
3643static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) 3643static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void)
3644{ 3644{
3645 return 0x00504740; 3645 return 0x00504740U;
3646} 3646}
3647static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) 3647static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void)
3648{ 3648{
3649 return 0x00504744; 3649 return 0x00504744U;
3650} 3650}
3651static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) 3651static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void)
3652{ 3652{
3653 return 0x00504748; 3653 return 0x00504748U;
3654} 3654}
3655static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) 3655static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void)
3656{ 3656{
3657 return 0x0050474c; 3657 return 0x0050474cU;
3658} 3658}
3659static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void) 3659static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void)
3660{ 3660{
3661 return 0x00504678; 3661 return 0x00504678U;
3662} 3662}
3663static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void) 3663static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void)
3664{ 3664{
3665 return 0x00504694; 3665 return 0x00504694U;
3666} 3666}
3667static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void) 3667static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void)
3668{ 3668{
3669 return 0x005046f0; 3669 return 0x005046f0U;
3670} 3670}
3671static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void) 3671static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void)
3672{ 3672{
3673 return 0x00504700; 3673 return 0x00504700U;
3674} 3674}
3675static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void) 3675static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void)
3676{ 3676{
3677 return 0x005046f4; 3677 return 0x005046f4U;
3678} 3678}
3679static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void) 3679static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void)
3680{ 3680{
3681 return 0x00504704; 3681 return 0x00504704U;
3682} 3682}
3683static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void) 3683static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void)
3684{ 3684{
3685 return 0x005046f8; 3685 return 0x005046f8U;
3686} 3686}
3687static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void) 3687static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void)
3688{ 3688{
3689 return 0x00504708; 3689 return 0x00504708U;
3690} 3690}
3691static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void) 3691static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void)
3692{ 3692{
3693 return 0x005046fc; 3693 return 0x005046fcU;
3694} 3694}
3695static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void) 3695static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void)
3696{ 3696{
3697 return 0x0050470c; 3697 return 0x0050470cU;
3698} 3698}
3699static inline u32 gr_fe_pwr_mode_r(void) 3699static inline u32 gr_fe_pwr_mode_r(void)
3700{ 3700{
3701 return 0x00404170; 3701 return 0x00404170U;
3702} 3702}
3703static inline u32 gr_fe_pwr_mode_mode_auto_f(void) 3703static inline u32 gr_fe_pwr_mode_mode_auto_f(void)
3704{ 3704{
3705 return 0x0; 3705 return 0x0U;
3706} 3706}
3707static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) 3707static inline u32 gr_fe_pwr_mode_mode_force_on_f(void)
3708{ 3708{
3709 return 0x2; 3709 return 0x2U;
3710} 3710}
3711static inline u32 gr_fe_pwr_mode_req_v(u32 r) 3711static inline u32 gr_fe_pwr_mode_req_v(u32 r)
3712{ 3712{
3713 return (r >> 4) & 0x1; 3713 return (r >> 4U) & 0x1U;
3714} 3714}
3715static inline u32 gr_fe_pwr_mode_req_send_f(void) 3715static inline u32 gr_fe_pwr_mode_req_send_f(void)
3716{ 3716{
3717 return 0x10; 3717 return 0x10U;
3718} 3718}
3719static inline u32 gr_fe_pwr_mode_req_done_v(void) 3719static inline u32 gr_fe_pwr_mode_req_done_v(void)
3720{ 3720{
3721 return 0x00000000; 3721 return 0x00000000U;
3722} 3722}
3723static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) 3723static inline u32 gr_gpcs_pri_mmu_ctrl_r(void)
3724{ 3724{
3725 return 0x00418880; 3725 return 0x00418880U;
3726} 3726}
3727static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) 3727static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void)
3728{ 3728{
3729 return 0x1 << 0; 3729 return 0x1U << 0U;
3730} 3730}
3731static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) 3731static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void)
3732{ 3732{
3733 return 0x1 << 11; 3733 return 0x1U << 11U;
3734} 3734}
3735static inline u32 gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m(void) 3735static inline u32 gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m(void)
3736{ 3736{
3737 return 0x1 << 12; 3737 return 0x1U << 12U;
3738} 3738}
3739static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) 3739static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void)
3740{ 3740{
3741 return 0x1 << 1; 3741 return 0x1U << 1U;
3742} 3742}
3743static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) 3743static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void)
3744{ 3744{
3745 return 0x1 << 2; 3745 return 0x1U << 2U;
3746} 3746}
3747static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) 3747static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void)
3748{ 3748{
3749 return 0x3 << 3; 3749 return 0x3U << 3U;
3750} 3750}
3751static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) 3751static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void)
3752{ 3752{
3753 return 0x3 << 5; 3753 return 0x3U << 5U;
3754} 3754}
3755static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) 3755static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void)
3756{ 3756{
3757 return 0x3 << 28; 3757 return 0x3U << 28U;
3758} 3758}
3759static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) 3759static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void)
3760{ 3760{
3761 return 0x1 << 30; 3761 return 0x1U << 30U;
3762} 3762}
3763static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) 3763static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
3764{ 3764{
3765 return 0x1 << 31; 3765 return 0x1U << 31U;
3766} 3766}
3767static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) 3767static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
3768{ 3768{
3769 return 0x00418890; 3769 return 0x00418890U;
3770} 3770}
3771static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) 3771static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void)
3772{ 3772{
3773 return 0x00418894; 3773 return 0x00418894U;
3774} 3774}
3775static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) 3775static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
3776{ 3776{
3777 return 0x004188b0; 3777 return 0x004188b0U;
3778} 3778}
3779static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_m(void) 3779static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_m(void)
3780{ 3780{
3781 return 0x1 << 16; 3781 return 0x1U << 16U;
3782} 3782}
3783static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) 3783static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r)
3784{ 3784{
3785 return (r >> 16) & 0x1; 3785 return (r >> 16U) & 0x1U;
3786} 3786}
3787static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) 3787static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void)
3788{ 3788{
3789 return 0x00000001; 3789 return 0x00000001U;
3790} 3790}
3791static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(void) 3791static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(void)
3792{ 3792{
3793 return 0x10000; 3793 return 0x10000U;
3794} 3794}
3795static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_v(void) 3795static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_v(void)
3796{ 3796{
3797 return 0x00000000; 3797 return 0x00000000U;
3798} 3798}
3799static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(void) 3799static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(void)
3800{ 3800{
3801 return 0x0; 3801 return 0x0U;
3802} 3802}
3803static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) 3803static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void)
3804{ 3804{
3805 return 0x004188b4; 3805 return 0x004188b4U;
3806} 3806}
3807static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) 3807static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void)
3808{ 3808{
3809 return 0x004188b8; 3809 return 0x004188b8U;
3810} 3810}
3811static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) 3811static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
3812{ 3812{
3813 return 0x004188ac; 3813 return 0x004188acU;
3814} 3814}
3815static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) 3815static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void)
3816{ 3816{
3817 return 0x00419e10; 3817 return 0x00419e10U;
3818} 3818}
3819static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) 3819static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v)
3820{ 3820{
3821 return (v & 0x1) << 0; 3821 return (v & 0x1U) << 0U;
3822} 3822}
3823static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) 3823static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void)
3824{ 3824{
3825 return 0x00000001; 3825 return 0x00000001U;
3826} 3826}
3827static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) 3827static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void)
3828{ 3828{
3829 return 0x1 << 31; 3829 return 0x1U << 31U;
3830} 3830}
3831static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) 3831static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r)
3832{ 3832{
3833 return (r >> 31) & 0x1; 3833 return (r >> 31U) & 0x1U;
3834} 3834}
3835static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) 3835static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void)
3836{ 3836{
3837 return 0x80000000; 3837 return 0x80000000U;
3838} 3838}
3839static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) 3839static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
3840{ 3840{
3841 return 0x0; 3841 return 0x0U;
3842} 3842}
3843static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void) 3843static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void)
3844{ 3844{
3845 return 0x1 << 3; 3845 return 0x1U << 3U;
3846} 3846}
3847static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void) 3847static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void)
3848{ 3848{
3849 return 0x8; 3849 return 0x8U;
3850} 3850}
3851static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void) 3851static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void)
3852{ 3852{
3853 return 0x0; 3853 return 0x0U;
3854} 3854}
3855static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) 3855static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
3856{ 3856{
3857 return 0x1 << 30; 3857 return 0x1U << 30U;
3858} 3858}
3859static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) 3859static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r)
3860{ 3860{
3861 return (r >> 30) & 0x1; 3861 return (r >> 30U) & 0x1U;
3862} 3862}
3863static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) 3863static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void)
3864{ 3864{
3865 return 0x40000000; 3865 return 0x40000000U;
3866} 3866}
3867#endif 3867#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h
index d920083e..2c3ebb45 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ltc_gm20b.h
@@ -58,470 +58,470 @@
58 58
59static inline u32 ltc_pltcg_base_v(void) 59static inline u32 ltc_pltcg_base_v(void)
60{ 60{
61 return 0x00140000; 61 return 0x00140000U;
62} 62}
63static inline u32 ltc_pltcg_extent_v(void) 63static inline u32 ltc_pltcg_extent_v(void)
64{ 64{
65 return 0x0017ffff; 65 return 0x0017ffffU;
66} 66}
67static inline u32 ltc_ltc0_ltss_v(void) 67static inline u32 ltc_ltc0_ltss_v(void)
68{ 68{
69 return 0x00140200; 69 return 0x00140200U;
70} 70}
71static inline u32 ltc_ltc0_lts0_v(void) 71static inline u32 ltc_ltc0_lts0_v(void)
72{ 72{
73 return 0x00140400; 73 return 0x00140400U;
74} 74}
75static inline u32 ltc_ltcs_ltss_v(void) 75static inline u32 ltc_ltcs_ltss_v(void)
76{ 76{
77 return 0x0017e200; 77 return 0x0017e200U;
78} 78}
79static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) 79static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
80{ 80{
81 return 0x0014046c; 81 return 0x0014046cU;
82} 82}
83static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) 83static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
84{ 84{
85 return 0x00140518; 85 return 0x00140518U;
86} 86}
87static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) 87static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
88{ 88{
89 return 0x0017e318; 89 return 0x0017e318U;
90} 90}
91static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) 91static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
92{ 92{
93 return 0x1 << 15; 93 return 0x1U << 15U;
94} 94}
95static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) 95static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
96{ 96{
97 return 0x00140494; 97 return 0x00140494U;
98} 98}
99static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) 99static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
100{ 100{
101 return (r >> 0) & 0xffff; 101 return (r >> 0U) & 0xffffU;
102} 102}
103static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) 103static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
104{ 104{
105 return (r >> 16) & 0x3; 105 return (r >> 16U) & 0x3U;
106} 106}
107static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) 107static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
108{ 108{
109 return 0x00000000; 109 return 0x00000000U;
110} 110}
111static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) 111static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
112{ 112{
113 return 0x00000001; 113 return 0x00000001U;
114} 114}
115static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) 115static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
116{ 116{
117 return 0x00000002; 117 return 0x00000002U;
118} 118}
119static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) 119static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
120{ 120{
121 return 0x0017e26c; 121 return 0x0017e26cU;
122} 122}
123static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) 123static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
124{ 124{
125 return 0x1; 125 return 0x1U;
126} 126}
127static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) 127static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
128{ 128{
129 return 0x2; 129 return 0x2U;
130} 130}
131static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) 131static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
132{ 132{
133 return (r >> 2) & 0x1; 133 return (r >> 2U) & 0x1U;
134} 134}
135static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) 135static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
136{ 136{
137 return 0x00000001; 137 return 0x00000001U;
138} 138}
139static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) 139static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
140{ 140{
141 return 0x4; 141 return 0x4U;
142} 142}
143static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) 143static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
144{ 144{
145 return 0x0014046c; 145 return 0x0014046cU;
146} 146}
147static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) 147static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
148{ 148{
149 return 0x0017e270; 149 return 0x0017e270U;
150} 150}
151static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) 151static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
152{ 152{
153 return (v & 0x1ffff) << 0; 153 return (v & 0x1ffffU) << 0U;
154} 154}
155static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) 155static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
156{ 156{
157 return 0x0017e274; 157 return 0x0017e274U;
158} 158}
159static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) 159static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
160{ 160{
161 return (v & 0x1ffff) << 0; 161 return (v & 0x1ffffU) << 0U;
162} 162}
163static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) 163static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
164{ 164{
165 return 0x0001ffff; 165 return 0x0001ffffU;
166} 166}
167static inline u32 ltc_ltcs_ltss_cbc_base_r(void) 167static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
168{ 168{
169 return 0x0017e278; 169 return 0x0017e278U;
170} 170}
171static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) 171static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
172{ 172{
173 return 0x0000000b; 173 return 0x0000000bU;
174} 174}
175static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) 175static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
176{ 176{
177 return (r >> 0) & 0x3ffffff; 177 return (r >> 0U) & 0x3ffffffU;
178} 178}
179static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) 179static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
180{ 180{
181 return 0x0017e27c; 181 return 0x0017e27cU;
182} 182}
183static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) 183static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
184{ 184{
185 return 0x0017e000; 185 return 0x0017e000U;
186} 186}
187static inline u32 ltc_ltcs_ltss_cbc_param_r(void) 187static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
188{ 188{
189 return 0x0017e280; 189 return 0x0017e280U;
190} 190}
191static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) 191static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
192{ 192{
193 return (r >> 0) & 0xffff; 193 return (r >> 0U) & 0xffffU;
194} 194}
195static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) 195static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
196{ 196{
197 return (r >> 24) & 0xf; 197 return (r >> 24U) & 0xfU;
198} 198}
199static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) 199static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
200{ 200{
201 return (r >> 28) & 0xf; 201 return (r >> 28U) & 0xfU;
202} 202}
203static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) 203static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
204{ 204{
205 return 0x0017e2ac; 205 return 0x0017e2acU;
206} 206}
207static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) 207static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
208{ 208{
209 return (v & 0x1f) << 16; 209 return (v & 0x1fU) << 16U;
210} 210}
211static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) 211static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
212{ 212{
213 return 0x0017e338; 213 return 0x0017e338U;
214} 214}
215static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) 215static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
216{ 216{
217 return (v & 0xf) << 0; 217 return (v & 0xfU) << 0U;
218} 218}
219static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) 219static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
220{ 220{
221 return 0x0017e33c + i*4; 221 return 0x0017e33cU + i*4U;
222} 222}
223static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) 223static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
224{ 224{
225 return 0x00000004; 225 return 0x00000004U;
226} 226}
227static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) 227static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
228{ 228{
229 return 0x0017e34c; 229 return 0x0017e34cU;
230} 230}
231static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) 231static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
232{ 232{
233 return 32; 233 return 32U;
234} 234}
235static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) 235static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
236{ 236{
237 return (v & 0xffffffff) << 0; 237 return (v & 0xffffffffU) << 0U;
238} 238}
239static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) 239static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
240{ 240{
241 return 0xffffffff << 0; 241 return 0xffffffffU << 0U;
242} 242}
243static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) 243static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
244{ 244{
245 return (r >> 0) & 0xffffffff; 245 return (r >> 0U) & 0xffffffffU;
246} 246}
247static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) 247static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
248{ 248{
249 return 0x0017e2b0; 249 return 0x0017e2b0U;
250} 250}
251static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) 251static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
252{ 252{
253 return 0x10000000; 253 return 0x10000000U;
254} 254}
255static inline u32 ltc_ltcs_ltss_g_elpg_r(void) 255static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
256{ 256{
257 return 0x0017e214; 257 return 0x0017e214U;
258} 258}
259static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) 259static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
260{ 260{
261 return (r >> 0) & 0x1; 261 return (r >> 0U) & 0x1U;
262} 262}
263static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) 263static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
264{ 264{
265 return 0x00000001; 265 return 0x00000001U;
266} 266}
267static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) 267static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
268{ 268{
269 return 0x1; 269 return 0x1U;
270} 270}
271static inline u32 ltc_ltc0_ltss_g_elpg_r(void) 271static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
272{ 272{
273 return 0x00140214; 273 return 0x00140214U;
274} 274}
275static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) 275static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
276{ 276{
277 return (r >> 0) & 0x1; 277 return (r >> 0U) & 0x1U;
278} 278}
279static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) 279static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
280{ 280{
281 return 0x00000001; 281 return 0x00000001U;
282} 282}
283static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) 283static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
284{ 284{
285 return 0x1; 285 return 0x1U;
286} 286}
287static inline u32 ltc_ltc1_ltss_g_elpg_r(void) 287static inline u32 ltc_ltc1_ltss_g_elpg_r(void)
288{ 288{
289 return 0x00142214; 289 return 0x00142214U;
290} 290}
291static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) 291static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r)
292{ 292{
293 return (r >> 0) & 0x1; 293 return (r >> 0U) & 0x1U;
294} 294}
295static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) 295static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void)
296{ 296{
297 return 0x00000001; 297 return 0x00000001U;
298} 298}
299static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) 299static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void)
300{ 300{
301 return 0x1; 301 return 0x1U;
302} 302}
303static inline u32 ltc_ltcs_ltss_intr_r(void) 303static inline u32 ltc_ltcs_ltss_intr_r(void)
304{ 304{
305 return 0x0017e20c; 305 return 0x0017e20cU;
306} 306}
307static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) 307static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
308{ 308{
309 return 0x1 << 20; 309 return 0x1U << 20U;
310} 310}
311static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) 311static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
312{ 312{
313 return 0x1 << 30; 313 return 0x1U << 30U;
314} 314}
315static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void) 315static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void)
316{ 316{
317 return 0x1 << 21; 317 return 0x1U << 21U;
318} 318}
319static inline u32 ltc_ltc0_lts0_intr_r(void) 319static inline u32 ltc_ltc0_lts0_intr_r(void)
320{ 320{
321 return 0x0014040c; 321 return 0x0014040cU;
322} 322}
323static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) 323static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
324{ 324{
325 return 0x0017e2a0; 325 return 0x0017e2a0U;
326} 326}
327static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) 327static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
328{ 328{
329 return (r >> 0) & 0x1; 329 return (r >> 0U) & 0x1U;
330} 330}
331static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) 331static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
332{ 332{
333 return 0x00000001; 333 return 0x00000001U;
334} 334}
335static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) 335static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
336{ 336{
337 return 0x1; 337 return 0x1U;
338} 338}
339static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) 339static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
340{ 340{
341 return (r >> 8) & 0xf; 341 return (r >> 8U) & 0xfU;
342} 342}
343static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) 343static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
344{ 344{
345 return 0x00000003; 345 return 0x00000003U;
346} 346}
347static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) 347static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
348{ 348{
349 return 0x300; 349 return 0x300U;
350} 350}
351static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) 351static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
352{ 352{
353 return (r >> 28) & 0x1; 353 return (r >> 28U) & 0x1U;
354} 354}
355static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) 355static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
356{ 356{
357 return 0x00000001; 357 return 0x00000001U;
358} 358}
359static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) 359static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
360{ 360{
361 return 0x10000000; 361 return 0x10000000U;
362} 362}
363static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) 363static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
364{ 364{
365 return (r >> 29) & 0x1; 365 return (r >> 29U) & 0x1U;
366} 366}
367static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) 367static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
368{ 368{
369 return 0x00000001; 369 return 0x00000001U;
370} 370}
371static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) 371static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
372{ 372{
373 return 0x20000000; 373 return 0x20000000U;
374} 374}
375static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) 375static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
376{ 376{
377 return (r >> 30) & 0x1; 377 return (r >> 30U) & 0x1U;
378} 378}
379static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) 379static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
380{ 380{
381 return 0x00000001; 381 return 0x00000001U;
382} 382}
383static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) 383static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
384{ 384{
385 return 0x40000000; 385 return 0x40000000U;
386} 386}
387static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) 387static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
388{ 388{
389 return 0x0017e2a4; 389 return 0x0017e2a4U;
390} 390}
391static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) 391static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
392{ 392{
393 return (r >> 0) & 0x1; 393 return (r >> 0U) & 0x1U;
394} 394}
395static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) 395static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
396{ 396{
397 return 0x00000001; 397 return 0x00000001U;
398} 398}
399static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) 399static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
400{ 400{
401 return 0x1; 401 return 0x1U;
402} 402}
403static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) 403static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
404{ 404{
405 return (r >> 8) & 0xf; 405 return (r >> 8U) & 0xfU;
406} 406}
407static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) 407static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
408{ 408{
409 return 0x00000003; 409 return 0x00000003U;
410} 410}
411static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) 411static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
412{ 412{
413 return 0x300; 413 return 0x300U;
414} 414}
415static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) 415static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
416{ 416{
417 return (r >> 16) & 0x1; 417 return (r >> 16U) & 0x1U;
418} 418}
419static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) 419static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
420{ 420{
421 return 0x00000001; 421 return 0x00000001U;
422} 422}
423static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) 423static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
424{ 424{
425 return 0x10000; 425 return 0x10000U;
426} 426}
427static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) 427static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
428{ 428{
429 return (r >> 28) & 0x1; 429 return (r >> 28U) & 0x1U;
430} 430}
431static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) 431static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
432{ 432{
433 return 0x00000001; 433 return 0x00000001U;
434} 434}
435static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) 435static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
436{ 436{
437 return 0x10000000; 437 return 0x10000000U;
438} 438}
439static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) 439static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
440{ 440{
441 return (r >> 29) & 0x1; 441 return (r >> 29U) & 0x1U;
442} 442}
443static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) 443static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
444{ 444{
445 return 0x00000001; 445 return 0x00000001U;
446} 446}
447static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) 447static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
448{ 448{
449 return 0x20000000; 449 return 0x20000000U;
450} 450}
451static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) 451static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
452{ 452{
453 return (r >> 30) & 0x1; 453 return (r >> 30U) & 0x1U;
454} 454}
455static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) 455static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
456{ 456{
457 return 0x00000001; 457 return 0x00000001U;
458} 458}
459static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) 459static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
460{ 460{
461 return 0x40000000; 461 return 0x40000000U;
462} 462}
463static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) 463static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
464{ 464{
465 return 0x001402a0; 465 return 0x001402a0U;
466} 466}
467static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) 467static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
468{ 468{
469 return (r >> 0) & 0x1; 469 return (r >> 0U) & 0x1U;
470} 470}
471static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) 471static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
472{ 472{
473 return 0x00000001; 473 return 0x00000001U;
474} 474}
475static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) 475static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
476{ 476{
477 return 0x1; 477 return 0x1U;
478} 478}
479static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) 479static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
480{ 480{
481 return 0x001402a4; 481 return 0x001402a4U;
482} 482}
483static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) 483static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
484{ 484{
485 return (r >> 0) & 0x1; 485 return (r >> 0U) & 0x1U;
486} 486}
487static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) 487static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
488{ 488{
489 return 0x00000001; 489 return 0x00000001U;
490} 490}
491static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) 491static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
492{ 492{
493 return 0x1; 493 return 0x1U;
494} 494}
495static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) 495static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void)
496{ 496{
497 return 0x001422a0; 497 return 0x001422a0U;
498} 498}
499static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) 499static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r)
500{ 500{
501 return (r >> 0) & 0x1; 501 return (r >> 0U) & 0x1U;
502} 502}
503static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) 503static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void)
504{ 504{
505 return 0x00000001; 505 return 0x00000001U;
506} 506}
507static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) 507static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void)
508{ 508{
509 return 0x1; 509 return 0x1U;
510} 510}
511static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) 511static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void)
512{ 512{
513 return 0x001422a4; 513 return 0x001422a4U;
514} 514}
515static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) 515static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r)
516{ 516{
517 return (r >> 0) & 0x1; 517 return (r >> 0U) & 0x1U;
518} 518}
519static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) 519static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void)
520{ 520{
521 return 0x00000001; 521 return 0x00000001U;
522} 522}
523static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) 523static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void)
524{ 524{
525 return 0x1; 525 return 0x1U;
526} 526}
527#endif 527#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_mc_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_mc_gm20b.h
index 5f0ad2cb..0264803f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_mc_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_mc_gm20b.h
@@ -58,230 +58,230 @@
58 58
59static inline u32 mc_boot_0_r(void) 59static inline u32 mc_boot_0_r(void)
60{ 60{
61 return 0x00000000; 61 return 0x00000000U;
62} 62}
63static inline u32 mc_boot_0_architecture_v(u32 r) 63static inline u32 mc_boot_0_architecture_v(u32 r)
64{ 64{
65 return (r >> 24) & 0x1f; 65 return (r >> 24U) & 0x1fU;
66} 66}
67static inline u32 mc_boot_0_implementation_v(u32 r) 67static inline u32 mc_boot_0_implementation_v(u32 r)
68{ 68{
69 return (r >> 20) & 0xf; 69 return (r >> 20U) & 0xfU;
70} 70}
71static inline u32 mc_boot_0_major_revision_v(u32 r) 71static inline u32 mc_boot_0_major_revision_v(u32 r)
72{ 72{
73 return (r >> 4) & 0xf; 73 return (r >> 4U) & 0xfU;
74} 74}
75static inline u32 mc_boot_0_minor_revision_v(u32 r) 75static inline u32 mc_boot_0_minor_revision_v(u32 r)
76{ 76{
77 return (r >> 0) & 0xf; 77 return (r >> 0U) & 0xfU;
78} 78}
79static inline u32 mc_intr_r(u32 i) 79static inline u32 mc_intr_r(u32 i)
80{ 80{
81 return 0x00000100 + i*4; 81 return 0x00000100U + i*4U;
82} 82}
83static inline u32 mc_intr_pfifo_pending_f(void) 83static inline u32 mc_intr_pfifo_pending_f(void)
84{ 84{
85 return 0x100; 85 return 0x100U;
86} 86}
87static inline u32 mc_intr_pmu_pending_f(void) 87static inline u32 mc_intr_pmu_pending_f(void)
88{ 88{
89 return 0x1000000; 89 return 0x1000000U;
90} 90}
91static inline u32 mc_intr_ltc_pending_f(void) 91static inline u32 mc_intr_ltc_pending_f(void)
92{ 92{
93 return 0x2000000; 93 return 0x2000000U;
94} 94}
95static inline u32 mc_intr_priv_ring_pending_f(void) 95static inline u32 mc_intr_priv_ring_pending_f(void)
96{ 96{
97 return 0x40000000; 97 return 0x40000000U;
98} 98}
99static inline u32 mc_intr_pbus_pending_f(void) 99static inline u32 mc_intr_pbus_pending_f(void)
100{ 100{
101 return 0x10000000; 101 return 0x10000000U;
102} 102}
103static inline u32 mc_intr_mask_0_r(void) 103static inline u32 mc_intr_mask_0_r(void)
104{ 104{
105 return 0x00000640; 105 return 0x00000640U;
106} 106}
107static inline u32 mc_intr_mask_0_pmu_enabled_f(void) 107static inline u32 mc_intr_mask_0_pmu_enabled_f(void)
108{ 108{
109 return 0x1000000; 109 return 0x1000000U;
110} 110}
111static inline u32 mc_intr_en_0_r(void) 111static inline u32 mc_intr_en_0_r(void)
112{ 112{
113 return 0x00000140; 113 return 0x00000140U;
114} 114}
115static inline u32 mc_intr_en_0_inta_disabled_f(void) 115static inline u32 mc_intr_en_0_inta_disabled_f(void)
116{ 116{
117 return 0x0; 117 return 0x0U;
118} 118}
119static inline u32 mc_intr_en_0_inta_hardware_f(void) 119static inline u32 mc_intr_en_0_inta_hardware_f(void)
120{ 120{
121 return 0x1; 121 return 0x1U;
122} 122}
123static inline u32 mc_intr_mask_1_r(void) 123static inline u32 mc_intr_mask_1_r(void)
124{ 124{
125 return 0x00000644; 125 return 0x00000644U;
126} 126}
127static inline u32 mc_intr_mask_1_pmu_s(void) 127static inline u32 mc_intr_mask_1_pmu_s(void)
128{ 128{
129 return 1; 129 return 1U;
130} 130}
131static inline u32 mc_intr_mask_1_pmu_f(u32 v) 131static inline u32 mc_intr_mask_1_pmu_f(u32 v)
132{ 132{
133 return (v & 0x1) << 24; 133 return (v & 0x1U) << 24U;
134} 134}
135static inline u32 mc_intr_mask_1_pmu_m(void) 135static inline u32 mc_intr_mask_1_pmu_m(void)
136{ 136{
137 return 0x1 << 24; 137 return 0x1U << 24U;
138} 138}
139static inline u32 mc_intr_mask_1_pmu_v(u32 r) 139static inline u32 mc_intr_mask_1_pmu_v(u32 r)
140{ 140{
141 return (r >> 24) & 0x1; 141 return (r >> 24U) & 0x1U;
142} 142}
143static inline u32 mc_intr_mask_1_pmu_enabled_f(void) 143static inline u32 mc_intr_mask_1_pmu_enabled_f(void)
144{ 144{
145 return 0x1000000; 145 return 0x1000000U;
146} 146}
147static inline u32 mc_intr_en_1_r(void) 147static inline u32 mc_intr_en_1_r(void)
148{ 148{
149 return 0x00000144; 149 return 0x00000144U;
150} 150}
151static inline u32 mc_intr_en_1_inta_disabled_f(void) 151static inline u32 mc_intr_en_1_inta_disabled_f(void)
152{ 152{
153 return 0x0; 153 return 0x0U;
154} 154}
155static inline u32 mc_intr_en_1_inta_hardware_f(void) 155static inline u32 mc_intr_en_1_inta_hardware_f(void)
156{ 156{
157 return 0x1; 157 return 0x1U;
158} 158}
159static inline u32 mc_enable_r(void) 159static inline u32 mc_enable_r(void)
160{ 160{
161 return 0x00000200; 161 return 0x00000200U;
162} 162}
163static inline u32 mc_enable_xbar_enabled_f(void) 163static inline u32 mc_enable_xbar_enabled_f(void)
164{ 164{
165 return 0x4; 165 return 0x4U;
166} 166}
167static inline u32 mc_enable_l2_enabled_f(void) 167static inline u32 mc_enable_l2_enabled_f(void)
168{ 168{
169 return 0x8; 169 return 0x8U;
170} 170}
171static inline u32 mc_enable_pmedia_s(void) 171static inline u32 mc_enable_pmedia_s(void)
172{ 172{
173 return 1; 173 return 1U;
174} 174}
175static inline u32 mc_enable_pmedia_f(u32 v) 175static inline u32 mc_enable_pmedia_f(u32 v)
176{ 176{
177 return (v & 0x1) << 4; 177 return (v & 0x1U) << 4U;
178} 178}
179static inline u32 mc_enable_pmedia_m(void) 179static inline u32 mc_enable_pmedia_m(void)
180{ 180{
181 return 0x1 << 4; 181 return 0x1U << 4U;
182} 182}
183static inline u32 mc_enable_pmedia_v(u32 r) 183static inline u32 mc_enable_pmedia_v(u32 r)
184{ 184{
185 return (r >> 4) & 0x1; 185 return (r >> 4U) & 0x1U;
186} 186}
187static inline u32 mc_enable_priv_ring_enabled_f(void) 187static inline u32 mc_enable_priv_ring_enabled_f(void)
188{ 188{
189 return 0x20; 189 return 0x20U;
190} 190}
191static inline u32 mc_enable_ce0_m(void) 191static inline u32 mc_enable_ce0_m(void)
192{ 192{
193 return 0x1 << 6; 193 return 0x1U << 6U;
194} 194}
195static inline u32 mc_enable_pfifo_enabled_f(void) 195static inline u32 mc_enable_pfifo_enabled_f(void)
196{ 196{
197 return 0x100; 197 return 0x100U;
198} 198}
199static inline u32 mc_enable_pgraph_enabled_f(void) 199static inline u32 mc_enable_pgraph_enabled_f(void)
200{ 200{
201 return 0x1000; 201 return 0x1000U;
202} 202}
203static inline u32 mc_enable_pwr_v(u32 r) 203static inline u32 mc_enable_pwr_v(u32 r)
204{ 204{
205 return (r >> 13) & 0x1; 205 return (r >> 13U) & 0x1U;
206} 206}
207static inline u32 mc_enable_pwr_disabled_v(void) 207static inline u32 mc_enable_pwr_disabled_v(void)
208{ 208{
209 return 0x00000000; 209 return 0x00000000U;
210} 210}
211static inline u32 mc_enable_pwr_enabled_f(void) 211static inline u32 mc_enable_pwr_enabled_f(void)
212{ 212{
213 return 0x2000; 213 return 0x2000U;
214} 214}
215static inline u32 mc_enable_pfb_enabled_f(void) 215static inline u32 mc_enable_pfb_enabled_f(void)
216{ 216{
217 return 0x100000; 217 return 0x100000U;
218} 218}
219static inline u32 mc_enable_ce2_m(void) 219static inline u32 mc_enable_ce2_m(void)
220{ 220{
221 return 0x1 << 21; 221 return 0x1U << 21U;
222} 222}
223static inline u32 mc_enable_ce2_enabled_f(void) 223static inline u32 mc_enable_ce2_enabled_f(void)
224{ 224{
225 return 0x200000; 225 return 0x200000U;
226} 226}
227static inline u32 mc_enable_blg_enabled_f(void) 227static inline u32 mc_enable_blg_enabled_f(void)
228{ 228{
229 return 0x8000000; 229 return 0x8000000U;
230} 230}
231static inline u32 mc_enable_perfmon_enabled_f(void) 231static inline u32 mc_enable_perfmon_enabled_f(void)
232{ 232{
233 return 0x10000000; 233 return 0x10000000U;
234} 234}
235static inline u32 mc_enable_hub_enabled_f(void) 235static inline u32 mc_enable_hub_enabled_f(void)
236{ 236{
237 return 0x20000000; 237 return 0x20000000U;
238} 238}
239static inline u32 mc_intr_ltc_r(void) 239static inline u32 mc_intr_ltc_r(void)
240{ 240{
241 return 0x0000017c; 241 return 0x0000017cU;
242} 242}
243static inline u32 mc_enable_pb_r(void) 243static inline u32 mc_enable_pb_r(void)
244{ 244{
245 return 0x00000204; 245 return 0x00000204U;
246} 246}
247static inline u32 mc_enable_pb_0_s(void) 247static inline u32 mc_enable_pb_0_s(void)
248{ 248{
249 return 1; 249 return 1U;
250} 250}
251static inline u32 mc_enable_pb_0_f(u32 v) 251static inline u32 mc_enable_pb_0_f(u32 v)
252{ 252{
253 return (v & 0x1) << 0; 253 return (v & 0x1U) << 0U;
254} 254}
255static inline u32 mc_enable_pb_0_m(void) 255static inline u32 mc_enable_pb_0_m(void)
256{ 256{
257 return 0x1 << 0; 257 return 0x1U << 0U;
258} 258}
259static inline u32 mc_enable_pb_0_v(u32 r) 259static inline u32 mc_enable_pb_0_v(u32 r)
260{ 260{
261 return (r >> 0) & 0x1; 261 return (r >> 0U) & 0x1U;
262} 262}
263static inline u32 mc_enable_pb_0_enabled_v(void) 263static inline u32 mc_enable_pb_0_enabled_v(void)
264{ 264{
265 return 0x00000001; 265 return 0x00000001U;
266} 266}
267static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) 267static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
268{ 268{
269 return (v & 0x1) << (0 + i*1); 269 return (v & 0x1U) << (0U + i*1U);
270} 270}
271static inline u32 mc_elpg_enable_r(void) 271static inline u32 mc_elpg_enable_r(void)
272{ 272{
273 return 0x0000020c; 273 return 0x0000020cU;
274} 274}
275static inline u32 mc_elpg_enable_xbar_enabled_f(void) 275static inline u32 mc_elpg_enable_xbar_enabled_f(void)
276{ 276{
277 return 0x4; 277 return 0x4U;
278} 278}
279static inline u32 mc_elpg_enable_pfb_enabled_f(void) 279static inline u32 mc_elpg_enable_pfb_enabled_f(void)
280{ 280{
281 return 0x100000; 281 return 0x100000U;
282} 282}
283static inline u32 mc_elpg_enable_hub_enabled_f(void) 283static inline u32 mc_elpg_enable_hub_enabled_f(void)
284{ 284{
285 return 0x20000000; 285 return 0x20000000U;
286} 286}
287#endif 287#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h
index cda6f1a0..46edf7aa 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pbdma_gm20b.h
@@ -58,506 +58,506 @@
58 58
59static inline u32 pbdma_gp_entry1_r(void) 59static inline u32 pbdma_gp_entry1_r(void)
60{ 60{
61 return 0x10000004; 61 return 0x10000004U;
62} 62}
63static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) 63static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
64{ 64{
65 return (r >> 0) & 0xff; 65 return (r >> 0U) & 0xffU;
66} 66}
67static inline u32 pbdma_gp_entry1_length_f(u32 v) 67static inline u32 pbdma_gp_entry1_length_f(u32 v)
68{ 68{
69 return (v & 0x1fffff) << 10; 69 return (v & 0x1fffffU) << 10U;
70} 70}
71static inline u32 pbdma_gp_entry1_length_v(u32 r) 71static inline u32 pbdma_gp_entry1_length_v(u32 r)
72{ 72{
73 return (r >> 10) & 0x1fffff; 73 return (r >> 10U) & 0x1fffffU;
74} 74}
75static inline u32 pbdma_gp_base_r(u32 i) 75static inline u32 pbdma_gp_base_r(u32 i)
76{ 76{
77 return 0x00040048 + i*8192; 77 return 0x00040048U + i*8192U;
78} 78}
79static inline u32 pbdma_gp_base__size_1_v(void) 79static inline u32 pbdma_gp_base__size_1_v(void)
80{ 80{
81 return 0x00000001; 81 return 0x00000001U;
82} 82}
83static inline u32 pbdma_gp_base_offset_f(u32 v) 83static inline u32 pbdma_gp_base_offset_f(u32 v)
84{ 84{
85 return (v & 0x1fffffff) << 3; 85 return (v & 0x1fffffffU) << 3U;
86} 86}
87static inline u32 pbdma_gp_base_rsvd_s(void) 87static inline u32 pbdma_gp_base_rsvd_s(void)
88{ 88{
89 return 3; 89 return 3U;
90} 90}
91static inline u32 pbdma_gp_base_hi_r(u32 i) 91static inline u32 pbdma_gp_base_hi_r(u32 i)
92{ 92{
93 return 0x0004004c + i*8192; 93 return 0x0004004cU + i*8192U;
94} 94}
95static inline u32 pbdma_gp_base_hi_offset_f(u32 v) 95static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
96{ 96{
97 return (v & 0xff) << 0; 97 return (v & 0xffU) << 0U;
98} 98}
99static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) 99static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
100{ 100{
101 return (v & 0x1f) << 16; 101 return (v & 0x1fU) << 16U;
102} 102}
103static inline u32 pbdma_gp_fetch_r(u32 i) 103static inline u32 pbdma_gp_fetch_r(u32 i)
104{ 104{
105 return 0x00040050 + i*8192; 105 return 0x00040050U + i*8192U;
106} 106}
107static inline u32 pbdma_gp_get_r(u32 i) 107static inline u32 pbdma_gp_get_r(u32 i)
108{ 108{
109 return 0x00040014 + i*8192; 109 return 0x00040014U + i*8192U;
110} 110}
111static inline u32 pbdma_gp_put_r(u32 i) 111static inline u32 pbdma_gp_put_r(u32 i)
112{ 112{
113 return 0x00040000 + i*8192; 113 return 0x00040000U + i*8192U;
114} 114}
115static inline u32 pbdma_pb_fetch_r(u32 i) 115static inline u32 pbdma_pb_fetch_r(u32 i)
116{ 116{
117 return 0x00040054 + i*8192; 117 return 0x00040054U + i*8192U;
118} 118}
119static inline u32 pbdma_pb_fetch_hi_r(u32 i) 119static inline u32 pbdma_pb_fetch_hi_r(u32 i)
120{ 120{
121 return 0x00040058 + i*8192; 121 return 0x00040058U + i*8192U;
122} 122}
123static inline u32 pbdma_get_r(u32 i) 123static inline u32 pbdma_get_r(u32 i)
124{ 124{
125 return 0x00040018 + i*8192; 125 return 0x00040018U + i*8192U;
126} 126}
127static inline u32 pbdma_get_hi_r(u32 i) 127static inline u32 pbdma_get_hi_r(u32 i)
128{ 128{
129 return 0x0004001c + i*8192; 129 return 0x0004001cU + i*8192U;
130} 130}
131static inline u32 pbdma_put_r(u32 i) 131static inline u32 pbdma_put_r(u32 i)
132{ 132{
133 return 0x0004005c + i*8192; 133 return 0x0004005cU + i*8192U;
134} 134}
135static inline u32 pbdma_put_hi_r(u32 i) 135static inline u32 pbdma_put_hi_r(u32 i)
136{ 136{
137 return 0x00040060 + i*8192; 137 return 0x00040060U + i*8192U;
138} 138}
139static inline u32 pbdma_formats_r(u32 i) 139static inline u32 pbdma_formats_r(u32 i)
140{ 140{
141 return 0x0004009c + i*8192; 141 return 0x0004009cU + i*8192U;
142} 142}
143static inline u32 pbdma_formats_gp_fermi0_f(void) 143static inline u32 pbdma_formats_gp_fermi0_f(void)
144{ 144{
145 return 0x0; 145 return 0x0U;
146} 146}
147static inline u32 pbdma_formats_pb_fermi1_f(void) 147static inline u32 pbdma_formats_pb_fermi1_f(void)
148{ 148{
149 return 0x100; 149 return 0x100U;
150} 150}
151static inline u32 pbdma_formats_mp_fermi0_f(void) 151static inline u32 pbdma_formats_mp_fermi0_f(void)
152{ 152{
153 return 0x0; 153 return 0x0U;
154} 154}
155static inline u32 pbdma_pb_header_r(u32 i) 155static inline u32 pbdma_pb_header_r(u32 i)
156{ 156{
157 return 0x00040084 + i*8192; 157 return 0x00040084U + i*8192U;
158} 158}
159static inline u32 pbdma_pb_header_priv_user_f(void) 159static inline u32 pbdma_pb_header_priv_user_f(void)
160{ 160{
161 return 0x0; 161 return 0x0U;
162} 162}
163static inline u32 pbdma_pb_header_method_zero_f(void) 163static inline u32 pbdma_pb_header_method_zero_f(void)
164{ 164{
165 return 0x0; 165 return 0x0U;
166} 166}
167static inline u32 pbdma_pb_header_subchannel_zero_f(void) 167static inline u32 pbdma_pb_header_subchannel_zero_f(void)
168{ 168{
169 return 0x0; 169 return 0x0U;
170} 170}
171static inline u32 pbdma_pb_header_level_main_f(void) 171static inline u32 pbdma_pb_header_level_main_f(void)
172{ 172{
173 return 0x0; 173 return 0x0U;
174} 174}
175static inline u32 pbdma_pb_header_first_true_f(void) 175static inline u32 pbdma_pb_header_first_true_f(void)
176{ 176{
177 return 0x400000; 177 return 0x400000U;
178} 178}
179static inline u32 pbdma_pb_header_type_inc_f(void) 179static inline u32 pbdma_pb_header_type_inc_f(void)
180{ 180{
181 return 0x20000000; 181 return 0x20000000U;
182} 182}
183static inline u32 pbdma_pb_header_type_non_inc_f(void) 183static inline u32 pbdma_pb_header_type_non_inc_f(void)
184{ 184{
185 return 0x60000000; 185 return 0x60000000U;
186} 186}
187static inline u32 pbdma_hdr_shadow_r(u32 i) 187static inline u32 pbdma_hdr_shadow_r(u32 i)
188{ 188{
189 return 0x00040118 + i*8192; 189 return 0x00040118U + i*8192U;
190} 190}
191static inline u32 pbdma_subdevice_r(u32 i) 191static inline u32 pbdma_subdevice_r(u32 i)
192{ 192{
193 return 0x00040094 + i*8192; 193 return 0x00040094U + i*8192U;
194} 194}
195static inline u32 pbdma_subdevice_id_f(u32 v) 195static inline u32 pbdma_subdevice_id_f(u32 v)
196{ 196{
197 return (v & 0xfff) << 0; 197 return (v & 0xfffU) << 0U;
198} 198}
199static inline u32 pbdma_subdevice_status_active_f(void) 199static inline u32 pbdma_subdevice_status_active_f(void)
200{ 200{
201 return 0x10000000; 201 return 0x10000000U;
202} 202}
203static inline u32 pbdma_subdevice_channel_dma_enable_f(void) 203static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
204{ 204{
205 return 0x20000000; 205 return 0x20000000U;
206} 206}
207static inline u32 pbdma_method0_r(u32 i) 207static inline u32 pbdma_method0_r(u32 i)
208{ 208{
209 return 0x000400c0 + i*8192; 209 return 0x000400c0U + i*8192U;
210} 210}
211static inline u32 pbdma_method0_fifo_size_v(void) 211static inline u32 pbdma_method0_fifo_size_v(void)
212{ 212{
213 return 0x00000004; 213 return 0x00000004U;
214} 214}
215static inline u32 pbdma_method0_addr_f(u32 v) 215static inline u32 pbdma_method0_addr_f(u32 v)
216{ 216{
217 return (v & 0xfff) << 2; 217 return (v & 0xfffU) << 2U;
218} 218}
219static inline u32 pbdma_method0_addr_v(u32 r) 219static inline u32 pbdma_method0_addr_v(u32 r)
220{ 220{
221 return (r >> 2) & 0xfff; 221 return (r >> 2U) & 0xfffU;
222} 222}
223static inline u32 pbdma_method0_subch_v(u32 r) 223static inline u32 pbdma_method0_subch_v(u32 r)
224{ 224{
225 return (r >> 16) & 0x7; 225 return (r >> 16U) & 0x7U;
226} 226}
227static inline u32 pbdma_method0_first_true_f(void) 227static inline u32 pbdma_method0_first_true_f(void)
228{ 228{
229 return 0x400000; 229 return 0x400000U;
230} 230}
231static inline u32 pbdma_method0_valid_true_f(void) 231static inline u32 pbdma_method0_valid_true_f(void)
232{ 232{
233 return 0x80000000; 233 return 0x80000000U;
234} 234}
235static inline u32 pbdma_method1_r(u32 i) 235static inline u32 pbdma_method1_r(u32 i)
236{ 236{
237 return 0x000400c8 + i*8192; 237 return 0x000400c8U + i*8192U;
238} 238}
239static inline u32 pbdma_method2_r(u32 i) 239static inline u32 pbdma_method2_r(u32 i)
240{ 240{
241 return 0x000400d0 + i*8192; 241 return 0x000400d0U + i*8192U;
242} 242}
243static inline u32 pbdma_method3_r(u32 i) 243static inline u32 pbdma_method3_r(u32 i)
244{ 244{
245 return 0x000400d8 + i*8192; 245 return 0x000400d8U + i*8192U;
246} 246}
247static inline u32 pbdma_data0_r(u32 i) 247static inline u32 pbdma_data0_r(u32 i)
248{ 248{
249 return 0x000400c4 + i*8192; 249 return 0x000400c4U + i*8192U;
250} 250}
251static inline u32 pbdma_target_r(u32 i) 251static inline u32 pbdma_target_r(u32 i)
252{ 252{
253 return 0x000400ac + i*8192; 253 return 0x000400acU + i*8192U;
254} 254}
255static inline u32 pbdma_target_engine_sw_f(void) 255static inline u32 pbdma_target_engine_sw_f(void)
256{ 256{
257 return 0x1f; 257 return 0x1fU;
258} 258}
259static inline u32 pbdma_acquire_r(u32 i) 259static inline u32 pbdma_acquire_r(u32 i)
260{ 260{
261 return 0x00040030 + i*8192; 261 return 0x00040030U + i*8192U;
262} 262}
263static inline u32 pbdma_acquire_retry_man_2_f(void) 263static inline u32 pbdma_acquire_retry_man_2_f(void)
264{ 264{
265 return 0x2; 265 return 0x2U;
266} 266}
267static inline u32 pbdma_acquire_retry_exp_2_f(void) 267static inline u32 pbdma_acquire_retry_exp_2_f(void)
268{ 268{
269 return 0x100; 269 return 0x100U;
270} 270}
271static inline u32 pbdma_acquire_timeout_exp_f(u32 v) 271static inline u32 pbdma_acquire_timeout_exp_f(u32 v)
272{ 272{
273 return (v & 0xf) << 11; 273 return (v & 0xfU) << 11U;
274} 274}
275static inline u32 pbdma_acquire_timeout_exp_max_v(void) 275static inline u32 pbdma_acquire_timeout_exp_max_v(void)
276{ 276{
277 return 0x0000000f; 277 return 0x0000000fU;
278} 278}
279static inline u32 pbdma_acquire_timeout_exp_max_f(void) 279static inline u32 pbdma_acquire_timeout_exp_max_f(void)
280{ 280{
281 return 0x7800; 281 return 0x7800U;
282} 282}
283static inline u32 pbdma_acquire_timeout_man_f(u32 v) 283static inline u32 pbdma_acquire_timeout_man_f(u32 v)
284{ 284{
285 return (v & 0xffff) << 15; 285 return (v & 0xffffU) << 15U;
286} 286}
287static inline u32 pbdma_acquire_timeout_man_max_v(void) 287static inline u32 pbdma_acquire_timeout_man_max_v(void)
288{ 288{
289 return 0x0000ffff; 289 return 0x0000ffffU;
290} 290}
291static inline u32 pbdma_acquire_timeout_man_max_f(void) 291static inline u32 pbdma_acquire_timeout_man_max_f(void)
292{ 292{
293 return 0x7fff8000; 293 return 0x7fff8000U;
294} 294}
295static inline u32 pbdma_acquire_timeout_en_enable_f(void) 295static inline u32 pbdma_acquire_timeout_en_enable_f(void)
296{ 296{
297 return 0x80000000; 297 return 0x80000000U;
298} 298}
299static inline u32 pbdma_acquire_timeout_en_disable_f(void) 299static inline u32 pbdma_acquire_timeout_en_disable_f(void)
300{ 300{
301 return 0x0; 301 return 0x0U;
302} 302}
303static inline u32 pbdma_status_r(u32 i) 303static inline u32 pbdma_status_r(u32 i)
304{ 304{
305 return 0x00040100 + i*8192; 305 return 0x00040100U + i*8192U;
306} 306}
307static inline u32 pbdma_channel_r(u32 i) 307static inline u32 pbdma_channel_r(u32 i)
308{ 308{
309 return 0x00040120 + i*8192; 309 return 0x00040120U + i*8192U;
310} 310}
311static inline u32 pbdma_signature_r(u32 i) 311static inline u32 pbdma_signature_r(u32 i)
312{ 312{
313 return 0x00040010 + i*8192; 313 return 0x00040010U + i*8192U;
314} 314}
315static inline u32 pbdma_signature_hw_valid_f(void) 315static inline u32 pbdma_signature_hw_valid_f(void)
316{ 316{
317 return 0xface; 317 return 0xfaceU;
318} 318}
319static inline u32 pbdma_signature_sw_zero_f(void) 319static inline u32 pbdma_signature_sw_zero_f(void)
320{ 320{
321 return 0x0; 321 return 0x0U;
322} 322}
323static inline u32 pbdma_userd_r(u32 i) 323static inline u32 pbdma_userd_r(u32 i)
324{ 324{
325 return 0x00040008 + i*8192; 325 return 0x00040008U + i*8192U;
326} 326}
327static inline u32 pbdma_userd_target_vid_mem_f(void) 327static inline u32 pbdma_userd_target_vid_mem_f(void)
328{ 328{
329 return 0x0; 329 return 0x0U;
330} 330}
331static inline u32 pbdma_userd_target_sys_mem_coh_f(void) 331static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
332{ 332{
333 return 0x2; 333 return 0x2U;
334} 334}
335static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) 335static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
336{ 336{
337 return 0x3; 337 return 0x3U;
338} 338}
339static inline u32 pbdma_userd_addr_f(u32 v) 339static inline u32 pbdma_userd_addr_f(u32 v)
340{ 340{
341 return (v & 0x7fffff) << 9; 341 return (v & 0x7fffffU) << 9U;
342} 342}
343static inline u32 pbdma_userd_hi_r(u32 i) 343static inline u32 pbdma_userd_hi_r(u32 i)
344{ 344{
345 return 0x0004000c + i*8192; 345 return 0x0004000cU + i*8192U;
346} 346}
347static inline u32 pbdma_userd_hi_addr_f(u32 v) 347static inline u32 pbdma_userd_hi_addr_f(u32 v)
348{ 348{
349 return (v & 0xff) << 0; 349 return (v & 0xffU) << 0U;
350} 350}
351static inline u32 pbdma_hce_ctrl_r(u32 i) 351static inline u32 pbdma_hce_ctrl_r(u32 i)
352{ 352{
353 return 0x000400e4 + i*8192; 353 return 0x000400e4U + i*8192U;
354} 354}
355static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) 355static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
356{ 356{
357 return 0x20; 357 return 0x20U;
358} 358}
359static inline u32 pbdma_intr_0_r(u32 i) 359static inline u32 pbdma_intr_0_r(u32 i)
360{ 360{
361 return 0x00040108 + i*8192; 361 return 0x00040108U + i*8192U;
362} 362}
363static inline u32 pbdma_intr_0_memreq_v(u32 r) 363static inline u32 pbdma_intr_0_memreq_v(u32 r)
364{ 364{
365 return (r >> 0) & 0x1; 365 return (r >> 0U) & 0x1U;
366} 366}
367static inline u32 pbdma_intr_0_memreq_pending_f(void) 367static inline u32 pbdma_intr_0_memreq_pending_f(void)
368{ 368{
369 return 0x1; 369 return 0x1U;
370} 370}
371static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) 371static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
372{ 372{
373 return 0x2; 373 return 0x2U;
374} 374}
375static inline u32 pbdma_intr_0_memack_extra_pending_f(void) 375static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
376{ 376{
377 return 0x4; 377 return 0x4U;
378} 378}
379static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) 379static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
380{ 380{
381 return 0x8; 381 return 0x8U;
382} 382}
383static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) 383static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
384{ 384{
385 return 0x10; 385 return 0x10U;
386} 386}
387static inline u32 pbdma_intr_0_memflush_pending_f(void) 387static inline u32 pbdma_intr_0_memflush_pending_f(void)
388{ 388{
389 return 0x20; 389 return 0x20U;
390} 390}
391static inline u32 pbdma_intr_0_memop_pending_f(void) 391static inline u32 pbdma_intr_0_memop_pending_f(void)
392{ 392{
393 return 0x40; 393 return 0x40U;
394} 394}
395static inline u32 pbdma_intr_0_lbconnect_pending_f(void) 395static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
396{ 396{
397 return 0x80; 397 return 0x80U;
398} 398}
399static inline u32 pbdma_intr_0_lbreq_pending_f(void) 399static inline u32 pbdma_intr_0_lbreq_pending_f(void)
400{ 400{
401 return 0x100; 401 return 0x100U;
402} 402}
403static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) 403static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
404{ 404{
405 return 0x200; 405 return 0x200U;
406} 406}
407static inline u32 pbdma_intr_0_lback_extra_pending_f(void) 407static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
408{ 408{
409 return 0x400; 409 return 0x400U;
410} 410}
411static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) 411static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
412{ 412{
413 return 0x800; 413 return 0x800U;
414} 414}
415static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) 415static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
416{ 416{
417 return 0x1000; 417 return 0x1000U;
418} 418}
419static inline u32 pbdma_intr_0_gpfifo_pending_f(void) 419static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
420{ 420{
421 return 0x2000; 421 return 0x2000U;
422} 422}
423static inline u32 pbdma_intr_0_gpptr_pending_f(void) 423static inline u32 pbdma_intr_0_gpptr_pending_f(void)
424{ 424{
425 return 0x4000; 425 return 0x4000U;
426} 426}
427static inline u32 pbdma_intr_0_gpentry_pending_f(void) 427static inline u32 pbdma_intr_0_gpentry_pending_f(void)
428{ 428{
429 return 0x8000; 429 return 0x8000U;
430} 430}
431static inline u32 pbdma_intr_0_gpcrc_pending_f(void) 431static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
432{ 432{
433 return 0x10000; 433 return 0x10000U;
434} 434}
435static inline u32 pbdma_intr_0_pbptr_pending_f(void) 435static inline u32 pbdma_intr_0_pbptr_pending_f(void)
436{ 436{
437 return 0x20000; 437 return 0x20000U;
438} 438}
439static inline u32 pbdma_intr_0_pbentry_pending_f(void) 439static inline u32 pbdma_intr_0_pbentry_pending_f(void)
440{ 440{
441 return 0x40000; 441 return 0x40000U;
442} 442}
443static inline u32 pbdma_intr_0_pbcrc_pending_f(void) 443static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
444{ 444{
445 return 0x80000; 445 return 0x80000U;
446} 446}
447static inline u32 pbdma_intr_0_xbarconnect_pending_f(void) 447static inline u32 pbdma_intr_0_xbarconnect_pending_f(void)
448{ 448{
449 return 0x100000; 449 return 0x100000U;
450} 450}
451static inline u32 pbdma_intr_0_method_pending_f(void) 451static inline u32 pbdma_intr_0_method_pending_f(void)
452{ 452{
453 return 0x200000; 453 return 0x200000U;
454} 454}
455static inline u32 pbdma_intr_0_methodcrc_pending_f(void) 455static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
456{ 456{
457 return 0x400000; 457 return 0x400000U;
458} 458}
459static inline u32 pbdma_intr_0_device_pending_f(void) 459static inline u32 pbdma_intr_0_device_pending_f(void)
460{ 460{
461 return 0x800000; 461 return 0x800000U;
462} 462}
463static inline u32 pbdma_intr_0_semaphore_pending_f(void) 463static inline u32 pbdma_intr_0_semaphore_pending_f(void)
464{ 464{
465 return 0x2000000; 465 return 0x2000000U;
466} 466}
467static inline u32 pbdma_intr_0_acquire_pending_f(void) 467static inline u32 pbdma_intr_0_acquire_pending_f(void)
468{ 468{
469 return 0x4000000; 469 return 0x4000000U;
470} 470}
471static inline u32 pbdma_intr_0_pri_pending_f(void) 471static inline u32 pbdma_intr_0_pri_pending_f(void)
472{ 472{
473 return 0x8000000; 473 return 0x8000000U;
474} 474}
475static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) 475static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
476{ 476{
477 return 0x20000000; 477 return 0x20000000U;
478} 478}
479static inline u32 pbdma_intr_0_pbseg_pending_f(void) 479static inline u32 pbdma_intr_0_pbseg_pending_f(void)
480{ 480{
481 return 0x40000000; 481 return 0x40000000U;
482} 482}
483static inline u32 pbdma_intr_0_signature_pending_f(void) 483static inline u32 pbdma_intr_0_signature_pending_f(void)
484{ 484{
485 return 0x80000000; 485 return 0x80000000U;
486} 486}
487static inline u32 pbdma_intr_1_r(u32 i) 487static inline u32 pbdma_intr_1_r(u32 i)
488{ 488{
489 return 0x00040148 + i*8192; 489 return 0x00040148U + i*8192U;
490} 490}
491static inline u32 pbdma_intr_en_0_r(u32 i) 491static inline u32 pbdma_intr_en_0_r(u32 i)
492{ 492{
493 return 0x0004010c + i*8192; 493 return 0x0004010cU + i*8192U;
494} 494}
495static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) 495static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
496{ 496{
497 return 0x100; 497 return 0x100U;
498} 498}
499static inline u32 pbdma_intr_en_1_r(u32 i) 499static inline u32 pbdma_intr_en_1_r(u32 i)
500{ 500{
501 return 0x0004014c + i*8192; 501 return 0x0004014cU + i*8192U;
502} 502}
503static inline u32 pbdma_intr_stall_r(u32 i) 503static inline u32 pbdma_intr_stall_r(u32 i)
504{ 504{
505 return 0x0004013c + i*8192; 505 return 0x0004013cU + i*8192U;
506} 506}
507static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) 507static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
508{ 508{
509 return 0x100; 509 return 0x100U;
510} 510}
511static inline u32 pbdma_udma_nop_r(void) 511static inline u32 pbdma_udma_nop_r(void)
512{ 512{
513 return 0x00000008; 513 return 0x00000008U;
514} 514}
515static inline u32 pbdma_syncpointa_r(u32 i) 515static inline u32 pbdma_syncpointa_r(u32 i)
516{ 516{
517 return 0x000400a4 + i*8192; 517 return 0x000400a4U + i*8192U;
518} 518}
519static inline u32 pbdma_syncpointa_payload_v(u32 r) 519static inline u32 pbdma_syncpointa_payload_v(u32 r)
520{ 520{
521 return (r >> 0) & 0xffffffff; 521 return (r >> 0U) & 0xffffffffU;
522} 522}
523static inline u32 pbdma_syncpointb_r(u32 i) 523static inline u32 pbdma_syncpointb_r(u32 i)
524{ 524{
525 return 0x000400a8 + i*8192; 525 return 0x000400a8U + i*8192U;
526} 526}
527static inline u32 pbdma_syncpointb_op_v(u32 r) 527static inline u32 pbdma_syncpointb_op_v(u32 r)
528{ 528{
529 return (r >> 0) & 0x3; 529 return (r >> 0U) & 0x3U;
530} 530}
531static inline u32 pbdma_syncpointb_op_wait_v(void) 531static inline u32 pbdma_syncpointb_op_wait_v(void)
532{ 532{
533 return 0x00000000; 533 return 0x00000000U;
534} 534}
535static inline u32 pbdma_syncpointb_wait_switch_v(u32 r) 535static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
536{ 536{
537 return (r >> 4) & 0x1; 537 return (r >> 4U) & 0x1U;
538} 538}
539static inline u32 pbdma_syncpointb_wait_switch_en_v(void) 539static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
540{ 540{
541 return 0x00000001; 541 return 0x00000001U;
542} 542}
543static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r) 543static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
544{ 544{
545 return (r >> 8) & 0xff; 545 return (r >> 8U) & 0xffU;
546} 546}
547static inline u32 pbdma_runlist_timeslice_r(u32 i) 547static inline u32 pbdma_runlist_timeslice_r(u32 i)
548{ 548{
549 return 0x000400f8 + i*8192; 549 return 0x000400f8U + i*8192U;
550} 550}
551static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) 551static inline u32 pbdma_runlist_timeslice_timeout_128_f(void)
552{ 552{
553 return 0x80; 553 return 0x80U;
554} 554}
555static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) 555static inline u32 pbdma_runlist_timeslice_timescale_3_f(void)
556{ 556{
557 return 0x3000; 557 return 0x3000U;
558} 558}
559static inline u32 pbdma_runlist_timeslice_enable_true_f(void) 559static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
560{ 560{
561 return 0x10000000; 561 return 0x10000000U;
562} 562}
563#endif 563#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h
index 75118476..ae34cabd 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_perf_gm20b.h
@@ -58,154 +58,154 @@
58 58
59static inline u32 perf_pmasys_control_r(void) 59static inline u32 perf_pmasys_control_r(void)
60{ 60{
61 return 0x001b4000; 61 return 0x001b4000U;
62} 62}
63static inline u32 perf_pmasys_control_membuf_status_v(u32 r) 63static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
64{ 64{
65 return (r >> 4) & 0x1; 65 return (r >> 4U) & 0x1U;
66} 66}
67static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) 67static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
68{ 68{
69 return 0x00000001; 69 return 0x00000001U;
70} 70}
71static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) 71static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
72{ 72{
73 return 0x10; 73 return 0x10U;
74} 74}
75static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) 75static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
76{ 76{
77 return (v & 0x1) << 5; 77 return (v & 0x1U) << 5U;
78} 78}
79static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) 79static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
80{ 80{
81 return (r >> 5) & 0x1; 81 return (r >> 5U) & 0x1U;
82} 82}
83static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) 83static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
84{ 84{
85 return 0x00000001; 85 return 0x00000001U;
86} 86}
87static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) 87static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
88{ 88{
89 return 0x20; 89 return 0x20U;
90} 90}
91static inline u32 perf_pmasys_mem_block_r(void) 91static inline u32 perf_pmasys_mem_block_r(void)
92{ 92{
93 return 0x001b4070; 93 return 0x001b4070U;
94} 94}
95static inline u32 perf_pmasys_mem_block_base_f(u32 v) 95static inline u32 perf_pmasys_mem_block_base_f(u32 v)
96{ 96{
97 return (v & 0xfffffff) << 0; 97 return (v & 0xfffffffU) << 0U;
98} 98}
99static inline u32 perf_pmasys_mem_block_target_f(u32 v) 99static inline u32 perf_pmasys_mem_block_target_f(u32 v)
100{ 100{
101 return (v & 0x3) << 28; 101 return (v & 0x3U) << 28U;
102} 102}
103static inline u32 perf_pmasys_mem_block_target_v(u32 r) 103static inline u32 perf_pmasys_mem_block_target_v(u32 r)
104{ 104{
105 return (r >> 28) & 0x3; 105 return (r >> 28U) & 0x3U;
106} 106}
107static inline u32 perf_pmasys_mem_block_target_lfb_v(void) 107static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
108{ 108{
109 return 0x00000000; 109 return 0x00000000U;
110} 110}
111static inline u32 perf_pmasys_mem_block_target_lfb_f(void) 111static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
112{ 112{
113 return 0x0; 113 return 0x0U;
114} 114}
115static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) 115static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
116{ 116{
117 return 0x00000002; 117 return 0x00000002U;
118} 118}
119static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) 119static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
120{ 120{
121 return 0x20000000; 121 return 0x20000000U;
122} 122}
123static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) 123static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
124{ 124{
125 return 0x00000003; 125 return 0x00000003U;
126} 126}
127static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) 127static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
128{ 128{
129 return 0x30000000; 129 return 0x30000000U;
130} 130}
131static inline u32 perf_pmasys_mem_block_valid_f(u32 v) 131static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
132{ 132{
133 return (v & 0x1) << 31; 133 return (v & 0x1U) << 31U;
134} 134}
135static inline u32 perf_pmasys_mem_block_valid_v(u32 r) 135static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
136{ 136{
137 return (r >> 31) & 0x1; 137 return (r >> 31U) & 0x1U;
138} 138}
139static inline u32 perf_pmasys_mem_block_valid_true_v(void) 139static inline u32 perf_pmasys_mem_block_valid_true_v(void)
140{ 140{
141 return 0x00000001; 141 return 0x00000001U;
142} 142}
143static inline u32 perf_pmasys_mem_block_valid_true_f(void) 143static inline u32 perf_pmasys_mem_block_valid_true_f(void)
144{ 144{
145 return 0x80000000; 145 return 0x80000000U;
146} 146}
147static inline u32 perf_pmasys_mem_block_valid_false_v(void) 147static inline u32 perf_pmasys_mem_block_valid_false_v(void)
148{ 148{
149 return 0x00000000; 149 return 0x00000000U;
150} 150}
151static inline u32 perf_pmasys_mem_block_valid_false_f(void) 151static inline u32 perf_pmasys_mem_block_valid_false_f(void)
152{ 152{
153 return 0x0; 153 return 0x0U;
154} 154}
155static inline u32 perf_pmasys_outbase_r(void) 155static inline u32 perf_pmasys_outbase_r(void)
156{ 156{
157 return 0x001b4074; 157 return 0x001b4074U;
158} 158}
159static inline u32 perf_pmasys_outbase_ptr_f(u32 v) 159static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
160{ 160{
161 return (v & 0x7ffffff) << 5; 161 return (v & 0x7ffffffU) << 5U;
162} 162}
163static inline u32 perf_pmasys_outbaseupper_r(void) 163static inline u32 perf_pmasys_outbaseupper_r(void)
164{ 164{
165 return 0x001b4078; 165 return 0x001b4078U;
166} 166}
167static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) 167static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
168{ 168{
169 return (v & 0xff) << 0; 169 return (v & 0xffU) << 0U;
170} 170}
171static inline u32 perf_pmasys_outsize_r(void) 171static inline u32 perf_pmasys_outsize_r(void)
172{ 172{
173 return 0x001b407c; 173 return 0x001b407cU;
174} 174}
175static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) 175static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
176{ 176{
177 return (v & 0x7ffffff) << 5; 177 return (v & 0x7ffffffU) << 5U;
178} 178}
179static inline u32 perf_pmasys_mem_bytes_r(void) 179static inline u32 perf_pmasys_mem_bytes_r(void)
180{ 180{
181 return 0x001b4084; 181 return 0x001b4084U;
182} 182}
183static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) 183static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
184{ 184{
185 return (v & 0xfffffff) << 4; 185 return (v & 0xfffffffU) << 4U;
186} 186}
187static inline u32 perf_pmasys_mem_bump_r(void) 187static inline u32 perf_pmasys_mem_bump_r(void)
188{ 188{
189 return 0x001b4088; 189 return 0x001b4088U;
190} 190}
191static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) 191static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
192{ 192{
193 return (v & 0xfffffff) << 4; 193 return (v & 0xfffffffU) << 4U;
194} 194}
195static inline u32 perf_pmasys_enginestatus_r(void) 195static inline u32 perf_pmasys_enginestatus_r(void)
196{ 196{
197 return 0x001b40a4; 197 return 0x001b40a4U;
198} 198}
199static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) 199static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
200{ 200{
201 return (v & 0x1) << 4; 201 return (v & 0x1U) << 4U;
202} 202}
203static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) 203static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
204{ 204{
205 return 0x00000001; 205 return 0x00000001U;
206} 206}
207static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) 207static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
208{ 208{
209 return 0x10; 209 return 0x10U;
210} 210}
211#endif 211#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pram_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pram_gm20b.h
index 107d1603..47a6bfa8 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pram_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pram_gm20b.h
@@ -58,6 +58,6 @@
58 58
59static inline u32 pram_data032_r(u32 i) 59static inline u32 pram_data032_r(u32 i)
60{ 60{
61 return 0x00700000 + i*4; 61 return 0x00700000U + i*4U;
62} 62}
63#endif 63#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h
index 14b8a014..c6f08ed3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h
@@ -58,110 +58,110 @@
58 58
59static inline u32 pri_ringmaster_command_r(void) 59static inline u32 pri_ringmaster_command_r(void)
60{ 60{
61 return 0x0012004c; 61 return 0x0012004cU;
62} 62}
63static inline u32 pri_ringmaster_command_cmd_m(void) 63static inline u32 pri_ringmaster_command_cmd_m(void)
64{ 64{
65 return 0x3f << 0; 65 return 0x3fU << 0U;
66} 66}
67static inline u32 pri_ringmaster_command_cmd_v(u32 r) 67static inline u32 pri_ringmaster_command_cmd_v(u32 r)
68{ 68{
69 return (r >> 0) & 0x3f; 69 return (r >> 0U) & 0x3fU;
70} 70}
71static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) 71static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
72{ 72{
73 return 0x00000000; 73 return 0x00000000U;
74} 74}
75static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) 75static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
76{ 76{
77 return 0x1; 77 return 0x1U;
78} 78}
79static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) 79static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
80{ 80{
81 return 0x2; 81 return 0x2U;
82} 82}
83static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) 83static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
84{ 84{
85 return 0x3; 85 return 0x3U;
86} 86}
87static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) 87static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
88{ 88{
89 return 0x0; 89 return 0x0U;
90} 90}
91static inline u32 pri_ringmaster_command_data_r(void) 91static inline u32 pri_ringmaster_command_data_r(void)
92{ 92{
93 return 0x00120048; 93 return 0x00120048U;
94} 94}
95static inline u32 pri_ringmaster_start_results_r(void) 95static inline u32 pri_ringmaster_start_results_r(void)
96{ 96{
97 return 0x00120050; 97 return 0x00120050U;
98} 98}
99static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) 99static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
100{ 100{
101 return (r >> 0) & 0x1; 101 return (r >> 0U) & 0x1U;
102} 102}
103static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) 103static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
104{ 104{
105 return 0x00000001; 105 return 0x00000001U;
106} 106}
107static inline u32 pri_ringmaster_intr_status0_r(void) 107static inline u32 pri_ringmaster_intr_status0_r(void)
108{ 108{
109 return 0x00120058; 109 return 0x00120058U;
110} 110}
111static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) 111static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
112{ 112{
113 return (r >> 0) & 0x1; 113 return (r >> 0U) & 0x1U;
114} 114}
115static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) 115static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
116{ 116{
117 return (r >> 1) & 0x1; 117 return (r >> 1U) & 0x1U;
118} 118}
119static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) 119static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
120{ 120{
121 return (r >> 2) & 0x1; 121 return (r >> 2U) & 0x1U;
122} 122}
123static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) 123static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
124{ 124{
125 return (r >> 8) & 0x1; 125 return (r >> 8U) & 0x1U;
126} 126}
127static inline u32 pri_ringmaster_intr_status1_r(void) 127static inline u32 pri_ringmaster_intr_status1_r(void)
128{ 128{
129 return 0x0012005c; 129 return 0x0012005cU;
130} 130}
131static inline u32 pri_ringmaster_global_ctl_r(void) 131static inline u32 pri_ringmaster_global_ctl_r(void)
132{ 132{
133 return 0x00120060; 133 return 0x00120060U;
134} 134}
135static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) 135static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
136{ 136{
137 return 0x1; 137 return 0x1U;
138} 138}
139static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) 139static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
140{ 140{
141 return 0x0; 141 return 0x0U;
142} 142}
143static inline u32 pri_ringmaster_enum_fbp_r(void) 143static inline u32 pri_ringmaster_enum_fbp_r(void)
144{ 144{
145 return 0x00120074; 145 return 0x00120074U;
146} 146}
147static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) 147static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
148{ 148{
149 return (r >> 0) & 0x1f; 149 return (r >> 0U) & 0x1fU;
150} 150}
151static inline u32 pri_ringmaster_enum_gpc_r(void) 151static inline u32 pri_ringmaster_enum_gpc_r(void)
152{ 152{
153 return 0x00120078; 153 return 0x00120078U;
154} 154}
155static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) 155static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
156{ 156{
157 return (r >> 0) & 0x1f; 157 return (r >> 0U) & 0x1fU;
158} 158}
159static inline u32 pri_ringmaster_enum_ltc_r(void) 159static inline u32 pri_ringmaster_enum_ltc_r(void)
160{ 160{
161 return 0x0012006c; 161 return 0x0012006cU;
162} 162}
163static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) 163static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
164{ 164{
165 return (r >> 0) & 0x1f; 165 return (r >> 0U) & 0x1fU;
166} 166}
167#endif 167#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h
index 73ecb615..8d1ffb2b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h
@@ -58,22 +58,22 @@
58 58
59static inline u32 pri_ringstation_gpc_master_config_r(u32 i) 59static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
60{ 60{
61 return 0x00128300 + i*4; 61 return 0x00128300U + i*4U;
62} 62}
63static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) 63static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
64{ 64{
65 return 0x00128120; 65 return 0x00128120U;
66} 66}
67static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) 67static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
68{ 68{
69 return 0x00128124; 69 return 0x00128124U;
70} 70}
71static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) 71static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
72{ 72{
73 return 0x00128128; 73 return 0x00128128U;
74} 74}
75static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) 75static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
76{ 76{
77 return 0x0012812c; 77 return 0x0012812cU;
78} 78}
79#endif 79#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h
index 36a33ee2..ac1d2456 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h
@@ -58,34 +58,34 @@
58 58
59static inline u32 pri_ringstation_sys_master_config_r(u32 i) 59static inline u32 pri_ringstation_sys_master_config_r(u32 i)
60{ 60{
61 return 0x00122300 + i*4; 61 return 0x00122300U + i*4U;
62} 62}
63static inline u32 pri_ringstation_sys_decode_config_r(void) 63static inline u32 pri_ringstation_sys_decode_config_r(void)
64{ 64{
65 return 0x00122204; 65 return 0x00122204U;
66} 66}
67static inline u32 pri_ringstation_sys_decode_config_ring_m(void) 67static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
68{ 68{
69 return 0x7 << 0; 69 return 0x7U << 0U;
70} 70}
71static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) 71static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
72{ 72{
73 return 0x1; 73 return 0x1U;
74} 74}
75static inline u32 pri_ringstation_sys_priv_error_adr_r(void) 75static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
76{ 76{
77 return 0x00122120; 77 return 0x00122120U;
78} 78}
79static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) 79static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
80{ 80{
81 return 0x00122124; 81 return 0x00122124U;
82} 82}
83static inline u32 pri_ringstation_sys_priv_error_info_r(void) 83static inline u32 pri_ringstation_sys_priv_error_info_r(void)
84{ 84{
85 return 0x00122128; 85 return 0x00122128U;
86} 86}
87static inline u32 pri_ringstation_sys_priv_error_code_r(void) 87static inline u32 pri_ringstation_sys_priv_error_code_r(void)
88{ 88{
89 return 0x0012212c; 89 return 0x0012212cU;
90} 90}
91#endif 91#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_proj_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_proj_gm20b.h
index c08dcc4c..d44cc463 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_proj_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_proj_gm20b.h
@@ -58,110 +58,110 @@
58 58
59static inline u32 proj_gpc_base_v(void) 59static inline u32 proj_gpc_base_v(void)
60{ 60{
61 return 0x00500000; 61 return 0x00500000U;
62} 62}
63static inline u32 proj_gpc_shared_base_v(void) 63static inline u32 proj_gpc_shared_base_v(void)
64{ 64{
65 return 0x00418000; 65 return 0x00418000U;
66} 66}
67static inline u32 proj_gpc_stride_v(void) 67static inline u32 proj_gpc_stride_v(void)
68{ 68{
69 return 0x00008000; 69 return 0x00008000U;
70} 70}
71static inline u32 proj_ltc_stride_v(void) 71static inline u32 proj_ltc_stride_v(void)
72{ 72{
73 return 0x00002000; 73 return 0x00002000U;
74} 74}
75static inline u32 proj_lts_stride_v(void) 75static inline u32 proj_lts_stride_v(void)
76{ 76{
77 return 0x00000200; 77 return 0x00000200U;
78} 78}
79static inline u32 proj_fbpa_stride_v(void) 79static inline u32 proj_fbpa_stride_v(void)
80{ 80{
81 return 0x00001000; 81 return 0x00001000U;
82} 82}
83static inline u32 proj_ppc_in_gpc_base_v(void) 83static inline u32 proj_ppc_in_gpc_base_v(void)
84{ 84{
85 return 0x00003000; 85 return 0x00003000U;
86} 86}
87static inline u32 proj_ppc_in_gpc_shared_base_v(void) 87static inline u32 proj_ppc_in_gpc_shared_base_v(void)
88{ 88{
89 return 0x00003e00; 89 return 0x00003e00U;
90} 90}
91static inline u32 proj_ppc_in_gpc_stride_v(void) 91static inline u32 proj_ppc_in_gpc_stride_v(void)
92{ 92{
93 return 0x00000200; 93 return 0x00000200U;
94} 94}
95static inline u32 proj_rop_base_v(void) 95static inline u32 proj_rop_base_v(void)
96{ 96{
97 return 0x00410000; 97 return 0x00410000U;
98} 98}
99static inline u32 proj_rop_shared_base_v(void) 99static inline u32 proj_rop_shared_base_v(void)
100{ 100{
101 return 0x00408800; 101 return 0x00408800U;
102} 102}
103static inline u32 proj_rop_stride_v(void) 103static inline u32 proj_rop_stride_v(void)
104{ 104{
105 return 0x00000400; 105 return 0x00000400U;
106} 106}
107static inline u32 proj_tpc_in_gpc_base_v(void) 107static inline u32 proj_tpc_in_gpc_base_v(void)
108{ 108{
109 return 0x00004000; 109 return 0x00004000U;
110} 110}
111static inline u32 proj_tpc_in_gpc_stride_v(void) 111static inline u32 proj_tpc_in_gpc_stride_v(void)
112{ 112{
113 return 0x00000800; 113 return 0x00000800U;
114} 114}
115static inline u32 proj_tpc_in_gpc_shared_base_v(void) 115static inline u32 proj_tpc_in_gpc_shared_base_v(void)
116{ 116{
117 return 0x00001800; 117 return 0x00001800U;
118} 118}
119static inline u32 proj_host_num_engines_v(void) 119static inline u32 proj_host_num_engines_v(void)
120{ 120{
121 return 0x00000002; 121 return 0x00000002U;
122} 122}
123static inline u32 proj_host_num_pbdma_v(void) 123static inline u32 proj_host_num_pbdma_v(void)
124{ 124{
125 return 0x00000001; 125 return 0x00000001U;
126} 126}
127static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) 127static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
128{ 128{
129 return 0x00000002; 129 return 0x00000002U;
130} 130}
131static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) 131static inline u32 proj_scal_litter_num_sm_per_tpc_v(void)
132{ 132{
133 return 0x00000001; 133 return 0x00000001U;
134} 134}
135static inline u32 proj_scal_litter_num_fbps_v(void) 135static inline u32 proj_scal_litter_num_fbps_v(void)
136{ 136{
137 return 0x00000001; 137 return 0x00000001U;
138} 138}
139static inline u32 proj_scal_litter_num_fbpas_v(void) 139static inline u32 proj_scal_litter_num_fbpas_v(void)
140{ 140{
141 return 0x00000001; 141 return 0x00000001U;
142} 142}
143static inline u32 proj_scal_litter_num_gpcs_v(void) 143static inline u32 proj_scal_litter_num_gpcs_v(void)
144{ 144{
145 return 0x00000001; 145 return 0x00000001U;
146} 146}
147static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) 147static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
148{ 148{
149 return 0x00000001; 149 return 0x00000001U;
150} 150}
151static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) 151static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
152{ 152{
153 return 0x00000002; 153 return 0x00000002U;
154} 154}
155static inline u32 proj_scal_litter_num_zcull_banks_v(void) 155static inline u32 proj_scal_litter_num_zcull_banks_v(void)
156{ 156{
157 return 0x00000004; 157 return 0x00000004U;
158} 158}
159static inline u32 proj_scal_max_gpcs_v(void) 159static inline u32 proj_scal_max_gpcs_v(void)
160{ 160{
161 return 0x00000020; 161 return 0x00000020U;
162} 162}
163static inline u32 proj_scal_max_tpc_per_gpc_v(void) 163static inline u32 proj_scal_max_tpc_per_gpc_v(void)
164{ 164{
165 return 0x00000008; 165 return 0x00000008U;
166} 166}
167#endif 167#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
index 679f4c55..fa232644 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pwr_gm20b.h
@@ -58,770 +58,770 @@
58 58
59static inline u32 pwr_falcon_irqsset_r(void) 59static inline u32 pwr_falcon_irqsset_r(void)
60{ 60{
61 return 0x0010a000; 61 return 0x0010a000U;
62} 62}
63static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) 63static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
64{ 64{
65 return 0x40; 65 return 0x40U;
66} 66}
67static inline u32 pwr_falcon_irqsclr_r(void) 67static inline u32 pwr_falcon_irqsclr_r(void)
68{ 68{
69 return 0x0010a004; 69 return 0x0010a004U;
70} 70}
71static inline u32 pwr_falcon_irqstat_r(void) 71static inline u32 pwr_falcon_irqstat_r(void)
72{ 72{
73 return 0x0010a008; 73 return 0x0010a008U;
74} 74}
75static inline u32 pwr_falcon_irqstat_halt_true_f(void) 75static inline u32 pwr_falcon_irqstat_halt_true_f(void)
76{ 76{
77 return 0x10; 77 return 0x10U;
78} 78}
79static inline u32 pwr_falcon_irqstat_exterr_true_f(void) 79static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
80{ 80{
81 return 0x20; 81 return 0x20U;
82} 82}
83static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) 83static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
84{ 84{
85 return 0x40; 85 return 0x40U;
86} 86}
87static inline u32 pwr_falcon_irqmode_r(void) 87static inline u32 pwr_falcon_irqmode_r(void)
88{ 88{
89 return 0x0010a00c; 89 return 0x0010a00cU;
90} 90}
91static inline u32 pwr_falcon_irqmset_r(void) 91static inline u32 pwr_falcon_irqmset_r(void)
92{ 92{
93 return 0x0010a010; 93 return 0x0010a010U;
94} 94}
95static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) 95static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
96{ 96{
97 return (v & 0x1) << 0; 97 return (v & 0x1U) << 0U;
98} 98}
99static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) 99static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
100{ 100{
101 return (v & 0x1) << 1; 101 return (v & 0x1U) << 1U;
102} 102}
103static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) 103static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
104{ 104{
105 return (v & 0x1) << 2; 105 return (v & 0x1U) << 2U;
106} 106}
107static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) 107static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
108{ 108{
109 return (v & 0x1) << 3; 109 return (v & 0x1U) << 3U;
110} 110}
111static inline u32 pwr_falcon_irqmset_halt_f(u32 v) 111static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
112{ 112{
113 return (v & 0x1) << 4; 113 return (v & 0x1U) << 4U;
114} 114}
115static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) 115static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
116{ 116{
117 return (v & 0x1) << 5; 117 return (v & 0x1U) << 5U;
118} 118}
119static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) 119static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
120{ 120{
121 return (v & 0x1) << 6; 121 return (v & 0x1U) << 6U;
122} 122}
123static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) 123static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
124{ 124{
125 return (v & 0x1) << 7; 125 return (v & 0x1U) << 7U;
126} 126}
127static inline u32 pwr_falcon_irqmclr_r(void) 127static inline u32 pwr_falcon_irqmclr_r(void)
128{ 128{
129 return 0x0010a014; 129 return 0x0010a014U;
130} 130}
131static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) 131static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
132{ 132{
133 return (v & 0x1) << 0; 133 return (v & 0x1U) << 0U;
134} 134}
135static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) 135static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
136{ 136{
137 return (v & 0x1) << 1; 137 return (v & 0x1U) << 1U;
138} 138}
139static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) 139static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
140{ 140{
141 return (v & 0x1) << 2; 141 return (v & 0x1U) << 2U;
142} 142}
143static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) 143static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
144{ 144{
145 return (v & 0x1) << 3; 145 return (v & 0x1U) << 3U;
146} 146}
147static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) 147static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
148{ 148{
149 return (v & 0x1) << 4; 149 return (v & 0x1U) << 4U;
150} 150}
151static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) 151static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
152{ 152{
153 return (v & 0x1) << 5; 153 return (v & 0x1U) << 5U;
154} 154}
155static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) 155static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
156{ 156{
157 return (v & 0x1) << 6; 157 return (v & 0x1U) << 6U;
158} 158}
159static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) 159static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
160{ 160{
161 return (v & 0x1) << 7; 161 return (v & 0x1U) << 7U;
162} 162}
163static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) 163static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
164{ 164{
165 return (v & 0xff) << 8; 165 return (v & 0xffU) << 8U;
166} 166}
167static inline u32 pwr_falcon_irqmask_r(void) 167static inline u32 pwr_falcon_irqmask_r(void)
168{ 168{
169 return 0x0010a018; 169 return 0x0010a018U;
170} 170}
171static inline u32 pwr_falcon_irqdest_r(void) 171static inline u32 pwr_falcon_irqdest_r(void)
172{ 172{
173 return 0x0010a01c; 173 return 0x0010a01cU;
174} 174}
175static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) 175static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
176{ 176{
177 return (v & 0x1) << 0; 177 return (v & 0x1U) << 0U;
178} 178}
179static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) 179static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
180{ 180{
181 return (v & 0x1) << 1; 181 return (v & 0x1U) << 1U;
182} 182}
183static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) 183static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
184{ 184{
185 return (v & 0x1) << 2; 185 return (v & 0x1U) << 2U;
186} 186}
187static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) 187static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
188{ 188{
189 return (v & 0x1) << 3; 189 return (v & 0x1U) << 3U;
190} 190}
191static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) 191static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
192{ 192{
193 return (v & 0x1) << 4; 193 return (v & 0x1U) << 4U;
194} 194}
195static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) 195static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
196{ 196{
197 return (v & 0x1) << 5; 197 return (v & 0x1U) << 5U;
198} 198}
199static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) 199static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
200{ 200{
201 return (v & 0x1) << 6; 201 return (v & 0x1U) << 6U;
202} 202}
203static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) 203static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
204{ 204{
205 return (v & 0x1) << 7; 205 return (v & 0x1U) << 7U;
206} 206}
207static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) 207static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
208{ 208{
209 return (v & 0xff) << 8; 209 return (v & 0xffU) << 8U;
210} 210}
211static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) 211static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
212{ 212{
213 return (v & 0x1) << 16; 213 return (v & 0x1U) << 16U;
214} 214}
215static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) 215static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
216{ 216{
217 return (v & 0x1) << 17; 217 return (v & 0x1U) << 17U;
218} 218}
219static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) 219static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
220{ 220{
221 return (v & 0x1) << 18; 221 return (v & 0x1U) << 18U;
222} 222}
223static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) 223static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
224{ 224{
225 return (v & 0x1) << 19; 225 return (v & 0x1U) << 19U;
226} 226}
227static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) 227static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
228{ 228{
229 return (v & 0x1) << 20; 229 return (v & 0x1U) << 20U;
230} 230}
231static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) 231static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
232{ 232{
233 return (v & 0x1) << 21; 233 return (v & 0x1U) << 21U;
234} 234}
235static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) 235static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
236{ 236{
237 return (v & 0x1) << 22; 237 return (v & 0x1U) << 22U;
238} 238}
239static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) 239static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
240{ 240{
241 return (v & 0x1) << 23; 241 return (v & 0x1U) << 23U;
242} 242}
243static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) 243static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
244{ 244{
245 return (v & 0xff) << 24; 245 return (v & 0xffU) << 24U;
246} 246}
247static inline u32 pwr_falcon_curctx_r(void) 247static inline u32 pwr_falcon_curctx_r(void)
248{ 248{
249 return 0x0010a050; 249 return 0x0010a050U;
250} 250}
251static inline u32 pwr_falcon_nxtctx_r(void) 251static inline u32 pwr_falcon_nxtctx_r(void)
252{ 252{
253 return 0x0010a054; 253 return 0x0010a054U;
254} 254}
255static inline u32 pwr_falcon_mailbox0_r(void) 255static inline u32 pwr_falcon_mailbox0_r(void)
256{ 256{
257 return 0x0010a040; 257 return 0x0010a040U;
258} 258}
259static inline u32 pwr_falcon_mailbox1_r(void) 259static inline u32 pwr_falcon_mailbox1_r(void)
260{ 260{
261 return 0x0010a044; 261 return 0x0010a044U;
262} 262}
263static inline u32 pwr_falcon_itfen_r(void) 263static inline u32 pwr_falcon_itfen_r(void)
264{ 264{
265 return 0x0010a048; 265 return 0x0010a048U;
266} 266}
267static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) 267static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
268{ 268{
269 return 0x1; 269 return 0x1U;
270} 270}
271static inline u32 pwr_falcon_idlestate_r(void) 271static inline u32 pwr_falcon_idlestate_r(void)
272{ 272{
273 return 0x0010a04c; 273 return 0x0010a04cU;
274} 274}
275static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) 275static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
276{ 276{
277 return (r >> 0) & 0x1; 277 return (r >> 0U) & 0x1U;
278} 278}
279static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) 279static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
280{ 280{
281 return (r >> 1) & 0x7fff; 281 return (r >> 1U) & 0x7fffU;
282} 282}
283static inline u32 pwr_falcon_os_r(void) 283static inline u32 pwr_falcon_os_r(void)
284{ 284{
285 return 0x0010a080; 285 return 0x0010a080U;
286} 286}
287static inline u32 pwr_falcon_engctl_r(void) 287static inline u32 pwr_falcon_engctl_r(void)
288{ 288{
289 return 0x0010a0a4; 289 return 0x0010a0a4U;
290} 290}
291static inline u32 pwr_falcon_cpuctl_r(void) 291static inline u32 pwr_falcon_cpuctl_r(void)
292{ 292{
293 return 0x0010a100; 293 return 0x0010a100U;
294} 294}
295static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) 295static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
296{ 296{
297 return (v & 0x1) << 1; 297 return (v & 0x1U) << 1U;
298} 298}
299static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) 299static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
300{ 300{
301 return (v & 0x1) << 4; 301 return (v & 0x1U) << 4U;
302} 302}
303static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) 303static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
304{ 304{
305 return 0x1 << 4; 305 return 0x1U << 4U;
306} 306}
307static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) 307static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
308{ 308{
309 return (r >> 4) & 0x1; 309 return (r >> 4U) & 0x1U;
310} 310}
311static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) 311static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
312{ 312{
313 return (v & 0x1) << 6; 313 return (v & 0x1U) << 6U;
314} 314}
315static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) 315static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
316{ 316{
317 return 0x1 << 6; 317 return 0x1U << 6U;
318} 318}
319static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) 319static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
320{ 320{
321 return (r >> 6) & 0x1; 321 return (r >> 6U) & 0x1U;
322} 322}
323static inline u32 pwr_falcon_cpuctl_alias_r(void) 323static inline u32 pwr_falcon_cpuctl_alias_r(void)
324{ 324{
325 return 0x0010a130; 325 return 0x0010a130U;
326} 326}
327static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) 327static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v)
328{ 328{
329 return (v & 0x1) << 1; 329 return (v & 0x1U) << 1U;
330} 330}
331static inline u32 pwr_pmu_scpctl_stat_r(void) 331static inline u32 pwr_pmu_scpctl_stat_r(void)
332{ 332{
333 return 0x0010ac08; 333 return 0x0010ac08U;
334} 334}
335static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) 335static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
336{ 336{
337 return (v & 0x1) << 20; 337 return (v & 0x1U) << 20U;
338} 338}
339static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) 339static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
340{ 340{
341 return 0x1 << 20; 341 return 0x1U << 20U;
342} 342}
343static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) 343static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
344{ 344{
345 return (r >> 20) & 0x1; 345 return (r >> 20U) & 0x1U;
346} 346}
347static inline u32 pwr_falcon_imemc_r(u32 i) 347static inline u32 pwr_falcon_imemc_r(u32 i)
348{ 348{
349 return 0x0010a180 + i*16; 349 return 0x0010a180U + i*16U;
350} 350}
351static inline u32 pwr_falcon_imemc_offs_f(u32 v) 351static inline u32 pwr_falcon_imemc_offs_f(u32 v)
352{ 352{
353 return (v & 0x3f) << 2; 353 return (v & 0x3fU) << 2U;
354} 354}
355static inline u32 pwr_falcon_imemc_blk_f(u32 v) 355static inline u32 pwr_falcon_imemc_blk_f(u32 v)
356{ 356{
357 return (v & 0xff) << 8; 357 return (v & 0xffU) << 8U;
358} 358}
359static inline u32 pwr_falcon_imemc_aincw_f(u32 v) 359static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
360{ 360{
361 return (v & 0x1) << 24; 361 return (v & 0x1U) << 24U;
362} 362}
363static inline u32 pwr_falcon_imemd_r(u32 i) 363static inline u32 pwr_falcon_imemd_r(u32 i)
364{ 364{
365 return 0x0010a184 + i*16; 365 return 0x0010a184U + i*16U;
366} 366}
367static inline u32 pwr_falcon_imemt_r(u32 i) 367static inline u32 pwr_falcon_imemt_r(u32 i)
368{ 368{
369 return 0x0010a188 + i*16; 369 return 0x0010a188U + i*16U;
370} 370}
371static inline u32 pwr_falcon_sctl_r(void) 371static inline u32 pwr_falcon_sctl_r(void)
372{ 372{
373 return 0x0010a240; 373 return 0x0010a240U;
374} 374}
375static inline u32 pwr_falcon_mmu_phys_sec_r(void) 375static inline u32 pwr_falcon_mmu_phys_sec_r(void)
376{ 376{
377 return 0x00100ce4; 377 return 0x00100ce4U;
378} 378}
379static inline u32 pwr_falcon_bootvec_r(void) 379static inline u32 pwr_falcon_bootvec_r(void)
380{ 380{
381 return 0x0010a104; 381 return 0x0010a104U;
382} 382}
383static inline u32 pwr_falcon_bootvec_vec_f(u32 v) 383static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
384{ 384{
385 return (v & 0xffffffff) << 0; 385 return (v & 0xffffffffU) << 0U;
386} 386}
387static inline u32 pwr_falcon_dmactl_r(void) 387static inline u32 pwr_falcon_dmactl_r(void)
388{ 388{
389 return 0x0010a10c; 389 return 0x0010a10cU;
390} 390}
391static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) 391static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
392{ 392{
393 return 0x1 << 1; 393 return 0x1U << 1U;
394} 394}
395static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) 395static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
396{ 396{
397 return 0x1 << 2; 397 return 0x1U << 2U;
398} 398}
399static inline u32 pwr_falcon_hwcfg_r(void) 399static inline u32 pwr_falcon_hwcfg_r(void)
400{ 400{
401 return 0x0010a108; 401 return 0x0010a108U;
402} 402}
403static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) 403static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
404{ 404{
405 return (r >> 0) & 0x1ff; 405 return (r >> 0U) & 0x1ffU;
406} 406}
407static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) 407static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
408{ 408{
409 return (r >> 9) & 0x1ff; 409 return (r >> 9U) & 0x1ffU;
410} 410}
411static inline u32 pwr_falcon_dmatrfbase_r(void) 411static inline u32 pwr_falcon_dmatrfbase_r(void)
412{ 412{
413 return 0x0010a110; 413 return 0x0010a110U;
414} 414}
415static inline u32 pwr_falcon_dmatrfmoffs_r(void) 415static inline u32 pwr_falcon_dmatrfmoffs_r(void)
416{ 416{
417 return 0x0010a114; 417 return 0x0010a114U;
418} 418}
419static inline u32 pwr_falcon_dmatrfcmd_r(void) 419static inline u32 pwr_falcon_dmatrfcmd_r(void)
420{ 420{
421 return 0x0010a118; 421 return 0x0010a118U;
422} 422}
423static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) 423static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
424{ 424{
425 return (v & 0x1) << 4; 425 return (v & 0x1U) << 4U;
426} 426}
427static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) 427static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
428{ 428{
429 return (v & 0x1) << 5; 429 return (v & 0x1U) << 5U;
430} 430}
431static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) 431static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
432{ 432{
433 return (v & 0x7) << 8; 433 return (v & 0x7U) << 8U;
434} 434}
435static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) 435static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
436{ 436{
437 return (v & 0x7) << 12; 437 return (v & 0x7U) << 12U;
438} 438}
439static inline u32 pwr_falcon_dmatrffboffs_r(void) 439static inline u32 pwr_falcon_dmatrffboffs_r(void)
440{ 440{
441 return 0x0010a11c; 441 return 0x0010a11cU;
442} 442}
443static inline u32 pwr_falcon_exterraddr_r(void) 443static inline u32 pwr_falcon_exterraddr_r(void)
444{ 444{
445 return 0x0010a168; 445 return 0x0010a168U;
446} 446}
447static inline u32 pwr_falcon_exterrstat_r(void) 447static inline u32 pwr_falcon_exterrstat_r(void)
448{ 448{
449 return 0x0010a16c; 449 return 0x0010a16cU;
450} 450}
451static inline u32 pwr_falcon_exterrstat_valid_m(void) 451static inline u32 pwr_falcon_exterrstat_valid_m(void)
452{ 452{
453 return 0x1 << 31; 453 return 0x1U << 31U;
454} 454}
455static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) 455static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
456{ 456{
457 return (r >> 31) & 0x1; 457 return (r >> 31U) & 0x1U;
458} 458}
459static inline u32 pwr_falcon_exterrstat_valid_true_v(void) 459static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
460{ 460{
461 return 0x00000001; 461 return 0x00000001U;
462} 462}
463static inline u32 pwr_pmu_falcon_icd_cmd_r(void) 463static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
464{ 464{
465 return 0x0010a200; 465 return 0x0010a200U;
466} 466}
467static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) 467static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
468{ 468{
469 return 4; 469 return 4U;
470} 470}
471static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) 471static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
472{ 472{
473 return (v & 0xf) << 0; 473 return (v & 0xfU) << 0U;
474} 474}
475static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) 475static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
476{ 476{
477 return 0xf << 0; 477 return 0xfU << 0U;
478} 478}
479static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) 479static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
480{ 480{
481 return (r >> 0) & 0xf; 481 return (r >> 0U) & 0xfU;
482} 482}
483static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) 483static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
484{ 484{
485 return 0x8; 485 return 0x8U;
486} 486}
487static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) 487static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
488{ 488{
489 return 0xe; 489 return 0xeU;
490} 490}
491static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) 491static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
492{ 492{
493 return (v & 0x1f) << 8; 493 return (v & 0x1fU) << 8U;
494} 494}
495static inline u32 pwr_pmu_falcon_icd_rdata_r(void) 495static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
496{ 496{
497 return 0x0010a20c; 497 return 0x0010a20cU;
498} 498}
499static inline u32 pwr_falcon_dmemc_r(u32 i) 499static inline u32 pwr_falcon_dmemc_r(u32 i)
500{ 500{
501 return 0x0010a1c0 + i*8; 501 return 0x0010a1c0U + i*8U;
502} 502}
503static inline u32 pwr_falcon_dmemc_offs_f(u32 v) 503static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
504{ 504{
505 return (v & 0x3f) << 2; 505 return (v & 0x3fU) << 2U;
506} 506}
507static inline u32 pwr_falcon_dmemc_offs_m(void) 507static inline u32 pwr_falcon_dmemc_offs_m(void)
508{ 508{
509 return 0x3f << 2; 509 return 0x3fU << 2U;
510} 510}
511static inline u32 pwr_falcon_dmemc_blk_f(u32 v) 511static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
512{ 512{
513 return (v & 0xff) << 8; 513 return (v & 0xffU) << 8U;
514} 514}
515static inline u32 pwr_falcon_dmemc_blk_m(void) 515static inline u32 pwr_falcon_dmemc_blk_m(void)
516{ 516{
517 return 0xff << 8; 517 return 0xffU << 8U;
518} 518}
519static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) 519static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
520{ 520{
521 return (v & 0x1) << 24; 521 return (v & 0x1U) << 24U;
522} 522}
523static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) 523static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
524{ 524{
525 return (v & 0x1) << 25; 525 return (v & 0x1U) << 25U;
526} 526}
527static inline u32 pwr_falcon_dmemd_r(u32 i) 527static inline u32 pwr_falcon_dmemd_r(u32 i)
528{ 528{
529 return 0x0010a1c4 + i*8; 529 return 0x0010a1c4U + i*8U;
530} 530}
531static inline u32 pwr_pmu_new_instblk_r(void) 531static inline u32 pwr_pmu_new_instblk_r(void)
532{ 532{
533 return 0x0010a480; 533 return 0x0010a480U;
534} 534}
535static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) 535static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
536{ 536{
537 return (v & 0xfffffff) << 0; 537 return (v & 0xfffffffU) << 0U;
538} 538}
539static inline u32 pwr_pmu_new_instblk_target_fb_f(void) 539static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
540{ 540{
541 return 0x0; 541 return 0x0U;
542} 542}
543static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) 543static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
544{ 544{
545 return 0x20000000; 545 return 0x20000000U;
546} 546}
547static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) 547static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
548{ 548{
549 return 0x30000000; 549 return 0x30000000U;
550} 550}
551static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) 551static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
552{ 552{
553 return (v & 0x1) << 30; 553 return (v & 0x1U) << 30U;
554} 554}
555static inline u32 pwr_pmu_mutex_id_r(void) 555static inline u32 pwr_pmu_mutex_id_r(void)
556{ 556{
557 return 0x0010a488; 557 return 0x0010a488U;
558} 558}
559static inline u32 pwr_pmu_mutex_id_value_v(u32 r) 559static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
560{ 560{
561 return (r >> 0) & 0xff; 561 return (r >> 0U) & 0xffU;
562} 562}
563static inline u32 pwr_pmu_mutex_id_value_init_v(void) 563static inline u32 pwr_pmu_mutex_id_value_init_v(void)
564{ 564{
565 return 0x00000000; 565 return 0x00000000U;
566} 566}
567static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) 567static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
568{ 568{
569 return 0x000000ff; 569 return 0x000000ffU;
570} 570}
571static inline u32 pwr_pmu_mutex_id_release_r(void) 571static inline u32 pwr_pmu_mutex_id_release_r(void)
572{ 572{
573 return 0x0010a48c; 573 return 0x0010a48cU;
574} 574}
575static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) 575static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
576{ 576{
577 return (v & 0xff) << 0; 577 return (v & 0xffU) << 0U;
578} 578}
579static inline u32 pwr_pmu_mutex_id_release_value_m(void) 579static inline u32 pwr_pmu_mutex_id_release_value_m(void)
580{ 580{
581 return 0xff << 0; 581 return 0xffU << 0U;
582} 582}
583static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) 583static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
584{ 584{
585 return 0x00000000; 585 return 0x00000000U;
586} 586}
587static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) 587static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
588{ 588{
589 return 0x0; 589 return 0x0U;
590} 590}
591static inline u32 pwr_pmu_mutex_r(u32 i) 591static inline u32 pwr_pmu_mutex_r(u32 i)
592{ 592{
593 return 0x0010a580 + i*4; 593 return 0x0010a580U + i*4U;
594} 594}
595static inline u32 pwr_pmu_mutex__size_1_v(void) 595static inline u32 pwr_pmu_mutex__size_1_v(void)
596{ 596{
597 return 0x00000010; 597 return 0x00000010U;
598} 598}
599static inline u32 pwr_pmu_mutex_value_f(u32 v) 599static inline u32 pwr_pmu_mutex_value_f(u32 v)
600{ 600{
601 return (v & 0xff) << 0; 601 return (v & 0xffU) << 0U;
602} 602}
603static inline u32 pwr_pmu_mutex_value_v(u32 r) 603static inline u32 pwr_pmu_mutex_value_v(u32 r)
604{ 604{
605 return (r >> 0) & 0xff; 605 return (r >> 0U) & 0xffU;
606} 606}
607static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) 607static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
608{ 608{
609 return 0x0; 609 return 0x0U;
610} 610}
611static inline u32 pwr_pmu_queue_head_r(u32 i) 611static inline u32 pwr_pmu_queue_head_r(u32 i)
612{ 612{
613 return 0x0010a4a0 + i*4; 613 return 0x0010a4a0U + i*4U;
614} 614}
615static inline u32 pwr_pmu_queue_head__size_1_v(void) 615static inline u32 pwr_pmu_queue_head__size_1_v(void)
616{ 616{
617 return 0x00000004; 617 return 0x00000004U;
618} 618}
619static inline u32 pwr_pmu_queue_head_address_f(u32 v) 619static inline u32 pwr_pmu_queue_head_address_f(u32 v)
620{ 620{
621 return (v & 0xffffffff) << 0; 621 return (v & 0xffffffffU) << 0U;
622} 622}
623static inline u32 pwr_pmu_queue_head_address_v(u32 r) 623static inline u32 pwr_pmu_queue_head_address_v(u32 r)
624{ 624{
625 return (r >> 0) & 0xffffffff; 625 return (r >> 0U) & 0xffffffffU;
626} 626}
627static inline u32 pwr_pmu_queue_tail_r(u32 i) 627static inline u32 pwr_pmu_queue_tail_r(u32 i)
628{ 628{
629 return 0x0010a4b0 + i*4; 629 return 0x0010a4b0U + i*4U;
630} 630}
631static inline u32 pwr_pmu_queue_tail__size_1_v(void) 631static inline u32 pwr_pmu_queue_tail__size_1_v(void)
632{ 632{
633 return 0x00000004; 633 return 0x00000004U;
634} 634}
635static inline u32 pwr_pmu_queue_tail_address_f(u32 v) 635static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
636{ 636{
637 return (v & 0xffffffff) << 0; 637 return (v & 0xffffffffU) << 0U;
638} 638}
639static inline u32 pwr_pmu_queue_tail_address_v(u32 r) 639static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
640{ 640{
641 return (r >> 0) & 0xffffffff; 641 return (r >> 0U) & 0xffffffffU;
642} 642}
643static inline u32 pwr_pmu_msgq_head_r(void) 643static inline u32 pwr_pmu_msgq_head_r(void)
644{ 644{
645 return 0x0010a4c8; 645 return 0x0010a4c8U;
646} 646}
647static inline u32 pwr_pmu_msgq_head_val_f(u32 v) 647static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
648{ 648{
649 return (v & 0xffffffff) << 0; 649 return (v & 0xffffffffU) << 0U;
650} 650}
651static inline u32 pwr_pmu_msgq_head_val_v(u32 r) 651static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
652{ 652{
653 return (r >> 0) & 0xffffffff; 653 return (r >> 0U) & 0xffffffffU;
654} 654}
655static inline u32 pwr_pmu_msgq_tail_r(void) 655static inline u32 pwr_pmu_msgq_tail_r(void)
656{ 656{
657 return 0x0010a4cc; 657 return 0x0010a4ccU;
658} 658}
659static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) 659static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
660{ 660{
661 return (v & 0xffffffff) << 0; 661 return (v & 0xffffffffU) << 0U;
662} 662}
663static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) 663static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
664{ 664{
665 return (r >> 0) & 0xffffffff; 665 return (r >> 0U) & 0xffffffffU;
666} 666}
667static inline u32 pwr_pmu_idle_mask_r(u32 i) 667static inline u32 pwr_pmu_idle_mask_r(u32 i)
668{ 668{
669 return 0x0010a504 + i*16; 669 return 0x0010a504U + i*16U;
670} 670}
671static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) 671static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
672{ 672{
673 return 0x1; 673 return 0x1U;
674} 674}
675static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) 675static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
676{ 676{
677 return 0x200000; 677 return 0x200000U;
678} 678}
679static inline u32 pwr_pmu_idle_count_r(u32 i) 679static inline u32 pwr_pmu_idle_count_r(u32 i)
680{ 680{
681 return 0x0010a508 + i*16; 681 return 0x0010a508U + i*16U;
682} 682}
683static inline u32 pwr_pmu_idle_count_value_f(u32 v) 683static inline u32 pwr_pmu_idle_count_value_f(u32 v)
684{ 684{
685 return (v & 0x7fffffff) << 0; 685 return (v & 0x7fffffffU) << 0U;
686} 686}
687static inline u32 pwr_pmu_idle_count_value_v(u32 r) 687static inline u32 pwr_pmu_idle_count_value_v(u32 r)
688{ 688{
689 return (r >> 0) & 0x7fffffff; 689 return (r >> 0U) & 0x7fffffffU;
690} 690}
691static inline u32 pwr_pmu_idle_count_reset_f(u32 v) 691static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
692{ 692{
693 return (v & 0x1) << 31; 693 return (v & 0x1U) << 31U;
694} 694}
695static inline u32 pwr_pmu_idle_ctrl_r(u32 i) 695static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
696{ 696{
697 return 0x0010a50c + i*16; 697 return 0x0010a50cU + i*16U;
698} 698}
699static inline u32 pwr_pmu_idle_ctrl_value_m(void) 699static inline u32 pwr_pmu_idle_ctrl_value_m(void)
700{ 700{
701 return 0x3 << 0; 701 return 0x3U << 0U;
702} 702}
703static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) 703static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
704{ 704{
705 return 0x2; 705 return 0x2U;
706} 706}
707static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) 707static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
708{ 708{
709 return 0x3; 709 return 0x3U;
710} 710}
711static inline u32 pwr_pmu_idle_ctrl_filter_m(void) 711static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
712{ 712{
713 return 0x1 << 2; 713 return 0x1U << 2U;
714} 714}
715static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) 715static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
716{ 716{
717 return 0x0; 717 return 0x0U;
718} 718}
719static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) 719static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
720{ 720{
721 return 0x0010a9f0 + i*8; 721 return 0x0010a9f0U + i*8U;
722} 722}
723static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) 723static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
724{ 724{
725 return 0x0010a9f4 + i*8; 725 return 0x0010a9f4U + i*8U;
726} 726}
727static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) 727static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
728{ 728{
729 return 0x0010aa30 + i*8; 729 return 0x0010aa30U + i*8U;
730} 730}
731static inline u32 pwr_pmu_debug_r(u32 i) 731static inline u32 pwr_pmu_debug_r(u32 i)
732{ 732{
733 return 0x0010a5c0 + i*4; 733 return 0x0010a5c0U + i*4U;
734} 734}
735static inline u32 pwr_pmu_debug__size_1_v(void) 735static inline u32 pwr_pmu_debug__size_1_v(void)
736{ 736{
737 return 0x00000004; 737 return 0x00000004U;
738} 738}
739static inline u32 pwr_pmu_mailbox_r(u32 i) 739static inline u32 pwr_pmu_mailbox_r(u32 i)
740{ 740{
741 return 0x0010a450 + i*4; 741 return 0x0010a450U + i*4U;
742} 742}
743static inline u32 pwr_pmu_mailbox__size_1_v(void) 743static inline u32 pwr_pmu_mailbox__size_1_v(void)
744{ 744{
745 return 0x0000000c; 745 return 0x0000000cU;
746} 746}
747static inline u32 pwr_pmu_bar0_addr_r(void) 747static inline u32 pwr_pmu_bar0_addr_r(void)
748{ 748{
749 return 0x0010a7a0; 749 return 0x0010a7a0U;
750} 750}
751static inline u32 pwr_pmu_bar0_data_r(void) 751static inline u32 pwr_pmu_bar0_data_r(void)
752{ 752{
753 return 0x0010a7a4; 753 return 0x0010a7a4U;
754} 754}
755static inline u32 pwr_pmu_bar0_ctl_r(void) 755static inline u32 pwr_pmu_bar0_ctl_r(void)
756{ 756{
757 return 0x0010a7ac; 757 return 0x0010a7acU;
758} 758}
759static inline u32 pwr_pmu_bar0_timeout_r(void) 759static inline u32 pwr_pmu_bar0_timeout_r(void)
760{ 760{
761 return 0x0010a7a8; 761 return 0x0010a7a8U;
762} 762}
763static inline u32 pwr_pmu_bar0_fecs_error_r(void) 763static inline u32 pwr_pmu_bar0_fecs_error_r(void)
764{ 764{
765 return 0x0010a988; 765 return 0x0010a988U;
766} 766}
767static inline u32 pwr_pmu_bar0_error_status_r(void) 767static inline u32 pwr_pmu_bar0_error_status_r(void)
768{ 768{
769 return 0x0010a7b0; 769 return 0x0010a7b0U;
770} 770}
771static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) 771static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
772{ 772{
773 return 0x0010a6c0 + i*4; 773 return 0x0010a6c0U + i*4U;
774} 774}
775static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) 775static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
776{ 776{
777 return 0x0010a6e8 + i*4; 777 return 0x0010a6e8U + i*4U;
778} 778}
779static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) 779static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
780{ 780{
781 return 0x0010a710 + i*4; 781 return 0x0010a710U + i*4U;
782} 782}
783static inline u32 pwr_pmu_pg_intren_r(u32 i) 783static inline u32 pwr_pmu_pg_intren_r(u32 i)
784{ 784{
785 return 0x0010a760 + i*4; 785 return 0x0010a760U + i*4U;
786} 786}
787static inline u32 pwr_fbif_transcfg_r(u32 i) 787static inline u32 pwr_fbif_transcfg_r(u32 i)
788{ 788{
789 return 0x0010ae00 + i*4; 789 return 0x0010ae00U + i*4U;
790} 790}
791static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) 791static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
792{ 792{
793 return 0x0; 793 return 0x0U;
794} 794}
795static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) 795static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
796{ 796{
797 return 0x1; 797 return 0x1U;
798} 798}
799static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) 799static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
800{ 800{
801 return 0x2; 801 return 0x2U;
802} 802}
803static inline u32 pwr_fbif_transcfg_mem_type_s(void) 803static inline u32 pwr_fbif_transcfg_mem_type_s(void)
804{ 804{
805 return 1; 805 return 1U;
806} 806}
807static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) 807static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
808{ 808{
809 return (v & 0x1) << 2; 809 return (v & 0x1U) << 2U;
810} 810}
811static inline u32 pwr_fbif_transcfg_mem_type_m(void) 811static inline u32 pwr_fbif_transcfg_mem_type_m(void)
812{ 812{
813 return 0x1 << 2; 813 return 0x1U << 2U;
814} 814}
815static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) 815static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
816{ 816{
817 return (r >> 2) & 0x1; 817 return (r >> 2U) & 0x1U;
818} 818}
819static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) 819static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
820{ 820{
821 return 0x0; 821 return 0x0U;
822} 822}
823static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) 823static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
824{ 824{
825 return 0x4; 825 return 0x4U;
826} 826}
827#endif 827#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ram_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ram_gm20b.h
index 2729256f..2414abf0 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ram_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_ram_gm20b.h
@@ -58,402 +58,402 @@
58 58
59static inline u32 ram_in_ramfc_s(void) 59static inline u32 ram_in_ramfc_s(void)
60{ 60{
61 return 4096; 61 return 4096U;
62} 62}
63static inline u32 ram_in_ramfc_w(void) 63static inline u32 ram_in_ramfc_w(void)
64{ 64{
65 return 0; 65 return 0U;
66} 66}
67static inline u32 ram_in_page_dir_base_target_f(u32 v) 67static inline u32 ram_in_page_dir_base_target_f(u32 v)
68{ 68{
69 return (v & 0x3) << 0; 69 return (v & 0x3U) << 0U;
70} 70}
71static inline u32 ram_in_page_dir_base_target_w(void) 71static inline u32 ram_in_page_dir_base_target_w(void)
72{ 72{
73 return 128; 73 return 128U;
74} 74}
75static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) 75static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
76{ 76{
77 return 0x0; 77 return 0x0U;
78} 78}
79static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) 79static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
80{ 80{
81 return 0x2; 81 return 0x2U;
82} 82}
83static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) 83static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
84{ 84{
85 return 0x3; 85 return 0x3U;
86} 86}
87static inline u32 ram_in_page_dir_base_vol_w(void) 87static inline u32 ram_in_page_dir_base_vol_w(void)
88{ 88{
89 return 128; 89 return 128U;
90} 90}
91static inline u32 ram_in_page_dir_base_vol_true_f(void) 91static inline u32 ram_in_page_dir_base_vol_true_f(void)
92{ 92{
93 return 0x4; 93 return 0x4U;
94} 94}
95static inline u32 ram_in_big_page_size_f(u32 v) 95static inline u32 ram_in_big_page_size_f(u32 v)
96{ 96{
97 return (v & 0x1) << 11; 97 return (v & 0x1U) << 11U;
98} 98}
99static inline u32 ram_in_big_page_size_m(void) 99static inline u32 ram_in_big_page_size_m(void)
100{ 100{
101 return 0x1 << 11; 101 return 0x1U << 11U;
102} 102}
103static inline u32 ram_in_big_page_size_w(void) 103static inline u32 ram_in_big_page_size_w(void)
104{ 104{
105 return 128; 105 return 128U;
106} 106}
107static inline u32 ram_in_big_page_size_128kb_f(void) 107static inline u32 ram_in_big_page_size_128kb_f(void)
108{ 108{
109 return 0x0; 109 return 0x0U;
110} 110}
111static inline u32 ram_in_big_page_size_64kb_f(void) 111static inline u32 ram_in_big_page_size_64kb_f(void)
112{ 112{
113 return 0x800; 113 return 0x800U;
114} 114}
115static inline u32 ram_in_page_dir_base_lo_f(u32 v) 115static inline u32 ram_in_page_dir_base_lo_f(u32 v)
116{ 116{
117 return (v & 0xfffff) << 12; 117 return (v & 0xfffffU) << 12U;
118} 118}
119static inline u32 ram_in_page_dir_base_lo_w(void) 119static inline u32 ram_in_page_dir_base_lo_w(void)
120{ 120{
121 return 128; 121 return 128U;
122} 122}
123static inline u32 ram_in_page_dir_base_hi_f(u32 v) 123static inline u32 ram_in_page_dir_base_hi_f(u32 v)
124{ 124{
125 return (v & 0xff) << 0; 125 return (v & 0xffU) << 0U;
126} 126}
127static inline u32 ram_in_page_dir_base_hi_w(void) 127static inline u32 ram_in_page_dir_base_hi_w(void)
128{ 128{
129 return 129; 129 return 129U;
130} 130}
131static inline u32 ram_in_adr_limit_lo_f(u32 v) 131static inline u32 ram_in_adr_limit_lo_f(u32 v)
132{ 132{
133 return (v & 0xfffff) << 12; 133 return (v & 0xfffffU) << 12U;
134} 134}
135static inline u32 ram_in_adr_limit_lo_w(void) 135static inline u32 ram_in_adr_limit_lo_w(void)
136{ 136{
137 return 130; 137 return 130U;
138} 138}
139static inline u32 ram_in_adr_limit_hi_f(u32 v) 139static inline u32 ram_in_adr_limit_hi_f(u32 v)
140{ 140{
141 return (v & 0xff) << 0; 141 return (v & 0xffU) << 0U;
142} 142}
143static inline u32 ram_in_adr_limit_hi_w(void) 143static inline u32 ram_in_adr_limit_hi_w(void)
144{ 144{
145 return 131; 145 return 131U;
146} 146}
147static inline u32 ram_in_engine_cs_w(void) 147static inline u32 ram_in_engine_cs_w(void)
148{ 148{
149 return 132; 149 return 132U;
150} 150}
151static inline u32 ram_in_engine_cs_wfi_v(void) 151static inline u32 ram_in_engine_cs_wfi_v(void)
152{ 152{
153 return 0x00000000; 153 return 0x00000000U;
154} 154}
155static inline u32 ram_in_engine_cs_wfi_f(void) 155static inline u32 ram_in_engine_cs_wfi_f(void)
156{ 156{
157 return 0x0; 157 return 0x0U;
158} 158}
159static inline u32 ram_in_engine_cs_fg_v(void) 159static inline u32 ram_in_engine_cs_fg_v(void)
160{ 160{
161 return 0x00000001; 161 return 0x00000001U;
162} 162}
163static inline u32 ram_in_engine_cs_fg_f(void) 163static inline u32 ram_in_engine_cs_fg_f(void)
164{ 164{
165 return 0x8; 165 return 0x8U;
166} 166}
167static inline u32 ram_in_gr_cs_w(void) 167static inline u32 ram_in_gr_cs_w(void)
168{ 168{
169 return 132; 169 return 132U;
170} 170}
171static inline u32 ram_in_gr_cs_wfi_f(void) 171static inline u32 ram_in_gr_cs_wfi_f(void)
172{ 172{
173 return 0x0; 173 return 0x0U;
174} 174}
175static inline u32 ram_in_gr_wfi_target_w(void) 175static inline u32 ram_in_gr_wfi_target_w(void)
176{ 176{
177 return 132; 177 return 132U;
178} 178}
179static inline u32 ram_in_gr_wfi_mode_w(void) 179static inline u32 ram_in_gr_wfi_mode_w(void)
180{ 180{
181 return 132; 181 return 132U;
182} 182}
183static inline u32 ram_in_gr_wfi_mode_physical_v(void) 183static inline u32 ram_in_gr_wfi_mode_physical_v(void)
184{ 184{
185 return 0x00000000; 185 return 0x00000000U;
186} 186}
187static inline u32 ram_in_gr_wfi_mode_physical_f(void) 187static inline u32 ram_in_gr_wfi_mode_physical_f(void)
188{ 188{
189 return 0x0; 189 return 0x0U;
190} 190}
191static inline u32 ram_in_gr_wfi_mode_virtual_v(void) 191static inline u32 ram_in_gr_wfi_mode_virtual_v(void)
192{ 192{
193 return 0x00000001; 193 return 0x00000001U;
194} 194}
195static inline u32 ram_in_gr_wfi_mode_virtual_f(void) 195static inline u32 ram_in_gr_wfi_mode_virtual_f(void)
196{ 196{
197 return 0x4; 197 return 0x4U;
198} 198}
199static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v) 199static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v)
200{ 200{
201 return (v & 0xfffff) << 12; 201 return (v & 0xfffffU) << 12U;
202} 202}
203static inline u32 ram_in_gr_wfi_ptr_lo_w(void) 203static inline u32 ram_in_gr_wfi_ptr_lo_w(void)
204{ 204{
205 return 132; 205 return 132U;
206} 206}
207static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v) 207static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v)
208{ 208{
209 return (v & 0xff) << 0; 209 return (v & 0xffU) << 0U;
210} 210}
211static inline u32 ram_in_gr_wfi_ptr_hi_w(void) 211static inline u32 ram_in_gr_wfi_ptr_hi_w(void)
212{ 212{
213 return 133; 213 return 133U;
214} 214}
215static inline u32 ram_in_base_shift_v(void) 215static inline u32 ram_in_base_shift_v(void)
216{ 216{
217 return 0x0000000c; 217 return 0x0000000cU;
218} 218}
219static inline u32 ram_in_alloc_size_v(void) 219static inline u32 ram_in_alloc_size_v(void)
220{ 220{
221 return 0x00001000; 221 return 0x00001000U;
222} 222}
223static inline u32 ram_fc_size_val_v(void) 223static inline u32 ram_fc_size_val_v(void)
224{ 224{
225 return 0x00000200; 225 return 0x00000200U;
226} 226}
227static inline u32 ram_fc_gp_put_w(void) 227static inline u32 ram_fc_gp_put_w(void)
228{ 228{
229 return 0; 229 return 0U;
230} 230}
231static inline u32 ram_fc_userd_w(void) 231static inline u32 ram_fc_userd_w(void)
232{ 232{
233 return 2; 233 return 2U;
234} 234}
235static inline u32 ram_fc_userd_hi_w(void) 235static inline u32 ram_fc_userd_hi_w(void)
236{ 236{
237 return 3; 237 return 3U;
238} 238}
239static inline u32 ram_fc_signature_w(void) 239static inline u32 ram_fc_signature_w(void)
240{ 240{
241 return 4; 241 return 4U;
242} 242}
243static inline u32 ram_fc_gp_get_w(void) 243static inline u32 ram_fc_gp_get_w(void)
244{ 244{
245 return 5; 245 return 5U;
246} 246}
247static inline u32 ram_fc_pb_get_w(void) 247static inline u32 ram_fc_pb_get_w(void)
248{ 248{
249 return 6; 249 return 6U;
250} 250}
251static inline u32 ram_fc_pb_get_hi_w(void) 251static inline u32 ram_fc_pb_get_hi_w(void)
252{ 252{
253 return 7; 253 return 7U;
254} 254}
255static inline u32 ram_fc_pb_top_level_get_w(void) 255static inline u32 ram_fc_pb_top_level_get_w(void)
256{ 256{
257 return 8; 257 return 8U;
258} 258}
259static inline u32 ram_fc_pb_top_level_get_hi_w(void) 259static inline u32 ram_fc_pb_top_level_get_hi_w(void)
260{ 260{
261 return 9; 261 return 9U;
262} 262}
263static inline u32 ram_fc_acquire_w(void) 263static inline u32 ram_fc_acquire_w(void)
264{ 264{
265 return 12; 265 return 12U;
266} 266}
267static inline u32 ram_fc_semaphorea_w(void) 267static inline u32 ram_fc_semaphorea_w(void)
268{ 268{
269 return 14; 269 return 14U;
270} 270}
271static inline u32 ram_fc_semaphoreb_w(void) 271static inline u32 ram_fc_semaphoreb_w(void)
272{ 272{
273 return 15; 273 return 15U;
274} 274}
275static inline u32 ram_fc_semaphorec_w(void) 275static inline u32 ram_fc_semaphorec_w(void)
276{ 276{
277 return 16; 277 return 16U;
278} 278}
279static inline u32 ram_fc_semaphored_w(void) 279static inline u32 ram_fc_semaphored_w(void)
280{ 280{
281 return 17; 281 return 17U;
282} 282}
283static inline u32 ram_fc_gp_base_w(void) 283static inline u32 ram_fc_gp_base_w(void)
284{ 284{
285 return 18; 285 return 18U;
286} 286}
287static inline u32 ram_fc_gp_base_hi_w(void) 287static inline u32 ram_fc_gp_base_hi_w(void)
288{ 288{
289 return 19; 289 return 19U;
290} 290}
291static inline u32 ram_fc_gp_fetch_w(void) 291static inline u32 ram_fc_gp_fetch_w(void)
292{ 292{
293 return 20; 293 return 20U;
294} 294}
295static inline u32 ram_fc_pb_fetch_w(void) 295static inline u32 ram_fc_pb_fetch_w(void)
296{ 296{
297 return 21; 297 return 21U;
298} 298}
299static inline u32 ram_fc_pb_fetch_hi_w(void) 299static inline u32 ram_fc_pb_fetch_hi_w(void)
300{ 300{
301 return 22; 301 return 22U;
302} 302}
303static inline u32 ram_fc_pb_put_w(void) 303static inline u32 ram_fc_pb_put_w(void)
304{ 304{
305 return 23; 305 return 23U;
306} 306}
307static inline u32 ram_fc_pb_put_hi_w(void) 307static inline u32 ram_fc_pb_put_hi_w(void)
308{ 308{
309 return 24; 309 return 24U;
310} 310}
311static inline u32 ram_fc_pb_header_w(void) 311static inline u32 ram_fc_pb_header_w(void)
312{ 312{
313 return 33; 313 return 33U;
314} 314}
315static inline u32 ram_fc_pb_count_w(void) 315static inline u32 ram_fc_pb_count_w(void)
316{ 316{
317 return 34; 317 return 34U;
318} 318}
319static inline u32 ram_fc_subdevice_w(void) 319static inline u32 ram_fc_subdevice_w(void)
320{ 320{
321 return 37; 321 return 37U;
322} 322}
323static inline u32 ram_fc_formats_w(void) 323static inline u32 ram_fc_formats_w(void)
324{ 324{
325 return 39; 325 return 39U;
326} 326}
327static inline u32 ram_fc_syncpointa_w(void) 327static inline u32 ram_fc_syncpointa_w(void)
328{ 328{
329 return 41; 329 return 41U;
330} 330}
331static inline u32 ram_fc_syncpointb_w(void) 331static inline u32 ram_fc_syncpointb_w(void)
332{ 332{
333 return 42; 333 return 42U;
334} 334}
335static inline u32 ram_fc_target_w(void) 335static inline u32 ram_fc_target_w(void)
336{ 336{
337 return 43; 337 return 43U;
338} 338}
339static inline u32 ram_fc_hce_ctrl_w(void) 339static inline u32 ram_fc_hce_ctrl_w(void)
340{ 340{
341 return 57; 341 return 57U;
342} 342}
343static inline u32 ram_fc_chid_w(void) 343static inline u32 ram_fc_chid_w(void)
344{ 344{
345 return 58; 345 return 58U;
346} 346}
347static inline u32 ram_fc_chid_id_f(u32 v) 347static inline u32 ram_fc_chid_id_f(u32 v)
348{ 348{
349 return (v & 0xfff) << 0; 349 return (v & 0xfffU) << 0U;
350} 350}
351static inline u32 ram_fc_chid_id_w(void) 351static inline u32 ram_fc_chid_id_w(void)
352{ 352{
353 return 0; 353 return 0U;
354} 354}
355static inline u32 ram_fc_runlist_timeslice_w(void) 355static inline u32 ram_fc_runlist_timeslice_w(void)
356{ 356{
357 return 62; 357 return 62U;
358} 358}
359static inline u32 ram_userd_base_shift_v(void) 359static inline u32 ram_userd_base_shift_v(void)
360{ 360{
361 return 0x00000009; 361 return 0x00000009U;
362} 362}
363static inline u32 ram_userd_chan_size_v(void) 363static inline u32 ram_userd_chan_size_v(void)
364{ 364{
365 return 0x00000200; 365 return 0x00000200U;
366} 366}
367static inline u32 ram_userd_put_w(void) 367static inline u32 ram_userd_put_w(void)
368{ 368{
369 return 16; 369 return 16U;
370} 370}
371static inline u32 ram_userd_get_w(void) 371static inline u32 ram_userd_get_w(void)
372{ 372{
373 return 17; 373 return 17U;
374} 374}
375static inline u32 ram_userd_ref_w(void) 375static inline u32 ram_userd_ref_w(void)
376{ 376{
377 return 18; 377 return 18U;
378} 378}
379static inline u32 ram_userd_put_hi_w(void) 379static inline u32 ram_userd_put_hi_w(void)
380{ 380{
381 return 19; 381 return 19U;
382} 382}
383static inline u32 ram_userd_ref_threshold_w(void) 383static inline u32 ram_userd_ref_threshold_w(void)
384{ 384{
385 return 20; 385 return 20U;
386} 386}
387static inline u32 ram_userd_top_level_get_w(void) 387static inline u32 ram_userd_top_level_get_w(void)
388{ 388{
389 return 22; 389 return 22U;
390} 390}
391static inline u32 ram_userd_top_level_get_hi_w(void) 391static inline u32 ram_userd_top_level_get_hi_w(void)
392{ 392{
393 return 23; 393 return 23U;
394} 394}
395static inline u32 ram_userd_get_hi_w(void) 395static inline u32 ram_userd_get_hi_w(void)
396{ 396{
397 return 24; 397 return 24U;
398} 398}
399static inline u32 ram_userd_gp_get_w(void) 399static inline u32 ram_userd_gp_get_w(void)
400{ 400{
401 return 34; 401 return 34U;
402} 402}
403static inline u32 ram_userd_gp_put_w(void) 403static inline u32 ram_userd_gp_put_w(void)
404{ 404{
405 return 35; 405 return 35U;
406} 406}
407static inline u32 ram_userd_gp_top_level_get_w(void) 407static inline u32 ram_userd_gp_top_level_get_w(void)
408{ 408{
409 return 22; 409 return 22U;
410} 410}
411static inline u32 ram_userd_gp_top_level_get_hi_w(void) 411static inline u32 ram_userd_gp_top_level_get_hi_w(void)
412{ 412{
413 return 23; 413 return 23U;
414} 414}
415static inline u32 ram_rl_entry_size_v(void) 415static inline u32 ram_rl_entry_size_v(void)
416{ 416{
417 return 0x00000008; 417 return 0x00000008U;
418} 418}
419static inline u32 ram_rl_entry_chid_f(u32 v) 419static inline u32 ram_rl_entry_chid_f(u32 v)
420{ 420{
421 return (v & 0xfff) << 0; 421 return (v & 0xfffU) << 0U;
422} 422}
423static inline u32 ram_rl_entry_id_f(u32 v) 423static inline u32 ram_rl_entry_id_f(u32 v)
424{ 424{
425 return (v & 0xfff) << 0; 425 return (v & 0xfffU) << 0U;
426} 426}
427static inline u32 ram_rl_entry_type_f(u32 v) 427static inline u32 ram_rl_entry_type_f(u32 v)
428{ 428{
429 return (v & 0x1) << 13; 429 return (v & 0x1U) << 13U;
430} 430}
431static inline u32 ram_rl_entry_type_chid_f(void) 431static inline u32 ram_rl_entry_type_chid_f(void)
432{ 432{
433 return 0x0; 433 return 0x0U;
434} 434}
435static inline u32 ram_rl_entry_type_tsg_f(void) 435static inline u32 ram_rl_entry_type_tsg_f(void)
436{ 436{
437 return 0x2000; 437 return 0x2000U;
438} 438}
439static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) 439static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
440{ 440{
441 return (v & 0xf) << 14; 441 return (v & 0xfU) << 14U;
442} 442}
443static inline u32 ram_rl_entry_timeslice_scale_3_f(void) 443static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
444{ 444{
445 return 0xc000; 445 return 0xc000U;
446} 446}
447static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) 447static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
448{ 448{
449 return (v & 0xff) << 18; 449 return (v & 0xffU) << 18U;
450} 450}
451static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) 451static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
452{ 452{
453 return 0x2000000; 453 return 0x2000000U;
454} 454}
455static inline u32 ram_rl_entry_tsg_length_f(u32 v) 455static inline u32 ram_rl_entry_tsg_length_f(u32 v)
456{ 456{
457 return (v & 0x3f) << 26; 457 return (v & 0x3fU) << 26U;
458} 458}
459#endif 459#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_therm_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_therm_gm20b.h
index eeea52e4..fc1cd517 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_therm_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_therm_gm20b.h
@@ -58,298 +58,298 @@
58 58
59static inline u32 therm_use_a_r(void) 59static inline u32 therm_use_a_r(void)
60{ 60{
61 return 0x00020798; 61 return 0x00020798U;
62} 62}
63static inline u32 therm_use_a_ext_therm_0_enable_f(void) 63static inline u32 therm_use_a_ext_therm_0_enable_f(void)
64{ 64{
65 return 0x1; 65 return 0x1U;
66} 66}
67static inline u32 therm_use_a_ext_therm_1_enable_f(void) 67static inline u32 therm_use_a_ext_therm_1_enable_f(void)
68{ 68{
69 return 0x2; 69 return 0x2U;
70} 70}
71static inline u32 therm_use_a_ext_therm_2_enable_f(void) 71static inline u32 therm_use_a_ext_therm_2_enable_f(void)
72{ 72{
73 return 0x4; 73 return 0x4U;
74} 74}
75static inline u32 therm_evt_ext_therm_0_r(void) 75static inline u32 therm_evt_ext_therm_0_r(void)
76{ 76{
77 return 0x00020700; 77 return 0x00020700U;
78} 78}
79static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) 79static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v)
80{ 80{
81 return (v & 0x3f) << 8; 81 return (v & 0x3fU) << 8U;
82} 82}
83static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) 83static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void)
84{ 84{
85 return 0x00000000; 85 return 0x00000000U;
86} 86}
87static inline u32 therm_evt_ext_therm_1_r(void) 87static inline u32 therm_evt_ext_therm_1_r(void)
88{ 88{
89 return 0x00020704; 89 return 0x00020704U;
90} 90}
91static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) 91static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v)
92{ 92{
93 return (v & 0x3f) << 8; 93 return (v & 0x3fU) << 8U;
94} 94}
95static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) 95static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void)
96{ 96{
97 return 0x00000000; 97 return 0x00000000U;
98} 98}
99static inline u32 therm_evt_ext_therm_2_r(void) 99static inline u32 therm_evt_ext_therm_2_r(void)
100{ 100{
101 return 0x00020708; 101 return 0x00020708U;
102} 102}
103static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) 103static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v)
104{ 104{
105 return (v & 0x3f) << 8; 105 return (v & 0x3fU) << 8U;
106} 106}
107static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) 107static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void)
108{ 108{
109 return 0x00000000; 109 return 0x00000000U;
110} 110}
111static inline u32 therm_weight_1_r(void) 111static inline u32 therm_weight_1_r(void)
112{ 112{
113 return 0x00020024; 113 return 0x00020024U;
114} 114}
115static inline u32 therm_config1_r(void) 115static inline u32 therm_config1_r(void)
116{ 116{
117 return 0x00020050; 117 return 0x00020050U;
118} 118}
119static inline u32 therm_config2_r(void) 119static inline u32 therm_config2_r(void)
120{ 120{
121 return 0x00020130; 121 return 0x00020130U;
122} 122}
123static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) 123static inline u32 therm_config2_slowdown_factor_extended_f(u32 v)
124{ 124{
125 return (v & 0x1) << 24; 125 return (v & 0x1U) << 24U;
126} 126}
127static inline u32 therm_config2_grad_enable_f(u32 v) 127static inline u32 therm_config2_grad_enable_f(u32 v)
128{ 128{
129 return (v & 0x1) << 31; 129 return (v & 0x1U) << 31U;
130} 130}
131static inline u32 therm_gate_ctrl_r(u32 i) 131static inline u32 therm_gate_ctrl_r(u32 i)
132{ 132{
133 return 0x00020200 + i*4; 133 return 0x00020200U + i*4U;
134} 134}
135static inline u32 therm_gate_ctrl_eng_clk_m(void) 135static inline u32 therm_gate_ctrl_eng_clk_m(void)
136{ 136{
137 return 0x3 << 0; 137 return 0x3U << 0U;
138} 138}
139static inline u32 therm_gate_ctrl_eng_clk_run_f(void) 139static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
140{ 140{
141 return 0x0; 141 return 0x0U;
142} 142}
143static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) 143static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
144{ 144{
145 return 0x1; 145 return 0x1U;
146} 146}
147static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) 147static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
148{ 148{
149 return 0x2; 149 return 0x2U;
150} 150}
151static inline u32 therm_gate_ctrl_blk_clk_m(void) 151static inline u32 therm_gate_ctrl_blk_clk_m(void)
152{ 152{
153 return 0x3 << 2; 153 return 0x3U << 2U;
154} 154}
155static inline u32 therm_gate_ctrl_blk_clk_run_f(void) 155static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
156{ 156{
157 return 0x0; 157 return 0x0U;
158} 158}
159static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) 159static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
160{ 160{
161 return 0x4; 161 return 0x4U;
162} 162}
163static inline u32 therm_gate_ctrl_eng_pwr_m(void) 163static inline u32 therm_gate_ctrl_eng_pwr_m(void)
164{ 164{
165 return 0x3 << 4; 165 return 0x3U << 4U;
166} 166}
167static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void) 167static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void)
168{ 168{
169 return 0x10; 169 return 0x10U;
170} 170}
171static inline u32 therm_gate_ctrl_eng_pwr_off_v(void) 171static inline u32 therm_gate_ctrl_eng_pwr_off_v(void)
172{ 172{
173 return 0x00000002; 173 return 0x00000002U;
174} 174}
175static inline u32 therm_gate_ctrl_eng_pwr_off_f(void) 175static inline u32 therm_gate_ctrl_eng_pwr_off_f(void)
176{ 176{
177 return 0x20; 177 return 0x20U;
178} 178}
179static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) 179static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
180{ 180{
181 return (v & 0x1f) << 8; 181 return (v & 0x1fU) << 8U;
182} 182}
183static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) 183static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
184{ 184{
185 return 0x1f << 8; 185 return 0x1fU << 8U;
186} 186}
187static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) 187static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
188{ 188{
189 return (v & 0x7) << 13; 189 return (v & 0x7U) << 13U;
190} 190}
191static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) 191static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
192{ 192{
193 return 0x7 << 13; 193 return 0x7U << 13U;
194} 194}
195static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) 195static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
196{ 196{
197 return (v & 0xf) << 16; 197 return (v & 0xfU) << 16U;
198} 198}
199static inline u32 therm_gate_ctrl_eng_delay_before_m(void) 199static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
200{ 200{
201 return 0xf << 16; 201 return 0xfU << 16U;
202} 202}
203static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) 203static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
204{ 204{
205 return (v & 0xf) << 20; 205 return (v & 0xfU) << 20U;
206} 206}
207static inline u32 therm_gate_ctrl_eng_delay_after_m(void) 207static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
208{ 208{
209 return 0xf << 20; 209 return 0xfU << 20U;
210} 210}
211static inline u32 therm_fecs_idle_filter_r(void) 211static inline u32 therm_fecs_idle_filter_r(void)
212{ 212{
213 return 0x00020288; 213 return 0x00020288U;
214} 214}
215static inline u32 therm_fecs_idle_filter_value_m(void) 215static inline u32 therm_fecs_idle_filter_value_m(void)
216{ 216{
217 return 0xffffffff << 0; 217 return 0xffffffffU << 0U;
218} 218}
219static inline u32 therm_hubmmu_idle_filter_r(void) 219static inline u32 therm_hubmmu_idle_filter_r(void)
220{ 220{
221 return 0x0002028c; 221 return 0x0002028cU;
222} 222}
223static inline u32 therm_hubmmu_idle_filter_value_m(void) 223static inline u32 therm_hubmmu_idle_filter_value_m(void)
224{ 224{
225 return 0xffffffff << 0; 225 return 0xffffffffU << 0U;
226} 226}
227static inline u32 therm_clk_slowdown_r(u32 i) 227static inline u32 therm_clk_slowdown_r(u32 i)
228{ 228{
229 return 0x00020160 + i*4; 229 return 0x00020160U + i*4U;
230} 230}
231static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) 231static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
232{ 232{
233 return (v & 0x3f) << 16; 233 return (v & 0x3fU) << 16U;
234} 234}
235static inline u32 therm_clk_slowdown_idle_factor_m(void) 235static inline u32 therm_clk_slowdown_idle_factor_m(void)
236{ 236{
237 return 0x3f << 16; 237 return 0x3fU << 16U;
238} 238}
239static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) 239static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
240{ 240{
241 return (r >> 16) & 0x3f; 241 return (r >> 16U) & 0x3fU;
242} 242}
243static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) 243static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void)
244{ 244{
245 return 0x0; 245 return 0x0U;
246} 246}
247static inline u32 therm_grad_stepping_table_r(u32 i) 247static inline u32 therm_grad_stepping_table_r(u32 i)
248{ 248{
249 return 0x000202c8 + i*4; 249 return 0x000202c8U + i*4U;
250} 250}
251static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) 251static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
252{ 252{
253 return (v & 0x3f) << 0; 253 return (v & 0x3fU) << 0U;
254} 254}
255static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) 255static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
256{ 256{
257 return 0x3f << 0; 257 return 0x3fU << 0U;
258} 258}
259static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) 259static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
260{ 260{
261 return 0x1; 261 return 0x1U;
262} 262}
263static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) 263static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void)
264{ 264{
265 return 0x2; 265 return 0x2U;
266} 266}
267static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) 267static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void)
268{ 268{
269 return 0x6; 269 return 0x6U;
270} 270}
271static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) 271static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void)
272{ 272{
273 return 0xe; 273 return 0xeU;
274} 274}
275static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) 275static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
276{ 276{
277 return (v & 0x3f) << 6; 277 return (v & 0x3fU) << 6U;
278} 278}
279static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) 279static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
280{ 280{
281 return 0x3f << 6; 281 return 0x3fU << 6U;
282} 282}
283static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) 283static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
284{ 284{
285 return (v & 0x3f) << 12; 285 return (v & 0x3fU) << 12U;
286} 286}
287static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) 287static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
288{ 288{
289 return 0x3f << 12; 289 return 0x3fU << 12U;
290} 290}
291static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) 291static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
292{ 292{
293 return (v & 0x3f) << 18; 293 return (v & 0x3fU) << 18U;
294} 294}
295static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) 295static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
296{ 296{
297 return 0x3f << 18; 297 return 0x3fU << 18U;
298} 298}
299static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) 299static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
300{ 300{
301 return (v & 0x3f) << 24; 301 return (v & 0x3fU) << 24U;
302} 302}
303static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) 303static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
304{ 304{
305 return 0x3f << 24; 305 return 0x3fU << 24U;
306} 306}
307static inline u32 therm_grad_stepping0_r(void) 307static inline u32 therm_grad_stepping0_r(void)
308{ 308{
309 return 0x000202c0; 309 return 0x000202c0U;
310} 310}
311static inline u32 therm_grad_stepping0_feature_s(void) 311static inline u32 therm_grad_stepping0_feature_s(void)
312{ 312{
313 return 1; 313 return 1U;
314} 314}
315static inline u32 therm_grad_stepping0_feature_f(u32 v) 315static inline u32 therm_grad_stepping0_feature_f(u32 v)
316{ 316{
317 return (v & 0x1) << 0; 317 return (v & 0x1U) << 0U;
318} 318}
319static inline u32 therm_grad_stepping0_feature_m(void) 319static inline u32 therm_grad_stepping0_feature_m(void)
320{ 320{
321 return 0x1 << 0; 321 return 0x1U << 0U;
322} 322}
323static inline u32 therm_grad_stepping0_feature_v(u32 r) 323static inline u32 therm_grad_stepping0_feature_v(u32 r)
324{ 324{
325 return (r >> 0) & 0x1; 325 return (r >> 0U) & 0x1U;
326} 326}
327static inline u32 therm_grad_stepping0_feature_enable_f(void) 327static inline u32 therm_grad_stepping0_feature_enable_f(void)
328{ 328{
329 return 0x1; 329 return 0x1U;
330} 330}
331static inline u32 therm_grad_stepping1_r(void) 331static inline u32 therm_grad_stepping1_r(void)
332{ 332{
333 return 0x000202c4; 333 return 0x000202c4U;
334} 334}
335static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) 335static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v)
336{ 336{
337 return (v & 0x1ffff) << 0; 337 return (v & 0x1ffffU) << 0U;
338} 338}
339static inline u32 therm_clk_timing_r(u32 i) 339static inline u32 therm_clk_timing_r(u32 i)
340{ 340{
341 return 0x000203c0 + i*4; 341 return 0x000203c0U + i*4U;
342} 342}
343static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) 343static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
344{ 344{
345 return (v & 0x1) << 16; 345 return (v & 0x1U) << 16U;
346} 346}
347static inline u32 therm_clk_timing_grad_slowdown_m(void) 347static inline u32 therm_clk_timing_grad_slowdown_m(void)
348{ 348{
349 return 0x1 << 16; 349 return 0x1U << 16U;
350} 350}
351static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) 351static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
352{ 352{
353 return 0x10000; 353 return 0x10000U;
354} 354}
355#endif 355#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h
index bca72f6f..38548645 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_timer_gm20b.h
@@ -58,58 +58,58 @@
58 58
59static inline u32 timer_pri_timeout_r(void) 59static inline u32 timer_pri_timeout_r(void)
60{ 60{
61 return 0x00009080; 61 return 0x00009080U;
62} 62}
63static inline u32 timer_pri_timeout_period_f(u32 v) 63static inline u32 timer_pri_timeout_period_f(u32 v)
64{ 64{
65 return (v & 0xffffff) << 0; 65 return (v & 0xffffffU) << 0U;
66} 66}
67static inline u32 timer_pri_timeout_period_m(void) 67static inline u32 timer_pri_timeout_period_m(void)
68{ 68{
69 return 0xffffff << 0; 69 return 0xffffffU << 0U;
70} 70}
71static inline u32 timer_pri_timeout_period_v(u32 r) 71static inline u32 timer_pri_timeout_period_v(u32 r)
72{ 72{
73 return (r >> 0) & 0xffffff; 73 return (r >> 0U) & 0xffffffU;
74} 74}
75static inline u32 timer_pri_timeout_en_f(u32 v) 75static inline u32 timer_pri_timeout_en_f(u32 v)
76{ 76{
77 return (v & 0x1) << 31; 77 return (v & 0x1U) << 31U;
78} 78}
79static inline u32 timer_pri_timeout_en_m(void) 79static inline u32 timer_pri_timeout_en_m(void)
80{ 80{
81 return 0x1 << 31; 81 return 0x1U << 31U;
82} 82}
83static inline u32 timer_pri_timeout_en_v(u32 r) 83static inline u32 timer_pri_timeout_en_v(u32 r)
84{ 84{
85 return (r >> 31) & 0x1; 85 return (r >> 31U) & 0x1U;
86} 86}
87static inline u32 timer_pri_timeout_en_en_enabled_f(void) 87static inline u32 timer_pri_timeout_en_en_enabled_f(void)
88{ 88{
89 return 0x80000000; 89 return 0x80000000U;
90} 90}
91static inline u32 timer_pri_timeout_en_en_disabled_f(void) 91static inline u32 timer_pri_timeout_en_en_disabled_f(void)
92{ 92{
93 return 0x0; 93 return 0x0U;
94} 94}
95static inline u32 timer_pri_timeout_save_0_r(void) 95static inline u32 timer_pri_timeout_save_0_r(void)
96{ 96{
97 return 0x00009084; 97 return 0x00009084U;
98} 98}
99static inline u32 timer_pri_timeout_save_1_r(void) 99static inline u32 timer_pri_timeout_save_1_r(void)
100{ 100{
101 return 0x00009088; 101 return 0x00009088U;
102} 102}
103static inline u32 timer_pri_timeout_fecs_errcode_r(void) 103static inline u32 timer_pri_timeout_fecs_errcode_r(void)
104{ 104{
105 return 0x0000908c; 105 return 0x0000908cU;
106} 106}
107static inline u32 timer_time_0_r(void) 107static inline u32 timer_time_0_r(void)
108{ 108{
109 return 0x00009400; 109 return 0x00009400U;
110} 110}
111static inline u32 timer_time_1_r(void) 111static inline u32 timer_time_1_r(void)
112{ 112{
113 return 0x00009410; 113 return 0x00009410U;
114} 114}
115#endif 115#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_top_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_top_gm20b.h
index 283006fb..6d48839e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_top_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_top_gm20b.h
@@ -58,178 +58,178 @@
58 58
59static inline u32 top_num_gpcs_r(void) 59static inline u32 top_num_gpcs_r(void)
60{ 60{
61 return 0x00022430; 61 return 0x00022430U;
62} 62}
63static inline u32 top_num_gpcs_value_v(u32 r) 63static inline u32 top_num_gpcs_value_v(u32 r)
64{ 64{
65 return (r >> 0) & 0x1f; 65 return (r >> 0U) & 0x1fU;
66} 66}
67static inline u32 top_tpc_per_gpc_r(void) 67static inline u32 top_tpc_per_gpc_r(void)
68{ 68{
69 return 0x00022434; 69 return 0x00022434U;
70} 70}
71static inline u32 top_tpc_per_gpc_value_v(u32 r) 71static inline u32 top_tpc_per_gpc_value_v(u32 r)
72{ 72{
73 return (r >> 0) & 0x1f; 73 return (r >> 0U) & 0x1fU;
74} 74}
75static inline u32 top_num_fbps_r(void) 75static inline u32 top_num_fbps_r(void)
76{ 76{
77 return 0x00022438; 77 return 0x00022438U;
78} 78}
79static inline u32 top_num_fbps_value_v(u32 r) 79static inline u32 top_num_fbps_value_v(u32 r)
80{ 80{
81 return (r >> 0) & 0x1f; 81 return (r >> 0U) & 0x1fU;
82} 82}
83static inline u32 top_ltc_per_fbp_r(void) 83static inline u32 top_ltc_per_fbp_r(void)
84{ 84{
85 return 0x00022450; 85 return 0x00022450U;
86} 86}
87static inline u32 top_ltc_per_fbp_value_v(u32 r) 87static inline u32 top_ltc_per_fbp_value_v(u32 r)
88{ 88{
89 return (r >> 0) & 0x1f; 89 return (r >> 0U) & 0x1fU;
90} 90}
91static inline u32 top_slices_per_ltc_r(void) 91static inline u32 top_slices_per_ltc_r(void)
92{ 92{
93 return 0x0002245c; 93 return 0x0002245cU;
94} 94}
95static inline u32 top_slices_per_ltc_value_v(u32 r) 95static inline u32 top_slices_per_ltc_value_v(u32 r)
96{ 96{
97 return (r >> 0) & 0x1f; 97 return (r >> 0U) & 0x1fU;
98} 98}
99static inline u32 top_num_ltcs_r(void) 99static inline u32 top_num_ltcs_r(void)
100{ 100{
101 return 0x00022454; 101 return 0x00022454U;
102} 102}
103static inline u32 top_device_info_r(u32 i) 103static inline u32 top_device_info_r(u32 i)
104{ 104{
105 return 0x00022700 + i*4; 105 return 0x00022700U + i*4U;
106} 106}
107static inline u32 top_device_info__size_1_v(void) 107static inline u32 top_device_info__size_1_v(void)
108{ 108{
109 return 0x00000040; 109 return 0x00000040U;
110} 110}
111static inline u32 top_device_info_chain_v(u32 r) 111static inline u32 top_device_info_chain_v(u32 r)
112{ 112{
113 return (r >> 31) & 0x1; 113 return (r >> 31U) & 0x1U;
114} 114}
115static inline u32 top_device_info_chain_enable_v(void) 115static inline u32 top_device_info_chain_enable_v(void)
116{ 116{
117 return 0x00000001; 117 return 0x00000001U;
118} 118}
119static inline u32 top_device_info_engine_enum_v(u32 r) 119static inline u32 top_device_info_engine_enum_v(u32 r)
120{ 120{
121 return (r >> 26) & 0xf; 121 return (r >> 26U) & 0xfU;
122} 122}
123static inline u32 top_device_info_runlist_enum_v(u32 r) 123static inline u32 top_device_info_runlist_enum_v(u32 r)
124{ 124{
125 return (r >> 21) & 0xf; 125 return (r >> 21U) & 0xfU;
126} 126}
127static inline u32 top_device_info_intr_enum_v(u32 r) 127static inline u32 top_device_info_intr_enum_v(u32 r)
128{ 128{
129 return (r >> 15) & 0x1f; 129 return (r >> 15U) & 0x1fU;
130} 130}
131static inline u32 top_device_info_reset_enum_v(u32 r) 131static inline u32 top_device_info_reset_enum_v(u32 r)
132{ 132{
133 return (r >> 9) & 0x1f; 133 return (r >> 9U) & 0x1fU;
134} 134}
135static inline u32 top_device_info_type_enum_v(u32 r) 135static inline u32 top_device_info_type_enum_v(u32 r)
136{ 136{
137 return (r >> 2) & 0x1fffffff; 137 return (r >> 2U) & 0x1fffffffU;
138} 138}
139static inline u32 top_device_info_type_enum_graphics_v(void) 139static inline u32 top_device_info_type_enum_graphics_v(void)
140{ 140{
141 return 0x00000000; 141 return 0x00000000U;
142} 142}
143static inline u32 top_device_info_type_enum_graphics_f(void) 143static inline u32 top_device_info_type_enum_graphics_f(void)
144{ 144{
145 return 0x0; 145 return 0x0U;
146} 146}
147static inline u32 top_device_info_type_enum_copy0_v(void) 147static inline u32 top_device_info_type_enum_copy0_v(void)
148{ 148{
149 return 0x00000001; 149 return 0x00000001U;
150} 150}
151static inline u32 top_device_info_type_enum_copy0_f(void) 151static inline u32 top_device_info_type_enum_copy0_f(void)
152{ 152{
153 return 0x4; 153 return 0x4U;
154} 154}
155static inline u32 top_device_info_type_enum_copy1_v(void) 155static inline u32 top_device_info_type_enum_copy1_v(void)
156{ 156{
157 return 0x00000002; 157 return 0x00000002U;
158} 158}
159static inline u32 top_device_info_type_enum_copy1_f(void) 159static inline u32 top_device_info_type_enum_copy1_f(void)
160{ 160{
161 return 0x8; 161 return 0x8U;
162} 162}
163static inline u32 top_device_info_type_enum_copy2_v(void) 163static inline u32 top_device_info_type_enum_copy2_v(void)
164{ 164{
165 return 0x00000003; 165 return 0x00000003U;
166} 166}
167static inline u32 top_device_info_type_enum_copy2_f(void) 167static inline u32 top_device_info_type_enum_copy2_f(void)
168{ 168{
169 return 0xc; 169 return 0xcU;
170} 170}
171static inline u32 top_device_info_engine_v(u32 r) 171static inline u32 top_device_info_engine_v(u32 r)
172{ 172{
173 return (r >> 5) & 0x1; 173 return (r >> 5U) & 0x1U;
174} 174}
175static inline u32 top_device_info_runlist_v(u32 r) 175static inline u32 top_device_info_runlist_v(u32 r)
176{ 176{
177 return (r >> 4) & 0x1; 177 return (r >> 4U) & 0x1U;
178} 178}
179static inline u32 top_device_info_intr_v(u32 r) 179static inline u32 top_device_info_intr_v(u32 r)
180{ 180{
181 return (r >> 3) & 0x1; 181 return (r >> 3U) & 0x1U;
182} 182}
183static inline u32 top_device_info_reset_v(u32 r) 183static inline u32 top_device_info_reset_v(u32 r)
184{ 184{
185 return (r >> 2) & 0x1; 185 return (r >> 2U) & 0x1U;
186} 186}
187static inline u32 top_device_info_entry_v(u32 r) 187static inline u32 top_device_info_entry_v(u32 r)
188{ 188{
189 return (r >> 0) & 0x3; 189 return (r >> 0U) & 0x3U;
190} 190}
191static inline u32 top_device_info_entry_not_valid_v(void) 191static inline u32 top_device_info_entry_not_valid_v(void)
192{ 192{
193 return 0x00000000; 193 return 0x00000000U;
194} 194}
195static inline u32 top_device_info_entry_enum_v(void) 195static inline u32 top_device_info_entry_enum_v(void)
196{ 196{
197 return 0x00000002; 197 return 0x00000002U;
198} 198}
199static inline u32 top_device_info_entry_engine_type_v(void) 199static inline u32 top_device_info_entry_engine_type_v(void)
200{ 200{
201 return 0x00000003; 201 return 0x00000003U;
202} 202}
203static inline u32 top_device_info_entry_data_v(void) 203static inline u32 top_device_info_entry_data_v(void)
204{ 204{
205 return 0x00000001; 205 return 0x00000001U;
206} 206}
207static inline u32 top_device_info_data_type_v(u32 r) 207static inline u32 top_device_info_data_type_v(u32 r)
208{ 208{
209 return (r >> 30) & 0x1; 209 return (r >> 30U) & 0x1U;
210} 210}
211static inline u32 top_device_info_data_type_enum2_v(void) 211static inline u32 top_device_info_data_type_enum2_v(void)
212{ 212{
213 return 0x00000000; 213 return 0x00000000U;
214} 214}
215static inline u32 top_device_info_data_pri_base_v(u32 r) 215static inline u32 top_device_info_data_pri_base_v(u32 r)
216{ 216{
217 return (r >> 12) & 0x7ff; 217 return (r >> 12U) & 0x7ffU;
218} 218}
219static inline u32 top_device_info_data_pri_base_align_v(void) 219static inline u32 top_device_info_data_pri_base_align_v(void)
220{ 220{
221 return 0x0000000c; 221 return 0x0000000cU;
222} 222}
223static inline u32 top_device_info_data_fault_id_enum_v(u32 r) 223static inline u32 top_device_info_data_fault_id_enum_v(u32 r)
224{ 224{
225 return (r >> 3) & 0x1f; 225 return (r >> 3U) & 0x1fU;
226} 226}
227static inline u32 top_device_info_data_fault_id_v(u32 r) 227static inline u32 top_device_info_data_fault_id_v(u32 r)
228{ 228{
229 return (r >> 2) & 0x1; 229 return (r >> 2U) & 0x1U;
230} 230}
231static inline u32 top_device_info_data_fault_id_valid_v(void) 231static inline u32 top_device_info_data_fault_id_valid_v(void)
232{ 232{
233 return 0x00000001; 233 return 0x00000001U;
234} 234}
235#endif 235#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_trim_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_trim_gm20b.h
index 96ac64a1..8f0a77a5 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_trim_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_trim_gm20b.h
@@ -58,446 +58,446 @@
58 58
59static inline u32 trim_sys_gpcpll_cfg_r(void) 59static inline u32 trim_sys_gpcpll_cfg_r(void)
60{ 60{
61 return 0x00137000; 61 return 0x00137000U;
62} 62}
63static inline u32 trim_sys_gpcpll_cfg_enable_m(void) 63static inline u32 trim_sys_gpcpll_cfg_enable_m(void)
64{ 64{
65 return 0x1 << 0; 65 return 0x1U << 0U;
66} 66}
67static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r) 67static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r)
68{ 68{
69 return (r >> 0) & 0x1; 69 return (r >> 0U) & 0x1U;
70} 70}
71static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void) 71static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void)
72{ 72{
73 return 0x0; 73 return 0x0U;
74} 74}
75static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void) 75static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void)
76{ 76{
77 return 0x1; 77 return 0x1U;
78} 78}
79static inline u32 trim_sys_gpcpll_cfg_iddq_m(void) 79static inline u32 trim_sys_gpcpll_cfg_iddq_m(void)
80{ 80{
81 return 0x1 << 1; 81 return 0x1U << 1U;
82} 82}
83static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r) 83static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r)
84{ 84{
85 return (r >> 1) & 0x1; 85 return (r >> 1U) & 0x1U;
86} 86}
87static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void) 87static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void)
88{ 88{
89 return 0x00000000; 89 return 0x00000000U;
90} 90}
91static inline u32 trim_sys_gpcpll_cfg_sync_mode_m(void) 91static inline u32 trim_sys_gpcpll_cfg_sync_mode_m(void)
92{ 92{
93 return 0x1 << 2; 93 return 0x1U << 2U;
94} 94}
95static inline u32 trim_sys_gpcpll_cfg_sync_mode_v(u32 r) 95static inline u32 trim_sys_gpcpll_cfg_sync_mode_v(u32 r)
96{ 96{
97 return (r >> 2) & 0x1; 97 return (r >> 2U) & 0x1U;
98} 98}
99static inline u32 trim_sys_gpcpll_cfg_sync_mode_enable_f(void) 99static inline u32 trim_sys_gpcpll_cfg_sync_mode_enable_f(void)
100{ 100{
101 return 0x4; 101 return 0x4U;
102} 102}
103static inline u32 trim_sys_gpcpll_cfg_sync_mode_disable_f(void) 103static inline u32 trim_sys_gpcpll_cfg_sync_mode_disable_f(void)
104{ 104{
105 return 0x0; 105 return 0x0U;
106} 106}
107static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void) 107static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void)
108{ 108{
109 return 0x1 << 4; 109 return 0x1U << 4U;
110} 110}
111static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void) 111static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void)
112{ 112{
113 return 0x0; 113 return 0x0U;
114} 114}
115static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void) 115static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void)
116{ 116{
117 return 0x10; 117 return 0x10U;
118} 118}
119static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r) 119static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r)
120{ 120{
121 return (r >> 17) & 0x1; 121 return (r >> 17U) & 0x1U;
122} 122}
123static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void) 123static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void)
124{ 124{
125 return 0x20000; 125 return 0x20000U;
126} 126}
127static inline u32 trim_sys_gpcpll_coeff_r(void) 127static inline u32 trim_sys_gpcpll_coeff_r(void)
128{ 128{
129 return 0x00137004; 129 return 0x00137004U;
130} 130}
131static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v) 131static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v)
132{ 132{
133 return (v & 0xff) << 0; 133 return (v & 0xffU) << 0U;
134} 134}
135static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void) 135static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void)
136{ 136{
137 return 0xff << 0; 137 return 0xffU << 0U;
138} 138}
139static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r) 139static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r)
140{ 140{
141 return (r >> 0) & 0xff; 141 return (r >> 0U) & 0xffU;
142} 142}
143static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v) 143static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v)
144{ 144{
145 return (v & 0xff) << 8; 145 return (v & 0xffU) << 8U;
146} 146}
147static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void) 147static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void)
148{ 148{
149 return 0xff << 8; 149 return 0xffU << 8U;
150} 150}
151static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r) 151static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r)
152{ 152{
153 return (r >> 8) & 0xff; 153 return (r >> 8U) & 0xffU;
154} 154}
155static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v) 155static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v)
156{ 156{
157 return (v & 0x3f) << 16; 157 return (v & 0x3fU) << 16U;
158} 158}
159static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void) 159static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void)
160{ 160{
161 return 0x3f << 16; 161 return 0x3fU << 16U;
162} 162}
163static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r) 163static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r)
164{ 164{
165 return (r >> 16) & 0x3f; 165 return (r >> 16U) & 0x3fU;
166} 166}
167static inline u32 trim_sys_sel_vco_r(void) 167static inline u32 trim_sys_sel_vco_r(void)
168{ 168{
169 return 0x00137100; 169 return 0x00137100U;
170} 170}
171static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void) 171static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void)
172{ 172{
173 return 0x1 << 0; 173 return 0x1U << 0U;
174} 174}
175static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void) 175static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void)
176{ 176{
177 return 0x00000000; 177 return 0x00000000U;
178} 178}
179static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void) 179static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void)
180{ 180{
181 return 0x0; 181 return 0x0U;
182} 182}
183static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void) 183static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void)
184{ 184{
185 return 0x0; 185 return 0x0U;
186} 186}
187static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void) 187static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void)
188{ 188{
189 return 0x1; 189 return 0x1U;
190} 190}
191static inline u32 trim_sys_gpc2clk_out_r(void) 191static inline u32 trim_sys_gpc2clk_out_r(void)
192{ 192{
193 return 0x00137250; 193 return 0x00137250U;
194} 194}
195static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void) 195static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void)
196{ 196{
197 return 6; 197 return 6U;
198} 198}
199static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v) 199static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v)
200{ 200{
201 return (v & 0x3f) << 0; 201 return (v & 0x3fU) << 0U;
202} 202}
203static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void) 203static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void)
204{ 204{
205 return 0x3f << 0; 205 return 0x3fU << 0U;
206} 206}
207static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r) 207static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r)
208{ 208{
209 return (r >> 0) & 0x3f; 209 return (r >> 0U) & 0x3fU;
210} 210}
211static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void) 211static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void)
212{ 212{
213 return 0x3c; 213 return 0x3cU;
214} 214}
215static inline u32 trim_sys_gpc2clk_out_vcodiv_s(void) 215static inline u32 trim_sys_gpc2clk_out_vcodiv_s(void)
216{ 216{
217 return 6; 217 return 6U;
218} 218}
219static inline u32 trim_sys_gpc2clk_out_vcodiv_f(u32 v) 219static inline u32 trim_sys_gpc2clk_out_vcodiv_f(u32 v)
220{ 220{
221 return (v & 0x3f) << 8; 221 return (v & 0x3fU) << 8U;
222} 222}
223static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void) 223static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void)
224{ 224{
225 return 0x3f << 8; 225 return 0x3fU << 8U;
226} 226}
227static inline u32 trim_sys_gpc2clk_out_vcodiv_v(u32 r) 227static inline u32 trim_sys_gpc2clk_out_vcodiv_v(u32 r)
228{ 228{
229 return (r >> 8) & 0x3f; 229 return (r >> 8U) & 0x3fU;
230} 230}
231static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void) 231static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void)
232{ 232{
233 return 0x0; 233 return 0x0U;
234} 234}
235static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void) 235static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void)
236{ 236{
237 return 0x1 << 31; 237 return 0x1U << 31U;
238} 238}
239static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void) 239static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void)
240{ 240{
241 return 0x80000000; 241 return 0x80000000U;
242} 242}
243static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i) 243static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i)
244{ 244{
245 return 0x00134124 + i*512; 245 return 0x00134124U + i*512U;
246} 246}
247static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) 247static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v)
248{ 248{
249 return (v & 0x3fff) << 0; 249 return (v & 0x3fffU) << 0U;
250} 250}
251static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) 251static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void)
252{ 252{
253 return 0x10000; 253 return 0x10000U;
254} 254}
255static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void) 255static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void)
256{ 256{
257 return 0x100000; 257 return 0x100000U;
258} 258}
259static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void) 259static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void)
260{ 260{
261 return 0x1000000; 261 return 0x1000000U;
262} 262}
263static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i) 263static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i)
264{ 264{
265 return 0x00134128 + i*512; 265 return 0x00134128U + i*512U;
266} 266}
267static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r) 267static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r)
268{ 268{
269 return (r >> 0) & 0xfffff; 269 return (r >> 0U) & 0xfffffU;
270} 270}
271static inline u32 trim_sys_gpcpll_cfg2_r(void) 271static inline u32 trim_sys_gpcpll_cfg2_r(void)
272{ 272{
273 return 0x0013700c; 273 return 0x0013700cU;
274} 274}
275static inline u32 trim_sys_gpcpll_cfg2_sdm_din_f(u32 v) 275static inline u32 trim_sys_gpcpll_cfg2_sdm_din_f(u32 v)
276{ 276{
277 return (v & 0xff) << 0; 277 return (v & 0xffU) << 0U;
278} 278}
279static inline u32 trim_sys_gpcpll_cfg2_sdm_din_m(void) 279static inline u32 trim_sys_gpcpll_cfg2_sdm_din_m(void)
280{ 280{
281 return 0xff << 0; 281 return 0xffU << 0U;
282} 282}
283static inline u32 trim_sys_gpcpll_cfg2_sdm_din_v(u32 r) 283static inline u32 trim_sys_gpcpll_cfg2_sdm_din_v(u32 r)
284{ 284{
285 return (r >> 0) & 0xff; 285 return (r >> 0U) & 0xffU;
286} 286}
287static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_f(u32 v) 287static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_f(u32 v)
288{ 288{
289 return (v & 0xff) << 8; 289 return (v & 0xffU) << 8U;
290} 290}
291static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_m(void) 291static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_m(void)
292{ 292{
293 return 0xff << 8; 293 return 0xffU << 8U;
294} 294}
295static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_v(u32 r) 295static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_v(u32 r)
296{ 296{
297 return (r >> 8) & 0xff; 297 return (r >> 8U) & 0xffU;
298} 298}
299static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v) 299static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v)
300{ 300{
301 return (v & 0xff) << 24; 301 return (v & 0xffU) << 24U;
302} 302}
303static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void) 303static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void)
304{ 304{
305 return 0xff << 24; 305 return 0xffU << 24U;
306} 306}
307static inline u32 trim_sys_gpcpll_cfg3_r(void) 307static inline u32 trim_sys_gpcpll_cfg3_r(void)
308{ 308{
309 return 0x00137018; 309 return 0x00137018U;
310} 310}
311static inline u32 trim_sys_gpcpll_cfg3_vco_ctrl_f(u32 v) 311static inline u32 trim_sys_gpcpll_cfg3_vco_ctrl_f(u32 v)
312{ 312{
313 return (v & 0x1ff) << 0; 313 return (v & 0x1ffU) << 0U;
314} 314}
315static inline u32 trim_sys_gpcpll_cfg3_vco_ctrl_m(void) 315static inline u32 trim_sys_gpcpll_cfg3_vco_ctrl_m(void)
316{ 316{
317 return 0x1ff << 0; 317 return 0x1ffU << 0U;
318} 318}
319static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v) 319static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v)
320{ 320{
321 return (v & 0xff) << 16; 321 return (v & 0xffU) << 16U;
322} 322}
323static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void) 323static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void)
324{ 324{
325 return 0xff << 16; 325 return 0xffU << 16U;
326} 326}
327static inline u32 trim_sys_gpcpll_cfg3_dfs_testout_v(u32 r) 327static inline u32 trim_sys_gpcpll_cfg3_dfs_testout_v(u32 r)
328{ 328{
329 return (r >> 24) & 0x7f; 329 return (r >> 24U) & 0x7fU;
330} 330}
331static inline u32 trim_sys_gpcpll_dvfs0_r(void) 331static inline u32 trim_sys_gpcpll_dvfs0_r(void)
332{ 332{
333 return 0x00137010; 333 return 0x00137010U;
334} 334}
335static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_f(u32 v) 335static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_f(u32 v)
336{ 336{
337 return (v & 0x7f) << 0; 337 return (v & 0x7fU) << 0U;
338} 338}
339static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_m(void) 339static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_m(void)
340{ 340{
341 return 0x7f << 0; 341 return 0x7fU << 0U;
342} 342}
343static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_v(u32 r) 343static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_v(u32 r)
344{ 344{
345 return (r >> 0) & 0x7f; 345 return (r >> 0U) & 0x7fU;
346} 346}
347static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_f(u32 v) 347static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_f(u32 v)
348{ 348{
349 return (v & 0x7f) << 8; 349 return (v & 0x7fU) << 8U;
350} 350}
351static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_m(void) 351static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_m(void)
352{ 352{
353 return 0x7f << 8; 353 return 0x7fU << 8U;
354} 354}
355static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_v(u32 r) 355static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_v(u32 r)
356{ 356{
357 return (r >> 8) & 0x7f; 357 return (r >> 8U) & 0x7fU;
358} 358}
359static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_f(u32 v) 359static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_f(u32 v)
360{ 360{
361 return (v & 0x3f) << 16; 361 return (v & 0x3fU) << 16U;
362} 362}
363static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_m(void) 363static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_m(void)
364{ 364{
365 return 0x3f << 16; 365 return 0x3fU << 16U;
366} 366}
367static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_v(u32 r) 367static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_v(u32 r)
368{ 368{
369 return (r >> 16) & 0x3f; 369 return (r >> 16U) & 0x3fU;
370} 370}
371static inline u32 trim_sys_gpcpll_dvfs0_mode_m(void) 371static inline u32 trim_sys_gpcpll_dvfs0_mode_m(void)
372{ 372{
373 return 0x1 << 28; 373 return 0x1U << 28U;
374} 374}
375static inline u32 trim_sys_gpcpll_dvfs0_mode_dvfspll_f(void) 375static inline u32 trim_sys_gpcpll_dvfs0_mode_dvfspll_f(void)
376{ 376{
377 return 0x0; 377 return 0x0U;
378} 378}
379static inline u32 trim_sys_gpcpll_dvfs1_r(void) 379static inline u32 trim_sys_gpcpll_dvfs1_r(void)
380{ 380{
381 return 0x00137014; 381 return 0x00137014U;
382} 382}
383static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_f(u32 v) 383static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_f(u32 v)
384{ 384{
385 return (v & 0x7f) << 0; 385 return (v & 0x7fU) << 0U;
386} 386}
387static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_m(void) 387static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_m(void)
388{ 388{
389 return 0x7f << 0; 389 return 0x7fU << 0U;
390} 390}
391static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_v(u32 r) 391static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_v(u32 r)
392{ 392{
393 return (r >> 0) & 0x7f; 393 return (r >> 0U) & 0x7fU;
394} 394}
395static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_strb_m(void) 395static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_strb_m(void)
396{ 396{
397 return 0x1 << 7; 397 return 0x1U << 7U;
398} 398}
399static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_f(u32 v) 399static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_f(u32 v)
400{ 400{
401 return (v & 0x7f) << 8; 401 return (v & 0x7fU) << 8U;
402} 402}
403static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_m(void) 403static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_m(void)
404{ 404{
405 return 0x7f << 8; 405 return 0x7fU << 8U;
406} 406}
407static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_v(u32 r) 407static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_v(u32 r)
408{ 408{
409 return (r >> 8) & 0x7f; 409 return (r >> 8U) & 0x7fU;
410} 410}
411static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_sel_m(void) 411static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_sel_m(void)
412{ 412{
413 return 0x1 << 15; 413 return 0x1U << 15U;
414} 414}
415static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_f(u32 v) 415static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_f(u32 v)
416{ 416{
417 return (v & 0xfff) << 16; 417 return (v & 0xfffU) << 16U;
418} 418}
419static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_m(void) 419static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_m(void)
420{ 420{
421 return 0xfff << 16; 421 return 0xfffU << 16U;
422} 422}
423static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_v(u32 r) 423static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_v(u32 r)
424{ 424{
425 return (r >> 16) & 0xfff; 425 return (r >> 16U) & 0xfffU;
426} 426}
427static inline u32 trim_sys_gpcpll_dvfs1_en_sdm_m(void) 427static inline u32 trim_sys_gpcpll_dvfs1_en_sdm_m(void)
428{ 428{
429 return 0x1 << 28; 429 return 0x1U << 28U;
430} 430}
431static inline u32 trim_sys_gpcpll_dvfs1_en_dfs_m(void) 431static inline u32 trim_sys_gpcpll_dvfs1_en_dfs_m(void)
432{ 432{
433 return 0x1 << 29; 433 return 0x1U << 29U;
434} 434}
435static inline u32 trim_sys_gpcpll_dvfs1_en_dfs_cal_m(void) 435static inline u32 trim_sys_gpcpll_dvfs1_en_dfs_cal_m(void)
436{ 436{
437 return 0x1 << 30; 437 return 0x1U << 30U;
438} 438}
439static inline u32 trim_sys_gpcpll_dvfs1_dfs_cal_done_v(u32 r) 439static inline u32 trim_sys_gpcpll_dvfs1_dfs_cal_done_v(u32 r)
440{ 440{
441 return (r >> 31) & 0x1; 441 return (r >> 31U) & 0x1U;
442} 442}
443static inline u32 trim_sys_gpcpll_dvfs2_r(void) 443static inline u32 trim_sys_gpcpll_dvfs2_r(void)
444{ 444{
445 return 0x00137020; 445 return 0x00137020U;
446} 446}
447static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void) 447static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void)
448{ 448{
449 return 0x0013701c; 449 return 0x0013701cU;
450} 450}
451static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void) 451static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void)
452{ 452{
453 return 0x1 << 22; 453 return 0x1U << 22U;
454} 454}
455static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void) 455static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void)
456{ 456{
457 return 0x400000; 457 return 0x400000U;
458} 458}
459static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void) 459static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void)
460{ 460{
461 return 0x0; 461 return 0x0U;
462} 462}
463static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void) 463static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void)
464{ 464{
465 return 0x1 << 31; 465 return 0x1U << 31U;
466} 466}
467static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void) 467static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void)
468{ 468{
469 return 0x80000000; 469 return 0x80000000U;
470} 470}
471static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void) 471static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void)
472{ 472{
473 return 0x0; 473 return 0x0U;
474} 474}
475static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void) 475static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void)
476{ 476{
477 return 0x001328a0; 477 return 0x001328a0U;
478} 478}
479static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r) 479static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r)
480{ 480{
481 return (r >> 24) & 0x1; 481 return (r >> 24U) & 0x1U;
482} 482}
483static inline u32 trim_gpc_bcast_gpcpll_dvfs2_r(void) 483static inline u32 trim_gpc_bcast_gpcpll_dvfs2_r(void)
484{ 484{
485 return 0x00132820; 485 return 0x00132820U;
486} 486}
487static inline u32 trim_sys_bypassctrl_r(void) 487static inline u32 trim_sys_bypassctrl_r(void)
488{ 488{
489 return 0x00137340; 489 return 0x00137340U;
490} 490}
491static inline u32 trim_sys_bypassctrl_gpcpll_m(void) 491static inline u32 trim_sys_bypassctrl_gpcpll_m(void)
492{ 492{
493 return 0x1 << 0; 493 return 0x1U << 0U;
494} 494}
495static inline u32 trim_sys_bypassctrl_gpcpll_bypassclk_f(void) 495static inline u32 trim_sys_bypassctrl_gpcpll_bypassclk_f(void)
496{ 496{
497 return 0x1; 497 return 0x1U;
498} 498}
499static inline u32 trim_sys_bypassctrl_gpcpll_vco_f(void) 499static inline u32 trim_sys_bypassctrl_gpcpll_vco_f(void)
500{ 500{
501 return 0x0; 501 return 0x0U;
502} 502}
503#endif 503#endif