13 files changed, 60 insertions, 6 deletions

diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
index bb99e644..0dba3542 100644
--- a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c
@@ -106,6 +106,11 @@ u32 gm20b_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp)
         return nvgpu_readl(g, fuse_status_opt_rop_l2_fbp_r(fbp));
 }
 
+u32 gm20b_fuse_status_opt_gpc(struct gk20a *g)
+{
+        return nvgpu_readl(g, fuse_status_opt_gpc_r());
+}
+
 u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc)
 {
         return nvgpu_readl(g, fuse_status_opt_tpc_gpc_r(gpc));
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h
index 5e2d194b..b22499ad 100644
--- a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h
+++ b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h
@@ -36,6 +36,7 @@ int gm20b_fuse_check_priv_security(struct gk20a *g);
 u32 gm20b_fuse_status_opt_fbio(struct gk20a *g);
 u32 gm20b_fuse_status_opt_fbp(struct gk20a *g);
 u32 gm20b_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp);
+u32 gm20b_fuse_status_opt_gpc(struct gk20a *g);
 u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc);
 void gm20b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val);
 u32 gm20b_fuse_opt_sec_debug_en(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 368c9321..c67f7870 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -550,6 +550,23 @@ void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
             ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v();
 }
 
+u32 gr_gm20b_get_gpc_mask(struct gk20a *g)
+{
+        u32 val;
+        struct gr_gk20a *gr = &g->gr;
+
+        /*
+         * For register NV_FUSE_STATUS_OPT_GPC a set bit with index i indicates
+         * corresponding GPC is floorswept
+         * But for s/w mask a set bit means GPC is enabled and it is disabled
+         * otherwise
+         * Hence toggle the bits of register value to get s/w mask
+         */
+        val = g->ops.fuse.fuse_status_opt_gpc(g);
+
+        return (~val) & (BIT32(gr->max_gpc_count) - 1U);
+}
+
 u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
 {
         u32 val;
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
index 7402478d..084b6157 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
@@ -83,6 +83,7 @@ void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
                                                u32 *ctrl_register_stride);
 u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
 void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
+u32 gr_gm20b_get_gpc_mask(struct gk20a *g);
 void gr_gm20b_load_tpc_mask(struct gk20a *g);
 void gr_gm20b_program_sm_id_numbering(struct gk20a *g,
                                              u32 gpc, u32 tpc, u32 smid);
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 3a2fa71d..e8ad68c2 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -293,6 +293,7 @@ static const struct gpu_ops gp106_ops = {
                 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
                 .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask,
                 .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask,
+                .get_gpc_mask = gr_gm20b_get_gpc_mask,
                 .alloc_obj_ctx = gk20a_alloc_obj_ctx,
                 .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull,
                 .get_zcull_info = gr_gk20a_get_zcull_info,
@@ -794,6 +795,7 @@ static const struct gpu_ops gp106_ops = {
                 .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio,
                 .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp,
                 .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp,
+                .fuse_status_opt_gpc = gm20b_fuse_status_opt_gpc,
                 .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc,
                 .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc,
                 .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en,
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 99ee2d10..6d37f4a2 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -330,6 +330,7 @@ static const struct gpu_ops gv100_ops = {
                 .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode,
                 .set_gpc_tpc_mask = gr_gv100_set_gpc_tpc_mask,
                 .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask,
+                .get_gpc_mask = gr_gm20b_get_gpc_mask,
                 .alloc_obj_ctx = gk20a_alloc_obj_ctx,
                 .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull,
                 .get_zcull_info = gr_gk20a_get_zcull_info,
@@ -887,6 +888,7 @@ static const struct gpu_ops gv100_ops = {
                 .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio,
                 .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp,
                 .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp,
+                .fuse_status_opt_gpc = gm20b_fuse_status_opt_gpc,
                 .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc,
                 .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc,
                 .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index d0f51055..593b553c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -264,6 +264,7 @@ struct gpu_ops {
                                 struct gk20a_ctxsw_ucode_segments *segments,
                                 u32 reg_offset);
                 int (*load_ctxsw_ucode)(struct gk20a *g);
+                u32 (*get_gpc_mask)(struct gk20a *g);
                 u32 (*get_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index);
                 void (*set_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index);
                 int (*alloc_obj_ctx)(struct channel_gk20a  *c,
@@ -1270,6 +1271,7 @@ struct gpu_ops {
                 u32 (*fuse_status_opt_fbio)(struct gk20a *g);
                 u32 (*fuse_status_opt_fbp)(struct gk20a *g);
                 u32 (*fuse_status_opt_rop_l2_fbp)(struct gk20a *g, u32 fbp);
+                u32 (*fuse_status_opt_gpc)(struct gk20a *g);
                 u32 (*fuse_status_opt_tpc_gpc)(struct gk20a *g, u32 gpc);
                 void (*fuse_ctrl_opt_tpc_gpc)(struct gk20a *g, u32 gpc, u32 val);
                 u32 (*fuse_opt_sec_debug_en)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h
index 99b4b3f3..d97eb7d8 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -56,6 +56,10 @@
 #ifndef _hw_fuse_gm20b_h_
 #define _hw_fuse_gm20b_h_
 
+static inline u32 fuse_status_opt_gpc_r(void)
+{
+        return 0x00021c1cU;
+}
 static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
 {
         return 0x00021c38U + i*4U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h
index 7d1fb075..bfb19b9b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -56,6 +56,10 @@
 #ifndef _hw_fuse_gp106_h_
 #define _hw_fuse_gp106_h_
 
+static inline u32 fuse_status_opt_gpc_r(void)
+{
+        return 0x00021c1cU;
+}
 static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
 {
         return 0x00021c38U + i*4U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h
index 29107fb8..521dcfe2 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -56,6 +56,10 @@
 #ifndef _hw_fuse_gp10b_h_
 #define _hw_fuse_gp10b_h_
 
+static inline u32 fuse_status_opt_gpc_r(void)
+{
+        return 0x00021c1cU;
+}
 static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
 {
         return 0x00021c38U + i*4U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h
index f7eacd29..48194ea9 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -56,6 +56,10 @@
 #ifndef _hw_fuse_gv100_h_
 #define _hw_fuse_gv100_h_
 
+static inline u32 fuse_status_opt_gpc_r(void)
+{
+        return 0x00021c1cU;
+}
 static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
 {
         return 0x00021c38U + i*4U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h
index f8d9b196..9395da3f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -56,6 +56,10 @@
 #ifndef _hw_fuse_gv11b_h_
 #define _hw_fuse_gv11b_h_
 
+static inline u32 fuse_status_opt_gpc_r(void)
+{
+        return 0x00021c1cU;
+}
 static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
 {
         return 0x00021c38U + i*4U;
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
index 19b4286d..e8ed63f4 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
@@ -262,7 +262,11 @@ gk20a_ctrl_ioctl_gpu_characteristics(
 
         gpu.compression_page_size = g->ops.fb.compression_page_size(g);
 
-        gpu.gpc_mask = (1 << g->gr.gpc_count)-1;
+        if (g->ops.gr.get_gpc_mask) {
+                gpu.gpc_mask = g->ops.gr.get_gpc_mask(g);
+        } else {
+                gpu.gpc_mask = BIT32(g->gr.gpc_count) - 1;
+        }
 
         gpu.flags = nvgpu_ctrl_ioctl_gpu_characteristics_flags(g);