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-rw-r--r--drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c33
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h18
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h245
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h18
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h18
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h73
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h18
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h73
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h18
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h18
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h73
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h18
12 files changed, 403 insertions, 220 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
index 420b65f1..a44df1e8 100644
--- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
@@ -23,6 +23,7 @@
23#include <nvgpu/hw/gk20a/hw_mc_gk20a.h> 23#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
24#include <nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h> 24#include <nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h>
25#include <nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h> 25#include <nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h>
26#include <nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h>
26 27
27void gk20a_enable_priv_ring(struct gk20a *g) 28void gk20a_enable_priv_ring(struct gk20a *g)
28{ 29{
@@ -71,6 +72,8 @@ void gk20a_priv_ring_isr(struct gk20a *g)
71 u32 status0, status1; 72 u32 status0, status1;
72 u32 cmd; 73 u32 cmd;
73 s32 retry = 100; 74 s32 retry = 100;
75 u32 gpc;
76 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
74 struct gk20a_platform *platform = dev_get_drvdata(g->dev); 77 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
75 78
76 if (platform->is_fmodel) 79 if (platform->is_fmodel)
@@ -82,20 +85,28 @@ void gk20a_priv_ring_isr(struct gk20a *g)
82 gk20a_dbg(gpu_dbg_intr, "ringmaster intr status0: 0x%08x," 85 gk20a_dbg(gpu_dbg_intr, "ringmaster intr status0: 0x%08x,"
83 "status1: 0x%08x", status0, status1); 86 "status1: 0x%08x", status0, status1);
84 87
85 if (status0 & (0x1 | 0x2 | 0x4)) { 88 if (pri_ringmaster_intr_status0_ring_start_conn_fault_v(status0) != 0 ||
89 pri_ringmaster_intr_status0_disconnect_fault_v(status0) != 0 ||
90 pri_ringmaster_intr_status0_overflow_fault_v(status0) != 0) {
86 gk20a_reset_priv_ring(g); 91 gk20a_reset_priv_ring(g);
87 } 92 }
88 93
89 if (status0 & 0x100) { 94 if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) {
90 gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", 95 gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x",
91 gk20a_readl(g, 0x122120), gk20a_readl(g, 0x122124), gk20a_readl(g, 0x122128), 96 gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()),
92 gk20a_readl(g, 0x12212c)); 97 gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()),
98 gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()),
99 gk20a_readl(g, pri_ringstation_sys_priv_error_code_r()));
93 } 100 }
94 101
95 if (status1 & 0x1) { 102 for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
96 gk20a_dbg(gpu_dbg_intr, "GPC write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", 103 if (status1 & BIT(gpc)) {
97 gk20a_readl(g, 0x128120), gk20a_readl(g, 0x128124), gk20a_readl(g, 0x128128), 104 gk20a_dbg(gpu_dbg_intr, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc,
98 gk20a_readl(g, 0x12812c)); 105 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_stride),
106 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_stride),
107 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_stride),
108 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc * gpc_stride));
109 }
99 } 110 }
100 111
101 cmd = gk20a_readl(g, pri_ringmaster_command_r()); 112 cmd = gk20a_readl(g, pri_ringmaster_command_r());
@@ -112,10 +123,4 @@ void gk20a_priv_ring_isr(struct gk20a *g)
112 if (retry <= 0) 123 if (retry <= 0)
113 gk20a_warn(dev_from_gk20a(g), 124 gk20a_warn(dev_from_gk20a(g),
114 "priv ringmaster cmd ack too many retries"); 125 "priv ringmaster cmd ack too many retries");
115
116 status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r());
117 status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r());
118
119 gk20a_dbg_info("ringmaster intr status0: 0x%08x,"
120 " status1: 0x%08x", status0, status1);
121} 126}
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h
index d4007613..10e3174d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -102,6 +102,22 @@ static inline u32 pri_ringmaster_intr_status0_r(void)
102{ 102{
103 return 0x00120058; 103 return 0x00120058;
104} 104}
105static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
106{
107 return (r >> 0) & 0x1;
108}
109static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
110{
111 return (r >> 1) & 0x1;
112}
113static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
114{
115 return (r >> 2) & 0x1;
116}
117static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
118{
119 return (r >> 8) & 0x1;
120}
105static inline u32 pri_ringmaster_intr_status1_r(void) 121static inline u32 pri_ringmaster_intr_status1_r(void)
106{ 122{
107 return 0x0012005c; 123 return 0x0012005c;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h
index e8aad933..7a48efd8 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h
@@ -1,7 +1,5 @@
1/* 1/*
2 * drivers/video/tegra/host/gk20a/hw_pri_ringstation_gpc_gk20a.h 2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Copyright (c) 2012-2013, NVIDIA Corporation. All rights reserved.
5 * 3 *
6 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -14,213 +12,62 @@
14 * 12 *
15 * You should have received a copy of the GNU General Public License 13 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
17 * 44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
18 */ 49 */
19 50#ifndef _hw_pri_ringstation_gpc_gk20a_h_
20 /* 51#define _hw_pri_ringstation_gpc_gk20a_h_
21 * Function naming determines intended use:
22 *
23 * <x>_r(void) : Returns the offset for register <x>.
24 *
25 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
26 *
27 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
28 *
29 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
30 * and masked to place it at field <y> of register <x>. This value
31 * can be |'d with others to produce a full register value for
32 * register <x>.
33 *
34 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
35 * value can be ~'d and then &'d to clear the value of field <y> for
36 * register <x>.
37 *
38 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
39 * to place it at field <y> of register <x>. This value can be |'d
40 * with others to produce a full register value for <x>.
41 *
42 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
43 * <x> value 'r' after being shifted to place its LSB at bit 0.
44 * This value is suitable for direct comparison with other unshifted
45 * values appropriate for use in field <y> of register <x>.
46 *
47 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
48 * field <y> of register <x>. This value is suitable for direct
49 * comparison with unshifted values appropriate for use in field <y>
50 * of register <x>.
51 */
52
53#ifndef __hw_pri_ringstation_gpc_gk20a_h__
54#define __hw_pri_ringstation_gpc_gk20a_h__
55/*This file is autogenerated. Do not edit. */
56 52
57static inline u32 pri_ringstation_gpc_master_config_r(u32 i) 53static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
58{ 54{
59 return 0x00128300+((i)*4); 55 return 0x00128300 + i*4;
60}
61static inline u32 pri_ringstation_gpc_master_config__size_1_v(void)
62{
63 return 64;
64}
65static inline u32 pri_ringstation_gpc_master_config_timeout_s(void)
66{
67 return 18;
68}
69static inline u32 pri_ringstation_gpc_master_config_timeout_f(u32 v)
70{
71 return (v & 0x3ffff) << 0;
72}
73static inline u32 pri_ringstation_gpc_master_config_timeout_m(void)
74{
75 return 0x3ffff << 0;
76}
77static inline u32 pri_ringstation_gpc_master_config_timeout_v(u32 r)
78{
79 return (r >> 0) & 0x3ffff;
80}
81static inline u32 pri_ringstation_gpc_master_config_timeout_i_v(void)
82{
83 return 0x00000064;
84}
85static inline u32 pri_ringstation_gpc_master_config_timeout_i_f(void)
86{
87 return 0x64;
88}
89static inline u32 pri_ringstation_gpc_master_config_fs_action_s(void)
90{
91 return 1;
92}
93static inline u32 pri_ringstation_gpc_master_config_fs_action_f(u32 v)
94{
95 return (v & 0x1) << 30;
96}
97static inline u32 pri_ringstation_gpc_master_config_fs_action_m(void)
98{
99 return 0x1 << 30;
100}
101static inline u32 pri_ringstation_gpc_master_config_fs_action_v(u32 r)
102{
103 return (r >> 30) & 0x1;
104}
105static inline u32 pri_ringstation_gpc_master_config_fs_action_error_v(void)
106{
107 return 0x00000000;
108}
109static inline u32 pri_ringstation_gpc_master_config_fs_action_error_f(void)
110{
111 return 0x0;
112}
113static inline u32 pri_ringstation_gpc_master_config_fs_action_soldier_on_v(void)
114{
115 return 0x00000001;
116}
117static inline u32 pri_ringstation_gpc_master_config_fs_action_soldier_on_f(void)
118{
119 return 0x40000000;
120}
121static inline u32 pri_ringstation_gpc_master_config_reset_action_s(void)
122{
123 return 1;
124}
125static inline u32 pri_ringstation_gpc_master_config_reset_action_f(u32 v)
126{
127 return (v & 0x1) << 31;
128}
129static inline u32 pri_ringstation_gpc_master_config_reset_action_m(void)
130{
131 return 0x1 << 31;
132}
133static inline u32 pri_ringstation_gpc_master_config_reset_action_v(u32 r)
134{
135 return (r >> 31) & 0x1;
136}
137static inline u32 pri_ringstation_gpc_master_config_reset_action_error_v(void)
138{
139 return 0x00000000;
140}
141static inline u32 pri_ringstation_gpc_master_config_reset_action_error_f(void)
142{
143 return 0x0;
144}
145static inline u32 pri_ringstation_gpc_master_config_reset_action_soldier_on_v(void)
146{
147 return 0x00000001;
148}
149static inline u32 pri_ringstation_gpc_master_config_reset_action_soldier_on_f(void)
150{
151 return 0x80000000;
152}
153static inline u32 pri_ringstation_gpc_master_config_setup_clocks_s(void)
154{
155 return 3;
156}
157static inline u32 pri_ringstation_gpc_master_config_setup_clocks_f(u32 v)
158{
159 return (v & 0x7) << 20;
160}
161static inline u32 pri_ringstation_gpc_master_config_setup_clocks_m(void)
162{
163 return 0x7 << 20;
164}
165static inline u32 pri_ringstation_gpc_master_config_setup_clocks_v(u32 r)
166{
167 return (r >> 20) & 0x7;
168}
169static inline u32 pri_ringstation_gpc_master_config_setup_clocks_i_v(void)
170{
171 return 0x00000000;
172}
173static inline u32 pri_ringstation_gpc_master_config_setup_clocks_i_f(void)
174{
175 return 0x0;
176}
177static inline u32 pri_ringstation_gpc_master_config_wait_clocks_s(void)
178{
179 return 3;
180}
181static inline u32 pri_ringstation_gpc_master_config_wait_clocks_f(u32 v)
182{
183 return (v & 0x7) << 24;
184}
185static inline u32 pri_ringstation_gpc_master_config_wait_clocks_m(void)
186{
187 return 0x7 << 24;
188} 56}
189static inline u32 pri_ringstation_gpc_master_config_wait_clocks_v(u32 r) 57static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
190{ 58{
191 return (r >> 24) & 0x7; 59 return 0x00128120;
192} 60}
193static inline u32 pri_ringstation_gpc_master_config_wait_clocks_i_v(void) 61static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
194{ 62{
195 return 0x00000000; 63 return 0x00128124;
196} 64}
197static inline u32 pri_ringstation_gpc_master_config_wait_clocks_i_f(void) 65static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
198{ 66{
199 return 0x0; 67 return 0x00128128;
200} 68}
201static inline u32 pri_ringstation_gpc_master_config_hold_clocks_s(void) 69static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
202{ 70{
203 return 3; 71 return 0x0012812c;
204} 72}
205static inline u32 pri_ringstation_gpc_master_config_hold_clocks_f(u32 v) 73#endif
206{
207 return (v & 0x7) << 27;
208}
209static inline u32 pri_ringstation_gpc_master_config_hold_clocks_m(void)
210{
211 return 0x7 << 27;
212}
213static inline u32 pri_ringstation_gpc_master_config_hold_clocks_v(u32 r)
214{
215 return (r >> 27) & 0x7;
216}
217static inline u32 pri_ringstation_gpc_master_config_hold_clocks_i_v(void)
218{
219 return 0x00000000;
220}
221static inline u32 pri_ringstation_gpc_master_config_hold_clocks_i_f(void)
222{
223 return 0x0;
224}
225
226#endif /* __hw_pri_ringstation_gpc_gk20a_h__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h
index c281dd54..5ef300e7 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2012-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -66,4 +66,20 @@ static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_starte
66{ 66{
67 return 0x1; 67 return 0x1;
68} 68}
69static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
70{
71 return 0x00122120;
72}
73static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
74{
75 return 0x00122124;
76}
77static inline u32 pri_ringstation_sys_priv_error_info_r(void)
78{
79 return 0x00122128;
80}
81static inline u32 pri_ringstation_sys_priv_error_code_r(void)
82{
83 return 0x0012212c;
84}
69#endif 85#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h
index 930592db..9c0f781f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -102,6 +102,22 @@ static inline u32 pri_ringmaster_intr_status0_r(void)
102{ 102{
103 return 0x00120058; 103 return 0x00120058;
104} 104}
105static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
106{
107 return (r >> 0) & 0x1;
108}
109static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
110{
111 return (r >> 1) & 0x1;
112}
113static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
114{
115 return (r >> 2) & 0x1;
116}
117static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
118{
119 return (r >> 8) & 0x1;
120}
105static inline u32 pri_ringmaster_intr_status1_r(void) 121static inline u32 pri_ringmaster_intr_status1_r(void)
106{ 122{
107 return 0x0012005c; 123 return 0x0012005c;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h
new file mode 100644
index 00000000..d9da79bd
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_gpc_gm20b.h
@@ -0,0 +1,73 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pri_ringstation_gpc_gm20b_h_
51#define _hw_pri_ringstation_gpc_gm20b_h_
52
53static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
54{
55 return 0x00128300 + i*4;
56}
57static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
58{
59 return 0x00128120;
60}
61static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
62{
63 return 0x00128124;
64}
65static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
66{
67 return 0x00128128;
68}
69static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
70{
71 return 0x0012812c;
72}
73#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h
index 7170a287..66b32604 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_pri_ringstation_sys_gm20b.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -66,4 +66,20 @@ static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_starte
66{ 66{
67 return 0x1; 67 return 0x1;
68} 68}
69static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
70{
71 return 0x00122120;
72}
73static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
74{
75 return 0x00122124;
76}
77static inline u32 pri_ringstation_sys_priv_error_info_r(void)
78{
79 return 0x00122128;
80}
81static inline u32 pri_ringstation_sys_priv_error_code_r(void)
82{
83 return 0x0012212c;
84}
69#endif 85#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h
new file mode 100644
index 00000000..ec2f8af6
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_gpc_gp106.h
@@ -0,0 +1,73 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pri_ringstation_gpc_gp106_h_
51#define _hw_pri_ringstation_gpc_gp106_h_
52
53static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
54{
55 return 0x00128300 + i*4;
56}
57static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
58{
59 return 0x00128120;
60}
61static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
62{
63 return 0x00128124;
64}
65static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
66{
67 return 0x00128128;
68}
69static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
70{
71 return 0x0012812c;
72}
73#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h
index a22d6a05..565ea8e9 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_pri_ringstation_sys_gp106.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -66,4 +66,20 @@ static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_starte
66{ 66{
67 return 0x1; 67 return 0x1;
68} 68}
69static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
70{
71 return 0x00122120;
72}
73static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
74{
75 return 0x00122124;
76}
77static inline u32 pri_ringstation_sys_priv_error_info_r(void)
78{
79 return 0x00122128;
80}
81static inline u32 pri_ringstation_sys_priv_error_code_r(void)
82{
83 return 0x0012212c;
84}
69#endif 85#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h
index 7a458858..6528a1c3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringmaster_gp10b.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -102,6 +102,22 @@ static inline u32 pri_ringmaster_intr_status0_r(void)
102{ 102{
103 return 0x00120058; 103 return 0x00120058;
104} 104}
105static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
106{
107 return (r >> 0) & 0x1;
108}
109static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
110{
111 return (r >> 1) & 0x1;
112}
113static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
114{
115 return (r >> 2) & 0x1;
116}
117static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
118{
119 return (r >> 8) & 0x1;
120}
105static inline u32 pri_ringmaster_intr_status1_r(void) 121static inline u32 pri_ringmaster_intr_status1_r(void)
106{ 122{
107 return 0x0012005c; 123 return 0x0012005c;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h
new file mode 100644
index 00000000..5194ad83
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_gpc_gp10b.h
@@ -0,0 +1,73 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_pri_ringstation_gpc_gp10b_h_
51#define _hw_pri_ringstation_gpc_gp10b_h_
52
53static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
54{
55 return 0x00128300 + i*4;
56}
57static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
58{
59 return 0x00128120;
60}
61static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
62{
63 return 0x00128124;
64}
65static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
66{
67 return 0x00128128;
68}
69static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
70{
71 return 0x0012812c;
72}
73#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h
index eb711452..7e1d5be7 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_pri_ringstation_sys_gp10b.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -66,4 +66,20 @@ static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_starte
66{ 66{
67 return 0x1; 67 return 0x1;
68} 68}
69static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
70{
71 return 0x00122120;
72}
73static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
74{
75 return 0x00122124;
76}
77static inline u32 pri_ringstation_sys_priv_error_info_r(void)
78{
79 return 0x00122128;
80}
81static inline u32 pri_ringstation_sys_priv_error_code_r(void)
82{
83 return 0x0012212c;
84}
69#endif 85#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 18:13:07 -0400