diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fuse_gp10b.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fuse_gp10b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gp10b.c | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 116 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gv11b.c | 121 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gv11b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 6 |
14 files changed, 177 insertions, 144 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 4ff85ee3..d6e0342b 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1246,6 +1246,8 @@ struct gpu_ops { | |||
1246 | } priv_ring; | 1246 | } priv_ring; |
1247 | struct { | 1247 | struct { |
1248 | int (*check_priv_security)(struct gk20a *g); | 1248 | int (*check_priv_security)(struct gk20a *g); |
1249 | bool (*is_opt_ecc_enable)(struct gk20a *g); | ||
1250 | bool (*is_opt_feature_override_disable)(struct gk20a *g); | ||
1249 | } fuse; | 1251 | } fuse; |
1250 | struct { | 1252 | struct { |
1251 | int (*init)(struct gk20a *g); | 1253 | int (*init)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 63e6206a..9490ec10 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -56,6 +56,7 @@ | |||
56 | #include "gp10b/pmu_gp10b.h" | 56 | #include "gp10b/pmu_gp10b.h" |
57 | #include "gp10b/gr_gp10b.h" | 57 | #include "gp10b/gr_gp10b.h" |
58 | #include "gp10b/priv_ring_gp10b.h" | 58 | #include "gp10b/priv_ring_gp10b.h" |
59 | #include "gp10b/fuse_gp10b.h" | ||
59 | 60 | ||
60 | #include "gp106/fifo_gp106.h" | 61 | #include "gp106/fifo_gp106.h" |
61 | #include "gp106/regops_gp106.h" | 62 | #include "gp106/regops_gp106.h" |
@@ -781,6 +782,9 @@ static const struct gpu_ops gp106_ops = { | |||
781 | }, | 782 | }, |
782 | .fuse = { | 783 | .fuse = { |
783 | .check_priv_security = gp106_fuse_check_priv_security, | 784 | .check_priv_security = gp106_fuse_check_priv_security, |
785 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, | ||
786 | .is_opt_feature_override_disable = | ||
787 | gp10b_fuse_is_opt_feature_override_disable, | ||
784 | }, | 788 | }, |
785 | .get_litter_value = gp106_get_litter_value, | 789 | .get_litter_value = gp106_get_litter_value, |
786 | .chip_init_gpu_characteristics = gp106_init_gpu_characteristics, | 790 | .chip_init_gpu_characteristics = gp106_init_gpu_characteristics, |
diff --git a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c index c1fc6be7..52087676 100644 --- a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B FUSE | 2 | * GP10B FUSE |
3 | * | 3 | * |
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -91,3 +91,14 @@ int gp10b_fuse_check_priv_security(struct gk20a *g) | |||
91 | 91 | ||
92 | return 0; | 92 | return 0; |
93 | } | 93 | } |
94 | |||
95 | bool gp10b_fuse_is_opt_ecc_enable(struct gk20a *g) | ||
96 | { | ||
97 | return gk20a_readl(g, fuse_opt_ecc_en_r()) != 0U; | ||
98 | } | ||
99 | |||
100 | bool gp10b_fuse_is_opt_feature_override_disable(struct gk20a *g) | ||
101 | { | ||
102 | return gk20a_readl(g, | ||
103 | fuse_opt_feature_fuses_override_disable_r()) != 0U; | ||
104 | } | ||
diff --git a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h index 1acb45d1..d9037e22 100644 --- a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B FUSE | 2 | * GP10B FUSE |
3 | * | 3 | * |
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -28,5 +28,7 @@ | |||
28 | struct gk20a; | 28 | struct gk20a; |
29 | 29 | ||
30 | int gp10b_fuse_check_priv_security(struct gk20a *g); | 30 | int gp10b_fuse_check_priv_security(struct gk20a *g); |
31 | bool gp10b_fuse_is_opt_ecc_enable(struct gk20a *g); | ||
32 | bool gp10b_fuse_is_opt_feature_override_disable(struct gk20a *g); | ||
31 | 33 | ||
32 | #endif | 34 | #endif |
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b.c b/drivers/gpu/nvgpu/gp10b/gp10b.c index 51dc4301..7991944c 100644 --- a/drivers/gpu/nvgpu/gp10b/gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B Graphics | 2 | * GP10B Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -28,15 +28,13 @@ | |||
28 | 28 | ||
29 | #include "gp10b.h" | 29 | #include "gp10b.h" |
30 | 30 | ||
31 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | ||
32 | #include <nvgpu/hw/gp10b/hw_gr_gp10b.h> | 31 | #include <nvgpu/hw/gp10b/hw_gr_gp10b.h> |
33 | 32 | ||
34 | static void gp10b_detect_ecc_enabled_units(struct gk20a *g) | 33 | static void gp10b_detect_ecc_enabled_units(struct gk20a *g) |
35 | { | 34 | { |
36 | u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r()); | 35 | bool opt_ecc_en = g->ops.fuse.is_opt_ecc_enable(g); |
37 | u32 opt_feature_fuses_override_disable = | 36 | bool opt_feature_fuses_override_disable = |
38 | gk20a_readl(g, | 37 | g->ops.fuse.is_opt_feature_override_disable(g); |
39 | fuse_opt_feature_fuses_override_disable_r()); | ||
40 | u32 fecs_feature_override_ecc = | 38 | u32 fecs_feature_override_ecc = |
41 | gk20a_readl(g, | 39 | gk20a_readl(g, |
42 | gr_fecs_feature_override_ecc_r()); | 40 | gr_fecs_feature_override_ecc_r()); |
@@ -51,9 +49,9 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g) | |||
51 | } else { | 49 | } else { |
52 | /* SM LRF */ | 50 | /* SM LRF */ |
53 | if (gr_fecs_feature_override_ecc_sm_lrf_override_v( | 51 | if (gr_fecs_feature_override_ecc_sm_lrf_override_v( |
54 | fecs_feature_override_ecc)) { | 52 | fecs_feature_override_ecc) == 1U) { |
55 | if (gr_fecs_feature_override_ecc_sm_lrf_v( | 53 | if (gr_fecs_feature_override_ecc_sm_lrf_v( |
56 | fecs_feature_override_ecc)) { | 54 | fecs_feature_override_ecc) == 1U) { |
57 | __nvgpu_set_enabled(g, | 55 | __nvgpu_set_enabled(g, |
58 | NVGPU_ECC_ENABLED_SM_LRF, true); | 56 | NVGPU_ECC_ENABLED_SM_LRF, true); |
59 | } | 57 | } |
@@ -66,9 +64,9 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g) | |||
66 | 64 | ||
67 | /* SM SHM */ | 65 | /* SM SHM */ |
68 | if (gr_fecs_feature_override_ecc_sm_shm_override_v( | 66 | if (gr_fecs_feature_override_ecc_sm_shm_override_v( |
69 | fecs_feature_override_ecc)) { | 67 | fecs_feature_override_ecc) == 1U) { |
70 | if (gr_fecs_feature_override_ecc_sm_shm_v( | 68 | if (gr_fecs_feature_override_ecc_sm_shm_v( |
71 | fecs_feature_override_ecc)) { | 69 | fecs_feature_override_ecc) == 1U) { |
72 | __nvgpu_set_enabled(g, | 70 | __nvgpu_set_enabled(g, |
73 | NVGPU_ECC_ENABLED_SM_SHM, true); | 71 | NVGPU_ECC_ENABLED_SM_SHM, true); |
74 | } | 72 | } |
@@ -81,9 +79,9 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g) | |||
81 | 79 | ||
82 | /* TEX */ | 80 | /* TEX */ |
83 | if (gr_fecs_feature_override_ecc_tex_override_v( | 81 | if (gr_fecs_feature_override_ecc_tex_override_v( |
84 | fecs_feature_override_ecc)) { | 82 | fecs_feature_override_ecc) == 1U) { |
85 | if (gr_fecs_feature_override_ecc_tex_v( | 83 | if (gr_fecs_feature_override_ecc_tex_v( |
86 | fecs_feature_override_ecc)) { | 84 | fecs_feature_override_ecc) == 1U) { |
87 | __nvgpu_set_enabled(g, | 85 | __nvgpu_set_enabled(g, |
88 | NVGPU_ECC_ENABLED_TEX, true); | 86 | NVGPU_ECC_ENABLED_TEX, true); |
89 | } | 87 | } |
@@ -96,9 +94,9 @@ static void gp10b_detect_ecc_enabled_units(struct gk20a *g) | |||
96 | 94 | ||
97 | /* LTC */ | 95 | /* LTC */ |
98 | if (gr_fecs_feature_override_ecc_ltc_override_v( | 96 | if (gr_fecs_feature_override_ecc_ltc_override_v( |
99 | fecs_feature_override_ecc)) { | 97 | fecs_feature_override_ecc) == 1U) { |
100 | if (gr_fecs_feature_override_ecc_ltc_v( | 98 | if (gr_fecs_feature_override_ecc_ltc_v( |
101 | fecs_feature_override_ecc)) { | 99 | fecs_feature_override_ecc) == 1U) { |
102 | __nvgpu_set_enabled(g, | 100 | __nvgpu_set_enabled(g, |
103 | NVGPU_ECC_ENABLED_LTC, true); | 101 | NVGPU_ECC_ENABLED_LTC, true); |
104 | } | 102 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 424c8490..16eddeca 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -43,7 +43,6 @@ | |||
43 | #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h> | 43 | #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h> |
44 | #include <nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h> | 44 | #include <nvgpu/hw/gp10b/hw_ctxsw_prog_gp10b.h> |
45 | #include <nvgpu/hw/gp10b/hw_mc_gp10b.h> | 45 | #include <nvgpu/hw/gp10b/hw_mc_gp10b.h> |
46 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | ||
47 | 46 | ||
48 | #define GFXP_WFI_TIMEOUT_COUNT_DEFAULT 100000 | 47 | #define GFXP_WFI_TIMEOUT_COUNT_DEFAULT 100000 |
49 | 48 | ||
@@ -2022,11 +2021,14 @@ u32 gp10b_gr_get_sm_hww_warp_esr(struct gk20a *g, | |||
2022 | 2021 | ||
2023 | u32 get_ecc_override_val(struct gk20a *g) | 2022 | u32 get_ecc_override_val(struct gk20a *g) |
2024 | { | 2023 | { |
2025 | u32 val; | 2024 | bool en = false; |
2026 | 2025 | ||
2027 | val = gk20a_readl(g, fuse_opt_ecc_en_r()); | 2026 | if (g->ops.fuse.is_opt_ecc_enable) { |
2028 | if (val) | 2027 | en = g->ops.fuse.is_opt_ecc_enable(g); |
2029 | return gk20a_readl(g, gr_fecs_feature_override_ecc_r()); | 2028 | if (en) { |
2029 | return gk20a_readl(g, gr_fecs_feature_override_ecc_r()); | ||
2030 | } | ||
2031 | } | ||
2030 | 2032 | ||
2031 | return 0; | 2033 | return 0; |
2032 | } | 2034 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index bbfce287..94adf727 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -694,6 +694,9 @@ static const struct gpu_ops gp10b_ops = { | |||
694 | }, | 694 | }, |
695 | .fuse = { | 695 | .fuse = { |
696 | .check_priv_security = gp10b_fuse_check_priv_security, | 696 | .check_priv_security = gp10b_fuse_check_priv_security, |
697 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, | ||
698 | .is_opt_feature_override_disable = | ||
699 | gp10b_fuse_is_opt_feature_override_disable, | ||
697 | }, | 700 | }, |
698 | .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics, | 701 | .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics, |
699 | .get_litter_value = gp10b_get_litter_value, | 702 | .get_litter_value = gp10b_get_litter_value, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 6f340e6a..ebcab011 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -73,6 +73,7 @@ | |||
73 | #include "gp10b/fecs_trace_gp10b.h" | 73 | #include "gp10b/fecs_trace_gp10b.h" |
74 | #include "gp10b/mm_gp10b.h" | 74 | #include "gp10b/mm_gp10b.h" |
75 | #include "gp10b/pmu_gp10b.h" | 75 | #include "gp10b/pmu_gp10b.h" |
76 | #include "gp10b/fuse_gp10b.h" | ||
76 | 77 | ||
77 | #include "gv11b/css_gr_gv11b.h" | 78 | #include "gv11b/css_gr_gv11b.h" |
78 | #include "gv11b/dbg_gpu_gv11b.h" | 79 | #include "gv11b/dbg_gpu_gv11b.h" |
@@ -872,6 +873,11 @@ static const struct gpu_ops gv100_ops = { | |||
872 | .set_ppriv_timeout_settings = | 873 | .set_ppriv_timeout_settings = |
873 | gk20a_priv_set_timeout_settings, | 874 | gk20a_priv_set_timeout_settings, |
874 | }, | 875 | }, |
876 | .fuse = { | ||
877 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, | ||
878 | .is_opt_feature_override_disable = | ||
879 | gp10b_fuse_is_opt_feature_override_disable, | ||
880 | }, | ||
875 | #if defined(CONFIG_TEGRA_NVLINK) | 881 | #if defined(CONFIG_TEGRA_NVLINK) |
876 | .nvlink = { | 882 | .nvlink = { |
877 | .discover_ioctrl = gv100_nvlink_discover_ioctrl, | 883 | .discover_ioctrl = gv100_nvlink_discover_ioctrl, |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 6ceaa47a..d3fe5f65 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -4488,11 +4488,125 @@ static int gr_gv11b_ecc_scrub_sm_icahe(struct gk20a *g) | |||
4488 | scrub_mask, scrub_done); | 4488 | scrub_mask, scrub_done); |
4489 | } | 4489 | } |
4490 | 4490 | ||
4491 | static void gr_gv11b_detect_ecc_enabled_units(struct gk20a *g) | ||
4492 | { | ||
4493 | bool opt_ecc_en = g->ops.fuse.is_opt_ecc_enable(g); | ||
4494 | bool opt_feature_fuses_override_disable = | ||
4495 | g->ops.fuse.is_opt_feature_override_disable(g); | ||
4496 | u32 fecs_feature_override_ecc = | ||
4497 | gk20a_readl(g, | ||
4498 | gr_fecs_feature_override_ecc_r()); | ||
4499 | |||
4500 | if (opt_feature_fuses_override_disable) { | ||
4501 | if (opt_ecc_en) { | ||
4502 | __nvgpu_set_enabled(g, | ||
4503 | NVGPU_ECC_ENABLED_SM_LRF, true); | ||
4504 | __nvgpu_set_enabled(g, | ||
4505 | NVGPU_ECC_ENABLED_SM_L1_DATA, true); | ||
4506 | __nvgpu_set_enabled(g, | ||
4507 | NVGPU_ECC_ENABLED_SM_L1_TAG, true); | ||
4508 | __nvgpu_set_enabled(g, | ||
4509 | NVGPU_ECC_ENABLED_SM_ICACHE, true); | ||
4510 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true); | ||
4511 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_CBU, true); | ||
4512 | } | ||
4513 | } else { | ||
4514 | /* SM LRF */ | ||
4515 | if (gr_fecs_feature_override_ecc_sm_lrf_override_v( | ||
4516 | fecs_feature_override_ecc) == 1U) { | ||
4517 | if (gr_fecs_feature_override_ecc_sm_lrf_v( | ||
4518 | fecs_feature_override_ecc) == 1U) { | ||
4519 | __nvgpu_set_enabled(g, | ||
4520 | NVGPU_ECC_ENABLED_SM_LRF, true); | ||
4521 | } | ||
4522 | } else { | ||
4523 | if (opt_ecc_en) { | ||
4524 | __nvgpu_set_enabled(g, | ||
4525 | NVGPU_ECC_ENABLED_SM_LRF, true); | ||
4526 | } | ||
4527 | } | ||
4528 | /* SM L1 DATA*/ | ||
4529 | if (gr_fecs_feature_override_ecc_sm_l1_data_override_v( | ||
4530 | fecs_feature_override_ecc) == 1U) { | ||
4531 | if (gr_fecs_feature_override_ecc_sm_l1_data_v( | ||
4532 | fecs_feature_override_ecc) == 1U) { | ||
4533 | __nvgpu_set_enabled(g, | ||
4534 | NVGPU_ECC_ENABLED_SM_L1_DATA, true); | ||
4535 | } | ||
4536 | } else { | ||
4537 | if (opt_ecc_en) { | ||
4538 | __nvgpu_set_enabled(g, | ||
4539 | NVGPU_ECC_ENABLED_SM_L1_DATA, true); | ||
4540 | } | ||
4541 | } | ||
4542 | /* SM L1 TAG*/ | ||
4543 | if (gr_fecs_feature_override_ecc_sm_l1_tag_override_v( | ||
4544 | fecs_feature_override_ecc) == 1U) { | ||
4545 | if (gr_fecs_feature_override_ecc_sm_l1_tag_v( | ||
4546 | fecs_feature_override_ecc) == 1U) { | ||
4547 | __nvgpu_set_enabled(g, | ||
4548 | NVGPU_ECC_ENABLED_SM_L1_TAG, true); | ||
4549 | } | ||
4550 | } else { | ||
4551 | if (opt_ecc_en) { | ||
4552 | __nvgpu_set_enabled(g, | ||
4553 | NVGPU_ECC_ENABLED_SM_L1_TAG, true); | ||
4554 | } | ||
4555 | } | ||
4556 | /* SM ICACHE*/ | ||
4557 | if ((gr_fecs_feature_override_ecc_1_sm_l0_icache_override_v( | ||
4558 | fecs_feature_override_ecc) == 1U) && | ||
4559 | (gr_fecs_feature_override_ecc_1_sm_l1_icache_override_v( | ||
4560 | fecs_feature_override_ecc) == 1U)) { | ||
4561 | if ((gr_fecs_feature_override_ecc_1_sm_l0_icache_v( | ||
4562 | fecs_feature_override_ecc) == 1U) && | ||
4563 | (gr_fecs_feature_override_ecc_1_sm_l1_icache_v( | ||
4564 | fecs_feature_override_ecc) == 1U)) { | ||
4565 | __nvgpu_set_enabled(g, | ||
4566 | NVGPU_ECC_ENABLED_SM_ICACHE, true); | ||
4567 | } | ||
4568 | } else { | ||
4569 | if (opt_ecc_en) { | ||
4570 | __nvgpu_set_enabled(g, | ||
4571 | NVGPU_ECC_ENABLED_SM_ICACHE, true); | ||
4572 | } | ||
4573 | } | ||
4574 | /* LTC */ | ||
4575 | if (gr_fecs_feature_override_ecc_ltc_override_v( | ||
4576 | fecs_feature_override_ecc) == 1U) { | ||
4577 | if (gr_fecs_feature_override_ecc_ltc_v( | ||
4578 | fecs_feature_override_ecc) == 1U) { | ||
4579 | __nvgpu_set_enabled(g, | ||
4580 | NVGPU_ECC_ENABLED_LTC, true); | ||
4581 | } | ||
4582 | } else { | ||
4583 | if (opt_ecc_en) { | ||
4584 | __nvgpu_set_enabled(g, | ||
4585 | NVGPU_ECC_ENABLED_LTC, true); | ||
4586 | } | ||
4587 | } | ||
4588 | /* SM CBU */ | ||
4589 | if (gr_fecs_feature_override_ecc_sm_cbu_override_v( | ||
4590 | fecs_feature_override_ecc) == 1U) { | ||
4591 | if (gr_fecs_feature_override_ecc_sm_cbu_v( | ||
4592 | fecs_feature_override_ecc) == 1U) { | ||
4593 | __nvgpu_set_enabled(g, | ||
4594 | NVGPU_ECC_ENABLED_SM_CBU, true); | ||
4595 | } | ||
4596 | } else { | ||
4597 | if (opt_ecc_en) { | ||
4598 | __nvgpu_set_enabled(g, | ||
4599 | NVGPU_ECC_ENABLED_SM_CBU, true); | ||
4600 | } | ||
4601 | } | ||
4602 | } | ||
4603 | } | ||
4604 | |||
4491 | void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g) | 4605 | void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g) |
4492 | { | 4606 | { |
4493 | nvgpu_log_fn(g, "ecc srub start "); | 4607 | nvgpu_log_fn(g, "ecc srub start "); |
4494 | 4608 | ||
4495 | gv11b_detect_ecc_enabled_units(g); | 4609 | gr_gv11b_detect_ecc_enabled_units(g); |
4496 | 4610 | ||
4497 | if (gr_gv11b_ecc_scrub_sm_lrf(g)) | 4611 | if (gr_gv11b_ecc_scrub_sm_lrf(g)) |
4498 | nvgpu_warn(g, "ECC SCRUB SM LRF Failed"); | 4612 | nvgpu_warn(g, "ECC SCRUB SM LRF Failed"); |
diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.c b/drivers/gpu/nvgpu/gv11b/gv11b.c index 44120498..5d2bfbd7 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b.c | |||
@@ -25,128 +25,7 @@ | |||
25 | #include <nvgpu/enabled.h> | 25 | #include <nvgpu/enabled.h> |
26 | 26 | ||
27 | #include "gk20a/gk20a.h" | 27 | #include "gk20a/gk20a.h" |
28 | #include "gp10b/gp10b.h" | ||
29 | |||
30 | #include "gv11b/gv11b.h" | 28 | #include "gv11b/gv11b.h" |
31 | #include <nvgpu/hw/gv11b/hw_fuse_gv11b.h> | ||
32 | #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> | ||
33 | |||
34 | void gv11b_detect_ecc_enabled_units(struct gk20a *g) | ||
35 | { | ||
36 | u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r()); | ||
37 | u32 opt_feature_fuses_override_disable = | ||
38 | gk20a_readl(g, | ||
39 | fuse_opt_feature_fuses_override_disable_r()); | ||
40 | u32 fecs_feature_override_ecc = | ||
41 | gk20a_readl(g, | ||
42 | gr_fecs_feature_override_ecc_r()); | ||
43 | |||
44 | if (opt_feature_fuses_override_disable) { | ||
45 | if (opt_ecc_en) { | ||
46 | __nvgpu_set_enabled(g, | ||
47 | NVGPU_ECC_ENABLED_SM_LRF, true); | ||
48 | __nvgpu_set_enabled(g, | ||
49 | NVGPU_ECC_ENABLED_SM_L1_DATA, true); | ||
50 | __nvgpu_set_enabled(g, | ||
51 | NVGPU_ECC_ENABLED_SM_L1_TAG, true); | ||
52 | __nvgpu_set_enabled(g, | ||
53 | NVGPU_ECC_ENABLED_SM_ICACHE, true); | ||
54 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true); | ||
55 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_CBU, true); | ||
56 | } | ||
57 | } else { | ||
58 | /* SM LRF */ | ||
59 | if (gr_fecs_feature_override_ecc_sm_lrf_override_v( | ||
60 | fecs_feature_override_ecc)) { | ||
61 | if (gr_fecs_feature_override_ecc_sm_lrf_v( | ||
62 | fecs_feature_override_ecc)) { | ||
63 | __nvgpu_set_enabled(g, | ||
64 | NVGPU_ECC_ENABLED_SM_LRF, true); | ||
65 | } | ||
66 | } else { | ||
67 | if (opt_ecc_en) { | ||
68 | __nvgpu_set_enabled(g, | ||
69 | NVGPU_ECC_ENABLED_SM_LRF, true); | ||
70 | } | ||
71 | } | ||
72 | /* SM L1 DATA*/ | ||
73 | if (gr_fecs_feature_override_ecc_sm_l1_data_override_v( | ||
74 | fecs_feature_override_ecc)) { | ||
75 | if (gr_fecs_feature_override_ecc_sm_l1_data_v( | ||
76 | fecs_feature_override_ecc)) { | ||
77 | __nvgpu_set_enabled(g, | ||
78 | NVGPU_ECC_ENABLED_SM_L1_DATA, true); | ||
79 | } | ||
80 | } else { | ||
81 | if (opt_ecc_en) { | ||
82 | __nvgpu_set_enabled(g, | ||
83 | NVGPU_ECC_ENABLED_SM_L1_DATA, true); | ||
84 | } | ||
85 | } | ||
86 | /* SM L1 TAG*/ | ||
87 | if (gr_fecs_feature_override_ecc_sm_l1_tag_override_v( | ||
88 | fecs_feature_override_ecc)) { | ||
89 | if (gr_fecs_feature_override_ecc_sm_l1_tag_v( | ||
90 | fecs_feature_override_ecc)) { | ||
91 | __nvgpu_set_enabled(g, | ||
92 | NVGPU_ECC_ENABLED_SM_L1_TAG, true); | ||
93 | } | ||
94 | } else { | ||
95 | if (opt_ecc_en) { | ||
96 | __nvgpu_set_enabled(g, | ||
97 | NVGPU_ECC_ENABLED_SM_L1_TAG, true); | ||
98 | } | ||
99 | } | ||
100 | /* SM ICACHE*/ | ||
101 | if (gr_fecs_feature_override_ecc_1_sm_l0_icache_override_v( | ||
102 | fecs_feature_override_ecc) && | ||
103 | gr_fecs_feature_override_ecc_1_sm_l1_icache_override_v( | ||
104 | fecs_feature_override_ecc)) { | ||
105 | if (gr_fecs_feature_override_ecc_1_sm_l0_icache_v( | ||
106 | fecs_feature_override_ecc) && | ||
107 | gr_fecs_feature_override_ecc_1_sm_l1_icache_v( | ||
108 | fecs_feature_override_ecc)) { | ||
109 | __nvgpu_set_enabled(g, | ||
110 | NVGPU_ECC_ENABLED_SM_ICACHE, true); | ||
111 | } | ||
112 | } else { | ||
113 | if (opt_ecc_en) { | ||
114 | __nvgpu_set_enabled(g, | ||
115 | NVGPU_ECC_ENABLED_SM_ICACHE, true); | ||
116 | } | ||
117 | } | ||
118 | /* LTC */ | ||
119 | if (gr_fecs_feature_override_ecc_ltc_override_v( | ||
120 | fecs_feature_override_ecc)) { | ||
121 | if (gr_fecs_feature_override_ecc_ltc_v( | ||
122 | fecs_feature_override_ecc)) { | ||
123 | __nvgpu_set_enabled(g, | ||
124 | NVGPU_ECC_ENABLED_LTC, true); | ||
125 | } | ||
126 | } else { | ||
127 | if (opt_ecc_en) { | ||
128 | __nvgpu_set_enabled(g, | ||
129 | NVGPU_ECC_ENABLED_LTC, true); | ||
130 | } | ||
131 | } | ||
132 | /* SM CBU */ | ||
133 | if (gr_fecs_feature_override_ecc_sm_cbu_override_v( | ||
134 | fecs_feature_override_ecc)) { | ||
135 | if (gr_fecs_feature_override_ecc_sm_cbu_v( | ||
136 | fecs_feature_override_ecc)) { | ||
137 | __nvgpu_set_enabled(g, | ||
138 | NVGPU_ECC_ENABLED_SM_CBU, true); | ||
139 | } | ||
140 | } else { | ||
141 | if (opt_ecc_en) { | ||
142 | __nvgpu_set_enabled(g, | ||
143 | NVGPU_ECC_ENABLED_SM_CBU, true); | ||
144 | } | ||
145 | } | ||
146 | } | ||
147 | } | ||
148 | |||
149 | |||
150 | 29 | ||
151 | int gv11b_init_gpu_characteristics(struct gk20a *g) | 30 | int gv11b_init_gpu_characteristics(struct gk20a *g) |
152 | { | 31 | { |
diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.h b/drivers/gpu/nvgpu/gv11b/gv11b.h index 17dfa7aa..3d5490e6 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gv11b.h | |||
@@ -27,7 +27,6 @@ | |||
27 | 27 | ||
28 | #include "gk20a/gk20a.h" | 28 | #include "gk20a/gk20a.h" |
29 | 29 | ||
30 | void gv11b_detect_ecc_enabled_units(struct gk20a *g); | ||
31 | int gv11b_init_gpu_characteristics(struct gk20a *g); | 30 | int gv11b_init_gpu_characteristics(struct gk20a *g); |
32 | 31 | ||
33 | #endif /* GV11B_H */ | 32 | #endif /* GV11B_H */ |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 325285a6..00367e5b 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -790,6 +790,9 @@ static const struct gpu_ops gv11b_ops = { | |||
790 | }, | 790 | }, |
791 | .fuse = { | 791 | .fuse = { |
792 | .check_priv_security = gp10b_fuse_check_priv_security, | 792 | .check_priv_security = gp10b_fuse_check_priv_security, |
793 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, | ||
794 | .is_opt_feature_override_disable = | ||
795 | gp10b_fuse_is_opt_feature_override_disable, | ||
793 | }, | 796 | }, |
794 | .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, | 797 | .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, |
795 | .get_litter_value = gv11b_get_litter_value, | 798 | .get_litter_value = gv11b_get_litter_value, |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 421f3692..090ac7b4 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -56,6 +56,7 @@ | |||
56 | #include "gp10b/regops_gp10b.h" | 56 | #include "gp10b/regops_gp10b.h" |
57 | #include "gp10b/therm_gp10b.h" | 57 | #include "gp10b/therm_gp10b.h" |
58 | #include "gp10b/priv_ring_gp10b.h" | 58 | #include "gp10b/priv_ring_gp10b.h" |
59 | #include "gp10b/fuse_gp10b.h" | ||
59 | 60 | ||
60 | #include "gm20b/ltc_gm20b.h" | 61 | #include "gm20b/ltc_gm20b.h" |
61 | #include "gm20b/gr_gm20b.h" | 62 | #include "gm20b/gr_gm20b.h" |
@@ -559,6 +560,9 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
559 | }, | 560 | }, |
560 | .fuse = { | 561 | .fuse = { |
561 | .check_priv_security = vgpu_gp10b_fuse_check_priv_security, | 562 | .check_priv_security = vgpu_gp10b_fuse_check_priv_security, |
563 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, | ||
564 | .is_opt_feature_override_disable = | ||
565 | gp10b_fuse_is_opt_feature_override_disable, | ||
562 | }, | 566 | }, |
563 | .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, | 567 | .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, |
564 | .get_litter_value = gp10b_get_litter_value, | 568 | .get_litter_value = gp10b_get_litter_value, |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 38f9a184..386389b7 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -64,6 +64,7 @@ | |||
64 | #include <gp10b/therm_gp10b.h> | 64 | #include <gp10b/therm_gp10b.h> |
65 | #include <gp10b/priv_ring_gp10b.h> | 65 | #include <gp10b/priv_ring_gp10b.h> |
66 | #include <gp10b/ltc_gp10b.h> | 66 | #include <gp10b/ltc_gp10b.h> |
67 | #include <gp10b/fuse_gp10b.h> | ||
67 | 68 | ||
68 | #include <gp106/pmu_gp106.h> | 69 | #include <gp106/pmu_gp106.h> |
69 | #include <gp106/acr_gp106.h> | 70 | #include <gp106/acr_gp106.h> |
@@ -628,6 +629,11 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
628 | .set_ppriv_timeout_settings = | 629 | .set_ppriv_timeout_settings = |
629 | gk20a_priv_set_timeout_settings, | 630 | gk20a_priv_set_timeout_settings, |
630 | }, | 631 | }, |
632 | .fuse = { | ||
633 | .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, | ||
634 | .is_opt_feature_override_disable = | ||
635 | gp10b_fuse_is_opt_feature_override_disable, | ||
636 | }, | ||
631 | .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics, | 637 | .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics, |
632 | .get_litter_value = gv11b_get_litter_value, | 638 | .get_litter_value = gv11b_get_litter_value, |
633 | }; | 639 | }; |