diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/gr_gp106.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/gr_gp106.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/pmu_gp106.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/pmu_gp106.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/enabled.h | 1 |
17 files changed, 65 insertions, 45 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 8728c9a7..8135f05e 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -992,7 +992,6 @@ struct gpu_ops { | |||
992 | struct { | 992 | struct { |
993 | void (*isr)(struct gk20a *g); | 993 | void (*isr)(struct gk20a *g); |
994 | } priv_ring; | 994 | } priv_ring; |
995 | bool privsecurity; | ||
996 | }; | 995 | }; |
997 | 996 | ||
998 | struct nvgpu_bios_ucode { | 997 | struct nvgpu_bios_ucode { |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 5d9cc32c..f60d880d 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -42,7 +42,7 @@ static void gr_gm20b_init_gpc_mmu(struct gk20a *g) | |||
42 | 42 | ||
43 | gk20a_dbg_info("initialize gpc mmu"); | 43 | gk20a_dbg_info("initialize gpc mmu"); |
44 | 44 | ||
45 | if (!g->ops.privsecurity) { | 45 | if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |
46 | /* Bypass MMU check for non-secure boot. For | 46 | /* Bypass MMU check for non-secure boot. For |
47 | * secure-boot,this register write has no-effect */ | 47 | * secure-boot,this register write has no-effect */ |
48 | gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff); | 48 | gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff); |
@@ -680,7 +680,7 @@ static int gr_gm20b_load_ctxsw_ucode_segments(struct gk20a *g, u64 addr_base, | |||
680 | gr_gk20a_load_ctxsw_ucode_boot(g, addr_base, segments, reg_offset); | 680 | gr_gk20a_load_ctxsw_ucode_boot(g, addr_base, segments, reg_offset); |
681 | 681 | ||
682 | /* start the falcon immediately if PRIV security is disabled*/ | 682 | /* start the falcon immediately if PRIV security is disabled*/ |
683 | if (!g->ops.privsecurity) { | 683 | if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |
684 | gk20a_writel(g, reg_offset + gr_fecs_cpuctl_r(), | 684 | gk20a_writel(g, reg_offset + gr_fecs_cpuctl_r(), |
685 | gr_fecs_cpuctl_startcpu_f(0x01)); | 685 | gr_fecs_cpuctl_startcpu_f(0x01)); |
686 | } | 686 | } |
@@ -1542,8 +1542,10 @@ static void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | |||
1542 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset, 0); | 1542 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset, 0); |
1543 | } | 1543 | } |
1544 | 1544 | ||
1545 | void gm20b_init_gr(struct gpu_ops *gops) | 1545 | void gm20b_init_gr(struct gk20a *g) |
1546 | { | 1546 | { |
1547 | struct gpu_ops *gops = &g->ops; | ||
1548 | |||
1547 | gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; | 1549 | gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; |
1548 | gops->gr.bundle_cb_defaults = gr_gm20b_bundle_cb_defaults; | 1550 | gops->gr.bundle_cb_defaults = gr_gm20b_bundle_cb_defaults; |
1549 | gops->gr.cb_size_default = gr_gm20b_cb_size_default; | 1551 | gops->gr.cb_size_default = gr_gm20b_cb_size_default; |
@@ -1565,7 +1567,7 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
1565 | gops->gr.init_fs_state = gr_gm20b_init_fs_state; | 1567 | gops->gr.init_fs_state = gr_gm20b_init_fs_state; |
1566 | gops->gr.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask; | 1568 | gops->gr.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask; |
1567 | gops->gr.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments; | 1569 | gops->gr.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments; |
1568 | if (gops->privsecurity) | 1570 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) |
1569 | gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; | 1571 | gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; |
1570 | else | 1572 | else |
1571 | gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; | 1573 | gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index e7dd091a..d3adacd8 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |||
@@ -36,7 +36,7 @@ enum { | |||
36 | #define NVB1C0_SET_RD_COALESCE 0x0228 | 36 | #define NVB1C0_SET_RD_COALESCE 0x0228 |
37 | 37 | ||
38 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 | 38 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 |
39 | void gm20b_init_gr(struct gpu_ops *gops); | 39 | void gm20b_init_gr(struct gk20a *g); |
40 | void gr_gm20b_commit_global_attrib_cb(struct gk20a *g, | 40 | void gr_gm20b_commit_global_attrib_cb(struct gk20a *g, |
41 | struct channel_ctx_gk20a *ch_ctx, | 41 | struct channel_ctx_gk20a *ch_ctx, |
42 | u64 addr, bool patch); | 42 | u64 addr, bool patch); |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 01e277ce..228e1a97 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -356,38 +356,38 @@ int gm20b_init_hal(struct gk20a *g) | |||
356 | 356 | ||
357 | #ifdef CONFIG_TEGRA_ACR | 357 | #ifdef CONFIG_TEGRA_ACR |
358 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 358 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { |
359 | gops->privsecurity = 1; | 359 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
360 | } else { | 360 | } else { |
361 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | 361 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); |
362 | if (!val) { | 362 | if (!val) { |
363 | gk20a_dbg_info("priv security is disabled in HW"); | 363 | gk20a_dbg_info("priv security is disabled in HW"); |
364 | gops->privsecurity = 0; | 364 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); |
365 | } else { | 365 | } else { |
366 | gops->privsecurity = 1; | 366 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
367 | } | 367 | } |
368 | } | 368 | } |
369 | #else | 369 | #else |
370 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 370 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { |
371 | gk20a_dbg_info("running ASIM with PRIV security disabled"); | 371 | gk20a_dbg_info("running ASIM with PRIV security disabled"); |
372 | gops->privsecurity = 0; | 372 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); |
373 | } else { | 373 | } else { |
374 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | 374 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); |
375 | if (!val) { | 375 | if (!val) { |
376 | gops->privsecurity = 0; | 376 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); |
377 | } else { | 377 | } else { |
378 | gk20a_dbg_info("priv security is not supported but enabled"); | 378 | gk20a_dbg_info("priv security is not supported but enabled"); |
379 | gops->privsecurity = 1; | 379 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
380 | return -EPERM; | 380 | return -EPERM; |
381 | } | 381 | } |
382 | } | 382 | } |
383 | #endif | 383 | #endif |
384 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | 384 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; |
385 | gm20b_init_gr(gops); | 385 | gm20b_init_gr(g); |
386 | gm20b_init_fb(gops); | 386 | gm20b_init_fb(gops); |
387 | gm20b_init_ce2(gops); | 387 | gm20b_init_ce2(gops); |
388 | gm20b_init_gr_ctx(gops); | 388 | gm20b_init_gr_ctx(gops); |
389 | gm20b_init_mm(gops); | 389 | gm20b_init_mm(gops); |
390 | gm20b_init_pmu_ops(gops); | 390 | gm20b_init_pmu_ops(g); |
391 | gm20b_init_clk_ops(gops); | 391 | gm20b_init_clk_ops(gops); |
392 | gm20b_init_regops(gops); | 392 | gm20b_init_regops(gops); |
393 | gm20b_init_therm_ops(gops); | 393 | gm20b_init_therm_ops(gops); |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 0f99c67e..98cd3906 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <nvgpu/timers.h> | 16 | #include <nvgpu/timers.h> |
17 | #include <nvgpu/pmu.h> | 17 | #include <nvgpu/pmu.h> |
18 | #include <nvgpu/fuse.h> | 18 | #include <nvgpu/fuse.h> |
19 | #include <nvgpu/enabled.h> | ||
19 | 20 | ||
20 | #include "gk20a/gk20a.h" | 21 | #include "gk20a/gk20a.h" |
21 | #include "gk20a/pmu_gk20a.h" | 22 | #include "gk20a/pmu_gk20a.h" |
@@ -273,9 +274,11 @@ static void pmu_dump_security_fuses_gm20b(struct gk20a *g) | |||
273 | val); | 274 | val); |
274 | } | 275 | } |
275 | 276 | ||
276 | void gm20b_init_pmu_ops(struct gpu_ops *gops) | 277 | void gm20b_init_pmu_ops(struct gk20a *g) |
277 | { | 278 | { |
278 | if (gops->privsecurity) { | 279 | struct gpu_ops *gops = &g->ops; |
280 | |||
281 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | ||
279 | gm20b_init_secure_pmu(gops); | 282 | gm20b_init_secure_pmu(gops); |
280 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | 283 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; |
281 | gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode; | 284 | gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode; |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h index e3deb6ef..424fab35 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B PMU | 2 | * GM20B PMU |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -16,7 +16,9 @@ | |||
16 | #ifndef __PMU_GM20B_H_ | 16 | #ifndef __PMU_GM20B_H_ |
17 | #define __PMU_GM20B_H_ | 17 | #define __PMU_GM20B_H_ |
18 | 18 | ||
19 | void gm20b_init_pmu_ops(struct gpu_ops *gops); | 19 | struct gk20a; |
20 | |||
21 | void gm20b_init_pmu_ops(struct gk20a *g); | ||
20 | void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags); | 22 | void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags); |
21 | int gm20b_pmu_init_acr(struct gk20a *g); | 23 | int gm20b_pmu_init_acr(struct gk20a *g); |
22 | void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr); | 24 | void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr); |
diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c index bf266b66..76e5cf89 100644 --- a/drivers/gpu/nvgpu/gp106/gr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c | |||
@@ -234,9 +234,11 @@ fail: | |||
234 | return err; | 234 | return err; |
235 | } | 235 | } |
236 | 236 | ||
237 | void gp106_init_gr(struct gpu_ops *gops) | 237 | void gp106_init_gr(struct gk20a *g) |
238 | { | 238 | { |
239 | gp10b_init_gr(gops); | 239 | struct gpu_ops *gops = &g->ops; |
240 | |||
241 | gp10b_init_gr(g); | ||
240 | gops->gr.is_valid_class = gr_gp106_is_valid_class; | 242 | gops->gr.is_valid_class = gr_gp106_is_valid_class; |
241 | gops->gr.pagepool_default_size = gr_gp106_pagepool_default_size; | 243 | gops->gr.pagepool_default_size = gr_gp106_pagepool_default_size; |
242 | gops->gr.handle_sw_method = gr_gp106_handle_sw_method; | 244 | gops->gr.handle_sw_method = gr_gp106_handle_sw_method; |
diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.h b/drivers/gpu/nvgpu/gp106/gr_gp106.h index 4fe22ee9..3f49aac6 100644 --- a/drivers/gpu/nvgpu/gp106/gr_gp106.h +++ b/drivers/gpu/nvgpu/gp106/gr_gp106.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP106 GPU GR | 2 | * GP106 GPU GR |
3 | * | 3 | * |
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -16,11 +16,13 @@ | |||
16 | #ifndef _NVGPU_GR_GP106_H_ | 16 | #ifndef _NVGPU_GR_GP106_H_ |
17 | #define _NVGPU_GR_GP106_H_ | 17 | #define _NVGPU_GR_GP106_H_ |
18 | 18 | ||
19 | struct gk20a; | ||
20 | |||
19 | enum { | 21 | enum { |
20 | PASCAL_B = 0xC197, | 22 | PASCAL_B = 0xC197, |
21 | PASCAL_COMPUTE_B = 0xC1C0, | 23 | PASCAL_COMPUTE_B = 0xC1C0, |
22 | }; | 24 | }; |
23 | 25 | ||
24 | void gp106_init_gr(struct gpu_ops *gops); | 26 | void gp106_init_gr(struct gk20a *g); |
25 | 27 | ||
26 | #endif | 28 | #endif |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 80117ede..49c4b358 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -416,18 +416,18 @@ int gp106_init_hal(struct gk20a *g) | |||
416 | gp106_ops.chip_init_gpu_characteristics; | 416 | gp106_ops.chip_init_gpu_characteristics; |
417 | gops->bios_init = gp106_ops.bios_init; | 417 | gops->bios_init = gp106_ops.bios_init; |
418 | 418 | ||
419 | gops->privsecurity = 1; | 419 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
420 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | 420 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); |
421 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); | 421 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); |
422 | 422 | ||
423 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; | 423 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; |
424 | gp106_init_gr(gops); | 424 | gp106_init_gr(g); |
425 | gp10b_init_fecs_trace_ops(gops); | 425 | gp10b_init_fecs_trace_ops(gops); |
426 | gp106_init_fb(gops); | 426 | gp106_init_fb(gops); |
427 | gp10b_init_ce(gops); | 427 | gp10b_init_ce(gops); |
428 | gp106_init_gr_ctx(gops); | 428 | gp106_init_gr_ctx(gops); |
429 | gp106_init_mm(gops); | 429 | gp106_init_mm(gops); |
430 | gp106_init_pmu_ops(gops); | 430 | gp106_init_pmu_ops(g); |
431 | gp106_init_clk_ops(gops); | 431 | gp106_init_clk_ops(gops); |
432 | gp106_init_clk_arb_ops(gops); | 432 | gp106_init_clk_arb_ops(gops); |
433 | gp106_init_regops(gops); | 433 | gp106_init_regops(gops); |
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c index a09aa30b..a9fb794d 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c | |||
@@ -12,6 +12,7 @@ | |||
12 | */ | 12 | */ |
13 | 13 | ||
14 | #include <nvgpu/pmu.h> | 14 | #include <nvgpu/pmu.h> |
15 | #include <nvgpu/enabled.h> | ||
15 | 16 | ||
16 | #include "gk20a/gk20a.h" | 17 | #include "gk20a/gk20a.h" |
17 | #include "gk20a/pmu_gk20a.h" | 18 | #include "gk20a/pmu_gk20a.h" |
@@ -289,11 +290,11 @@ static int gp106_load_falcon_ucode(struct gk20a *g, u32 falconidmask) | |||
289 | return 0; | 290 | return 0; |
290 | } | 291 | } |
291 | 292 | ||
292 | void gp106_init_pmu_ops(struct gpu_ops *gops) | 293 | void gp106_init_pmu_ops(struct gk20a *g) |
293 | { | 294 | { |
295 | struct gpu_ops *gops = &g->ops; | ||
294 | gk20a_dbg_fn(""); | 296 | gk20a_dbg_fn(""); |
295 | 297 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | |
296 | if (gops->privsecurity) { | ||
297 | gp106_init_secure_pmu(gops); | 298 | gp106_init_secure_pmu(gops); |
298 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | 299 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; |
299 | gops->pmu.load_lsfalcon_ucode = gp106_load_falcon_ucode; | 300 | gops->pmu.load_lsfalcon_ucode = gp106_load_falcon_ucode; |
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.h b/drivers/gpu/nvgpu/gp106/pmu_gp106.h index 5f399b89..68a00bb5 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.h +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.h | |||
@@ -17,7 +17,9 @@ | |||
17 | #define gp106_dbg_pmu(fmt, arg...) \ | 17 | #define gp106_dbg_pmu(fmt, arg...) \ |
18 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) | 18 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) |
19 | 19 | ||
20 | void gp106_init_pmu_ops(struct gpu_ops *gops); | 20 | struct gk20a; |
21 | |||
22 | void gp106_init_pmu_ops(struct gk20a *g); | ||
21 | void gp106_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, | 23 | void gp106_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, |
22 | struct pmu_pg_stats_data *pg_stat_data); | 24 | struct pmu_pg_stats_data *pg_stat_data); |
23 | bool gp106_pmu_is_engine_in_reset(struct gk20a *g); | 25 | bool gp106_pmu_is_engine_in_reset(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 67a38e6e..d2b86e51 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -2368,9 +2368,11 @@ int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch) | |||
2368 | return __gr_gk20a_exec_ctx_ops(ch, &ops, 1, 1, 0, false); | 2368 | return __gr_gk20a_exec_ctx_ops(ch, &ops, 1, 1, 0, false); |
2369 | } | 2369 | } |
2370 | 2370 | ||
2371 | void gp10b_init_gr(struct gpu_ops *gops) | 2371 | void gp10b_init_gr(struct gk20a *g) |
2372 | { | 2372 | { |
2373 | gm20b_init_gr(gops); | 2373 | struct gpu_ops *gops = &g->ops; |
2374 | |||
2375 | gm20b_init_gr(g); | ||
2374 | gops->gr.init_fs_state = gr_gp10b_init_fs_state; | 2376 | gops->gr.init_fs_state = gr_gp10b_init_fs_state; |
2375 | gops->gr.init_preemption_state = gr_gp10b_init_preemption_state; | 2377 | gops->gr.init_preemption_state = gr_gp10b_init_preemption_state; |
2376 | gops->gr.is_valid_class = gr_gp10b_is_valid_class; | 2378 | gops->gr.is_valid_class = gr_gp10b_is_valid_class; |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index aac9eb65..161fec87 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h | |||
@@ -20,7 +20,7 @@ | |||
20 | 20 | ||
21 | #include "gk20a/mm_gk20a.h" | 21 | #include "gk20a/mm_gk20a.h" |
22 | 22 | ||
23 | struct gpu_ops; | 23 | struct gk20a; |
24 | struct gr_gk20a_isr_data; | 24 | struct gr_gk20a_isr_data; |
25 | 25 | ||
26 | enum { | 26 | enum { |
@@ -41,7 +41,7 @@ enum { | |||
41 | #define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528 | 41 | #define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528 |
42 | #define NVC0C0_SET_RD_COALESCE 0x0228 | 42 | #define NVC0C0_SET_RD_COALESCE 0x0228 |
43 | 43 | ||
44 | void gp10b_init_gr(struct gpu_ops *ops); | 44 | void gp10b_init_gr(struct gk20a *g); |
45 | int gr_gp10b_init_fs_state(struct gk20a *g); | 45 | int gr_gp10b_init_fs_state(struct gk20a *g); |
46 | int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size, | 46 | int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size, |
47 | struct nvgpu_mem *mem); | 47 | struct nvgpu_mem *mem); |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 818949f0..6b4fbf40 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -368,49 +368,49 @@ int gp10b_init_hal(struct gk20a *g) | |||
368 | 368 | ||
369 | #ifdef CONFIG_TEGRA_ACR | 369 | #ifdef CONFIG_TEGRA_ACR |
370 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 370 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { |
371 | gops->privsecurity = 0; | 371 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); |
372 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | 372 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
373 | } else if (g->is_virtual) { | 373 | } else if (g->is_virtual) { |
374 | gops->privsecurity = 1; | 374 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
375 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | 375 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); |
376 | } else { | 376 | } else { |
377 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | 377 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); |
378 | if (val) { | 378 | if (val) { |
379 | gops->privsecurity = 1; | 379 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
380 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | 380 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); |
381 | } else { | 381 | } else { |
382 | gk20a_dbg_info("priv security is disabled in HW"); | 382 | gk20a_dbg_info("priv security is disabled in HW"); |
383 | gops->privsecurity = 0; | 383 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); |
384 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | 384 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
385 | } | 385 | } |
386 | } | 386 | } |
387 | #else | 387 | #else |
388 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 388 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { |
389 | gk20a_dbg_info("running simulator with PRIV security disabled"); | 389 | gk20a_dbg_info("running simulator with PRIV security disabled"); |
390 | gops->privsecurity = 0; | 390 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); |
391 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | 391 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
392 | } else { | 392 | } else { |
393 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | 393 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); |
394 | if (val) { | 394 | if (val) { |
395 | gk20a_dbg_info("priv security is not supported but enabled"); | 395 | gk20a_dbg_info("priv security is not supported but enabled"); |
396 | gops->privsecurity = 1; | 396 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
397 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | 397 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); |
398 | return -EPERM; | 398 | return -EPERM; |
399 | } else { | 399 | } else { |
400 | gops->privsecurity = 0; | 400 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); |
401 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | 401 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
402 | } | 402 | } |
403 | } | 403 | } |
404 | #endif | 404 | #endif |
405 | 405 | ||
406 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | 406 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; |
407 | gp10b_init_gr(gops); | 407 | gp10b_init_gr(g); |
408 | gp10b_init_fecs_trace_ops(gops); | 408 | gp10b_init_fecs_trace_ops(gops); |
409 | gp10b_init_fb(gops); | 409 | gp10b_init_fb(gops); |
410 | gp10b_init_ce(gops); | 410 | gp10b_init_ce(gops); |
411 | gp10b_init_gr_ctx(gops); | 411 | gp10b_init_gr_ctx(gops); |
412 | gp10b_init_mm(gops); | 412 | gp10b_init_mm(gops); |
413 | gp10b_init_pmu_ops(gops); | 413 | gp10b_init_pmu_ops(g); |
414 | gp10b_init_regops(gops); | 414 | gp10b_init_regops(gops); |
415 | gp10b_init_therm_ops(gops); | 415 | gp10b_init_therm_ops(gops); |
416 | gk20a_init_pramin_ops(gops); | 416 | gk20a_init_pramin_ops(gops); |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index dbaf3ebf..e9a9b922 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <nvgpu/pmu.h> | 16 | #include <nvgpu/pmu.h> |
17 | #include <nvgpu/log.h> | 17 | #include <nvgpu/log.h> |
18 | #include <nvgpu/fuse.h> | 18 | #include <nvgpu/fuse.h> |
19 | #include <nvgpu/enabled.h> | ||
19 | 20 | ||
20 | #include "gk20a/gk20a.h" | 21 | #include "gk20a/gk20a.h" |
21 | #include "gk20a/pmu_gk20a.h" | 22 | #include "gk20a/pmu_gk20a.h" |
@@ -391,10 +392,11 @@ static bool gp10b_is_pmu_supported(struct gk20a *g) | |||
391 | return true; | 392 | return true; |
392 | } | 393 | } |
393 | 394 | ||
394 | void gp10b_init_pmu_ops(struct gpu_ops *gops) | 395 | void gp10b_init_pmu_ops(struct gk20a *g) |
395 | { | 396 | { |
397 | struct gpu_ops *gops = &g->ops; | ||
396 | gops->pmu.is_pmu_supported = gp10b_is_pmu_supported; | 398 | gops->pmu.is_pmu_supported = gp10b_is_pmu_supported; |
397 | if (gops->privsecurity) { | 399 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |
398 | gm20b_init_secure_pmu(gops); | 400 | gm20b_init_secure_pmu(gops); |
399 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | 401 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; |
400 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; | 402 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h index 9fc6228d..5ba7bb9b 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h | |||
@@ -16,7 +16,9 @@ | |||
16 | #ifndef __PMU_GP10B_H_ | 16 | #ifndef __PMU_GP10B_H_ |
17 | #define __PMU_GP10B_H_ | 17 | #define __PMU_GP10B_H_ |
18 | 18 | ||
19 | void gp10b_init_pmu_ops(struct gpu_ops *gops); | 19 | struct gk20a; |
20 | |||
21 | void gp10b_init_pmu_ops(struct gk20a *g); | ||
20 | int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask); | 22 | int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask); |
21 | int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); | 23 | int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); |
22 | void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr); | 24 | void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index 7d495f48..7aac4be9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h | |||
@@ -42,6 +42,7 @@ struct gk20a; | |||
42 | */ | 42 | */ |
43 | 43 | ||
44 | #define NVGPU_SEC_SECUREGPCCS 32 | 44 | #define NVGPU_SEC_SECUREGPCCS 32 |
45 | #define NVGPU_SEC_PRIVSECURITY 33 | ||
45 | 46 | ||
46 | /* | 47 | /* |
47 | * PMU flags. | 48 | * PMU flags. |