diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_fw.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | 19 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlvolt.h | 15 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/bios.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h | 61 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pstate/pstate.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_pmu.c | 110 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_pmu.h | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_rail.c | 35 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_rail.h | 4 |
11 files changed, 270 insertions, 15 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c index 6a038317..1070579e 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c | |||
@@ -1299,6 +1299,12 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) | |||
1299 | boardobjgrp_pmugetstatus_impl_v1; | 1299 | boardobjgrp_pmugetstatus_impl_v1; |
1300 | g->ops.pmu_ver.boardobj.is_boardobjgrp_pmucmd_id_valid = | 1300 | g->ops.pmu_ver.boardobj.is_boardobjgrp_pmucmd_id_valid = |
1301 | is_boardobjgrp_pmucmd_id_valid_v1; | 1301 | is_boardobjgrp_pmucmd_id_valid_v1; |
1302 | g->ops.pmu_ver.volt.volt_set_voltage = | ||
1303 | nvgpu_volt_set_voltage_gv10x; | ||
1304 | g->ops.pmu_ver.volt.volt_get_voltage = | ||
1305 | nvgpu_volt_rail_get_voltage_gv10x; | ||
1306 | g->ops.pmu_ver.volt.volt_send_load_cmd_to_pmu = | ||
1307 | nvgpu_volt_send_load_cmd_to_pmu_gv10x; | ||
1302 | } else { | 1308 | } else { |
1303 | g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params = | 1309 | g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params = |
1304 | get_pmu_init_msg_pmu_queue_params_v4; | 1310 | get_pmu_init_msg_pmu_queue_params_v4; |
@@ -1458,6 +1464,12 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) | |||
1458 | boardobjgrp_pmugetstatus_impl; | 1464 | boardobjgrp_pmugetstatus_impl; |
1459 | g->ops.pmu_ver.boardobj.is_boardobjgrp_pmucmd_id_valid = | 1465 | g->ops.pmu_ver.boardobj.is_boardobjgrp_pmucmd_id_valid = |
1460 | is_boardobjgrp_pmucmd_id_valid_v0; | 1466 | is_boardobjgrp_pmucmd_id_valid_v0; |
1467 | g->ops.pmu_ver.volt.volt_set_voltage = | ||
1468 | nvgpu_volt_set_voltage_gp10x; | ||
1469 | g->ops.pmu_ver.volt.volt_get_voltage = | ||
1470 | nvgpu_volt_rail_get_voltage_gp10x; | ||
1471 | g->ops.pmu_ver.volt.volt_send_load_cmd_to_pmu = | ||
1472 | nvgpu_volt_send_load_cmd_to_pmu_gp10x; | ||
1461 | break; | 1473 | break; |
1462 | case APP_VERSION_GM20B: | 1474 | case APP_VERSION_GM20B: |
1463 | g->ops.pmu_ver.pg_cmd_eng_buf_load_size = | 1475 | g->ops.pmu_ver.pg_cmd_eng_buf_load_size = |
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c index bb4edf38..d1058864 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | |||
@@ -1035,6 +1035,25 @@ static void pmu_rpc_handler(struct gk20a *g, struct pmu_msg *msg, | |||
1035 | break; | 1035 | break; |
1036 | } | 1036 | } |
1037 | break; | 1037 | break; |
1038 | case PMU_UNIT_VOLT: | ||
1039 | switch (rpc.function) { | ||
1040 | case NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD: | ||
1041 | nvgpu_pmu_dbg(g, | ||
1042 | "reply NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD"); | ||
1043 | break; | ||
1044 | case NV_PMU_RPC_ID_VOLT_VOLT_SET_VOLTAGE: | ||
1045 | nvgpu_pmu_dbg(g, | ||
1046 | "reply NV_PMU_RPC_ID_VOLT_VOLT_SET_VOLTAGE"); | ||
1047 | break; | ||
1048 | case NV_PMU_RPC_ID_VOLT_VOLT_RAIL_GET_VOLTAGE: | ||
1049 | nvgpu_pmu_dbg(g, | ||
1050 | "reply NV_PMU_RPC_ID_VOLT_VOLT_RAIL_GET_VOLTAGE"); | ||
1051 | break; | ||
1052 | case NV_PMU_RPC_ID_VOLT_LOAD: | ||
1053 | nvgpu_pmu_dbg(g, | ||
1054 | "reply NV_PMU_RPC_ID_VOLT_LOAD"); | ||
1055 | } | ||
1056 | break; | ||
1038 | /* TBD case will be added */ | 1057 | /* TBD case will be added */ |
1039 | default: | 1058 | default: |
1040 | nvgpu_err(g, " Invalid RPC response, stats 0x%x", | 1059 | nvgpu_err(g, " Invalid RPC response, stats 0x%x", |
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h index c99aa79f..1a82fbed 100644 --- a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h +++ b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * general p state infrastructure | 2 | * general p state infrastructure |
3 | * | 3 | * |
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -89,6 +89,7 @@ enum nv_pmu_pmgr_pwm_source { | |||
89 | #define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01 | 89 | #define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01 |
90 | #define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE 0x02 | 90 | #define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE 0x02 |
91 | #define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE 0x03 | 91 | #define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE 0x03 |
92 | #define CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN 0x04 | ||
92 | 93 | ||
93 | /*! | 94 | /*! |
94 | * Macros for Voltage Domains. | 95 | * Macros for Voltage Domains. |
@@ -126,4 +127,16 @@ struct ctrl_volt_volt_rail_list { | |||
126 | rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS]; | 127 | rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS]; |
127 | }; | 128 | }; |
128 | 129 | ||
130 | struct ctrl_volt_volt_rail_list_item_v1 { | ||
131 | u8 rail_idx; | ||
132 | u32 voltage_uv; | ||
133 | u32 voltage_min_noise_unaware_uv; | ||
134 | }; | ||
135 | |||
136 | struct ctrl_volt_volt_rail_list_v1 { | ||
137 | u8 num_rails; | ||
138 | struct ctrl_volt_volt_rail_list_item_v1 | ||
139 | rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS]; | ||
140 | }; | ||
141 | |||
129 | #endif | 142 | #endif |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 9a0cfd02..58570d6d 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -747,6 +747,13 @@ struct gpu_ops { | |||
747 | struct boardobjgrp *pboardobjgrp, | 747 | struct boardobjgrp *pboardobjgrp, |
748 | struct boardobjgrp_pmu_cmd *cmd); | 748 | struct boardobjgrp_pmu_cmd *cmd); |
749 | } boardobj; | 749 | } boardobj; |
750 | struct { | ||
751 | u32 (*volt_set_voltage)(struct gk20a *g, | ||
752 | u32 logic_voltage_uv, u32 sram_voltage_uv); | ||
753 | u32 (*volt_get_voltage)(struct gk20a *g, | ||
754 | u8 volt_domain, u32 *pvoltage_uv); | ||
755 | u32 (*volt_send_load_cmd_to_pmu)(struct gk20a *g); | ||
756 | } volt; | ||
750 | } pmu_ver; | 757 | } pmu_ver; |
751 | struct { | 758 | struct { |
752 | int (*get_netlist_name)(struct gk20a *g, int index, char *name); | 759 | int (*get_netlist_name)(struct gk20a *g, int index, char *name); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h index fb0a313f..75f8da35 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/bios.h +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h | |||
@@ -725,6 +725,7 @@ struct vbios_voltage_rail_table_1x_header { | |||
725 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09 0X00000009 | 725 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09 0X00000009 |
726 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A 0X0000000A | 726 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A 0X0000000A |
727 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B 0X0000000B | 727 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B 0X0000000B |
728 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0C 0X0000000C | ||
728 | 729 | ||
729 | struct vbios_voltage_rail_table_1x_entry { | 730 | struct vbios_voltage_rail_table_1x_entry { |
730 | u32 boot_voltage_uv; | 731 | u32 boot_voltage_uv; |
@@ -735,6 +736,7 @@ struct vbios_voltage_rail_table_1x_entry { | |||
735 | u8 boot_volt_vfe_equ_idx; | 736 | u8 boot_volt_vfe_equ_idx; |
736 | u8 vmin_limit_vfe_equ_idx; | 737 | u8 vmin_limit_vfe_equ_idx; |
737 | u8 volt_margin_limit_vfe_equ_idx; | 738 | u8 volt_margin_limit_vfe_equ_idx; |
739 | u8 volt_scale_exp_pwr_equ_idx; | ||
738 | } __packed; | 740 | } __packed; |
739 | 741 | ||
740 | /* Voltage Device Table */ | 742 | /* Voltage Device Table */ |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h index c3d540cc..3b286139 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -49,6 +49,8 @@ struct nv_pmu_volt_volt_rail_boardobj_set { | |||
49 | u8 volt_margin_limit_vfe_equ_idx; | 49 | u8 volt_margin_limit_vfe_equ_idx; |
50 | u8 pwr_equ_idx; | 50 | u8 pwr_equ_idx; |
51 | u8 volt_dev_idx_default; | 51 | u8 volt_dev_idx_default; |
52 | u8 volt_dev_idx_ipc_vmin; | ||
53 | u8 volt_scale_exp_pwr_equ_idx; | ||
52 | struct ctrl_boardobjgrp_mask_e32 volt_dev_mask; | 54 | struct ctrl_boardobjgrp_mask_e32 volt_dev_mask; |
53 | s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES]; | 55 | s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES]; |
54 | }; | 56 | }; |
@@ -101,7 +103,6 @@ NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_device); | |||
101 | 103 | ||
102 | /* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */ | 104 | /* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */ |
103 | struct nv_pmu_volt_volt_policy_boardobjgrp_set_header { | 105 | struct nv_pmu_volt_volt_policy_boardobjgrp_set_header { |
104 | |||
105 | struct nv_pmu_boardobjgrp_e32 super; | 106 | struct nv_pmu_boardobjgrp_e32 super; |
106 | }; | 107 | }; |
107 | 108 | ||
@@ -332,4 +333,60 @@ struct nv_pmu_volt_volt_rail_list { | |||
332 | rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS]; | 333 | rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS]; |
333 | }; | 334 | }; |
334 | 335 | ||
336 | struct nv_pmu_volt_volt_rail_list_V1 { | ||
337 | u8 num_rails; | ||
338 | struct ctrl_volt_volt_rail_list_item_v1 | ||
339 | rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS]; | ||
340 | }; | ||
341 | |||
342 | /* VOLT RPC */ | ||
343 | #define NV_PMU_RPC_ID_VOLT_BOARD_OBJ_GRP_CMD 0x00 | ||
344 | #define NV_PMU_RPC_ID_VOLT_VOLT_SET_VOLTAGE 0x01 | ||
345 | #define NV_PMU_RPC_ID_VOLT_LOAD 0x02 | ||
346 | #define NV_PMU_RPC_ID_VOLT_VOLT_RAIL_GET_VOLTAGE 0x03 | ||
347 | #define NV_PMU_RPC_ID_VOLT_VOLT_POLICY_SANITY_CHECK 0x04 | ||
348 | #define NV_PMU_RPC_ID_VOLT_TEST_EXECUTE 0x05 | ||
349 | #define NV_PMU_RPC_ID_VOLT__COUNT 0x06 | ||
350 | |||
351 | /* | ||
352 | * Defines the structure that holds data | ||
353 | * used to execute LOAD RPC. | ||
354 | */ | ||
355 | struct nv_pmu_rpc_struct_volt_load { | ||
356 | /*[IN/OUT] Must be first field in RPC structure */ | ||
357 | struct nv_pmu_rpc_header hdr; | ||
358 | u32 scratch[1]; | ||
359 | }; | ||
360 | |||
361 | /* | ||
362 | * Defines the structure that holds data | ||
363 | * used to execute VOLT_SET_VOLTAGE RPC. | ||
364 | */ | ||
365 | struct nv_pmu_rpc_struct_volt_volt_set_voltage { | ||
366 | /*[IN/OUT] Must be first field in RPC structure */ | ||
367 | struct nv_pmu_rpc_header hdr; | ||
368 | /*[IN] ID of the client that wants to set the voltage */ | ||
369 | u8 client_id; | ||
370 | /* | ||
371 | * [IN] The list containing target voltage and | ||
372 | * noise-unaware Vmin value for the VOLT_RAILs. | ||
373 | */ | ||
374 | struct ctrl_volt_volt_rail_list_v1 rail_list; | ||
375 | u32 scratch[1]; | ||
376 | }; | ||
377 | |||
378 | /* | ||
379 | * Defines the structure that holds data | ||
380 | * used to execute VOLT_RAIL_GET_VOLTAGE RPC. | ||
381 | */ | ||
382 | struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage { | ||
383 | /*[IN/OUT] Must be first field in RPC structure */ | ||
384 | struct nv_pmu_rpc_header hdr; | ||
385 | /* [OUT] Current voltage in uv */ | ||
386 | u32 voltage_uv; | ||
387 | /* [IN] Voltage Rail Table Index */ | ||
388 | u8 rail_idx; | ||
389 | u32 scratch[1]; | ||
390 | }; | ||
391 | |||
335 | #endif /* _GPMUIFVOLT_H_*/ | 392 | #endif /* _GPMUIFVOLT_H_*/ |
diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c index e164cc83..c3f34027 100644 --- a/drivers/gpu/nvgpu/pstate/pstate.c +++ b/drivers/gpu/nvgpu/pstate/pstate.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * general p state infrastructure | 2 | * general p state infrastructure |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -136,7 +136,7 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g) | |||
136 | if (err) | 136 | if (err) |
137 | return err; | 137 | return err; |
138 | 138 | ||
139 | err = volt_pmu_send_load_cmd_to_pmu(g); | 139 | err = g->ops.pmu_ver.volt.volt_send_load_cmd_to_pmu(g); |
140 | if (err) { | 140 | if (err) { |
141 | nvgpu_err(g, | 141 | nvgpu_err(g, |
142 | "Failed to send VOLT LOAD CMD to PMU: status = 0x%08x.", | 142 | "Failed to send VOLT LOAD CMD to PMU: status = 0x%08x.", |
diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.c b/drivers/gpu/nvgpu/volt/volt_pmu.c index 915db9a7..4608918c 100644 --- a/drivers/gpu/nvgpu/volt/volt_pmu.c +++ b/drivers/gpu/nvgpu/volt/volt_pmu.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -115,7 +115,7 @@ volt_pmu_rpc_execute: | |||
115 | return status; | 115 | return status; |
116 | } | 116 | } |
117 | 117 | ||
118 | u32 volt_pmu_send_load_cmd_to_pmu(struct gk20a *g) | 118 | u32 nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g) |
119 | { | 119 | { |
120 | struct nv_pmu_volt_rpc rpc_call = { 0 }; | 120 | struct nv_pmu_volt_rpc rpc_call = { 0 }; |
121 | u32 status = 0; | 121 | u32 status = 0; |
@@ -131,7 +131,23 @@ u32 volt_pmu_send_load_cmd_to_pmu(struct gk20a *g) | |||
131 | return status; | 131 | return status; |
132 | } | 132 | } |
133 | 133 | ||
134 | static u32 volt_rail_get_voltage(struct gk20a *g, | 134 | u32 nvgpu_volt_send_load_cmd_to_pmu_gv10x(struct gk20a *g) |
135 | { | ||
136 | struct nvgpu_pmu *pmu = &g->pmu; | ||
137 | struct nv_pmu_rpc_struct_volt_load rpc; | ||
138 | u32 status = 0; | ||
139 | |||
140 | memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_volt_load)); | ||
141 | PMU_RPC_EXECUTE(status, pmu, VOLT, LOAD, &rpc, 0); | ||
142 | if (status) { | ||
143 | nvgpu_err(g, "Failed to execute RPC status=0x%x", | ||
144 | status); | ||
145 | } | ||
146 | |||
147 | return status; | ||
148 | } | ||
149 | |||
150 | u32 nvgpu_volt_rail_get_voltage_gp10x(struct gk20a *g, | ||
135 | u8 volt_domain, u32 *pvoltage_uv) | 151 | u8 volt_domain, u32 *pvoltage_uv) |
136 | { | 152 | { |
137 | struct nv_pmu_volt_rpc rpc_call = { 0 }; | 153 | struct nv_pmu_volt_rpc rpc_call = { 0 }; |
@@ -165,6 +181,37 @@ static u32 volt_rail_get_voltage(struct gk20a *g, | |||
165 | return status; | 181 | return status; |
166 | } | 182 | } |
167 | 183 | ||
184 | u32 nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g, | ||
185 | u8 volt_domain, u32 *pvoltage_uv) | ||
186 | { | ||
187 | struct nvgpu_pmu *pmu = &g->pmu; | ||
188 | struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage rpc; | ||
189 | u32 status = 0; | ||
190 | u8 rail_idx; | ||
191 | |||
192 | rail_idx = volt_rail_volt_domain_convert_to_idx(g, volt_domain); | ||
193 | if ((rail_idx == CTRL_VOLT_RAIL_INDEX_INVALID) || | ||
194 | (!VOLT_RAIL_INDEX_IS_VALID(&g->perf_pmu.volt, rail_idx))) { | ||
195 | nvgpu_err(g, | ||
196 | "failed: volt_domain = %d, voltage rail table = %d.", | ||
197 | volt_domain, rail_idx); | ||
198 | return -EINVAL; | ||
199 | } | ||
200 | |||
201 | memset(&rpc, 0, | ||
202 | sizeof(struct nv_pmu_rpc_struct_volt_volt_rail_get_voltage)); | ||
203 | rpc.rail_idx = rail_idx; | ||
204 | |||
205 | PMU_RPC_EXECUTE_CPB(status, pmu, VOLT, VOLT_SET_VOLTAGE, &rpc, 0); | ||
206 | if (status) { | ||
207 | nvgpu_err(g, "Failed to execute RPC status=0x%x", | ||
208 | status); | ||
209 | } | ||
210 | |||
211 | *pvoltage_uv = rpc.voltage_uv; | ||
212 | |||
213 | return status; | ||
214 | } | ||
168 | 215 | ||
169 | static u32 volt_policy_set_voltage(struct gk20a *g, u8 client_id, | 216 | static u32 volt_policy_set_voltage(struct gk20a *g, u8 client_id, |
170 | struct ctrl_perf_volt_rail_list *prail_list) | 217 | struct ctrl_perf_volt_rail_list *prail_list) |
@@ -217,9 +264,54 @@ exit: | |||
217 | return status; | 264 | return status; |
218 | } | 265 | } |
219 | 266 | ||
220 | u32 volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv, u32 sram_voltage_uv) | 267 | static u32 volt_set_voltage_gv10x_rpc(struct gk20a *g, u8 client_id, |
268 | struct ctrl_volt_volt_rail_list_v1 *prail_list) | ||
221 | { | 269 | { |
222 | u32 status = 0; | 270 | struct nvgpu_pmu *pmu = &g->pmu; |
271 | struct nv_pmu_rpc_struct_volt_volt_set_voltage rpc; | ||
272 | int status = 0; | ||
273 | |||
274 | memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_volt_volt_set_voltage)); | ||
275 | rpc.client_id = 0x1; | ||
276 | rpc.rail_list = *prail_list; | ||
277 | |||
278 | PMU_RPC_EXECUTE(status, pmu, VOLT, VOLT_SET_VOLTAGE, &rpc, 0); | ||
279 | if (status) { | ||
280 | nvgpu_err(g, "Failed to execute RPC status=0x%x", | ||
281 | status); | ||
282 | } | ||
283 | |||
284 | return status; | ||
285 | } | ||
286 | |||
287 | u32 nvgpu_volt_set_voltage_gv10x(struct gk20a *g, u32 logic_voltage_uv, | ||
288 | u32 sram_voltage_uv) | ||
289 | { | ||
290 | int status = 0; | ||
291 | struct ctrl_volt_volt_rail_list_v1 rail_list = { 0 }; | ||
292 | |||
293 | rail_list.num_rails = RAIL_COUNT; | ||
294 | rail_list.rails[0].rail_idx = | ||
295 | volt_rail_volt_domain_convert_to_idx(g, | ||
296 | CTRL_VOLT_DOMAIN_LOGIC); | ||
297 | rail_list.rails[0].voltage_uv = logic_voltage_uv; | ||
298 | rail_list.rails[0].voltage_min_noise_unaware_uv = logic_voltage_uv; | ||
299 | rail_list.rails[1].rail_idx = | ||
300 | volt_rail_volt_domain_convert_to_idx(g, | ||
301 | CTRL_VOLT_DOMAIN_SRAM); | ||
302 | rail_list.rails[1].voltage_uv = sram_voltage_uv; | ||
303 | rail_list.rails[1].voltage_min_noise_unaware_uv = sram_voltage_uv; | ||
304 | |||
305 | status = volt_set_voltage_gv10x_rpc(g, | ||
306 | CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ, &rail_list); | ||
307 | |||
308 | return status; | ||
309 | } | ||
310 | |||
311 | u32 nvgpu_volt_set_voltage_gp10x(struct gk20a *g, u32 logic_voltage_uv, | ||
312 | u32 sram_voltage_uv) | ||
313 | { | ||
314 | int status = 0; | ||
223 | struct ctrl_perf_volt_rail_list rail_list = { 0 }; | 315 | struct ctrl_perf_volt_rail_list rail_list = { 0 }; |
224 | 316 | ||
225 | rail_list.num_rails = RAIL_COUNT; | 317 | rail_list.num_rails = RAIL_COUNT; |
@@ -234,12 +326,18 @@ u32 volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv, u32 sram_voltage_uv) | |||
234 | CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ, &rail_list); | 326 | CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ, &rail_list); |
235 | 327 | ||
236 | return status; | 328 | return status; |
329 | } | ||
237 | 330 | ||
331 | u32 volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv, u32 sram_voltage_uv) | ||
332 | { | ||
333 | return g->ops.pmu_ver.volt.volt_set_voltage(g, | ||
334 | logic_voltage_uv, sram_voltage_uv); | ||
238 | } | 335 | } |
239 | 336 | ||
240 | u32 volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv) | 337 | u32 volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv) |
241 | { | 338 | { |
242 | return volt_rail_get_voltage(g, volt_domain, voltage_uv); | 339 | return g->ops.pmu_ver.volt.volt_get_voltage(g, |
340 | volt_domain, voltage_uv); | ||
243 | } | 341 | } |
244 | 342 | ||
245 | static int volt_policy_set_noiseaware_vmin(struct gk20a *g, | 343 | static int volt_policy_set_noiseaware_vmin(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.h b/drivers/gpu/nvgpu/volt/volt_pmu.h index 55be9c45..fbdf7c1e 100644 --- a/drivers/gpu/nvgpu/volt/volt_pmu.h +++ b/drivers/gpu/nvgpu/volt/volt_pmu.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -29,4 +29,18 @@ u32 volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv, | |||
29 | u32 volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv); | 29 | u32 volt_get_voltage(struct gk20a *g, u32 volt_domain, u32 *voltage_uv); |
30 | int volt_set_noiseaware_vmin(struct gk20a *g, u32 logic_voltage_uv, | 30 | int volt_set_noiseaware_vmin(struct gk20a *g, u32 logic_voltage_uv, |
31 | u32 sram_voltage_uv); | 31 | u32 sram_voltage_uv); |
32 | |||
33 | u32 nvgpu_volt_set_voltage_gp10x(struct gk20a *g, u32 logic_voltage_uv, | ||
34 | u32 sram_voltage_uv); | ||
35 | u32 nvgpu_volt_rail_get_voltage_gp10x(struct gk20a *g, | ||
36 | u8 volt_domain, u32 *pvoltage_uv); | ||
37 | u32 nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g); | ||
38 | |||
39 | u32 nvgpu_volt_set_voltage_gv10x(struct gk20a *g, u32 logic_voltage_uv, | ||
40 | u32 sram_voltage_uv); | ||
41 | u32 nvgpu_volt_rail_get_voltage_gv10x(struct gk20a *g, | ||
42 | u8 volt_domain, u32 *pvoltage_uv); | ||
43 | u32 nvgpu_volt_send_load_cmd_to_pmu_gv10x(struct gk20a *g); | ||
44 | |||
45 | |||
32 | #endif | 46 | #endif |
diff --git a/drivers/gpu/nvgpu/volt/volt_rail.c b/drivers/gpu/nvgpu/volt/volt_rail.c index f78fc315..3461653f 100644 --- a/drivers/gpu/nvgpu/volt/volt_rail.c +++ b/drivers/gpu/nvgpu/volt/volt_rail.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -34,8 +34,10 @@ u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain) | |||
34 | { | 34 | { |
35 | switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) { | 35 | switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) { |
36 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL: | 36 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL: |
37 | if (volt_domain == CTRL_BOARDOBJ_IDX_INVALID) | 37 | switch (volt_domain) { |
38 | case CTRL_VOLT_DOMAIN_LOGIC: | ||
38 | return 0; | 39 | return 0; |
40 | } | ||
39 | break; | 41 | break; |
40 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL: | 42 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL: |
41 | switch (volt_domain) { | 43 | switch (volt_domain) { |
@@ -63,6 +65,22 @@ u32 volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail | |||
63 | status = -EINVAL; | 65 | status = -EINVAL; |
64 | goto exit; | 66 | goto exit; |
65 | } | 67 | } |
68 | } else if (operation_type == | ||
69 | CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN) { | ||
70 | if (pvolt_rail->volt_dev_idx_ipc_vmin == | ||
71 | CTRL_BOARDOBJ_IDX_INVALID) { | ||
72 | pvolt_rail->volt_dev_idx_ipc_vmin = volt_dev_idx; | ||
73 | /* | ||
74 | * Exit on purpose as we do not want to register | ||
75 | * IPC_VMIN device against the rail to avoid | ||
76 | * setting current voltage instead of | ||
77 | * IPC Vmin voltage. | ||
78 | */ | ||
79 | goto exit; | ||
80 | } else { | ||
81 | status = -EINVAL; | ||
82 | goto exit; | ||
83 | } | ||
66 | } else { | 84 | } else { |
67 | goto exit; | 85 | goto exit; |
68 | } | 86 | } |
@@ -136,6 +154,9 @@ static u32 volt_rail_init_pmudata_super(struct gk20a *g, | |||
136 | prail->volt_margin_limit_vfe_equ_idx; | 154 | prail->volt_margin_limit_vfe_equ_idx; |
137 | rail_pmu_data->pwr_equ_idx = prail->pwr_equ_idx; | 155 | rail_pmu_data->pwr_equ_idx = prail->pwr_equ_idx; |
138 | rail_pmu_data->volt_dev_idx_default = prail->volt_dev_idx_default; | 156 | rail_pmu_data->volt_dev_idx_default = prail->volt_dev_idx_default; |
157 | rail_pmu_data->volt_scale_exp_pwr_equ_idx = | ||
158 | prail->volt_scale_exp_pwr_equ_idx; | ||
159 | rail_pmu_data->volt_dev_idx_ipc_vmin = prail->volt_dev_idx_ipc_vmin; | ||
139 | 160 | ||
140 | for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { | 161 | for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { |
141 | rail_pmu_data->volt_delta_uv[i] = prail->volt_delta_uv[i] + | 162 | rail_pmu_data->volt_delta_uv[i] = prail->volt_delta_uv[i] + |
@@ -187,6 +208,8 @@ static struct voltage_rail *construct_volt_rail(struct gk20a *g, void *pargs) | |||
187 | ptemp_rail->vmin_limit_vfe_equ_idx; | 208 | ptemp_rail->vmin_limit_vfe_equ_idx; |
188 | board_obj_volt_rail_ptr->volt_margin_limit_vfe_equ_idx = | 209 | board_obj_volt_rail_ptr->volt_margin_limit_vfe_equ_idx = |
189 | ptemp_rail->volt_margin_limit_vfe_equ_idx; | 210 | ptemp_rail->volt_margin_limit_vfe_equ_idx; |
211 | board_obj_volt_rail_ptr->volt_scale_exp_pwr_equ_idx = | ||
212 | ptemp_rail->volt_scale_exp_pwr_equ_idx; | ||
190 | 213 | ||
191 | gk20a_dbg_info("Done"); | 214 | gk20a_dbg_info("Done"); |
192 | 215 | ||
@@ -285,6 +308,14 @@ static u32 volt_get_volt_rail_table(struct gk20a *g, | |||
285 | (u8)entry.ov_limit_vfe_equ_idx; | 308 | (u8)entry.ov_limit_vfe_equ_idx; |
286 | 309 | ||
287 | if (header.table_entry_size >= | 310 | if (header.table_entry_size >= |
311 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0C) | ||
312 | rail_type_data.volt_rail.volt_scale_exp_pwr_equ_idx = | ||
313 | (u8)entry.volt_scale_exp_pwr_equ_idx; | ||
314 | else | ||
315 | rail_type_data.volt_rail.volt_scale_exp_pwr_equ_idx = | ||
316 | CTRL_BOARDOBJ_IDX_INVALID; | ||
317 | |||
318 | if (header.table_entry_size >= | ||
288 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B) | 319 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B) |
289 | rail_type_data.volt_rail.volt_margin_limit_vfe_equ_idx = | 320 | rail_type_data.volt_rail.volt_margin_limit_vfe_equ_idx = |
290 | (u8)entry.volt_margin_limit_vfe_equ_idx; | 321 | (u8)entry.volt_margin_limit_vfe_equ_idx; |
diff --git a/drivers/gpu/nvgpu/volt/volt_rail.h b/drivers/gpu/nvgpu/volt/volt_rail.h index 9a3fcda0..be3cbb72 100644 --- a/drivers/gpu/nvgpu/volt/volt_rail.h +++ b/drivers/gpu/nvgpu/volt/volt_rail.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -51,7 +51,9 @@ struct voltage_rail { | |||
51 | u8 alt_rel_limit_vfe_equ_idx; | 51 | u8 alt_rel_limit_vfe_equ_idx; |
52 | u8 ov_limit_vfe_equ_idx; | 52 | u8 ov_limit_vfe_equ_idx; |
53 | u8 pwr_equ_idx; | 53 | u8 pwr_equ_idx; |
54 | u8 volt_scale_exp_pwr_equ_idx; | ||
54 | u8 volt_dev_idx_default; | 55 | u8 volt_dev_idx_default; |
56 | u8 volt_dev_idx_ipc_vmin; | ||
55 | u8 boot_volt_vfe_equ_idx; | 57 | u8 boot_volt_vfe_equ_idx; |
56 | u8 vmin_limit_vfe_equ_idx; | 58 | u8 vmin_limit_vfe_equ_idx; |
57 | u8 volt_margin_limit_vfe_equ_idx; | 59 | u8 volt_margin_limit_vfe_equ_idx; |