diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 51 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 67 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 32 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/pmu_gv11b.h | 5 |
4 files changed, 122 insertions, 33 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 74bc48fb..bd13ec08 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -32,19 +32,23 @@ | |||
32 | #include "gk20a/regops_gk20a.h" | 32 | #include "gk20a/regops_gk20a.h" |
33 | #include "gk20a/fb_gk20a.h" | 33 | #include "gk20a/fb_gk20a.h" |
34 | #include "gk20a/mm_gk20a.h" | 34 | #include "gk20a/mm_gk20a.h" |
35 | #include "gk20a/pmu_gk20a.h" | ||
35 | 36 | ||
36 | #include "gm20b/ltc_gm20b.h" | 37 | #include "gm20b/ltc_gm20b.h" |
37 | #include "gm20b/gr_gm20b.h" | 38 | #include "gm20b/gr_gm20b.h" |
38 | #include "gm20b/fifo_gm20b.h" | 39 | #include "gm20b/fifo_gm20b.h" |
39 | #include "gm20b/fb_gm20b.h" | 40 | #include "gm20b/fb_gm20b.h" |
40 | #include "gm20b/mm_gm20b.h" | 41 | #include "gm20b/mm_gm20b.h" |
42 | #include "gm20b/pmu_gm20b.h" | ||
43 | #include "gm20b/acr_gm20b.h" | ||
41 | 44 | ||
42 | #include "gp10b/fb_gp10b.h" | 45 | #include "gp10b/fb_gp10b.h" |
43 | 46 | ||
44 | #include "gp106/clk_gp106.h" | 47 | #include "gp106/clk_gp106.h" |
45 | #include "gp106/clk_arb_gp106.h" | 48 | #include "gp106/clk_arb_gp106.h" |
46 | #include "gp106/pmu_gp106.h" | 49 | #include "gp106/pmu_gp106.h" |
47 | 50 | #include "gp106/acr_gp106.h" | |
51 | #include "gp106/sec2_gp106.h" | ||
48 | #include "gm206/bios_gm206.h" | 52 | #include "gm206/bios_gm206.h" |
49 | #include "gp106/therm_gp106.h" | 53 | #include "gp106/therm_gp106.h" |
50 | #include "gp106/xve_gp106.h" | 54 | #include "gp106/xve_gp106.h" |
@@ -58,6 +62,7 @@ | |||
58 | #include "gp10b/fifo_gp10b.h" | 62 | #include "gp10b/fifo_gp10b.h" |
59 | #include "gp10b/fecs_trace_gp10b.h" | 63 | #include "gp10b/fecs_trace_gp10b.h" |
60 | #include "gp10b/mm_gp10b.h" | 64 | #include "gp10b/mm_gp10b.h" |
65 | #include "gp10b/pmu_gp10b.h" | ||
61 | 66 | ||
62 | #include "gv11b/hal_gv11b.h" | 67 | #include "gv11b/hal_gv11b.h" |
63 | #include "gv11b/gr_gv11b.h" | 68 | #include "gv11b/gr_gv11b.h" |
@@ -87,6 +92,7 @@ | |||
87 | #include <nvgpu/hw/gv100/hw_ram_gv100.h> | 92 | #include <nvgpu/hw/gv100/hw_ram_gv100.h> |
88 | #include <nvgpu/hw/gv100/hw_top_gv100.h> | 93 | #include <nvgpu/hw/gv100/hw_top_gv100.h> |
89 | #include <nvgpu/hw/gv100/hw_pram_gv100.h> | 94 | #include <nvgpu/hw/gv100/hw_pram_gv100.h> |
95 | #include <nvgpu/hw/gv100/hw_pwr_gv100.h> | ||
90 | 96 | ||
91 | static int gv100_get_litter_value(struct gk20a *g, int value) | 97 | static int gv100_get_litter_value(struct gk20a *g, int value) |
92 | { | 98 | { |
@@ -345,6 +351,45 @@ static const struct gpu_ops gv100_ops = { | |||
345 | .exit = gk20a_pramin_exit, | 351 | .exit = gk20a_pramin_exit, |
346 | .data032_r = pram_data032_r, | 352 | .data032_r = pram_data032_r, |
347 | }, | 353 | }, |
354 | .pmu = { | ||
355 | .init_wpr_region = gm20b_pmu_init_acr, | ||
356 | .load_lsfalcon_ucode = gp106_load_falcon_ucode, | ||
357 | .is_lazy_bootstrap = gp106_is_lazy_bootstrap, | ||
358 | .is_priv_load = gp106_is_priv_load, | ||
359 | .prepare_ucode = gp106_prepare_ucode_blob, | ||
360 | .pmu_setup_hw_and_bootstrap = gp106_bootstrap_hs_flcn, | ||
361 | .get_wpr = gp106_wpr_info, | ||
362 | .alloc_blob_space = gp106_alloc_blob_space, | ||
363 | .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg, | ||
364 | .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc, | ||
365 | .falcon_wait_for_halt = sec2_wait_for_halt, | ||
366 | .falcon_clear_halt_interrupt_status = | ||
367 | sec2_clear_halt_interrupt_status, | ||
368 | .init_falcon_setup_hw = init_sec2_setup_hw1, | ||
369 | .pmu_queue_tail = gk20a_pmu_queue_tail, | ||
370 | .pmu_get_queue_head = pwr_pmu_queue_head_r, | ||
371 | .pmu_mutex_release = gk20a_pmu_mutex_release, | ||
372 | .is_pmu_supported = gp106_is_pmu_supported, | ||
373 | .pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list, | ||
374 | .pmu_elpg_statistics = gp106_pmu_elpg_statistics, | ||
375 | .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, | ||
376 | .pmu_is_lpwr_feature_supported = | ||
377 | gp106_pmu_is_lpwr_feature_supported, | ||
378 | .pmu_msgq_tail = gk20a_pmu_msgq_tail, | ||
379 | .pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list, | ||
380 | .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, | ||
381 | .pmu_queue_head = gk20a_pmu_queue_head, | ||
382 | .pmu_pg_param_post_init = nvgpu_lpwr_post_init, | ||
383 | .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, | ||
384 | .pmu_pg_init_param = gp106_pg_param_init, | ||
385 | .reset_engine = gp106_pmu_engine_reset, | ||
386 | .pmu_lpwr_disable_pg = nvgpu_lpwr_disable_pg, | ||
387 | .write_dmatrfbase = gp10b_write_dmatrfbase, | ||
388 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, | ||
389 | .is_engine_in_reset = gp106_pmu_is_engine_in_reset, | ||
390 | .pmu_get_queue_tail = pwr_pmu_queue_tail_r, | ||
391 | .pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg, | ||
392 | }, | ||
348 | .clk = { | 393 | .clk = { |
349 | .init_clk_support = gp106_init_clk_support, | 394 | .init_clk_support = gp106_init_clk_support, |
350 | .get_crystal_clk_hz = gp106_crystal_clk_hz, | 395 | .get_crystal_clk_hz = gp106_crystal_clk_hz, |
@@ -444,6 +489,7 @@ int gv100_init_hal(struct gk20a *g) | |||
444 | gops->fecs_trace = gv100_ops.fecs_trace; | 489 | gops->fecs_trace = gv100_ops.fecs_trace; |
445 | gops->pramin = gv100_ops.pramin; | 490 | gops->pramin = gv100_ops.pramin; |
446 | gops->therm = gv100_ops.therm; | 491 | gops->therm = gv100_ops.therm; |
492 | gops->pmu = gv100_ops.pmu; | ||
447 | gops->mc = gv100_ops.mc; | 493 | gops->mc = gv100_ops.mc; |
448 | gops->debug = gv100_ops.debug; | 494 | gops->debug = gv100_ops.debug; |
449 | gops->dbg_session_ops = gv100_ops.dbg_session_ops; | 495 | gops->dbg_session_ops = gv100_ops.dbg_session_ops; |
@@ -470,13 +516,14 @@ int gv100_init_hal(struct gk20a *g) | |||
470 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | 516 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); |
471 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | 517 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
472 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | 518 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); |
519 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); | ||
473 | /* for now */ | 520 | /* for now */ |
474 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 521 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
475 | 522 | ||
523 | g->pmu_lsf_pmu_wpr_init_done = 0; | ||
476 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; | 524 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; |
477 | 525 | ||
478 | gv11b_init_gr(g); | 526 | gv11b_init_gr(g); |
479 | gp106_init_pmu_ops(g); | ||
480 | 527 | ||
481 | gv11b_init_uncompressed_kind_map(); | 528 | gv11b_init_uncompressed_kind_map(); |
482 | gv11b_init_kind_attr(); | 529 | gv11b_init_kind_attr(); |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index f572084d..521cafa3 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -31,12 +31,15 @@ | |||
31 | #include "gk20a/flcn_gk20a.h" | 31 | #include "gk20a/flcn_gk20a.h" |
32 | #include "gk20a/regops_gk20a.h" | 32 | #include "gk20a/regops_gk20a.h" |
33 | #include "gk20a/fb_gk20a.h" | 33 | #include "gk20a/fb_gk20a.h" |
34 | #include "gk20a/pmu_gk20a.h" | ||
34 | 35 | ||
35 | #include "gm20b/ltc_gm20b.h" | 36 | #include "gm20b/ltc_gm20b.h" |
36 | #include "gm20b/gr_gm20b.h" | 37 | #include "gm20b/gr_gm20b.h" |
37 | #include "gm20b/fb_gm20b.h" | 38 | #include "gm20b/fb_gm20b.h" |
38 | #include "gm20b/fifo_gm20b.h" | 39 | #include "gm20b/fifo_gm20b.h" |
39 | #include "gm20b/mm_gm20b.h" | 40 | #include "gm20b/mm_gm20b.h" |
41 | #include "gm20b/acr_gm20b.h" | ||
42 | #include "gm20b/pmu_gm20b.h" | ||
40 | 43 | ||
41 | #include "gp10b/ltc_gp10b.h" | 44 | #include "gp10b/ltc_gp10b.h" |
42 | #include "gp10b/therm_gp10b.h" | 45 | #include "gp10b/therm_gp10b.h" |
@@ -47,6 +50,9 @@ | |||
47 | #include "gp10b/fecs_trace_gp10b.h" | 50 | #include "gp10b/fecs_trace_gp10b.h" |
48 | #include "gp10b/fb_gp10b.h" | 51 | #include "gp10b/fb_gp10b.h" |
49 | #include "gp10b/mm_gp10b.h" | 52 | #include "gp10b/mm_gp10b.h" |
53 | #include "gp10b/pmu_gp10b.h" | ||
54 | |||
55 | #include "gp106/pmu_gp106.h" | ||
50 | 56 | ||
51 | #include "hal_gv11b.h" | 57 | #include "hal_gv11b.h" |
52 | #include "gr_gv11b.h" | 58 | #include "gr_gv11b.h" |
@@ -70,6 +76,7 @@ | |||
70 | #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h> | 76 | #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h> |
71 | #include <nvgpu/hw/gv11b/hw_ram_gv11b.h> | 77 | #include <nvgpu/hw/gv11b/hw_ram_gv11b.h> |
72 | #include <nvgpu/hw/gv11b/hw_top_gv11b.h> | 78 | #include <nvgpu/hw/gv11b/hw_top_gv11b.h> |
79 | #include <nvgpu/hw/gv11b/hw_pwr_gv11b.h> | ||
73 | 80 | ||
74 | static int gv11b_get_litter_value(struct gk20a *g, int value) | 81 | static int gv11b_get_litter_value(struct gk20a *g, int value) |
75 | { | 82 | { |
@@ -368,6 +375,30 @@ static const struct gpu_ops gv11b_ops = { | |||
368 | .init_therm_setup_hw = gp10b_init_therm_setup_hw, | 375 | .init_therm_setup_hw = gp10b_init_therm_setup_hw, |
369 | .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, | 376 | .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, |
370 | }, | 377 | }, |
378 | .pmu = { | ||
379 | .pmu_setup_elpg = gp10b_pmu_setup_elpg, | ||
380 | .pmu_get_queue_head = pwr_pmu_queue_head_r, | ||
381 | .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, | ||
382 | .pmu_get_queue_tail = pwr_pmu_queue_tail_r, | ||
383 | .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, | ||
384 | .pmu_queue_head = gk20a_pmu_queue_head, | ||
385 | .pmu_queue_tail = gk20a_pmu_queue_tail, | ||
386 | .pmu_msgq_tail = gk20a_pmu_msgq_tail, | ||
387 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, | ||
388 | .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, | ||
389 | .pmu_mutex_release = gk20a_pmu_mutex_release, | ||
390 | .write_dmatrfbase = gp10b_write_dmatrfbase, | ||
391 | .pmu_elpg_statistics = gp106_pmu_elpg_statistics, | ||
392 | .pmu_pg_init_param = gv11b_pg_gr_init, | ||
393 | .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, | ||
394 | .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, | ||
395 | .dump_secure_fuses = pmu_dump_security_fuses_gp10b, | ||
396 | .reset_engine = gp106_pmu_engine_reset, | ||
397 | .is_engine_in_reset = gp106_pmu_is_engine_in_reset, | ||
398 | .pmu_nsbootstrap = gv11b_pmu_bootstrap, | ||
399 | .pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask, | ||
400 | .is_pmu_supported = gv11b_is_pmu_supported, | ||
401 | }, | ||
371 | .regops = { | 402 | .regops = { |
372 | .get_global_whitelist_ranges = | 403 | .get_global_whitelist_ranges = |
373 | gv11b_get_global_whitelist_ranges, | 404 | gv11b_get_global_whitelist_ranges, |
@@ -463,6 +494,7 @@ int gv11b_init_hal(struct gk20a *g) | |||
463 | gops->mm = gv11b_ops.mm; | 494 | gops->mm = gv11b_ops.mm; |
464 | gops->fecs_trace = gv11b_ops.fecs_trace; | 495 | gops->fecs_trace = gv11b_ops.fecs_trace; |
465 | gops->therm = gv11b_ops.therm; | 496 | gops->therm = gv11b_ops.therm; |
497 | gops->pmu = gv11b_ops.pmu; | ||
466 | gops->regops = gv11b_ops.regops; | 498 | gops->regops = gv11b_ops.regops; |
467 | gops->mc = gv11b_ops.mc; | 499 | gops->mc = gv11b_ops.mc; |
468 | gops->debug = gv11b_ops.debug; | 500 | gops->debug = gv11b_ops.debug; |
@@ -479,13 +511,44 @@ int gv11b_init_hal(struct gk20a *g) | |||
479 | gv11b_ops.chip_init_gpu_characteristics; | 511 | gv11b_ops.chip_init_gpu_characteristics; |
480 | gops->get_litter_value = gv11b_ops.get_litter_value; | 512 | gops->get_litter_value = gv11b_ops.get_litter_value; |
481 | 513 | ||
482 | /* boot in non-secure modes for time beeing */ | 514 | /* boot in non-secure modes for time being */ |
483 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false); | 515 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false); |
484 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | 516 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); |
485 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | 517 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
486 | 518 | ||
519 | /* priv security dependent ops */ | ||
520 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | ||
521 | /* Add in ops from gm20b acr */ | ||
522 | gops->pmu.prepare_ucode = prepare_ucode_blob, | ||
523 | gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn, | ||
524 | gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap, | ||
525 | gops->pmu.is_priv_load = gm20b_is_priv_load, | ||
526 | gops->pmu.get_wpr = gm20b_wpr_info, | ||
527 | gops->pmu.alloc_blob_space = gm20b_alloc_blob_space, | ||
528 | gops->pmu.pmu_populate_loader_cfg = | ||
529 | gm20b_pmu_populate_loader_cfg, | ||
530 | gops->pmu.flcn_populate_bl_dmem_desc = | ||
531 | gm20b_flcn_populate_bl_dmem_desc, | ||
532 | gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt, | ||
533 | gops->pmu.falcon_clear_halt_interrupt_status = | ||
534 | clear_halt_interrupt_status, | ||
535 | gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1, | ||
536 | |||
537 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | ||
538 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; | ||
539 | gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; | ||
540 | gops->pmu.is_priv_load = gp10b_is_priv_load; | ||
541 | } else { | ||
542 | /* Inherit from gk20a */ | ||
543 | gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, | ||
544 | gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1, | ||
545 | |||
546 | gops->pmu.load_lsfalcon_ucode = NULL; | ||
547 | gops->pmu.init_wpr_region = NULL; | ||
548 | gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; | ||
549 | } | ||
550 | |||
487 | gv11b_init_gr(g); | 551 | gv11b_init_gr(g); |
488 | gv11b_init_pmu_ops(g); | ||
489 | 552 | ||
490 | gv11b_init_uncompressed_kind_map(); | 553 | gv11b_init_uncompressed_kind_map(); |
491 | gv11b_init_kind_attr(); | 554 | gv11b_init_kind_attr(); |
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 35719dff..2b89fbcc 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | |||
@@ -36,12 +36,12 @@ | |||
36 | 36 | ||
37 | #define ALIGN_4KB 12 | 37 | #define ALIGN_4KB 12 |
38 | 38 | ||
39 | static bool gv11b_is_pmu_supported(struct gk20a *g) | 39 | bool gv11b_is_pmu_supported(struct gk20a *g) |
40 | { | 40 | { |
41 | return true; | 41 | return true; |
42 | } | 42 | } |
43 | 43 | ||
44 | static int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) | 44 | int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) |
45 | { | 45 | { |
46 | struct gk20a *g = gk20a_from_pmu(pmu); | 46 | struct gk20a *g = gk20a_from_pmu(pmu); |
47 | struct mm_gk20a *mm = &g->mm; | 47 | struct mm_gk20a *mm = &g->mm; |
@@ -178,7 +178,7 @@ static void pmu_handle_pg_param_msg(struct gk20a *g, struct pmu_msg *msg, | |||
178 | msg->msg.pg.msg_type); | 178 | msg->msg.pg.msg_type); |
179 | } | 179 | } |
180 | 180 | ||
181 | static int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) | 181 | int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) |
182 | { | 182 | { |
183 | struct nvgpu_pmu *pmu = &g->pmu; | 183 | struct nvgpu_pmu *pmu = &g->pmu; |
184 | struct pmu_cmd cmd; | 184 | struct pmu_cmd cmd; |
@@ -206,7 +206,7 @@ static int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) | |||
206 | return 0; | 206 | return 0; |
207 | } | 207 | } |
208 | 208 | ||
209 | static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) | 209 | int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) |
210 | { | 210 | { |
211 | struct nvgpu_pmu *pmu = &g->pmu; | 211 | struct nvgpu_pmu *pmu = &g->pmu; |
212 | struct pmu_cmd cmd; | 212 | struct pmu_cmd cmd; |
@@ -234,27 +234,3 @@ static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) | |||
234 | 234 | ||
235 | return 0; | 235 | return 0; |
236 | } | 236 | } |
237 | |||
238 | void gv11b_init_pmu_ops(struct gk20a *g) | ||
239 | { | ||
240 | struct gpu_ops *gops = &g->ops; | ||
241 | |||
242 | gp10b_init_pmu_ops(g); | ||
243 | gops->pmu.pmu_nsbootstrap = gv11b_pmu_bootstrap; | ||
244 | gops->pmu.is_pmu_supported = gv11b_is_pmu_supported; | ||
245 | gops->pmu.reset_engine = gp106_pmu_engine_reset; | ||
246 | gops->pmu.is_engine_in_reset = gp106_pmu_is_engine_in_reset; | ||
247 | gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r; | ||
248 | gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v; | ||
249 | gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r; | ||
250 | gops->pmu.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v; | ||
251 | gops->pmu.pmu_queue_head = gk20a_pmu_queue_head; | ||
252 | gops->pmu.pmu_queue_tail = gk20a_pmu_queue_tail; | ||
253 | gops->pmu.pmu_mutex_acquire = gk20a_pmu_mutex_acquire; | ||
254 | gops->pmu.pmu_mutex_release = gk20a_pmu_mutex_release; | ||
255 | gops->pmu.pmu_msgq_tail = gk20a_pmu_msgq_tail; | ||
256 | gops->pmu.pmu_mutex_size = pwr_pmu_mutex__size_1_v; | ||
257 | gops->pmu.pmu_elpg_statistics = gp106_pmu_elpg_statistics; | ||
258 | gops->pmu.pmu_pg_init_param = gv11b_pg_gr_init; | ||
259 | gops->pmu.pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask; | ||
260 | } | ||
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h index ce10c4cb..03fec2a3 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h | |||
@@ -18,6 +18,9 @@ | |||
18 | 18 | ||
19 | struct gk20a; | 19 | struct gk20a; |
20 | 20 | ||
21 | void gv11b_init_pmu_ops(struct gk20a *g); | 21 | bool gv11b_is_pmu_supported(struct gk20a *g); |
22 | int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu); | ||
23 | int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); | ||
24 | int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id); | ||
22 | 25 | ||
23 | #endif /*__PMU_GV11B_H_*/ | 26 | #endif /*__PMU_GV11B_H_*/ |