diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/common/fifo/channel.c | 33 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 64 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 88 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 15 |
6 files changed, 110 insertions, 124 deletions
diff --git a/drivers/gpu/nvgpu/common/fifo/channel.c b/drivers/gpu/nvgpu/common/fifo/channel.c index cbffb6de..4b76dcdd 100644 --- a/drivers/gpu/nvgpu/common/fifo/channel.c +++ b/drivers/gpu/nvgpu/common/fifo/channel.c | |||
@@ -164,28 +164,26 @@ int gk20a_enable_channel_tsg(struct gk20a *g, struct channel_gk20a *ch) | |||
164 | { | 164 | { |
165 | struct tsg_gk20a *tsg; | 165 | struct tsg_gk20a *tsg; |
166 | 166 | ||
167 | if (gk20a_is_channel_marked_as_tsg(ch)) { | 167 | tsg = tsg_gk20a_from_ch(ch); |
168 | tsg = &g->fifo.tsg[ch->tsgid]; | 168 | if (tsg != NULL) { |
169 | g->ops.fifo.enable_tsg(tsg); | 169 | g->ops.fifo.enable_tsg(tsg); |
170 | return 0; | ||
170 | } else { | 171 | } else { |
171 | g->ops.fifo.enable_channel(ch); | 172 | return -EINVAL; |
172 | } | 173 | } |
173 | |||
174 | return 0; | ||
175 | } | 174 | } |
176 | 175 | ||
177 | int gk20a_disable_channel_tsg(struct gk20a *g, struct channel_gk20a *ch) | 176 | int gk20a_disable_channel_tsg(struct gk20a *g, struct channel_gk20a *ch) |
178 | { | 177 | { |
179 | struct tsg_gk20a *tsg; | 178 | struct tsg_gk20a *tsg; |
180 | 179 | ||
181 | if (gk20a_is_channel_marked_as_tsg(ch)) { | 180 | tsg = tsg_gk20a_from_ch(ch); |
182 | tsg = &g->fifo.tsg[ch->tsgid]; | 181 | if (tsg != NULL) { |
183 | g->ops.fifo.disable_tsg(tsg); | 182 | g->ops.fifo.disable_tsg(tsg); |
183 | return 0; | ||
184 | } else { | 184 | } else { |
185 | g->ops.fifo.disable_channel(ch); | 185 | return -EINVAL; |
186 | } | 186 | } |
187 | |||
188 | return 0; | ||
189 | } | 187 | } |
190 | 188 | ||
191 | void gk20a_channel_abort_clean_up(struct channel_gk20a *ch) | 189 | void gk20a_channel_abort_clean_up(struct channel_gk20a *ch) |
@@ -238,19 +236,8 @@ void gk20a_channel_abort(struct channel_gk20a *ch, bool channel_preempt) | |||
238 | 236 | ||
239 | if (tsg != NULL) { | 237 | if (tsg != NULL) { |
240 | return gk20a_fifo_abort_tsg(ch->g, tsg, channel_preempt); | 238 | return gk20a_fifo_abort_tsg(ch->g, tsg, channel_preempt); |
241 | } | 239 | } else { |
242 | 240 | nvgpu_err(ch->g, "chid: %d is not bound to tsg", ch->chid); | |
243 | /* make sure new kickoffs are prevented */ | ||
244 | gk20a_channel_set_timedout(ch); | ||
245 | |||
246 | ch->g->ops.fifo.disable_channel(ch); | ||
247 | |||
248 | if (channel_preempt) { | ||
249 | ch->g->ops.fifo.preempt_channel(ch->g, ch); | ||
250 | } | ||
251 | |||
252 | if (ch->g->ops.fifo.ch_abort_clean_up) { | ||
253 | ch->g->ops.fifo.ch_abort_clean_up(ch); | ||
254 | } | 241 | } |
255 | } | 242 | } |
256 | 243 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c index cac3ce27..6b384c89 100644 --- a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c | |||
@@ -457,9 +457,14 @@ int gk20a_fecs_trace_bind_channel(struct gk20a *g, | |||
457 | struct gk20a_fecs_trace *trace = g->fecs_trace; | 457 | struct gk20a_fecs_trace *trace = g->fecs_trace; |
458 | struct nvgpu_mem *mem; | 458 | struct nvgpu_mem *mem; |
459 | u32 context_ptr = gk20a_fecs_trace_fecs_context_ptr(g, ch); | 459 | u32 context_ptr = gk20a_fecs_trace_fecs_context_ptr(g, ch); |
460 | pid_t pid; | ||
461 | u32 aperture_mask; | 460 | u32 aperture_mask; |
462 | 461 | ||
462 | tsg = tsg_gk20a_from_ch(ch); | ||
463 | if (tsg == NULL) { | ||
464 | nvgpu_err(g, "chid: %d is not bound to tsg", ch->chid); | ||
465 | return -EINVAL; | ||
466 | } | ||
467 | |||
463 | nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, | 468 | nvgpu_log(g, gpu_dbg_fn|gpu_dbg_ctxsw, |
464 | "chid=%d context_ptr=%x inst_block=%llx", | 469 | "chid=%d context_ptr=%x inst_block=%llx", |
465 | ch->chid, context_ptr, | 470 | ch->chid, context_ptr, |
@@ -519,11 +524,7 @@ int gk20a_fecs_trace_bind_channel(struct gk20a *g, | |||
519 | /* pid (process identifier) in user space, corresponds to tgid (thread | 524 | /* pid (process identifier) in user space, corresponds to tgid (thread |
520 | * group id) in kernel space. | 525 | * group id) in kernel space. |
521 | */ | 526 | */ |
522 | if (gk20a_is_channel_marked_as_tsg(ch)) | 527 | gk20a_fecs_trace_hash_add(g, context_ptr, tsg->tgid); |
523 | pid = tsg_gk20a_from_ch(ch)->tgid; | ||
524 | else | ||
525 | pid = ch->tgid; | ||
526 | gk20a_fecs_trace_hash_add(g, context_ptr, pid); | ||
527 | 528 | ||
528 | return 0; | 529 | return 0; |
529 | } | 530 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index d4e386bd..f12c78f8 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -1580,7 +1580,8 @@ void gk20a_fifo_abort_tsg(struct gk20a *g, struct tsg_gk20a *tsg, bool preempt) | |||
1580 | 1580 | ||
1581 | int gk20a_fifo_deferred_reset(struct gk20a *g, struct channel_gk20a *ch) | 1581 | int gk20a_fifo_deferred_reset(struct gk20a *g, struct channel_gk20a *ch) |
1582 | { | 1582 | { |
1583 | u32 engine_id, engines; | 1583 | unsigned long engine_id, engines = 0U; |
1584 | struct tsg_gk20a *tsg; | ||
1584 | 1585 | ||
1585 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | 1586 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); |
1586 | gr_gk20a_disable_ctxsw(g); | 1587 | gr_gk20a_disable_ctxsw(g); |
@@ -1589,12 +1590,14 @@ int gk20a_fifo_deferred_reset(struct gk20a *g, struct channel_gk20a *ch) | |||
1589 | goto clean_up; | 1590 | goto clean_up; |
1590 | } | 1591 | } |
1591 | 1592 | ||
1592 | if (gk20a_is_channel_marked_as_tsg(ch)) { | 1593 | tsg = tsg_gk20a_from_ch(ch); |
1593 | engines = gk20a_fifo_engines_on_id(g, ch->tsgid, true); | 1594 | if (tsg != NULL) { |
1595 | engines = gk20a_fifo_engines_on_id(g, tsg->tsgid, true); | ||
1594 | } else { | 1596 | } else { |
1595 | engines = gk20a_fifo_engines_on_id(g, ch->chid, false); | 1597 | nvgpu_err(g, "chid: %d is not bound to tsg", ch->chid); |
1596 | } | 1598 | } |
1597 | if (!engines) { | 1599 | |
1600 | if (engines == 0U) { | ||
1598 | goto clean_up; | 1601 | goto clean_up; |
1599 | } | 1602 | } |
1600 | 1603 | ||
@@ -1750,16 +1753,18 @@ static bool gk20a_fifo_handle_mmu_fault_locked( | |||
1750 | } else if (type == fifo_engine_status_id_type_chid_v()) { | 1753 | } else if (type == fifo_engine_status_id_type_chid_v()) { |
1751 | ch = &g->fifo.channel[id]; | 1754 | ch = &g->fifo.channel[id]; |
1752 | refch = gk20a_channel_get(ch); | 1755 | refch = gk20a_channel_get(ch); |
1756 | if (refch != NULL) { | ||
1757 | tsg = tsg_gk20a_from_ch(refch); | ||
1758 | } | ||
1753 | } | 1759 | } |
1754 | } else { | 1760 | } else { |
1755 | /* read channel based on instruction pointer */ | 1761 | /* read channel based on instruction pointer */ |
1756 | ch = gk20a_refch_from_inst_ptr(g, | 1762 | ch = gk20a_refch_from_inst_ptr(g, |
1757 | mmfault_info.inst_ptr); | 1763 | mmfault_info.inst_ptr); |
1758 | refch = ch; | 1764 | refch = ch; |
1759 | } | 1765 | if (refch != NULL) { |
1760 | 1766 | tsg = tsg_gk20a_from_ch(refch); | |
1761 | if (ch && gk20a_is_channel_marked_as_tsg(ch)) { | 1767 | } |
1762 | tsg = &g->fifo.tsg[ch->tsgid]; | ||
1763 | } | 1768 | } |
1764 | 1769 | ||
1765 | /* check if engine reset should be deferred */ | 1770 | /* check if engine reset should be deferred */ |
@@ -1786,16 +1791,10 @@ static bool gk20a_fifo_handle_mmu_fault_locked( | |||
1786 | } | 1791 | } |
1787 | 1792 | ||
1788 | #ifdef CONFIG_GK20A_CTXSW_TRACE | 1793 | #ifdef CONFIG_GK20A_CTXSW_TRACE |
1789 | /* | 1794 | if (tsg) { |
1790 | * For non fake mmu fault, both tsg and ch pointers | ||
1791 | * could be valid. Check tsg first. | ||
1792 | */ | ||
1793 | if (tsg) | ||
1794 | gk20a_ctxsw_trace_tsg_reset(g, tsg); | 1795 | gk20a_ctxsw_trace_tsg_reset(g, tsg); |
1795 | else if (ch) | 1796 | } |
1796 | gk20a_ctxsw_trace_channel_reset(g, ch); | ||
1797 | #endif | 1797 | #endif |
1798 | |||
1799 | /* | 1798 | /* |
1800 | * Disable the channel/TSG from hw and increment syncpoints. | 1799 | * Disable the channel/TSG from hw and increment syncpoints. |
1801 | */ | 1800 | */ |
@@ -1815,26 +1814,10 @@ static bool gk20a_fifo_handle_mmu_fault_locked( | |||
1815 | if (refch) { | 1814 | if (refch) { |
1816 | gk20a_channel_put(ch); | 1815 | gk20a_channel_put(ch); |
1817 | } | 1816 | } |
1818 | } else if (ch) { | 1817 | } else if (refch != NULL) { |
1819 | if (refch) { | 1818 | nvgpu_err(g, "mmu error in unbound channel %d", |
1820 | if (g->fifo.deferred_reset_pending) { | 1819 | ch->chid); |
1821 | g->ops.fifo.disable_channel(ch); | 1820 | gk20a_channel_put(ch); |
1822 | } else { | ||
1823 | if (!fake_fault) { | ||
1824 | gk20a_fifo_set_ctx_mmu_error_ch( | ||
1825 | g, refch); | ||
1826 | } | ||
1827 | |||
1828 | verbose = gk20a_fifo_error_ch(g, | ||
1829 | refch); | ||
1830 | gk20a_channel_abort(ch, false); | ||
1831 | } | ||
1832 | gk20a_channel_put(ch); | ||
1833 | } else { | ||
1834 | nvgpu_err(g, | ||
1835 | "mmu error in freed channel %d", | ||
1836 | ch->chid); | ||
1837 | } | ||
1838 | } else if (mmfault_info.inst_ptr == | 1821 | } else if (mmfault_info.inst_ptr == |
1839 | nvgpu_inst_block_addr(g, &g->mm.bar1.inst_block)) { | 1822 | nvgpu_inst_block_addr(g, &g->mm.bar1.inst_block)) { |
1840 | nvgpu_err(g, "mmu fault from bar1"); | 1823 | nvgpu_err(g, "mmu fault from bar1"); |
@@ -2116,7 +2099,7 @@ void gk20a_fifo_recover(struct gk20a *g, u32 __engine_ids, | |||
2116 | rc_type, NULL); | 2099 | rc_type, NULL); |
2117 | } | 2100 | } |
2118 | 2101 | ||
2119 | /* force reset channel and tsg (if it's part of one) */ | 2102 | /* force reset channel and tsg */ |
2120 | int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, | 2103 | int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, |
2121 | u32 err_code, bool verbose) | 2104 | u32 err_code, bool verbose) |
2122 | { | 2105 | { |
@@ -2126,7 +2109,6 @@ int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, | |||
2126 | struct tsg_gk20a *tsg = tsg_gk20a_from_ch(ch); | 2109 | struct tsg_gk20a *tsg = tsg_gk20a_from_ch(ch); |
2127 | 2110 | ||
2128 | if (tsg != NULL) { | 2111 | if (tsg != NULL) { |
2129 | |||
2130 | nvgpu_rwsem_down_read(&tsg->ch_list_lock); | 2112 | nvgpu_rwsem_down_read(&tsg->ch_list_lock); |
2131 | 2113 | ||
2132 | nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list, | 2114 | nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list, |
@@ -2142,9 +2124,7 @@ int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, | |||
2142 | gk20a_fifo_recover_tsg(g, tsg, verbose, | 2124 | gk20a_fifo_recover_tsg(g, tsg, verbose, |
2143 | RC_TYPE_FORCE_RESET); | 2125 | RC_TYPE_FORCE_RESET); |
2144 | } else { | 2126 | } else { |
2145 | g->ops.fifo.set_error_notifier(ch, err_code); | 2127 | nvgpu_err(g, "chid: %d is not bound to tsg", ch->chid); |
2146 | gk20a_fifo_recover_ch(g, ch, verbose, | ||
2147 | RC_TYPE_FORCE_RESET); | ||
2148 | } | 2128 | } |
2149 | 2129 | ||
2150 | return 0; | 2130 | return 0; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 58aa233f..46cbfd8c 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -3018,7 +3018,6 @@ static void gr_gk20a_free_channel_pm_ctx(struct gk20a *g, | |||
3018 | int gk20a_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags) | 3018 | int gk20a_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags) |
3019 | { | 3019 | { |
3020 | struct gk20a *g = c->g; | 3020 | struct gk20a *g = c->g; |
3021 | struct fifo_gk20a *f = &g->fifo; | ||
3022 | struct nvgpu_gr_ctx *gr_ctx; | 3021 | struct nvgpu_gr_ctx *gr_ctx; |
3023 | struct tsg_gk20a *tsg = NULL; | 3022 | struct tsg_gk20a *tsg = NULL; |
3024 | int err = 0; | 3023 | int err = 0; |
@@ -3041,11 +3040,11 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags) | |||
3041 | } | 3040 | } |
3042 | c->obj_class = class_num; | 3041 | c->obj_class = class_num; |
3043 | 3042 | ||
3044 | if (!gk20a_is_channel_marked_as_tsg(c)) { | 3043 | tsg = tsg_gk20a_from_ch(c); |
3044 | if (tsg == NULL) { | ||
3045 | return -EINVAL; | 3045 | return -EINVAL; |
3046 | } | 3046 | } |
3047 | 3047 | ||
3048 | tsg = &f->tsg[c->tsgid]; | ||
3049 | gr_ctx = &tsg->gr_ctx; | 3048 | gr_ctx = &tsg->gr_ctx; |
3050 | 3049 | ||
3051 | if (!nvgpu_mem_is_valid(&gr_ctx->mem)) { | 3050 | if (!nvgpu_mem_is_valid(&gr_ctx->mem)) { |
@@ -5213,21 +5212,21 @@ static void gk20a_gr_set_error_notifier(struct gk20a *g, | |||
5213 | return; | 5212 | return; |
5214 | } | 5213 | } |
5215 | 5214 | ||
5216 | if (gk20a_is_channel_marked_as_tsg(ch)) { | 5215 | tsg = tsg_gk20a_from_ch(ch); |
5217 | tsg = &g->fifo.tsg[ch->tsgid]; | 5216 | if (tsg != NULL) { |
5218 | nvgpu_rwsem_down_read(&tsg->ch_list_lock); | 5217 | nvgpu_rwsem_down_read(&tsg->ch_list_lock); |
5219 | nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list, | 5218 | nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list, |
5220 | channel_gk20a, ch_entry) { | 5219 | channel_gk20a, ch_entry) { |
5221 | if (gk20a_channel_get(ch_tsg)) { | 5220 | if (gk20a_channel_get(ch_tsg)) { |
5222 | g->ops.fifo.set_error_notifier(ch_tsg, | 5221 | g->ops.fifo.set_error_notifier(ch_tsg, |
5223 | error_notifier); | 5222 | error_notifier); |
5224 | gk20a_channel_put(ch_tsg); | 5223 | gk20a_channel_put(ch_tsg); |
5225 | } | 5224 | } |
5226 | 5225 | ||
5227 | } | 5226 | } |
5228 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); | 5227 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); |
5229 | } else { | 5228 | } else { |
5230 | g->ops.fifo.set_error_notifier(ch, error_notifier); | 5229 | nvgpu_err(g, "chid: %d is not bound to tsg", ch->chid); |
5231 | } | 5230 | } |
5232 | } | 5231 | } |
5233 | 5232 | ||
@@ -5394,12 +5393,21 @@ int gk20a_gr_handle_semaphore_pending(struct gk20a *g, | |||
5394 | struct gr_gk20a_isr_data *isr_data) | 5393 | struct gr_gk20a_isr_data *isr_data) |
5395 | { | 5394 | { |
5396 | struct channel_gk20a *ch = isr_data->ch; | 5395 | struct channel_gk20a *ch = isr_data->ch; |
5397 | struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; | 5396 | struct tsg_gk20a *tsg; |
5397 | |||
5398 | if (ch == NULL) { | ||
5399 | return 0; | ||
5400 | } | ||
5398 | 5401 | ||
5399 | g->ops.fifo.post_event_id(tsg, | 5402 | tsg = tsg_gk20a_from_ch(ch); |
5400 | NVGPU_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN); | 5403 | if (tsg != NULL) { |
5404 | g->ops.fifo.post_event_id(tsg, | ||
5405 | NVGPU_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN); | ||
5401 | 5406 | ||
5402 | nvgpu_cond_broadcast(&ch->semaphore_wq); | 5407 | nvgpu_cond_broadcast(&ch->semaphore_wq); |
5408 | } else { | ||
5409 | nvgpu_err(g, "chid: %d is not bound to tsg", ch->chid); | ||
5410 | } | ||
5403 | 5411 | ||
5404 | return 0; | 5412 | return 0; |
5405 | } | 5413 | } |
@@ -5434,7 +5442,12 @@ int gk20a_gr_handle_notify_pending(struct gk20a *g, | |||
5434 | u32 buffer_size; | 5442 | u32 buffer_size; |
5435 | u32 offset; | 5443 | u32 offset; |
5436 | bool exit; | 5444 | bool exit; |
5445 | #endif | ||
5446 | if (ch == NULL || tsg_gk20a_from_ch(ch) == NULL) { | ||
5447 | return 0; | ||
5448 | } | ||
5437 | 5449 | ||
5450 | #if defined(CONFIG_GK20A_CYCLE_STATS) | ||
5438 | /* GL will never use payload 0 for cycle state */ | 5451 | /* GL will never use payload 0 for cycle state */ |
5439 | if ((ch->cyclestate.cyclestate_buffer == NULL) || (isr_data->data_lo == 0)) | 5452 | if ((ch->cyclestate.cyclestate_buffer == NULL) || (isr_data->data_lo == 0)) |
5440 | return 0; | 5453 | return 0; |
@@ -5975,7 +5988,7 @@ int gk20a_gr_isr(struct gk20a *g) | |||
5975 | u32 chid; | 5988 | u32 chid; |
5976 | 5989 | ||
5977 | nvgpu_log_fn(g, " "); | 5990 | nvgpu_log_fn(g, " "); |
5978 | nvgpu_log(g, gpu_dbg_intr, "pgraph intr %08x", gr_intr); | 5991 | nvgpu_log(g, gpu_dbg_intr, "pgraph intr 0x%08x", gr_intr); |
5979 | 5992 | ||
5980 | if (gr_intr == 0U) { | 5993 | if (gr_intr == 0U) { |
5981 | return 0; | 5994 | return 0; |
@@ -6009,11 +6022,13 @@ int gk20a_gr_isr(struct gk20a *g) | |||
6009 | chid = ch != NULL ? ch->chid : FIFO_INVAL_CHANNEL_ID; | 6022 | chid = ch != NULL ? ch->chid : FIFO_INVAL_CHANNEL_ID; |
6010 | 6023 | ||
6011 | if (ch == NULL) { | 6024 | if (ch == NULL) { |
6012 | nvgpu_err(g, "ch id is INVALID 0xffffffff"); | 6025 | nvgpu_err(g, "pgraph intr: 0x%08x, chid: INVALID", gr_intr); |
6013 | } | 6026 | } else { |
6014 | 6027 | tsg = tsg_gk20a_from_ch(ch); | |
6015 | if ((ch != NULL) && gk20a_is_channel_marked_as_tsg(ch)) { | 6028 | if (tsg == NULL) { |
6016 | tsg = &g->fifo.tsg[ch->tsgid]; | 6029 | nvgpu_err(g, "pgraph intr: 0x%08x, chid: %d " |
6030 | "not bound to tsg", gr_intr, chid); | ||
6031 | } | ||
6017 | } | 6032 | } |
6018 | 6033 | ||
6019 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, | 6034 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, |
@@ -6198,7 +6213,9 @@ int gk20a_gr_isr(struct gk20a *g) | |||
6198 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, | 6213 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, |
6199 | "GPC exception pending"); | 6214 | "GPC exception pending"); |
6200 | 6215 | ||
6201 | fault_ch = isr_data.ch; | 6216 | if (tsg != NULL) { |
6217 | fault_ch = isr_data.ch; | ||
6218 | } | ||
6202 | 6219 | ||
6203 | /* fault_ch can be NULL */ | 6220 | /* fault_ch can be NULL */ |
6204 | /* check if any gpc has an exception */ | 6221 | /* check if any gpc has an exception */ |
@@ -6225,39 +6242,42 @@ int gk20a_gr_isr(struct gk20a *g) | |||
6225 | } | 6242 | } |
6226 | 6243 | ||
6227 | if (need_reset) { | 6244 | if (need_reset) { |
6228 | if (tsgid != NVGPU_INVALID_TSG_ID) { | 6245 | if (tsg != NULL) { |
6229 | gk20a_fifo_recover(g, gr_engine_id, | 6246 | gk20a_fifo_recover(g, gr_engine_id, |
6230 | tsgid, true, true, true, | 6247 | tsgid, true, true, true, |
6231 | RC_TYPE_GR_FAULT); | 6248 | RC_TYPE_GR_FAULT); |
6232 | } else if (ch) { | ||
6233 | gk20a_fifo_recover(g, gr_engine_id, | ||
6234 | ch->chid, false, true, true, | ||
6235 | RC_TYPE_GR_FAULT); | ||
6236 | } else { | 6249 | } else { |
6250 | if (ch != NULL) { | ||
6251 | nvgpu_err(g, "chid: %d referenceable but not " | ||
6252 | "bound to tsg", chid); | ||
6253 | } | ||
6237 | gk20a_fifo_recover(g, gr_engine_id, | 6254 | gk20a_fifo_recover(g, gr_engine_id, |
6238 | 0, false, false, true, | 6255 | 0, false, false, true, |
6239 | RC_TYPE_GR_FAULT); | 6256 | RC_TYPE_GR_FAULT); |
6240 | } | 6257 | } |
6241 | } | 6258 | } |
6242 | 6259 | ||
6243 | if ((gr_intr != 0U) && (ch == NULL)) { | 6260 | if (gr_intr != 0U) { |
6244 | /* Clear interrupts for unused channel. This is | 6261 | /* clear unhandled interrupts */ |
6245 | probably an interrupt during gk20a_free_channel() */ | 6262 | if (ch == NULL) { |
6246 | nvgpu_err(g, | 6263 | /* |
6247 | "unhandled gr interrupt 0x%08x for unreferenceable channel, clearing", | 6264 | * This is probably an interrupt during |
6248 | gr_intr); | 6265 | * gk20a_free_channel() |
6266 | */ | ||
6267 | nvgpu_err(g, "unhandled gr intr 0x%08x for " | ||
6268 | "unreferenceable channel, clearing", | ||
6269 | gr_intr); | ||
6270 | } else { | ||
6271 | nvgpu_err(g, "unhandled gr intr 0x%08x for chid: %d", | ||
6272 | gr_intr, chid); | ||
6273 | } | ||
6249 | gk20a_writel(g, gr_intr_r(), gr_intr); | 6274 | gk20a_writel(g, gr_intr_r(), gr_intr); |
6250 | gr_intr = 0; | ||
6251 | } | 6275 | } |
6252 | 6276 | ||
6253 | gk20a_writel(g, gr_gpfifo_ctl_r(), | 6277 | gk20a_writel(g, gr_gpfifo_ctl_r(), |
6254 | grfifo_ctl | gr_gpfifo_ctl_access_f(1) | | 6278 | grfifo_ctl | gr_gpfifo_ctl_access_f(1) | |
6255 | gr_gpfifo_ctl_semaphore_access_f(1)); | 6279 | gr_gpfifo_ctl_semaphore_access_f(1)); |
6256 | 6280 | ||
6257 | if (gr_intr) { | ||
6258 | nvgpu_err(g, | ||
6259 | "unhandled gr interrupt 0x%08x", gr_intr); | ||
6260 | } | ||
6261 | 6281 | ||
6262 | /* Posting of BPT events should be the last thing in this function */ | 6282 | /* Posting of BPT events should be the last thing in this function */ |
6263 | if ((global_esr != 0U) && (tsg != NULL)) { | 6283 | if ((global_esr != 0U) && (tsg != NULL)) { |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index a3655146..8d02c8f6 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1691,6 +1691,14 @@ void gr_gp10b_get_access_map(struct gk20a *g, | |||
1691 | static int gr_gp10b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a *fault_ch) | 1691 | static int gr_gp10b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a *fault_ch) |
1692 | { | 1692 | { |
1693 | int ret = 0; | 1693 | int ret = 0; |
1694 | struct tsg_gk20a *tsg; | ||
1695 | |||
1696 | tsg = tsg_gk20a_from_ch(fault_ch); | ||
1697 | if (tsg == NULL) { | ||
1698 | nvgpu_err(g, "CILP: chid: %d is not bound to tsg", | ||
1699 | fault_ch->chid); | ||
1700 | return -EINVAL; | ||
1701 | } | ||
1694 | 1702 | ||
1695 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, " "); | 1703 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, " "); |
1696 | 1704 | ||
@@ -1711,18 +1719,11 @@ static int gr_gp10b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a | |||
1711 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: restarted runlist"); | 1719 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: restarted runlist"); |
1712 | 1720 | ||
1713 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | 1721 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
1714 | "CILP: tsgid: 0x%x", fault_ch->tsgid); | 1722 | "CILP: tsgid: 0x%x", tsg->tsgid); |
1715 | 1723 | ||
1716 | if (gk20a_is_channel_marked_as_tsg(fault_ch)) { | 1724 | gk20a_fifo_issue_preempt(g, tsg->tsgid, true); |
1717 | gk20a_fifo_issue_preempt(g, fault_ch->tsgid, true); | 1725 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
1718 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | ||
1719 | "CILP: preempted tsg"); | 1726 | "CILP: preempted tsg"); |
1720 | } else { | ||
1721 | gk20a_fifo_issue_preempt(g, fault_ch->chid, false); | ||
1722 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | ||
1723 | "CILP: preempted channel"); | ||
1724 | } | ||
1725 | |||
1726 | return ret; | 1727 | return ret; |
1727 | } | 1728 | } |
1728 | 1729 | ||
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 4055d5af..60ab628a 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -641,9 +641,8 @@ int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, | |||
641 | 641 | ||
642 | nvgpu_log_fn(g, " "); | 642 | nvgpu_log_fn(g, " "); |
643 | 643 | ||
644 | if (gk20a_is_channel_marked_as_tsg(ch)) { | 644 | tsg = tsg_gk20a_from_ch(ch); |
645 | tsg = &g->fifo.tsg[ch->tsgid]; | 645 | if (tsg != NULL) { |
646 | |||
647 | nvgpu_rwsem_down_read(&tsg->ch_list_lock); | 646 | nvgpu_rwsem_down_read(&tsg->ch_list_lock); |
648 | 647 | ||
649 | nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list, | 648 | nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list, |
@@ -658,8 +657,7 @@ int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, | |||
658 | 657 | ||
659 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); | 658 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); |
660 | } else { | 659 | } else { |
661 | g->ops.fifo.set_error_notifier(ch, err_code); | 660 | nvgpu_err(g, "chid: %d is not bound to tsg", ch->chid); |
662 | gk20a_channel_set_timedout(ch); | ||
663 | } | 661 | } |
664 | 662 | ||
665 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET; | 663 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET; |
@@ -698,9 +696,8 @@ static void vgpu_fifo_set_ctx_mmu_error_ch_tsg(struct gk20a *g, | |||
698 | struct tsg_gk20a *tsg = NULL; | 696 | struct tsg_gk20a *tsg = NULL; |
699 | struct channel_gk20a *ch_tsg = NULL; | 697 | struct channel_gk20a *ch_tsg = NULL; |
700 | 698 | ||
701 | if (gk20a_is_channel_marked_as_tsg(ch)) { | 699 | tsg = tsg_gk20a_from_ch(ch); |
702 | tsg = &g->fifo.tsg[ch->tsgid]; | 700 | if (tsg != NULL) { |
703 | |||
704 | nvgpu_rwsem_down_read(&tsg->ch_list_lock); | 701 | nvgpu_rwsem_down_read(&tsg->ch_list_lock); |
705 | 702 | ||
706 | nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list, | 703 | nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list, |
@@ -713,7 +710,7 @@ static void vgpu_fifo_set_ctx_mmu_error_ch_tsg(struct gk20a *g, | |||
713 | 710 | ||
714 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); | 711 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); |
715 | } else { | 712 | } else { |
716 | vgpu_fifo_set_ctx_mmu_error_ch(g, ch); | 713 | nvgpu_err(g, "chid: %d is not bound to tsg", ch->chid); |
717 | } | 714 | } |
718 | } | 715 | } |
719 | 716 | ||