diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/common/xve/xve_gp106.c | 56 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/kref.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/ptimer.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/xve.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/lpwr/lpwr.c | 79 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/perf/perf.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/perf/vfe_equ.c | 53 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/perf/vfe_var.c | 92 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmgr/pmgr.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmgr/pmgrpmu.c | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmgr/pwrdev.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmgr/pwrmonitor.c | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmgr/pwrpolicy.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pstate/pstate.c | 129 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/therm/thrmchannel.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/therm/thrmdev.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/therm/thrmpmu.c | 5 |
17 files changed, 335 insertions, 179 deletions
diff --git a/drivers/gpu/nvgpu/common/xve/xve_gp106.c b/drivers/gpu/nvgpu/common/xve/xve_gp106.c index 3ed02f1b..29d97843 100644 --- a/drivers/gpu/nvgpu/common/xve/xve_gp106.c +++ b/drivers/gpu/nvgpu/common/xve/xve_gp106.c | |||
@@ -104,15 +104,19 @@ int xve_get_speed_gp106(struct gk20a *g, u32 *xve_link_speed) | |||
104 | * Can't use a switch statement becuase switch statements dont work with | 104 | * Can't use a switch statement becuase switch statements dont work with |
105 | * function calls. | 105 | * function calls. |
106 | */ | 106 | */ |
107 | if (link_speed == xve_link_control_status_link_speed_link_speed_2p5_v()) | 107 | if (link_speed == xve_link_control_status_link_speed_link_speed_2p5_v()) { |
108 | real_link_speed = GPU_XVE_SPEED_2P5; | 108 | real_link_speed = GPU_XVE_SPEED_2P5; |
109 | if (link_speed == xve_link_control_status_link_speed_link_speed_5p0_v()) | 109 | } |
110 | if (link_speed == xve_link_control_status_link_speed_link_speed_5p0_v()) { | ||
110 | real_link_speed = GPU_XVE_SPEED_5P0; | 111 | real_link_speed = GPU_XVE_SPEED_5P0; |
111 | if (link_speed == xve_link_control_status_link_speed_link_speed_8p0_v()) | 112 | } |
113 | if (link_speed == xve_link_control_status_link_speed_link_speed_8p0_v()) { | ||
112 | real_link_speed = GPU_XVE_SPEED_8P0; | 114 | real_link_speed = GPU_XVE_SPEED_8P0; |
115 | } | ||
113 | 116 | ||
114 | if (real_link_speed == 0U) | 117 | if (real_link_speed == 0U) { |
115 | return -ENODEV; | 118 | return -ENODEV; |
119 | } | ||
116 | 120 | ||
117 | *xve_link_speed = real_link_speed; | 121 | *xve_link_speed = real_link_speed; |
118 | return 0; | 122 | return 0; |
@@ -240,8 +244,9 @@ static int __do_xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed) | |||
240 | if ((xp_pl_link_config_ltssm_status_f(pl_link_config) == | 244 | if ((xp_pl_link_config_ltssm_status_f(pl_link_config) == |
241 | xp_pl_link_config_ltssm_status_idle_v()) && | 245 | xp_pl_link_config_ltssm_status_idle_v()) && |
242 | (xp_pl_link_config_ltssm_directive_f(pl_link_config) == | 246 | (xp_pl_link_config_ltssm_directive_f(pl_link_config) == |
243 | xp_pl_link_config_ltssm_directive_normal_operations_v())) | 247 | xp_pl_link_config_ltssm_directive_normal_operations_v())) { |
244 | break; | 248 | break; |
249 | } | ||
245 | } while (nvgpu_timeout_expired(&timeout) == 0); | 250 | } while (nvgpu_timeout_expired(&timeout) == 0); |
246 | 251 | ||
247 | if (nvgpu_timeout_peek_expired(&timeout)) { | 252 | if (nvgpu_timeout_peek_expired(&timeout)) { |
@@ -283,23 +288,24 @@ static int __do_xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed) | |||
283 | pl_link_config &= ~xp_pl_link_config_target_tx_width_m(); | 288 | pl_link_config &= ~xp_pl_link_config_target_tx_width_m(); |
284 | 289 | ||
285 | /* Can't use a switch due to oddities in register definitions. */ | 290 | /* Can't use a switch due to oddities in register definitions. */ |
286 | if (link_width == xve_link_control_status_link_width_x1_v()) | 291 | if (link_width == xve_link_control_status_link_width_x1_v()) { |
287 | pl_link_config |= xp_pl_link_config_target_tx_width_f( | 292 | pl_link_config |= xp_pl_link_config_target_tx_width_f( |
288 | xp_pl_link_config_target_tx_width_x1_v()); | 293 | xp_pl_link_config_target_tx_width_x1_v()); |
289 | else if (link_width == xve_link_control_status_link_width_x2_v()) | 294 | } else if (link_width == xve_link_control_status_link_width_x2_v()) { |
290 | pl_link_config |= xp_pl_link_config_target_tx_width_f( | 295 | pl_link_config |= xp_pl_link_config_target_tx_width_f( |
291 | xp_pl_link_config_target_tx_width_x2_v()); | 296 | xp_pl_link_config_target_tx_width_x2_v()); |
292 | else if (link_width == xve_link_control_status_link_width_x4_v()) | 297 | } else if (link_width == xve_link_control_status_link_width_x4_v()) { |
293 | pl_link_config |= xp_pl_link_config_target_tx_width_f( | 298 | pl_link_config |= xp_pl_link_config_target_tx_width_f( |
294 | xp_pl_link_config_target_tx_width_x4_v()); | 299 | xp_pl_link_config_target_tx_width_x4_v()); |
295 | else if (link_width == xve_link_control_status_link_width_x8_v()) | 300 | } else if (link_width == xve_link_control_status_link_width_x8_v()) { |
296 | pl_link_config |= xp_pl_link_config_target_tx_width_f( | 301 | pl_link_config |= xp_pl_link_config_target_tx_width_f( |
297 | xp_pl_link_config_target_tx_width_x8_v()); | 302 | xp_pl_link_config_target_tx_width_x8_v()); |
298 | else if (link_width == xve_link_control_status_link_width_x16_v()) | 303 | } else if (link_width == xve_link_control_status_link_width_x16_v()) { |
299 | pl_link_config |= xp_pl_link_config_target_tx_width_f( | 304 | pl_link_config |= xp_pl_link_config_target_tx_width_f( |
300 | xp_pl_link_config_target_tx_width_x16_v()); | 305 | xp_pl_link_config_target_tx_width_x16_v()); |
301 | else | 306 | } else { |
302 | BUG(); | 307 | BUG(); |
308 | } | ||
303 | 309 | ||
304 | xv_sc_dbg(g, LINK_SETTINGS, " pl_link_config = 0x%08x", pl_link_config); | 310 | xv_sc_dbg(g, LINK_SETTINGS, " pl_link_config = 0x%08x", pl_link_config); |
305 | xv_sc_dbg(g, LINK_SETTINGS, " Done"); | 311 | xv_sc_dbg(g, LINK_SETTINGS, " Done"); |
@@ -311,8 +317,9 @@ static int __do_xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed) | |||
311 | do { | 317 | do { |
312 | gk20a_writel(g, xp_pl_link_config_r(0), pl_link_config); | 318 | gk20a_writel(g, xp_pl_link_config_r(0), pl_link_config); |
313 | if (pl_link_config == | 319 | if (pl_link_config == |
314 | gk20a_readl(g, xp_pl_link_config_r(0))) | 320 | gk20a_readl(g, xp_pl_link_config_r(0))) { |
315 | break; | 321 | break; |
322 | } | ||
316 | } while (nvgpu_timeout_expired(&timeout) == 0); | 323 | } while (nvgpu_timeout_expired(&timeout) == 0); |
317 | 324 | ||
318 | if (nvgpu_timeout_peek_expired(&timeout)) { | 325 | if (nvgpu_timeout_peek_expired(&timeout)) { |
@@ -346,8 +353,9 @@ static int __do_xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed) | |||
346 | (xp_pl_link_config_ltssm_status_f(pl_link_config) == | 353 | (xp_pl_link_config_ltssm_status_f(pl_link_config) == |
347 | xp_pl_link_config_ltssm_status_idle_v()) && | 354 | xp_pl_link_config_ltssm_status_idle_v()) && |
348 | (xp_pl_link_config_ltssm_directive_f(pl_link_config) == | 355 | (xp_pl_link_config_ltssm_directive_f(pl_link_config) == |
349 | xp_pl_link_config_ltssm_directive_normal_operations_v())) | 356 | xp_pl_link_config_ltssm_directive_normal_operations_v())) { |
350 | break; | 357 | break; |
358 | } | ||
351 | } while (nvgpu_timeout_expired(&timeout) == 0); | 359 | } while (nvgpu_timeout_expired(&timeout) == 0); |
352 | 360 | ||
353 | if (nvgpu_timeout_peek_expired(&timeout)) { | 361 | if (nvgpu_timeout_peek_expired(&timeout)) { |
@@ -403,20 +411,21 @@ static int __do_xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed) | |||
403 | 411 | ||
404 | link_config &= ~xp_pl_link_config_max_link_rate_m(); | 412 | link_config &= ~xp_pl_link_config_max_link_rate_m(); |
405 | if (new_link_speed == | 413 | if (new_link_speed == |
406 | xve_link_control_status_link_speed_link_speed_2p5_v()) | 414 | xve_link_control_status_link_speed_link_speed_2p5_v()) { |
407 | link_config |= xp_pl_link_config_max_link_rate_f( | 415 | link_config |= xp_pl_link_config_max_link_rate_f( |
408 | xp_pl_link_config_max_link_rate_2500_mtps_v()); | 416 | xp_pl_link_config_max_link_rate_2500_mtps_v()); |
409 | else if (new_link_speed == | 417 | } else if (new_link_speed == |
410 | xve_link_control_status_link_speed_link_speed_5p0_v()) | 418 | xve_link_control_status_link_speed_link_speed_5p0_v()) { |
411 | link_config |= xp_pl_link_config_max_link_rate_f( | 419 | link_config |= xp_pl_link_config_max_link_rate_f( |
412 | xp_pl_link_config_max_link_rate_5000_mtps_v()); | 420 | xp_pl_link_config_max_link_rate_5000_mtps_v()); |
413 | else if (new_link_speed == | 421 | } else if (new_link_speed == |
414 | xve_link_control_status_link_speed_link_speed_8p0_v()) | 422 | xve_link_control_status_link_speed_link_speed_8p0_v()) { |
415 | link_config |= xp_pl_link_config_max_link_rate_f( | 423 | link_config |= xp_pl_link_config_max_link_rate_f( |
416 | xp_pl_link_config_max_link_rate_8000_mtps_v()); | 424 | xp_pl_link_config_max_link_rate_8000_mtps_v()); |
417 | else | 425 | } else { |
418 | link_config |= xp_pl_link_config_max_link_rate_f( | 426 | link_config |= xp_pl_link_config_max_link_rate_f( |
419 | xp_pl_link_config_max_link_rate_2500_mtps_v()); | 427 | xp_pl_link_config_max_link_rate_2500_mtps_v()); |
428 | } | ||
420 | 429 | ||
421 | gk20a_writel(g, xp_pl_link_config_r(0), link_config); | 430 | gk20a_writel(g, xp_pl_link_config_r(0), link_config); |
422 | err_status = -ENODEV; | 431 | err_status = -ENODEV; |
@@ -452,16 +461,19 @@ int xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed) | |||
452 | u32 current_link_speed; | 461 | u32 current_link_speed; |
453 | int err; | 462 | int err; |
454 | 463 | ||
455 | if ((next_link_speed & GPU_XVE_SPEED_MASK) == 0) | 464 | if ((next_link_speed & GPU_XVE_SPEED_MASK) == 0) { |
456 | return -EINVAL; | 465 | return -EINVAL; |
466 | } | ||
457 | 467 | ||
458 | err = g->ops.xve.get_speed(g, ¤t_link_speed); | 468 | err = g->ops.xve.get_speed(g, ¤t_link_speed); |
459 | if (err) | 469 | if (err) { |
460 | return err; | 470 | return err; |
471 | } | ||
461 | 472 | ||
462 | /* No-op. */ | 473 | /* No-op. */ |
463 | if (current_link_speed == next_link_speed) | 474 | if (current_link_speed == next_link_speed) { |
464 | return 0; | 475 | return 0; |
476 | } | ||
465 | 477 | ||
466 | return __do_xve_set_speed_gp106(g, next_link_speed); | 478 | return __do_xve_set_speed_gp106(g, next_link_speed); |
467 | } | 479 | } |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/kref.h b/drivers/gpu/nvgpu/include/nvgpu/kref.h index 72b21ec4..2cbc07bc 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/kref.h +++ b/drivers/gpu/nvgpu/include/nvgpu/kref.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -66,8 +66,9 @@ static inline int nvgpu_ref_put(struct nvgpu_ref *ref, | |||
66 | void (*release)(struct nvgpu_ref *r)) | 66 | void (*release)(struct nvgpu_ref *r)) |
67 | { | 67 | { |
68 | if (nvgpu_atomic_sub_and_test(1, &ref->refcount)) { | 68 | if (nvgpu_atomic_sub_and_test(1, &ref->refcount)) { |
69 | if (release != NULL) | 69 | if (release != NULL) { |
70 | release(ref); | 70 | release(ref); |
71 | } | ||
71 | return 1; | 72 | return 1; |
72 | } | 73 | } |
73 | return 0; | 74 | return 0; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/ptimer.h b/drivers/gpu/nvgpu/include/nvgpu/ptimer.h index 598e064f..3369eb20 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/ptimer.h +++ b/drivers/gpu/nvgpu/include/nvgpu/ptimer.h | |||
@@ -42,10 +42,11 @@ static inline u32 ptimer_scalingfactor10x(u32 ptimer_src_freq) | |||
42 | 42 | ||
43 | static inline u32 scale_ptimer(u32 timeout , u32 scale10x) | 43 | static inline u32 scale_ptimer(u32 timeout , u32 scale10x) |
44 | { | 44 | { |
45 | if (((timeout*10) % scale10x) >= (scale10x/2)) | 45 | if (((timeout*10) % scale10x) >= (scale10x/2)) { |
46 | return ((timeout * 10) / scale10x) + 1; | 46 | return ((timeout * 10) / scale10x) + 1; |
47 | else | 47 | } else { |
48 | return (timeout * 10) / scale10x; | 48 | return (timeout * 10) / scale10x; |
49 | } | ||
49 | } | 50 | } |
50 | 51 | ||
51 | int nvgpu_get_timestamps_zipper(struct gk20a *g, | 52 | int nvgpu_get_timestamps_zipper(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/xve.h b/drivers/gpu/nvgpu/include/nvgpu/xve.h index acaf441c..2d0d6982 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/xve.h +++ b/drivers/gpu/nvgpu/include/nvgpu/xve.h | |||
@@ -55,8 +55,9 @@ | |||
55 | static inline const char *xve_speed_to_str(u32 speed) | 55 | static inline const char *xve_speed_to_str(u32 speed) |
56 | { | 56 | { |
57 | if (!speed || !is_power_of_2(speed) || | 57 | if (!speed || !is_power_of_2(speed) || |
58 | !(speed & GPU_XVE_SPEED_MASK)) | 58 | !(speed & GPU_XVE_SPEED_MASK)) { |
59 | return "Unknown ???"; | 59 | return "Unknown ???"; |
60 | } | ||
60 | 61 | ||
61 | return speed & GPU_XVE_SPEED_2P5 ? "Gen1" : | 62 | return speed & GPU_XVE_SPEED_2P5 ? "Gen1" : |
62 | speed & GPU_XVE_SPEED_5P0 ? "Gen2" : | 63 | speed & GPU_XVE_SPEED_5P0 ? "Gen2" : |
diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.c b/drivers/gpu/nvgpu/lpwr/lpwr.c index 3be8269a..a536bf9e 100644 --- a/drivers/gpu/nvgpu/lpwr/lpwr.c +++ b/drivers/gpu/nvgpu/lpwr/lpwr.c | |||
@@ -42,14 +42,16 @@ static int get_lpwr_idx_table(struct gk20a *g) | |||
42 | 42 | ||
43 | lpwr_idx_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g, | 43 | lpwr_idx_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g, |
44 | g->bios.perf_token, LOWPOWER_TABLE); | 44 | g->bios.perf_token, LOWPOWER_TABLE); |
45 | if (lpwr_idx_table_ptr == NULL) | 45 | if (lpwr_idx_table_ptr == NULL) { |
46 | return -EINVAL; | 46 | return -EINVAL; |
47 | } | ||
47 | 48 | ||
48 | memcpy(&header, lpwr_idx_table_ptr, | 49 | memcpy(&header, lpwr_idx_table_ptr, |
49 | sizeof(struct nvgpu_bios_lpwr_idx_table_1x_header)); | 50 | sizeof(struct nvgpu_bios_lpwr_idx_table_1x_header)); |
50 | 51 | ||
51 | if (header.entry_count >= LPWR_VBIOS_IDX_ENTRY_COUNT_MAX) | 52 | if (header.entry_count >= LPWR_VBIOS_IDX_ENTRY_COUNT_MAX) { |
52 | return -EINVAL; | 53 | return -EINVAL; |
54 | } | ||
53 | 55 | ||
54 | pidx_data->base_sampling_period = (u16)header.base_sampling_period; | 56 | pidx_data->base_sampling_period = (u16)header.base_sampling_period; |
55 | 57 | ||
@@ -84,8 +86,9 @@ static int get_lpwr_gr_table(struct gk20a *g) | |||
84 | 86 | ||
85 | lpwr_gr_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g, | 87 | lpwr_gr_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g, |
86 | g->bios.perf_token, LOWPOWER_GR_TABLE); | 88 | g->bios.perf_token, LOWPOWER_GR_TABLE); |
87 | if (lpwr_gr_table_ptr == NULL) | 89 | if (lpwr_gr_table_ptr == NULL) { |
88 | return -EINVAL; | 90 | return -EINVAL; |
91 | } | ||
89 | 92 | ||
90 | memcpy(&header, lpwr_gr_table_ptr, | 93 | memcpy(&header, lpwr_gr_table_ptr, |
91 | sizeof(struct nvgpu_bios_lpwr_gr_table_1x_header)); | 94 | sizeof(struct nvgpu_bios_lpwr_gr_table_1x_header)); |
@@ -106,9 +109,10 @@ static int get_lpwr_gr_table(struct gk20a *g) | |||
106 | NVGPU_PMU_GR_FEATURE_MASK_ALL; | 109 | NVGPU_PMU_GR_FEATURE_MASK_ALL; |
107 | 110 | ||
108 | if (!BIOS_GET_FIELD(entry.feautre_mask, | 111 | if (!BIOS_GET_FIELD(entry.feautre_mask, |
109 | NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG)) | 112 | NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG)) { |
110 | pgr_data->entry[idx].feature_mask &= | 113 | pgr_data->entry[idx].feature_mask &= |
111 | ~NVGPU_PMU_GR_FEATURE_MASK_RPPG; | 114 | ~NVGPU_PMU_GR_FEATURE_MASK_RPPG; |
115 | } | ||
112 | } | 116 | } |
113 | 117 | ||
114 | } | 118 | } |
@@ -128,14 +132,16 @@ static int get_lpwr_ms_table(struct gk20a *g) | |||
128 | 132 | ||
129 | lpwr_ms_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g, | 133 | lpwr_ms_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g, |
130 | g->bios.perf_token, LOWPOWER_MS_TABLE); | 134 | g->bios.perf_token, LOWPOWER_MS_TABLE); |
131 | if (lpwr_ms_table_ptr == NULL) | 135 | if (lpwr_ms_table_ptr == NULL) { |
132 | return -EINVAL; | 136 | return -EINVAL; |
137 | } | ||
133 | 138 | ||
134 | memcpy(&header, lpwr_ms_table_ptr, | 139 | memcpy(&header, lpwr_ms_table_ptr, |
135 | sizeof(struct nvgpu_bios_lpwr_ms_table_1x_header)); | 140 | sizeof(struct nvgpu_bios_lpwr_ms_table_1x_header)); |
136 | 141 | ||
137 | if (header.entry_count >= LPWR_VBIOS_MS_ENTRY_COUNT_MAX) | 142 | if (header.entry_count >= LPWR_VBIOS_MS_ENTRY_COUNT_MAX) { |
138 | return -EINVAL; | 143 | return -EINVAL; |
144 | } | ||
139 | 145 | ||
140 | pms_data->default_entry_idx = (u8)header.default_entry_idx; | 146 | pms_data->default_entry_idx = (u8)header.default_entry_idx; |
141 | 147 | ||
@@ -157,19 +163,22 @@ static int get_lpwr_ms_table(struct gk20a *g) | |||
157 | NVGPU_PMU_MS_FEATURE_MASK_ALL; | 163 | NVGPU_PMU_MS_FEATURE_MASK_ALL; |
158 | 164 | ||
159 | if (!BIOS_GET_FIELD(entry.feautre_mask, | 165 | if (!BIOS_GET_FIELD(entry.feautre_mask, |
160 | NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING)) | 166 | NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING)) { |
161 | pms_data->entry[idx].feature_mask &= | 167 | pms_data->entry[idx].feature_mask &= |
162 | ~NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING; | 168 | ~NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING; |
169 | } | ||
163 | 170 | ||
164 | if (!BIOS_GET_FIELD(entry.feautre_mask, | 171 | if (!BIOS_GET_FIELD(entry.feautre_mask, |
165 | NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR)) | 172 | NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR)) { |
166 | pms_data->entry[idx].feature_mask &= | 173 | pms_data->entry[idx].feature_mask &= |
167 | ~NVGPU_PMU_MS_FEATURE_MASK_SW_ASR; | 174 | ~NVGPU_PMU_MS_FEATURE_MASK_SW_ASR; |
175 | } | ||
168 | 176 | ||
169 | if (!BIOS_GET_FIELD(entry.feautre_mask, | 177 | if (!BIOS_GET_FIELD(entry.feautre_mask, |
170 | NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG)) | 178 | NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG)) { |
171 | pms_data->entry[idx].feature_mask &= | 179 | pms_data->entry[idx].feature_mask &= |
172 | ~NVGPU_PMU_MS_FEATURE_MASK_RPPG; | 180 | ~NVGPU_PMU_MS_FEATURE_MASK_RPPG; |
181 | } | ||
173 | } | 182 | } |
174 | 183 | ||
175 | pms_data->entry[idx].dynamic_current_logic = | 184 | pms_data->entry[idx].dynamic_current_logic = |
@@ -189,12 +198,14 @@ u32 nvgpu_lpwr_pg_setup(struct gk20a *g) | |||
189 | nvgpu_log_fn(g, " "); | 198 | nvgpu_log_fn(g, " "); |
190 | 199 | ||
191 | err = get_lpwr_gr_table(g); | 200 | err = get_lpwr_gr_table(g); |
192 | if (err) | 201 | if (err) { |
193 | return err; | 202 | return err; |
203 | } | ||
194 | 204 | ||
195 | err = get_lpwr_ms_table(g); | 205 | err = get_lpwr_ms_table(g); |
196 | if (err) | 206 | if (err) { |
197 | return err; | 207 | return err; |
208 | } | ||
198 | 209 | ||
199 | err = get_lpwr_idx_table(g); | 210 | err = get_lpwr_idx_table(g); |
200 | 211 | ||
@@ -232,13 +243,15 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate) | |||
232 | 243 | ||
233 | pstate_info = pstate_get_clk_set_info(g, pstate, | 244 | pstate_info = pstate_get_clk_set_info(g, pstate, |
234 | clkwhich_mclk); | 245 | clkwhich_mclk); |
235 | if (!pstate_info) | 246 | if (!pstate_info) { |
236 | return -EINVAL; | 247 | return -EINVAL; |
248 | } | ||
237 | 249 | ||
238 | if (pstate_info->max_mhz > | 250 | if (pstate_info->max_mhz > |
239 | MAX_SWASR_MCLK_FREQ_WITHOUT_WR_TRAINING_MAXWELL_MHZ) | 251 | MAX_SWASR_MCLK_FREQ_WITHOUT_WR_TRAINING_MAXWELL_MHZ) { |
240 | payload |= | 252 | payload |= |
241 | NV_PMU_PG_PARAM_MCLK_CHANGE_GDDR5_WR_TRAINING_ENABLED; | 253 | NV_PMU_PG_PARAM_MCLK_CHANGE_GDDR5_WR_TRAINING_ENABLED; |
254 | } | ||
242 | 255 | ||
243 | if (payload != g->perf_pmu.lpwr.mclk_change_cache) { | 256 | if (payload != g->perf_pmu.lpwr.mclk_change_cache) { |
244 | g->perf_pmu.lpwr.mclk_change_cache = payload; | 257 | g->perf_pmu.lpwr.mclk_change_cache = payload; |
@@ -311,14 +324,16 @@ u32 nvgpu_lpwr_is_mscg_supported(struct gk20a *g, u32 pstate_num) | |||
311 | 324 | ||
312 | nvgpu_log_fn(g, " "); | 325 | nvgpu_log_fn(g, " "); |
313 | 326 | ||
314 | if (!pstate) | 327 | if (!pstate) { |
315 | return 0; | 328 | return 0; |
329 | } | ||
316 | 330 | ||
317 | ms_idx = pidx_data->entry[pstate->lpwr_entry_idx].ms_idx; | 331 | ms_idx = pidx_data->entry[pstate->lpwr_entry_idx].ms_idx; |
318 | if (pms_data->entry[ms_idx].ms_enabled) | 332 | if (pms_data->entry[ms_idx].ms_enabled) { |
319 | return 1; | 333 | return 1; |
320 | else | 334 | } else { |
321 | return 0; | 335 | return 0; |
336 | } | ||
322 | } | 337 | } |
323 | 338 | ||
324 | u32 nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num) | 339 | u32 nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num) |
@@ -332,14 +347,16 @@ u32 nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num) | |||
332 | 347 | ||
333 | nvgpu_log_fn(g, " "); | 348 | nvgpu_log_fn(g, " "); |
334 | 349 | ||
335 | if (!pstate) | 350 | if (!pstate) { |
336 | return 0; | 351 | return 0; |
352 | } | ||
337 | 353 | ||
338 | idx = pidx_data->entry[pstate->lpwr_entry_idx].gr_idx; | 354 | idx = pidx_data->entry[pstate->lpwr_entry_idx].gr_idx; |
339 | if (pgr_data->entry[idx].gr_enabled) | 355 | if (pgr_data->entry[idx].gr_enabled) { |
340 | return 1; | 356 | return 1; |
341 | else | 357 | } else { |
342 | return 0; | 358 | return 0; |
359 | } | ||
343 | } | 360 | } |
344 | 361 | ||
345 | 362 | ||
@@ -353,8 +370,9 @@ int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock) | |||
353 | 370 | ||
354 | nvgpu_log_fn(g, " "); | 371 | nvgpu_log_fn(g, " "); |
355 | 372 | ||
356 | if (pstate_lock) | 373 | if (pstate_lock) { |
357 | nvgpu_clk_arb_pstate_change_lock(g, true); | 374 | nvgpu_clk_arb_pstate_change_lock(g, true); |
375 | } | ||
358 | nvgpu_mutex_acquire(&pmu->pg_mutex); | 376 | nvgpu_mutex_acquire(&pmu->pg_mutex); |
359 | 377 | ||
360 | present_pstate = nvgpu_clk_arb_get_current_pstate(g); | 378 | present_pstate = nvgpu_clk_arb_get_current_pstate(g); |
@@ -362,20 +380,23 @@ int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock) | |||
362 | is_mscg_supported = nvgpu_lpwr_is_mscg_supported(g, | 380 | is_mscg_supported = nvgpu_lpwr_is_mscg_supported(g, |
363 | present_pstate); | 381 | present_pstate); |
364 | if (is_mscg_supported && g->mscg_enabled) { | 382 | if (is_mscg_supported && g->mscg_enabled) { |
365 | if (!pmu->mscg_stat) | 383 | if (!pmu->mscg_stat) { |
366 | pmu->mscg_stat = PMU_MSCG_ENABLED; | 384 | pmu->mscg_stat = PMU_MSCG_ENABLED; |
385 | } | ||
367 | } | 386 | } |
368 | 387 | ||
369 | is_rppg_supported = nvgpu_lpwr_is_rppg_supported(g, | 388 | is_rppg_supported = nvgpu_lpwr_is_rppg_supported(g, |
370 | present_pstate); | 389 | present_pstate); |
371 | if (is_rppg_supported) { | 390 | if (is_rppg_supported) { |
372 | if (g->support_pmu && g->can_elpg) | 391 | if (g->support_pmu && g->can_elpg) { |
373 | status = nvgpu_pmu_enable_elpg(g); | 392 | status = nvgpu_pmu_enable_elpg(g); |
393 | } | ||
374 | } | 394 | } |
375 | 395 | ||
376 | nvgpu_mutex_release(&pmu->pg_mutex); | 396 | nvgpu_mutex_release(&pmu->pg_mutex); |
377 | if (pstate_lock) | 397 | if (pstate_lock) { |
378 | nvgpu_clk_arb_pstate_change_lock(g, false); | 398 | nvgpu_clk_arb_pstate_change_lock(g, false); |
399 | } | ||
379 | 400 | ||
380 | return status; | 401 | return status; |
381 | } | 402 | } |
@@ -390,8 +411,9 @@ int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock) | |||
390 | 411 | ||
391 | nvgpu_log_fn(g, " "); | 412 | nvgpu_log_fn(g, " "); |
392 | 413 | ||
393 | if (pstate_lock) | 414 | if (pstate_lock) { |
394 | nvgpu_clk_arb_pstate_change_lock(g, true); | 415 | nvgpu_clk_arb_pstate_change_lock(g, true); |
416 | } | ||
395 | nvgpu_mutex_acquire(&pmu->pg_mutex); | 417 | nvgpu_mutex_acquire(&pmu->pg_mutex); |
396 | 418 | ||
397 | present_pstate = nvgpu_clk_arb_get_current_pstate(g); | 419 | present_pstate = nvgpu_clk_arb_get_current_pstate(g); |
@@ -401,22 +423,25 @@ int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock) | |||
401 | if (is_rppg_supported) { | 423 | if (is_rppg_supported) { |
402 | if (g->support_pmu && g->elpg_enabled) { | 424 | if (g->support_pmu && g->elpg_enabled) { |
403 | status = nvgpu_pmu_disable_elpg(g); | 425 | status = nvgpu_pmu_disable_elpg(g); |
404 | if (status) | 426 | if (status) { |
405 | goto exit_unlock; | 427 | goto exit_unlock; |
428 | } | ||
406 | } | 429 | } |
407 | } | 430 | } |
408 | 431 | ||
409 | is_mscg_supported = nvgpu_lpwr_is_mscg_supported(g, | 432 | is_mscg_supported = nvgpu_lpwr_is_mscg_supported(g, |
410 | present_pstate); | 433 | present_pstate); |
411 | if (is_mscg_supported && g->mscg_enabled) { | 434 | if (is_mscg_supported && g->mscg_enabled) { |
412 | if (pmu->mscg_stat) | 435 | if (pmu->mscg_stat) { |
413 | pmu->mscg_stat = PMU_MSCG_DISABLED; | 436 | pmu->mscg_stat = PMU_MSCG_DISABLED; |
437 | } | ||
414 | } | 438 | } |
415 | 439 | ||
416 | exit_unlock: | 440 | exit_unlock: |
417 | nvgpu_mutex_release(&pmu->pg_mutex); | 441 | nvgpu_mutex_release(&pmu->pg_mutex); |
418 | if (pstate_lock) | 442 | if (pstate_lock) { |
419 | nvgpu_clk_arb_pstate_change_lock(g, false); | 443 | nvgpu_clk_arb_pstate_change_lock(g, false); |
444 | } | ||
420 | 445 | ||
421 | nvgpu_log_fn(g, "done"); | 446 | nvgpu_log_fn(g, "done"); |
422 | return status; | 447 | return status; |
diff --git a/drivers/gpu/nvgpu/perf/perf.c b/drivers/gpu/nvgpu/perf/perf.c index 71bbcd40..f8b1daf0 100644 --- a/drivers/gpu/nvgpu/perf/perf.c +++ b/drivers/gpu/nvgpu/perf/perf.c | |||
@@ -46,8 +46,9 @@ static void perfrpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, | |||
46 | return; | 46 | return; |
47 | } | 47 | } |
48 | 48 | ||
49 | if (phandlerparams->prpccall->b_supported) | 49 | if (phandlerparams->prpccall->b_supported) { |
50 | phandlerparams->success = 1; | 50 | phandlerparams->success = 1; |
51 | } | ||
51 | } | 52 | } |
52 | 53 | ||
53 | static int pmu_handle_perf_event(struct gk20a *g, void *pmu_msg) | 54 | static int pmu_handle_perf_event(struct gk20a *g, void *pmu_msg) |
diff --git a/drivers/gpu/nvgpu/perf/vfe_equ.c b/drivers/gpu/nvgpu/perf/vfe_equ.c index fdeee9a7..8b308f37 100644 --- a/drivers/gpu/nvgpu/perf/vfe_equ.c +++ b/drivers/gpu/nvgpu/perf/vfe_equ.c | |||
@@ -62,8 +62,9 @@ static int _vfe_equs_pmudata_instget(struct gk20a *g, | |||
62 | nvgpu_log_info(g, " "); | 62 | nvgpu_log_info(g, " "); |
63 | 63 | ||
64 | /* check whether pmuboardobjgrp has a valid boardobj in index */ | 64 | /* check whether pmuboardobjgrp has a valid boardobj in index */ |
65 | if (idx >= CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) | 65 | if (idx >= CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) { |
66 | return -EINVAL; | 66 | return -EINVAL; |
67 | } | ||
67 | 68 | ||
68 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 69 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
69 | &pgrp_set->objects[idx].data.board_obj; | 70 | &pgrp_set->objects[idx].data.board_obj; |
@@ -105,8 +106,9 @@ int vfe_equ_sw_setup(struct gk20a *g) | |||
105 | pboardobjgrp->pmudatainstget = _vfe_equs_pmudata_instget; | 106 | pboardobjgrp->pmudatainstget = _vfe_equs_pmudata_instget; |
106 | 107 | ||
107 | status = devinit_get_vfe_equ_table(g, pvfeequobjs); | 108 | status = devinit_get_vfe_equ_table(g, pvfeequobjs); |
108 | if (status) | 109 | if (status) { |
109 | goto done; | 110 | goto done; |
111 | } | ||
110 | 112 | ||
111 | done: | 113 | done: |
112 | nvgpu_log_info(g, " done status %x", status); | 114 | nvgpu_log_info(g, " done status %x", status); |
@@ -122,8 +124,9 @@ int vfe_equ_pmu_setup(struct gk20a *g) | |||
122 | 124 | ||
123 | pboardobjgrp = &g->perf_pmu.vfe_equobjs.super.super; | 125 | pboardobjgrp = &g->perf_pmu.vfe_equobjs.super.super; |
124 | 126 | ||
125 | if (!pboardobjgrp->bconstructed) | 127 | if (!pboardobjgrp->bconstructed) { |
126 | return -EINVAL; | 128 | return -EINVAL; |
129 | } | ||
127 | 130 | ||
128 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 131 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
129 | 132 | ||
@@ -171,12 +174,12 @@ static int devinit_get_vfe_equ_table(struct gk20a *g, | |||
171 | } | 174 | } |
172 | 175 | ||
173 | if (vfeequs_tbl_header.vfe_equ_entry_size == | 176 | if (vfeequs_tbl_header.vfe_equ_entry_size == |
174 | VBIOS_VFE_3X_EQU_ENTRY_SIZE_17) | 177 | VBIOS_VFE_3X_EQU_ENTRY_SIZE_17) { |
175 | szfmt = VBIOS_VFE_3X_EQU_ENTRY_SIZE_17; | 178 | szfmt = VBIOS_VFE_3X_EQU_ENTRY_SIZE_17; |
176 | else if (vfeequs_tbl_header.vfe_equ_entry_size == | 179 | } else if (vfeequs_tbl_header.vfe_equ_entry_size == |
177 | VBIOS_VFE_3X_EQU_ENTRY_SIZE_18) | 180 | VBIOS_VFE_3X_EQU_ENTRY_SIZE_18) { |
178 | szfmt = VBIOS_VFE_3X_EQU_ENTRY_SIZE_18; | 181 | szfmt = VBIOS_VFE_3X_EQU_ENTRY_SIZE_18; |
179 | else { | 182 | } else { |
180 | status = -EINVAL; | 183 | status = -EINVAL; |
181 | goto done; | 184 | goto done; |
182 | } | 185 | } |
@@ -340,8 +343,9 @@ static int _vfe_equ_pmudatainit_super(struct gk20a *g, | |||
340 | nvgpu_log_info(g, " "); | 343 | nvgpu_log_info(g, " "); |
341 | 344 | ||
342 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); | 345 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); |
343 | if (status != 0) | 346 | if (status != 0) { |
344 | return status; | 347 | return status; |
348 | } | ||
345 | 349 | ||
346 | pvfe_equ = (struct vfe_equ *)board_obj_ptr; | 350 | pvfe_equ = (struct vfe_equ *)board_obj_ptr; |
347 | 351 | ||
@@ -367,8 +371,9 @@ static int vfe_equ_construct_super(struct gk20a *g, | |||
367 | 371 | ||
368 | status = boardobj_construct_super(g, ppboardobj, | 372 | status = boardobj_construct_super(g, ppboardobj, |
369 | size, pargs); | 373 | size, pargs); |
370 | if (status) | 374 | if (status) { |
371 | return -EINVAL; | 375 | return -EINVAL; |
376 | } | ||
372 | 377 | ||
373 | pvfeequ = (struct vfe_equ *)*ppboardobj; | 378 | pvfeequ = (struct vfe_equ *)*ppboardobj; |
374 | 379 | ||
@@ -395,8 +400,9 @@ static int _vfe_equ_pmudatainit_compare(struct gk20a *g, | |||
395 | nvgpu_log_info(g, " "); | 400 | nvgpu_log_info(g, " "); |
396 | 401 | ||
397 | status = _vfe_equ_pmudatainit_super(g, board_obj_ptr, ppmudata); | 402 | status = _vfe_equ_pmudatainit_super(g, board_obj_ptr, ppmudata); |
398 | if (status != 0) | 403 | if (status != 0) { |
399 | return status; | 404 | return status; |
405 | } | ||
400 | 406 | ||
401 | pvfe_equ_compare = (struct vfe_equ_compare *)board_obj_ptr; | 407 | pvfe_equ_compare = (struct vfe_equ_compare *)board_obj_ptr; |
402 | 408 | ||
@@ -421,13 +427,15 @@ static int vfe_equ_construct_compare(struct gk20a *g, | |||
421 | (struct vfe_equ_compare *)pargs; | 427 | (struct vfe_equ_compare *)pargs; |
422 | int status = 0; | 428 | int status = 0; |
423 | 429 | ||
424 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_COMPARE) | 430 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_COMPARE) { |
425 | return -EINVAL; | 431 | return -EINVAL; |
432 | } | ||
426 | 433 | ||
427 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_EQU_TYPE_COMPARE); | 434 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_EQU_TYPE_COMPARE); |
428 | status = vfe_equ_construct_super(g, ppboardobj, size, pargs); | 435 | status = vfe_equ_construct_super(g, ppboardobj, size, pargs); |
429 | if (status) | 436 | if (status) { |
430 | return -EINVAL; | 437 | return -EINVAL; |
438 | } | ||
431 | 439 | ||
432 | pvfeequ = (struct vfe_equ_compare *)*ppboardobj; | 440 | pvfeequ = (struct vfe_equ_compare *)*ppboardobj; |
433 | 441 | ||
@@ -454,8 +462,9 @@ static int _vfe_equ_pmudatainit_minmax(struct gk20a *g, | |||
454 | nvgpu_log_info(g, " "); | 462 | nvgpu_log_info(g, " "); |
455 | 463 | ||
456 | status = _vfe_equ_pmudatainit_super(g, board_obj_ptr, ppmudata); | 464 | status = _vfe_equ_pmudatainit_super(g, board_obj_ptr, ppmudata); |
457 | if (status != 0) | 465 | if (status != 0) { |
458 | return status; | 466 | return status; |
467 | } | ||
459 | 468 | ||
460 | pvfe_equ_minmax = (struct vfe_equ_minmax *)board_obj_ptr; | 469 | pvfe_equ_minmax = (struct vfe_equ_minmax *)board_obj_ptr; |
461 | 470 | ||
@@ -479,13 +488,15 @@ static int vfe_equ_construct_minmax(struct gk20a *g, | |||
479 | (struct vfe_equ_minmax *)pargs; | 488 | (struct vfe_equ_minmax *)pargs; |
480 | int status = 0; | 489 | int status = 0; |
481 | 490 | ||
482 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_MINMAX) | 491 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_MINMAX) { |
483 | return -EINVAL; | 492 | return -EINVAL; |
493 | } | ||
484 | 494 | ||
485 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_EQU_TYPE_MINMAX); | 495 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_EQU_TYPE_MINMAX); |
486 | status = vfe_equ_construct_super(g, ppboardobj, size, pargs); | 496 | status = vfe_equ_construct_super(g, ppboardobj, size, pargs); |
487 | if (status) | 497 | if (status) { |
488 | return -EINVAL; | 498 | return -EINVAL; |
499 | } | ||
489 | 500 | ||
490 | pvfeequ = (struct vfe_equ_minmax *)*ppboardobj; | 501 | pvfeequ = (struct vfe_equ_minmax *)*ppboardobj; |
491 | 502 | ||
@@ -510,8 +521,9 @@ static int _vfe_equ_pmudatainit_quadratic(struct gk20a *g, | |||
510 | nvgpu_log_info(g, " "); | 521 | nvgpu_log_info(g, " "); |
511 | 522 | ||
512 | status = _vfe_equ_pmudatainit_super(g, board_obj_ptr, ppmudata); | 523 | status = _vfe_equ_pmudatainit_super(g, board_obj_ptr, ppmudata); |
513 | if (status != 0) | 524 | if (status != 0) { |
514 | return status; | 525 | return status; |
526 | } | ||
515 | 527 | ||
516 | pvfe_equ_quadratic = (struct vfe_equ_quadratic *)board_obj_ptr; | 528 | pvfe_equ_quadratic = (struct vfe_equ_quadratic *)board_obj_ptr; |
517 | 529 | ||
@@ -535,13 +547,15 @@ static int vfe_equ_construct_quadratic(struct gk20a *g, | |||
535 | int status = 0; | 547 | int status = 0; |
536 | u32 i; | 548 | u32 i; |
537 | 549 | ||
538 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_QUADRATIC) | 550 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_QUADRATIC) { |
539 | return -EINVAL; | 551 | return -EINVAL; |
552 | } | ||
540 | 553 | ||
541 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_EQU_TYPE_QUADRATIC); | 554 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_EQU_TYPE_QUADRATIC); |
542 | status = vfe_equ_construct_super(g, ppboardobj, size, pargs); | 555 | status = vfe_equ_construct_super(g, ppboardobj, size, pargs); |
543 | if (status) | 556 | if (status) { |
544 | return -EINVAL; | 557 | return -EINVAL; |
558 | } | ||
545 | 559 | ||
546 | pvfeequ = (struct vfe_equ_quadratic *)*ppboardobj; | 560 | pvfeequ = (struct vfe_equ_quadratic *)*ppboardobj; |
547 | 561 | ||
@@ -583,8 +597,9 @@ static struct vfe_equ *construct_vfe_equ(struct gk20a *g, void *pargs) | |||
583 | 597 | ||
584 | } | 598 | } |
585 | 599 | ||
586 | if (status) | 600 | if (status) { |
587 | return NULL; | 601 | return NULL; |
602 | } | ||
588 | 603 | ||
589 | nvgpu_log_info(g, " Done"); | 604 | nvgpu_log_info(g, " Done"); |
590 | 605 | ||
diff --git a/drivers/gpu/nvgpu/perf/vfe_var.c b/drivers/gpu/nvgpu/perf/vfe_var.c index 5f6e9de7..9be069b0 100644 --- a/drivers/gpu/nvgpu/perf/vfe_var.c +++ b/drivers/gpu/nvgpu/perf/vfe_var.c | |||
@@ -72,8 +72,9 @@ static int _vfe_vars_pmudata_instget(struct gk20a *g, | |||
72 | nvgpu_log_info(g, " "); | 72 | nvgpu_log_info(g, " "); |
73 | 73 | ||
74 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 74 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
75 | if (idx >= CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) | 75 | if (idx >= CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) { |
76 | return -EINVAL; | 76 | return -EINVAL; |
77 | } | ||
77 | 78 | ||
78 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 79 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
79 | &pgrp_set->objects[idx].data.board_obj; | 80 | &pgrp_set->objects[idx].data.board_obj; |
@@ -90,8 +91,9 @@ static int _vfe_vars_pmustatus_instget(struct gk20a *g, void *pboardobjgrppmu, | |||
90 | pboardobjgrppmu; | 91 | pboardobjgrppmu; |
91 | 92 | ||
92 | if (((u32)BIT(idx) & | 93 | if (((u32)BIT(idx) & |
93 | pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) | 94 | pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) { |
94 | return -EINVAL; | 95 | return -EINVAL; |
96 | } | ||
95 | 97 | ||
96 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) | 98 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) |
97 | &pgrp_get_status->objects[idx].data.board_obj; | 99 | &pgrp_get_status->objects[idx].data.board_obj; |
@@ -134,8 +136,9 @@ int vfe_var_sw_setup(struct gk20a *g) | |||
134 | pboardobjgrp->pmustatusinstget = _vfe_vars_pmustatus_instget; | 136 | pboardobjgrp->pmustatusinstget = _vfe_vars_pmustatus_instget; |
135 | 137 | ||
136 | status = devinit_get_vfe_var_table(g, pvfevarobjs); | 138 | status = devinit_get_vfe_var_table(g, pvfevarobjs); |
137 | if (status) | 139 | if (status) { |
138 | goto done; | 140 | goto done; |
141 | } | ||
139 | 142 | ||
140 | status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g, | 143 | status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g, |
141 | &g->perf_pmu.vfe_varobjs.super.super, | 144 | &g->perf_pmu.vfe_varobjs.super.super, |
@@ -161,8 +164,9 @@ int vfe_var_pmu_setup(struct gk20a *g) | |||
161 | 164 | ||
162 | pboardobjgrp = &g->perf_pmu.vfe_varobjs.super.super; | 165 | pboardobjgrp = &g->perf_pmu.vfe_varobjs.super.super; |
163 | 166 | ||
164 | if (!pboardobjgrp->bconstructed) | 167 | if (!pboardobjgrp->bconstructed) { |
165 | return -EINVAL; | 168 | return -EINVAL; |
169 | } | ||
166 | 170 | ||
167 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 171 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
168 | 172 | ||
@@ -304,8 +308,9 @@ static int _vfe_var_pmudatainit_super(struct gk20a *g, | |||
304 | nvgpu_log_info(g, " "); | 308 | nvgpu_log_info(g, " "); |
305 | 309 | ||
306 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); | 310 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); |
307 | if (status != 0) | 311 | if (status != 0) { |
308 | return status; | 312 | return status; |
313 | } | ||
309 | 314 | ||
310 | pvfe_var = (struct vfe_var *)board_obj_ptr; | 315 | pvfe_var = (struct vfe_var *)board_obj_ptr; |
311 | pset = (struct nv_pmu_vfe_var *) ppmudata; | 316 | pset = (struct nv_pmu_vfe_var *) ppmudata; |
@@ -332,8 +337,9 @@ static int vfe_var_construct_super(struct gk20a *g, | |||
332 | nvgpu_log_info(g, " "); | 337 | nvgpu_log_info(g, " "); |
333 | 338 | ||
334 | status = boardobj_construct_super(g, ppboardobj, size, pargs); | 339 | status = boardobj_construct_super(g, ppboardobj, size, pargs); |
335 | if (status) | 340 | if (status) { |
336 | return -EINVAL; | 341 | return -EINVAL; |
342 | } | ||
337 | 343 | ||
338 | pvfevar = (struct vfe_var *)*ppboardobj; | 344 | pvfevar = (struct vfe_var *)*ppboardobj; |
339 | 345 | ||
@@ -373,8 +379,9 @@ static int vfe_var_construct_derived(struct gk20a *g, | |||
373 | 379 | ||
374 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_DERIVED); | 380 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_DERIVED); |
375 | status = vfe_var_construct_super(g, ppboardobj, size, pargs); | 381 | status = vfe_var_construct_super(g, ppboardobj, size, pargs); |
376 | if (status) | 382 | if (status) { |
377 | return -EINVAL; | 383 | return -EINVAL; |
384 | } | ||
378 | 385 | ||
379 | pvfevar = (struct vfe_var_derived *)*ppboardobj; | 386 | pvfevar = (struct vfe_var_derived *)*ppboardobj; |
380 | 387 | ||
@@ -395,8 +402,9 @@ static int _vfe_var_pmudatainit_derived_product(struct gk20a *g, | |||
395 | nvgpu_log_info(g, " "); | 402 | nvgpu_log_info(g, " "); |
396 | 403 | ||
397 | status = _vfe_var_pmudatainit_derived(g, board_obj_ptr, ppmudata); | 404 | status = _vfe_var_pmudatainit_derived(g, board_obj_ptr, ppmudata); |
398 | if (status != 0) | 405 | if (status != 0) { |
399 | return status; | 406 | return status; |
407 | } | ||
400 | 408 | ||
401 | pvfe_var_derived_product = | 409 | pvfe_var_derived_product = |
402 | (struct vfe_var_derived_product *)board_obj_ptr; | 410 | (struct vfe_var_derived_product *)board_obj_ptr; |
@@ -418,13 +426,15 @@ static int vfe_var_construct_derived_product(struct gk20a *g, | |||
418 | (struct vfe_var_derived_product *)pargs; | 426 | (struct vfe_var_derived_product *)pargs; |
419 | int status = 0; | 427 | int status = 0; |
420 | 428 | ||
421 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_DERIVED_PRODUCT) | 429 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_DERIVED_PRODUCT) { |
422 | return -EINVAL; | 430 | return -EINVAL; |
431 | } | ||
423 | 432 | ||
424 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_DERIVED_PRODUCT); | 433 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_DERIVED_PRODUCT); |
425 | status = vfe_var_construct_derived(g, ppboardobj, size, pargs); | 434 | status = vfe_var_construct_derived(g, ppboardobj, size, pargs); |
426 | if (status) | 435 | if (status) { |
427 | return -EINVAL; | 436 | return -EINVAL; |
437 | } | ||
428 | 438 | ||
429 | pvfevar = (struct vfe_var_derived_product *)*ppboardobj; | 439 | pvfevar = (struct vfe_var_derived_product *)*ppboardobj; |
430 | 440 | ||
@@ -449,8 +459,9 @@ static int _vfe_var_pmudatainit_derived_sum(struct gk20a *g, | |||
449 | nvgpu_log_info(g, " "); | 459 | nvgpu_log_info(g, " "); |
450 | 460 | ||
451 | status = _vfe_var_pmudatainit_derived(g, board_obj_ptr, ppmudata); | 461 | status = _vfe_var_pmudatainit_derived(g, board_obj_ptr, ppmudata); |
452 | if (status != 0) | 462 | if (status != 0) { |
453 | return status; | 463 | return status; |
464 | } | ||
454 | 465 | ||
455 | pvfe_var_derived_sum = (struct vfe_var_derived_sum *)board_obj_ptr; | 466 | pvfe_var_derived_sum = (struct vfe_var_derived_sum *)board_obj_ptr; |
456 | pset = (struct nv_pmu_vfe_var_derived_sum *)ppmudata; | 467 | pset = (struct nv_pmu_vfe_var_derived_sum *)ppmudata; |
@@ -471,13 +482,15 @@ static int vfe_var_construct_derived_sum(struct gk20a *g, | |||
471 | (struct vfe_var_derived_sum *)pargs; | 482 | (struct vfe_var_derived_sum *)pargs; |
472 | int status = 0; | 483 | int status = 0; |
473 | 484 | ||
474 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_DERIVED_SUM) | 485 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_DERIVED_SUM) { |
475 | return -EINVAL; | 486 | return -EINVAL; |
487 | } | ||
476 | 488 | ||
477 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_DERIVED_SUM); | 489 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_DERIVED_SUM); |
478 | status = vfe_var_construct_derived(g, ppboardobj, size, pargs); | 490 | status = vfe_var_construct_derived(g, ppboardobj, size, pargs); |
479 | if (status) | 491 | if (status) { |
480 | return -EINVAL; | 492 | return -EINVAL; |
493 | } | ||
481 | 494 | ||
482 | pvfevar = (struct vfe_var_derived_sum *)*ppboardobj; | 495 | pvfevar = (struct vfe_var_derived_sum *)*ppboardobj; |
483 | 496 | ||
@@ -501,8 +514,9 @@ static int _vfe_var_pmudatainit_single(struct gk20a *g, | |||
501 | nvgpu_log_info(g, " "); | 514 | nvgpu_log_info(g, " "); |
502 | 515 | ||
503 | status = _vfe_var_pmudatainit_super(g, board_obj_ptr, ppmudata); | 516 | status = _vfe_var_pmudatainit_super(g, board_obj_ptr, ppmudata); |
504 | if (status != 0) | 517 | if (status != 0) { |
505 | return status; | 518 | return status; |
519 | } | ||
506 | 520 | ||
507 | pvfe_var_single = (struct vfe_var_single *)board_obj_ptr; | 521 | pvfe_var_single = (struct vfe_var_single *)board_obj_ptr; |
508 | pset = (struct nv_pmu_vfe_var_single *) | 522 | pset = (struct nv_pmu_vfe_var_single *) |
@@ -537,13 +551,15 @@ static u32 vfe_var_construct_single_frequency(struct gk20a *g, | |||
537 | 551 | ||
538 | nvgpu_log_info(g, " "); | 552 | nvgpu_log_info(g, " "); |
539 | 553 | ||
540 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_FREQUENCY) | 554 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_FREQUENCY) { |
541 | return -EINVAL; | 555 | return -EINVAL; |
556 | } | ||
542 | 557 | ||
543 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_FREQUENCY); | 558 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_FREQUENCY); |
544 | status = vfe_var_construct_single(g, ppboardobj, size, pargs); | 559 | status = vfe_var_construct_single(g, ppboardobj, size, pargs); |
545 | if (status) | 560 | if (status) { |
546 | return -EINVAL; | 561 | return -EINVAL; |
562 | } | ||
547 | 563 | ||
548 | pvfevar = (struct vfe_var_single_frequency *)*ppboardobj; | 564 | pvfevar = (struct vfe_var_single_frequency *)*ppboardobj; |
549 | 565 | ||
@@ -581,8 +597,9 @@ static int _vfe_var_pmudatainit_single_sensed_fuse(struct gk20a *g, | |||
581 | nvgpu_log_info(g, " "); | 597 | nvgpu_log_info(g, " "); |
582 | 598 | ||
583 | status = _vfe_var_pmudatainit_single_sensed(g, board_obj_ptr, ppmudata); | 599 | status = _vfe_var_pmudatainit_single_sensed(g, board_obj_ptr, ppmudata); |
584 | if (status != 0) | 600 | if (status != 0) { |
585 | return status; | 601 | return status; |
602 | } | ||
586 | 603 | ||
587 | pvfe_var_single_sensed_fuse = | 604 | pvfe_var_single_sensed_fuse = |
588 | (struct vfe_var_single_sensed_fuse *)board_obj_ptr; | 605 | (struct vfe_var_single_sensed_fuse *)board_obj_ptr; |
@@ -618,8 +635,9 @@ static u32 vfe_var_construct_single_sensed(struct gk20a *g, | |||
618 | 635 | ||
619 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED); | 636 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED); |
620 | status = vfe_var_construct_single(g, ppboardobj, size, pargs); | 637 | status = vfe_var_construct_single(g, ppboardobj, size, pargs); |
621 | if (status) | 638 | if (status) { |
622 | return -EINVAL; | 639 | return -EINVAL; |
640 | } | ||
623 | 641 | ||
624 | pvfevar = (struct vfe_var_single_sensed *)*ppboardobj; | 642 | pvfevar = (struct vfe_var_single_sensed *)*ppboardobj; |
625 | 643 | ||
@@ -643,13 +661,15 @@ static u32 vfe_var_construct_single_sensed_fuse(struct gk20a *g, | |||
643 | 661 | ||
644 | nvgpu_log_info(g, " "); | 662 | nvgpu_log_info(g, " "); |
645 | 663 | ||
646 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_FUSE) | 664 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_FUSE) { |
647 | return -EINVAL; | 665 | return -EINVAL; |
666 | } | ||
648 | 667 | ||
649 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_FUSE); | 668 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_FUSE); |
650 | status = vfe_var_construct_single_sensed(g, ppboardobj, size, pargs); | 669 | status = vfe_var_construct_single_sensed(g, ppboardobj, size, pargs); |
651 | if (status) | 670 | if (status) { |
652 | return -EINVAL; | 671 | return -EINVAL; |
672 | } | ||
653 | 673 | ||
654 | pvfevar = (struct vfe_var_single_sensed_fuse *)*ppboardobj; | 674 | pvfevar = (struct vfe_var_single_sensed_fuse *)*ppboardobj; |
655 | 675 | ||
@@ -690,8 +710,9 @@ static u32 vfe_var_construct_single_sensed_fuse(struct gk20a *g, | |||
690 | goto exit; | 710 | goto exit; |
691 | } | 711 | } |
692 | exit: | 712 | exit: |
693 | if (status) | 713 | if (status) { |
694 | (*ppboardobj)->destruct(*ppboardobj); | 714 | (*ppboardobj)->destruct(*ppboardobj); |
715 | } | ||
695 | 716 | ||
696 | return status; | 717 | return status; |
697 | } | 718 | } |
@@ -707,8 +728,9 @@ static int _vfe_var_pmudatainit_single_sensed_temp(struct gk20a *g, | |||
707 | nvgpu_log_info(g, " "); | 728 | nvgpu_log_info(g, " "); |
708 | 729 | ||
709 | status = _vfe_var_pmudatainit_single_sensed(g, board_obj_ptr, ppmudata); | 730 | status = _vfe_var_pmudatainit_single_sensed(g, board_obj_ptr, ppmudata); |
710 | if (status != 0) | 731 | if (status != 0) { |
711 | return status; | 732 | return status; |
733 | } | ||
712 | 734 | ||
713 | pvfe_var_single_sensed_temp = | 735 | pvfe_var_single_sensed_temp = |
714 | (struct vfe_var_single_sensed_temp *)board_obj_ptr; | 736 | (struct vfe_var_single_sensed_temp *)board_obj_ptr; |
@@ -736,13 +758,15 @@ static u32 vfe_var_construct_single_sensed_temp(struct gk20a *g, | |||
736 | (struct vfe_var_single_sensed_temp *)pargs; | 758 | (struct vfe_var_single_sensed_temp *)pargs; |
737 | u32 status = 0; | 759 | u32 status = 0; |
738 | 760 | ||
739 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_TEMP) | 761 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_TEMP) { |
740 | return -EINVAL; | 762 | return -EINVAL; |
763 | } | ||
741 | 764 | ||
742 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_TEMP); | 765 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_TEMP); |
743 | status = vfe_var_construct_single_sensed(g, ppboardobj, size, pargs); | 766 | status = vfe_var_construct_single_sensed(g, ppboardobj, size, pargs); |
744 | if (status) | 767 | if (status) { |
745 | return -EINVAL; | 768 | return -EINVAL; |
769 | } | ||
746 | 770 | ||
747 | pvfevar = (struct vfe_var_single_sensed_temp *)*ppboardobj; | 771 | pvfevar = (struct vfe_var_single_sensed_temp *)*ppboardobj; |
748 | 772 | ||
@@ -784,13 +808,15 @@ static int vfe_var_construct_single_voltage(struct gk20a *g, | |||
784 | struct vfe_var_single_voltage *pvfevar; | 808 | struct vfe_var_single_voltage *pvfevar; |
785 | int status = 0; | 809 | int status = 0; |
786 | 810 | ||
787 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_VOLTAGE) | 811 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_VOLTAGE) { |
788 | return -EINVAL; | 812 | return -EINVAL; |
813 | } | ||
789 | 814 | ||
790 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_VOLTAGE); | 815 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_VOLTAGE); |
791 | status = vfe_var_construct_super(g, ppboardobj, size, pargs); | 816 | status = vfe_var_construct_super(g, ppboardobj, size, pargs); |
792 | if (status) | 817 | if (status) { |
793 | return -EINVAL; | 818 | return -EINVAL; |
819 | } | ||
794 | 820 | ||
795 | pvfevar = (struct vfe_var_single_voltage *)*ppboardobj; | 821 | pvfevar = (struct vfe_var_single_voltage *)*ppboardobj; |
796 | 822 | ||
@@ -847,8 +873,9 @@ static struct vfe_var *construct_vfe_var(struct gk20a *g, void *pargs) | |||
847 | return NULL; | 873 | return NULL; |
848 | } | 874 | } |
849 | 875 | ||
850 | if (status) | 876 | if (status) { |
851 | return NULL; | 877 | return NULL; |
878 | } | ||
852 | 879 | ||
853 | nvgpu_log_info(g, "done"); | 880 | nvgpu_log_info(g, "done"); |
854 | 881 | ||
@@ -896,12 +923,12 @@ static int devinit_get_vfe_var_table(struct gk20a *g, | |||
896 | } | 923 | } |
897 | 924 | ||
898 | if (vfevars_tbl_header.vfe_var_entry_size == | 925 | if (vfevars_tbl_header.vfe_var_entry_size == |
899 | VBIOS_VFE_3X_VAR_ENTRY_SIZE_19) | 926 | VBIOS_VFE_3X_VAR_ENTRY_SIZE_19) { |
900 | szfmt = VBIOS_VFE_3X_VAR_ENTRY_SIZE_19; | 927 | szfmt = VBIOS_VFE_3X_VAR_ENTRY_SIZE_19; |
901 | else if (vfevars_tbl_header.vfe_var_entry_size == | 928 | } else if (vfevars_tbl_header.vfe_var_entry_size == |
902 | VBIOS_VFE_3X_VAR_ENTRY_SIZE_11) | 929 | VBIOS_VFE_3X_VAR_ENTRY_SIZE_11) { |
903 | szfmt = VBIOS_VFE_3X_VAR_ENTRY_SIZE_11; | 930 | szfmt = VBIOS_VFE_3X_VAR_ENTRY_SIZE_11; |
904 | else { | 931 | } else { |
905 | status = -EINVAL; | 932 | status = -EINVAL; |
906 | goto done; | 933 | goto done; |
907 | } | 934 | } |
@@ -1047,8 +1074,9 @@ static int vfe_var_construct_single(struct gk20a *g, | |||
1047 | 1074 | ||
1048 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE); | 1075 | ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE); |
1049 | status = vfe_var_construct_super(g, ppboardobj, size, pargs); | 1076 | status = vfe_var_construct_super(g, ppboardobj, size, pargs); |
1050 | if (status) | 1077 | if (status) { |
1051 | return -EINVAL; | 1078 | return -EINVAL; |
1079 | } | ||
1052 | 1080 | ||
1053 | pvfevar = (struct vfe_var_single *)*ppboardobj; | 1081 | pvfevar = (struct vfe_var_single *)*ppboardobj; |
1054 | 1082 | ||
diff --git a/drivers/gpu/nvgpu/pmgr/pmgr.c b/drivers/gpu/nvgpu/pmgr/pmgr.c index 6be0f82f..227a9893 100644 --- a/drivers/gpu/nvgpu/pmgr/pmgr.c +++ b/drivers/gpu/nvgpu/pmgr/pmgr.c | |||
@@ -30,9 +30,10 @@ int pmgr_pwr_devices_get_power(struct gk20a *g, u32 *val) | |||
30 | int status; | 30 | int status; |
31 | 31 | ||
32 | status = pmgr_pmu_pwr_devices_query_blocking(g, 1, &payload); | 32 | status = pmgr_pmu_pwr_devices_query_blocking(g, 1, &payload); |
33 | if (status) | 33 | if (status) { |
34 | nvgpu_err(g, "pmgr_pwr_devices_get_current_power failed %x", | 34 | nvgpu_err(g, "pmgr_pwr_devices_get_current_power failed %x", |
35 | status); | 35 | status); |
36 | } | ||
36 | 37 | ||
37 | *val = payload.devices[0].powerm_w; | 38 | *val = payload.devices[0].powerm_w; |
38 | 39 | ||
@@ -45,9 +46,10 @@ int pmgr_pwr_devices_get_current(struct gk20a *g, u32 *val) | |||
45 | int status; | 46 | int status; |
46 | 47 | ||
47 | status = pmgr_pmu_pwr_devices_query_blocking(g, 1, &payload); | 48 | status = pmgr_pmu_pwr_devices_query_blocking(g, 1, &payload); |
48 | if (status) | 49 | if (status) { |
49 | nvgpu_err(g, "pmgr_pwr_devices_get_current failed %x", | 50 | nvgpu_err(g, "pmgr_pwr_devices_get_current failed %x", |
50 | status); | 51 | status); |
52 | } | ||
51 | 53 | ||
52 | *val = payload.devices[0].currentm_a; | 54 | *val = payload.devices[0].currentm_a; |
53 | 55 | ||
@@ -60,9 +62,10 @@ int pmgr_pwr_devices_get_voltage(struct gk20a *g, u32 *val) | |||
60 | int status; | 62 | int status; |
61 | 63 | ||
62 | status = pmgr_pmu_pwr_devices_query_blocking(g, 1, &payload); | 64 | status = pmgr_pmu_pwr_devices_query_blocking(g, 1, &payload); |
63 | if (status) | 65 | if (status) { |
64 | nvgpu_err(g, "pmgr_pwr_devices_get_current_voltage failed %x", | 66 | nvgpu_err(g, "pmgr_pwr_devices_get_current_voltage failed %x", |
65 | status); | 67 | status); |
68 | } | ||
66 | 69 | ||
67 | *val = payload.devices[0].voltageu_v; | 70 | *val = payload.devices[0].voltageu_v; |
68 | 71 | ||
diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c index 69c43a01..d0c0e763 100644 --- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c +++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c | |||
@@ -168,9 +168,10 @@ static u32 pmgr_send_i2c_device_topology_to_pmu(struct gk20a *g) | |||
168 | PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED, | 168 | PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED, |
169 | &i2c_desc_table); | 169 | &i2c_desc_table); |
170 | 170 | ||
171 | if (status) | 171 | if (status) { |
172 | nvgpu_err(g, "pmgr_pmu_set_object failed %x", | 172 | nvgpu_err(g, "pmgr_pmu_set_object failed %x", |
173 | status); | 173 | status); |
174 | } | ||
174 | 175 | ||
175 | return status; | 176 | return status; |
176 | } | 177 | } |
@@ -183,8 +184,9 @@ static int pmgr_send_pwr_device_topology_to_pmu(struct gk20a *g) | |||
183 | 184 | ||
184 | /* Set the BA-device-independent HW information */ | 185 | /* Set the BA-device-independent HW information */ |
185 | pwr_desc_table = nvgpu_kzalloc(g, sizeof(*pwr_desc_table)); | 186 | pwr_desc_table = nvgpu_kzalloc(g, sizeof(*pwr_desc_table)); |
186 | if (!pwr_desc_table) | 187 | if (!pwr_desc_table) { |
187 | return -ENOMEM; | 188 | return -ENOMEM; |
189 | } | ||
188 | 190 | ||
189 | ppwr_desc_header = &(pwr_desc_table->hdr.data); | 191 | ppwr_desc_header = &(pwr_desc_table->hdr.data); |
190 | ppwr_desc_header->ba_info.b_initialized_and_used = false; | 192 | ppwr_desc_header->ba_info.b_initialized_and_used = false; |
@@ -212,9 +214,10 @@ static int pmgr_send_pwr_device_topology_to_pmu(struct gk20a *g) | |||
212 | (u16)sizeof(struct nv_pmu_pmgr_pwr_device_desc_table), | 214 | (u16)sizeof(struct nv_pmu_pmgr_pwr_device_desc_table), |
213 | pwr_desc_table); | 215 | pwr_desc_table); |
214 | 216 | ||
215 | if (status) | 217 | if (status) { |
216 | nvgpu_err(g, "pmgr_pmu_set_object failed %x", | 218 | nvgpu_err(g, "pmgr_pmu_set_object failed %x", |
217 | status); | 219 | status); |
220 | } | ||
218 | 221 | ||
219 | exit: | 222 | exit: |
220 | nvgpu_kfree(g, pwr_desc_table); | 223 | nvgpu_kfree(g, pwr_desc_table); |
@@ -230,8 +233,9 @@ static int pmgr_send_pwr_mointer_to_pmu(struct gk20a *g) | |||
230 | int status = 0; | 233 | int status = 0; |
231 | 234 | ||
232 | pwr_monitor_pack = nvgpu_kzalloc(g, sizeof(*pwr_monitor_pack)); | 235 | pwr_monitor_pack = nvgpu_kzalloc(g, sizeof(*pwr_monitor_pack)); |
233 | if (!pwr_monitor_pack) | 236 | if (!pwr_monitor_pack) { |
234 | return -ENOMEM; | 237 | return -ENOMEM; |
238 | } | ||
235 | 239 | ||
236 | /* Copy all the global settings from the RM copy */ | 240 | /* Copy all the global settings from the RM copy */ |
237 | pwr_channel_hdr = &(pwr_monitor_pack->channels.hdr.data); | 241 | pwr_channel_hdr = &(pwr_monitor_pack->channels.hdr.data); |
@@ -281,9 +285,10 @@ static int pmgr_send_pwr_mointer_to_pmu(struct gk20a *g) | |||
281 | (u16)sizeof(struct nv_pmu_pmgr_pwr_monitor_pack), | 285 | (u16)sizeof(struct nv_pmu_pmgr_pwr_monitor_pack), |
282 | pwr_monitor_pack); | 286 | pwr_monitor_pack); |
283 | 287 | ||
284 | if (status) | 288 | if (status) { |
285 | nvgpu_err(g, "pmgr_pmu_set_object failed %x", | 289 | nvgpu_err(g, "pmgr_pmu_set_object failed %x", |
286 | status); | 290 | status); |
291 | } | ||
287 | 292 | ||
288 | exit: | 293 | exit: |
289 | nvgpu_kfree(g, pwr_monitor_pack); | 294 | nvgpu_kfree(g, pwr_monitor_pack); |
@@ -365,9 +370,10 @@ static int pmgr_send_pwr_policy_to_pmu(struct gk20a *g) | |||
365 | (u16)sizeof(struct nv_pmu_pmgr_pwr_policy_pack), | 370 | (u16)sizeof(struct nv_pmu_pmgr_pwr_policy_pack), |
366 | ppwrpack); | 371 | ppwrpack); |
367 | 372 | ||
368 | if (status) | 373 | if (status) { |
369 | nvgpu_err(g, "pmgr_pmu_set_object failed %x", | 374 | nvgpu_err(g, "pmgr_pmu_set_object failed %x", |
370 | status); | 375 | status); |
376 | } | ||
371 | 377 | ||
372 | exit: | 378 | exit: |
373 | if (ppwrpack) { | 379 | if (ppwrpack) { |
diff --git a/drivers/gpu/nvgpu/pmgr/pwrdev.c b/drivers/gpu/nvgpu/pmgr/pwrdev.c index 235629d6..90d39610 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrdev.c +++ b/drivers/gpu/nvgpu/pmgr/pwrdev.c | |||
@@ -40,8 +40,9 @@ static int _pwr_device_pmudata_instget(struct gk20a *g, | |||
40 | 40 | ||
41 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 41 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
42 | if (((u32)BIT(idx) & | 42 | if (((u32)BIT(idx) & |
43 | ppmgrdevice->hdr.data.super.obj_mask.super.data[0]) == 0) | 43 | ppmgrdevice->hdr.data.super.obj_mask.super.data[0]) == 0) { |
44 | return -EINVAL; | 44 | return -EINVAL; |
45 | } | ||
45 | 46 | ||
46 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 47 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
47 | &ppmgrdevice->devices[idx].data.board_obj; | 48 | &ppmgrdevice->devices[idx].data.board_obj; |
@@ -99,8 +100,9 @@ static struct boardobj *construct_pwr_device(struct gk20a *g, | |||
99 | 100 | ||
100 | status = boardobj_construct_super(g, &board_obj_ptr, | 101 | status = boardobj_construct_super(g, &board_obj_ptr, |
101 | pargs_size, pargs); | 102 | pargs_size, pargs); |
102 | if (status) | 103 | if (status) { |
103 | return NULL; | 104 | return NULL; |
105 | } | ||
104 | 106 | ||
105 | pwrdev = (struct pwr_device_ina3221*)board_obj_ptr; | 107 | pwrdev = (struct pwr_device_ina3221*)board_obj_ptr; |
106 | 108 | ||
@@ -250,8 +252,9 @@ static int devinit_get_pwr_device_table(struct gk20a *g, | |||
250 | pwr_device_data.ina3221.curr_correct_m = (1 << 12); | 252 | pwr_device_data.ina3221.curr_correct_m = (1 << 12); |
251 | } | 253 | } |
252 | pwr_device_size = sizeof(struct pwr_device_ina3221); | 254 | pwr_device_size = sizeof(struct pwr_device_ina3221); |
253 | } else | 255 | } else { |
254 | continue; | 256 | continue; |
257 | } | ||
255 | 258 | ||
256 | pwr_device_data.boardobj.type = CTRL_PMGR_PWR_DEVICE_TYPE_INA3221; | 259 | pwr_device_data.boardobj.type = CTRL_PMGR_PWR_DEVICE_TYPE_INA3221; |
257 | pwr_device_data.pwrdev.power_rail = (u8)0; | 260 | pwr_device_data.pwrdev.power_rail = (u8)0; |
@@ -306,8 +309,9 @@ int pmgr_device_sw_setup(struct gk20a *g) | |||
306 | pboardobjgrp->pmudatainstget = _pwr_device_pmudata_instget; | 309 | pboardobjgrp->pmudatainstget = _pwr_device_pmudata_instget; |
307 | 310 | ||
308 | status = devinit_get_pwr_device_table(g, ppwrdeviceobjs); | 311 | status = devinit_get_pwr_device_table(g, ppwrdeviceobjs); |
309 | if (status) | 312 | if (status) { |
310 | goto done; | 313 | goto done; |
314 | } | ||
311 | 315 | ||
312 | done: | 316 | done: |
313 | nvgpu_log_info(g, " done status %x", status); | 317 | nvgpu_log_info(g, " done status %x", status); |
diff --git a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c index 53c7a1c4..9b2f91de 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c +++ b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c | |||
@@ -40,8 +40,9 @@ static int _pwr_channel_pmudata_instget(struct gk20a *g, | |||
40 | 40 | ||
41 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 41 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
42 | if (((u32)BIT(idx) & | 42 | if (((u32)BIT(idx) & |
43 | ppmgrchannel->hdr.data.super.obj_mask.super.data[0]) == 0) | 43 | ppmgrchannel->hdr.data.super.obj_mask.super.data[0]) == 0) { |
44 | return -EINVAL; | 44 | return -EINVAL; |
45 | } | ||
45 | 46 | ||
46 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 47 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
47 | &ppmgrchannel->channels[idx].data.board_obj; | 48 | &ppmgrchannel->channels[idx].data.board_obj; |
@@ -66,8 +67,9 @@ static int _pwr_channel_rels_pmudata_instget(struct gk20a *g, | |||
66 | 67 | ||
67 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 68 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
68 | if (((u32)BIT(idx) & | 69 | if (((u32)BIT(idx) & |
69 | ppmgrchrels->hdr.data.super.obj_mask.super.data[0]) == 0) | 70 | ppmgrchrels->hdr.data.super.obj_mask.super.data[0]) == 0) { |
70 | return -EINVAL; | 71 | return -EINVAL; |
72 | } | ||
71 | 73 | ||
72 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 74 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
73 | &ppmgrchrels->ch_rels[idx].data.board_obj; | 75 | &ppmgrchrels->ch_rels[idx].data.board_obj; |
@@ -150,8 +152,9 @@ static struct boardobj *construct_pwr_topology(struct gk20a *g, | |||
150 | 152 | ||
151 | status = boardobj_construct_super(g, &board_obj_ptr, | 153 | status = boardobj_construct_super(g, &board_obj_ptr, |
152 | pargs_size, pargs); | 154 | pargs_size, pargs); |
153 | if (status) | 155 | if (status) { |
154 | return NULL; | 156 | return NULL; |
157 | } | ||
155 | 158 | ||
156 | pwrchannel = (struct pwr_channel_sensor*)board_obj_ptr; | 159 | pwrchannel = (struct pwr_channel_sensor*)board_obj_ptr; |
157 | 160 | ||
@@ -253,8 +256,9 @@ static int devinit_get_pwr_topology_table(struct gk20a *g, | |||
253 | NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX); | 256 | NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX); |
254 | 257 | ||
255 | pwr_topology_size = sizeof(struct pwr_channel_sensor); | 258 | pwr_topology_size = sizeof(struct pwr_channel_sensor); |
256 | } else | 259 | } else { |
257 | continue; | 260 | continue; |
261 | } | ||
258 | 262 | ||
259 | /* Initialize data for the parent class */ | 263 | /* Initialize data for the parent class */ |
260 | pwr_topology_data.boardobj.type = CTRL_PMGR_PWR_CHANNEL_TYPE_SENSOR; | 264 | pwr_topology_data.boardobj.type = CTRL_PMGR_PWR_CHANNEL_TYPE_SENSOR; |
@@ -345,12 +349,14 @@ int pmgr_monitor_sw_setup(struct gk20a *g) | |||
345 | ppwrmonitorobjs = &(g->pmgr_pmu.pmgr_monitorobjs); | 349 | ppwrmonitorobjs = &(g->pmgr_pmu.pmgr_monitorobjs); |
346 | 350 | ||
347 | status = devinit_get_pwr_topology_table(g, ppwrmonitorobjs); | 351 | status = devinit_get_pwr_topology_table(g, ppwrmonitorobjs); |
348 | if (status) | 352 | if (status) { |
349 | goto done; | 353 | goto done; |
354 | } | ||
350 | 355 | ||
351 | status = _pwr_channel_state_init(g); | 356 | status = _pwr_channel_state_init(g); |
352 | if (status) | 357 | if (status) { |
353 | goto done; | 358 | goto done; |
359 | } | ||
354 | 360 | ||
355 | /* Initialise physicalChannelMask */ | 361 | /* Initialise physicalChannelMask */ |
356 | g->pmgr_pmu.pmgr_monitorobjs.physical_channel_mask = 0; | 362 | g->pmgr_pmu.pmgr_monitorobjs.physical_channel_mask = 0; |
diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c index 13a94e4f..d3fd941e 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c +++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c | |||
@@ -264,8 +264,9 @@ static struct boardobj *construct_pwr_policy(struct gk20a *g, | |||
264 | 264 | ||
265 | status = boardobj_construct_super(g, &board_obj_ptr, | 265 | status = boardobj_construct_super(g, &board_obj_ptr, |
266 | pargs_size, pargs); | 266 | pargs_size, pargs); |
267 | if (status) | 267 | if (status) { |
268 | return NULL; | 268 | return NULL; |
269 | } | ||
269 | 270 | ||
270 | pwrpolicyhwthreshold = (struct pwr_policy_hw_threshold*)board_obj_ptr; | 271 | pwrpolicyhwthreshold = (struct pwr_policy_hw_threshold*)board_obj_ptr; |
271 | pwrpolicy = (struct pwr_policy *)board_obj_ptr; | 272 | pwrpolicy = (struct pwr_policy *)board_obj_ptr; |
@@ -575,8 +576,9 @@ static int devinit_get_pwr_policy_table(struct gk20a *g, | |||
575 | packed_entry->flags0, | 576 | packed_entry->flags0, |
576 | NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS); | 577 | NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS); |
577 | 578 | ||
578 | if (class_type != NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD) | 579 | if (class_type != NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD) { |
579 | continue; | 580 | continue; |
581 | } | ||
580 | 582 | ||
581 | /* unpack power policy table entry */ | 583 | /* unpack power policy table entry */ |
582 | devinit_unpack_pwr_policy_entry(&entry, packed_entry); | 584 | devinit_unpack_pwr_policy_entry(&entry, packed_entry); |
@@ -759,8 +761,9 @@ int pmgr_policy_sw_setup(struct gk20a *g) | |||
759 | pboardobjgrp = &(g->pmgr_pmu.pmgr_policyobjs.pwr_policies.super); | 761 | pboardobjgrp = &(g->pmgr_pmu.pmgr_policyobjs.pwr_policies.super); |
760 | 762 | ||
761 | status = devinit_get_pwr_policy_table(g, ppwrpolicyobjs); | 763 | status = devinit_get_pwr_policy_table(g, ppwrpolicyobjs); |
762 | if (status) | 764 | if (status) { |
763 | goto done; | 765 | goto done; |
766 | } | ||
764 | 767 | ||
765 | g->pmgr_pmu.pmgr_policyobjs.b_enabled = true; | 768 | g->pmgr_pmu.pmgr_policyobjs.b_enabled = true; |
766 | 769 | ||
diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c index 9b7d9b7e..616d6747 100644 --- a/drivers/gpu/nvgpu/pstate/pstate.c +++ b/drivers/gpu/nvgpu/pstate/pstate.c | |||
@@ -35,8 +35,9 @@ static int pstate_sw_setup(struct gk20a *g); | |||
35 | 35 | ||
36 | void gk20a_deinit_pstate_support(struct gk20a *g) | 36 | void gk20a_deinit_pstate_support(struct gk20a *g) |
37 | { | 37 | { |
38 | if (g->ops.clk.mclk_deinit) | 38 | if (g->ops.clk.mclk_deinit) { |
39 | g->ops.clk.mclk_deinit(g); | 39 | g->ops.clk.mclk_deinit(g); |
40 | } | ||
40 | 41 | ||
41 | nvgpu_mutex_destroy(&g->perf_pmu.pstatesobjs.pstate_mutex); | 42 | nvgpu_mutex_destroy(&g->perf_pmu.pstatesobjs.pstate_mutex); |
42 | } | 43 | } |
@@ -49,69 +50,84 @@ int gk20a_init_pstate_support(struct gk20a *g) | |||
49 | nvgpu_log_fn(g, " "); | 50 | nvgpu_log_fn(g, " "); |
50 | 51 | ||
51 | err = volt_rail_sw_setup(g); | 52 | err = volt_rail_sw_setup(g); |
52 | if (err) | 53 | if (err) { |
53 | return err; | 54 | return err; |
55 | } | ||
54 | 56 | ||
55 | err = volt_dev_sw_setup(g); | 57 | err = volt_dev_sw_setup(g); |
56 | if (err) | 58 | if (err) { |
57 | return err; | 59 | return err; |
60 | } | ||
58 | 61 | ||
59 | err = volt_policy_sw_setup(g); | 62 | err = volt_policy_sw_setup(g); |
60 | if (err) | 63 | if (err) { |
61 | return err; | 64 | return err; |
65 | } | ||
62 | 66 | ||
63 | err = clk_vin_sw_setup(g); | 67 | err = clk_vin_sw_setup(g); |
64 | if (err) | 68 | if (err) { |
65 | return err; | 69 | return err; |
70 | } | ||
66 | 71 | ||
67 | err = clk_fll_sw_setup(g); | 72 | err = clk_fll_sw_setup(g); |
68 | if (err) | 73 | if (err) { |
69 | return err; | 74 | return err; |
75 | } | ||
70 | 76 | ||
71 | err = therm_domain_sw_setup(g); | 77 | err = therm_domain_sw_setup(g); |
72 | if (err) | 78 | if (err) { |
73 | return err; | 79 | return err; |
80 | } | ||
74 | 81 | ||
75 | err = vfe_var_sw_setup(g); | 82 | err = vfe_var_sw_setup(g); |
76 | if (err) | 83 | if (err) { |
77 | return err; | 84 | return err; |
85 | } | ||
78 | 86 | ||
79 | err = vfe_equ_sw_setup(g); | 87 | err = vfe_equ_sw_setup(g); |
80 | if (err) | 88 | if (err) { |
81 | return err; | 89 | return err; |
90 | } | ||
82 | 91 | ||
83 | err = clk_domain_sw_setup(g); | 92 | err = clk_domain_sw_setup(g); |
84 | if (err) | 93 | if (err) { |
85 | return err; | 94 | return err; |
95 | } | ||
86 | 96 | ||
87 | err = clk_vf_point_sw_setup(g); | 97 | err = clk_vf_point_sw_setup(g); |
88 | if (err) | 98 | if (err) { |
89 | return err; | 99 | return err; |
100 | } | ||
90 | 101 | ||
91 | err = clk_prog_sw_setup(g); | 102 | err = clk_prog_sw_setup(g); |
92 | if (err) | 103 | if (err) { |
93 | return err; | 104 | return err; |
105 | } | ||
94 | 106 | ||
95 | err = pstate_sw_setup(g); | 107 | err = pstate_sw_setup(g); |
96 | if (err) | 108 | if (err) { |
97 | return err; | 109 | return err; |
110 | } | ||
98 | 111 | ||
99 | if(g->ops.clk.support_pmgr_domain) { | 112 | if(g->ops.clk.support_pmgr_domain) { |
100 | err = pmgr_domain_sw_setup(g); | 113 | err = pmgr_domain_sw_setup(g); |
101 | if (err) | 114 | if (err) { |
102 | return err; | 115 | return err; |
116 | } | ||
103 | } | 117 | } |
104 | 118 | ||
105 | if (g->ops.clk.support_clk_freq_controller) { | 119 | if (g->ops.clk.support_clk_freq_controller) { |
106 | err = clk_freq_controller_sw_setup(g); | 120 | err = clk_freq_controller_sw_setup(g); |
107 | if (err) | 121 | if (err) { |
108 | return err; | 122 | return err; |
123 | } | ||
109 | } | 124 | } |
110 | 125 | ||
111 | if(g->ops.clk.support_lpwr_pg) { | 126 | if(g->ops.clk.support_lpwr_pg) { |
112 | err = nvgpu_lpwr_pg_setup(g); | 127 | err = nvgpu_lpwr_pg_setup(g); |
113 | if (err) | 128 | if (err) { |
114 | return err; | 129 | return err; |
130 | } | ||
115 | } | 131 | } |
116 | 132 | ||
117 | return err; | 133 | return err; |
@@ -133,16 +149,19 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g) | |||
133 | } | 149 | } |
134 | 150 | ||
135 | err = volt_rail_pmu_setup(g); | 151 | err = volt_rail_pmu_setup(g); |
136 | if (err) | 152 | if (err) { |
137 | return err; | 153 | return err; |
154 | } | ||
138 | 155 | ||
139 | err = volt_dev_pmu_setup(g); | 156 | err = volt_dev_pmu_setup(g); |
140 | if (err) | 157 | if (err) { |
141 | return err; | 158 | return err; |
159 | } | ||
142 | 160 | ||
143 | err = volt_policy_pmu_setup(g); | 161 | err = volt_policy_pmu_setup(g); |
144 | if (err) | 162 | if (err) { |
145 | return err; | 163 | return err; |
164 | } | ||
146 | 165 | ||
147 | err = g->ops.pmu_ver.volt.volt_send_load_cmd_to_pmu(g); | 166 | err = g->ops.pmu_ver.volt.volt_send_load_cmd_to_pmu(g); |
148 | if (err) { | 167 | if (err) { |
@@ -153,52 +172,64 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g) | |||
153 | } | 172 | } |
154 | 173 | ||
155 | err = therm_domain_pmu_setup(g); | 174 | err = therm_domain_pmu_setup(g); |
156 | if (err) | 175 | if (err) { |
157 | return err; | 176 | return err; |
177 | } | ||
158 | 178 | ||
159 | err = vfe_var_pmu_setup(g); | 179 | err = vfe_var_pmu_setup(g); |
160 | if (err) | 180 | if (err) { |
161 | return err; | 181 | return err; |
182 | } | ||
162 | 183 | ||
163 | err = vfe_equ_pmu_setup(g); | 184 | err = vfe_equ_pmu_setup(g); |
164 | if (err) | 185 | if (err) { |
165 | return err; | 186 | return err; |
187 | } | ||
166 | 188 | ||
167 | err = clk_domain_pmu_setup(g); | 189 | err = clk_domain_pmu_setup(g); |
168 | if (err) | 190 | if (err) { |
169 | return err; | 191 | return err; |
192 | } | ||
170 | 193 | ||
171 | err = clk_prog_pmu_setup(g); | 194 | err = clk_prog_pmu_setup(g); |
172 | if (err) | 195 | if (err) { |
173 | return err; | 196 | return err; |
197 | } | ||
174 | 198 | ||
175 | err = clk_vin_pmu_setup(g); | 199 | err = clk_vin_pmu_setup(g); |
176 | if (err) | 200 | if (err) { |
177 | return err; | 201 | return err; |
202 | } | ||
178 | 203 | ||
179 | err = clk_fll_pmu_setup(g); | 204 | err = clk_fll_pmu_setup(g); |
180 | if (err) | 205 | if (err) { |
181 | return err; | 206 | return err; |
207 | } | ||
182 | 208 | ||
183 | err = clk_vf_point_pmu_setup(g); | 209 | err = clk_vf_point_pmu_setup(g); |
184 | if (err) | 210 | if (err) { |
185 | return err; | 211 | return err; |
212 | } | ||
186 | 213 | ||
187 | if (g->ops.clk.support_clk_freq_controller) { | 214 | if (g->ops.clk.support_clk_freq_controller) { |
188 | err = clk_freq_controller_pmu_setup(g); | 215 | err = clk_freq_controller_pmu_setup(g); |
189 | if (err) | 216 | if (err) { |
190 | return err; | 217 | return err; |
218 | } | ||
191 | } | 219 | } |
192 | err = clk_pmu_vin_load(g); | 220 | err = clk_pmu_vin_load(g); |
193 | if (err) | 221 | if (err) { |
194 | return err; | 222 | return err; |
223 | } | ||
195 | 224 | ||
196 | err = g->ops.pmu_ver.clk.perf_pmu_vfe_load(g); | 225 | err = g->ops.pmu_ver.clk.perf_pmu_vfe_load(g); |
197 | if (err) | 226 | if (err) { |
198 | return err; | 227 | return err; |
228 | } | ||
199 | 229 | ||
200 | if (g->ops.clk.support_pmgr_domain) | 230 | if (g->ops.clk.support_pmgr_domain) { |
201 | err = pmgr_domain_pmu_setup(g); | 231 | err = pmgr_domain_pmu_setup(g); |
232 | } | ||
202 | 233 | ||
203 | return err; | 234 | return err; |
204 | } | 235 | } |
@@ -211,8 +242,9 @@ static int pstate_construct_super(struct gk20a *g, struct boardobj **ppboardobj, | |||
211 | int err; | 242 | int err; |
212 | 243 | ||
213 | err = boardobj_construct_super(g, ppboardobj, size, args); | 244 | err = boardobj_construct_super(g, ppboardobj, size, args); |
214 | if (err) | 245 | if (err) { |
215 | return err; | 246 | return err; |
247 | } | ||
216 | 248 | ||
217 | pstate = (struct pstate *)*ppboardobj; | 249 | pstate = (struct pstate *)*ppboardobj; |
218 | 250 | ||
@@ -239,9 +271,10 @@ static struct pstate *pstate_construct(struct gk20a *g, void *args) | |||
239 | 271 | ||
240 | if ((tmp->super.type != CTRL_PERF_PSTATE_TYPE_3X) || | 272 | if ((tmp->super.type != CTRL_PERF_PSTATE_TYPE_3X) || |
241 | (pstate_construct_3x(g, (struct boardobj **)&pstate, | 273 | (pstate_construct_3x(g, (struct boardobj **)&pstate, |
242 | sizeof(struct pstate), args))) | 274 | sizeof(struct pstate), args))) { |
243 | nvgpu_err(g, | 275 | nvgpu_err(g, |
244 | "error constructing pstate num=%u", tmp->num); | 276 | "error constructing pstate num=%u", tmp->num); |
277 | } | ||
245 | 278 | ||
246 | return pstate; | 279 | return pstate; |
247 | } | 280 | } |
@@ -330,8 +363,9 @@ static int parse_pstate_table_5x(struct gk20a *g, | |||
330 | ((hdr->base_entry_size != VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_2) && | 363 | ((hdr->base_entry_size != VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_2) && |
331 | (hdr->base_entry_size != VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3)) || | 364 | (hdr->base_entry_size != VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3)) || |
332 | (hdr->clock_entry_size != VBIOS_PSTATE_CLOCK_ENTRY_5X_SIZE_6) || | 365 | (hdr->clock_entry_size != VBIOS_PSTATE_CLOCK_ENTRY_5X_SIZE_6) || |
333 | (hdr->clock_entry_count > CLK_SET_INFO_MAX_SIZE)) | 366 | (hdr->clock_entry_count > CLK_SET_INFO_MAX_SIZE)) { |
334 | return -EINVAL; | 367 | return -EINVAL; |
368 | } | ||
335 | 369 | ||
336 | p += hdr->header_size; | 370 | p += hdr->header_size; |
337 | 371 | ||
@@ -341,20 +375,24 @@ static int parse_pstate_table_5x(struct gk20a *g, | |||
341 | for (i = 0; i < hdr->base_entry_count; i++, p += entry_size) { | 375 | for (i = 0; i < hdr->base_entry_count; i++, p += entry_size) { |
342 | entry = (struct vbios_pstate_entry_5x *)p; | 376 | entry = (struct vbios_pstate_entry_5x *)p; |
343 | 377 | ||
344 | if (entry->pstate_level == VBIOS_PERFLEVEL_SKIP_ENTRY) | 378 | if (entry->pstate_level == VBIOS_PERFLEVEL_SKIP_ENTRY) { |
345 | continue; | 379 | continue; |
380 | } | ||
346 | 381 | ||
347 | err = parse_pstate_entry_5x(g, hdr, entry, &_pstate); | 382 | err = parse_pstate_entry_5x(g, hdr, entry, &_pstate); |
348 | if (err) | 383 | if (err) { |
349 | goto done; | 384 | goto done; |
385 | } | ||
350 | 386 | ||
351 | pstate = pstate_construct(g, &_pstate); | 387 | pstate = pstate_construct(g, &_pstate); |
352 | if (!pstate) | 388 | if (!pstate) { |
353 | goto done; | 389 | goto done; |
390 | } | ||
354 | 391 | ||
355 | err = pstate_insert(g, pstate, i); | 392 | err = pstate_insert(g, pstate, i); |
356 | if (err) | 393 | if (err) { |
357 | goto done; | 394 | goto done; |
395 | } | ||
358 | } | 396 | } |
359 | 397 | ||
360 | done: | 398 | done: |
@@ -371,8 +409,9 @@ static int pstate_sw_setup(struct gk20a *g) | |||
371 | nvgpu_cond_init(&g->perf_pmu.pstatesobjs.pstate_notifier_wq); | 409 | nvgpu_cond_init(&g->perf_pmu.pstatesobjs.pstate_notifier_wq); |
372 | 410 | ||
373 | err = nvgpu_mutex_init(&g->perf_pmu.pstatesobjs.pstate_mutex); | 411 | err = nvgpu_mutex_init(&g->perf_pmu.pstatesobjs.pstate_mutex); |
374 | if (err) | 412 | if (err) { |
375 | return err; | 413 | return err; |
414 | } | ||
376 | 415 | ||
377 | err = boardobjgrpconstruct_e32(g, &g->perf_pmu.pstatesobjs.super); | 416 | err = boardobjgrpconstruct_e32(g, &g->perf_pmu.pstatesobjs.super); |
378 | if (err) { | 417 | if (err) { |
@@ -401,8 +440,9 @@ static int pstate_sw_setup(struct gk20a *g) | |||
401 | 440 | ||
402 | err = parse_pstate_table_5x(g, hdr); | 441 | err = parse_pstate_table_5x(g, hdr); |
403 | done: | 442 | done: |
404 | if (err) | 443 | if (err) { |
405 | nvgpu_mutex_destroy(&g->perf_pmu.pstatesobjs.pstate_mutex); | 444 | nvgpu_mutex_destroy(&g->perf_pmu.pstatesobjs.pstate_mutex); |
445 | } | ||
406 | return err; | 446 | return err; |
407 | } | 447 | } |
408 | 448 | ||
@@ -418,8 +458,9 @@ struct pstate *pstate_find(struct gk20a *g, u32 num) | |||
418 | struct pstate *, pstate, i) { | 458 | struct pstate *, pstate, i) { |
419 | nvgpu_log_info(g, "pstate=%p num=%u (looking for num=%u)", | 459 | nvgpu_log_info(g, "pstate=%p num=%u (looking for num=%u)", |
420 | pstate, pstate->num, num); | 460 | pstate, pstate->num, num); |
421 | if (pstate->num == num) | 461 | if (pstate->num == num) { |
422 | return pstate; | 462 | return pstate; |
463 | } | ||
423 | } | 464 | } |
424 | return NULL; | 465 | return NULL; |
425 | } | 466 | } |
@@ -433,13 +474,15 @@ struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g, | |||
433 | 474 | ||
434 | nvgpu_log_info(g, "pstate = %p", pstate); | 475 | nvgpu_log_info(g, "pstate = %p", pstate); |
435 | 476 | ||
436 | if (!pstate) | 477 | if (!pstate) { |
437 | return NULL; | 478 | return NULL; |
479 | } | ||
438 | 480 | ||
439 | for (clkidx = 0; clkidx < pstate->clklist.num_info; clkidx++) { | 481 | for (clkidx = 0; clkidx < pstate->clklist.num_info; clkidx++) { |
440 | info = &pstate->clklist.clksetinfo[clkidx]; | 482 | info = &pstate->clklist.clksetinfo[clkidx]; |
441 | if (info->clkwhich == clkwhich) | 483 | if (info->clkwhich == clkwhich) { |
442 | return info; | 484 | return info; |
485 | } | ||
443 | } | 486 | } |
444 | return NULL; | 487 | return NULL; |
445 | } | 488 | } |
diff --git a/drivers/gpu/nvgpu/therm/thrmchannel.c b/drivers/gpu/nvgpu/therm/thrmchannel.c index 7d196422..8130656c 100644 --- a/drivers/gpu/nvgpu/therm/thrmchannel.c +++ b/drivers/gpu/nvgpu/therm/thrmchannel.c | |||
@@ -73,8 +73,9 @@ static struct boardobj *construct_channel_device(struct gk20a *g, | |||
73 | 73 | ||
74 | status = boardobj_construct_super(g, &board_obj_ptr, | 74 | status = boardobj_construct_super(g, &board_obj_ptr, |
75 | pargs_size, pargs); | 75 | pargs_size, pargs); |
76 | if (status) | 76 | if (status) { |
77 | return NULL; | 77 | return NULL; |
78 | } | ||
78 | 79 | ||
79 | /* Set Super class interfaces */ | 80 | /* Set Super class interfaces */ |
80 | board_obj_ptr->pmudatainit = _therm_channel_pmudatainit_device; | 81 | board_obj_ptr->pmudatainit = _therm_channel_pmudatainit_device; |
@@ -108,8 +109,9 @@ static int _therm_channel_pmudata_instget(struct gk20a *g, | |||
108 | 109 | ||
109 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 110 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
110 | if (((u32)BIT(idx) & | 111 | if (((u32)BIT(idx) & |
111 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) | 112 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { |
112 | return -EINVAL; | 113 | return -EINVAL; |
114 | } | ||
113 | 115 | ||
114 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 116 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
115 | &pgrp_set->objects[idx].data.board_obj; | 117 | &pgrp_set->objects[idx].data.board_obj; |
@@ -233,8 +235,9 @@ int therm_channel_sw_setup(struct gk20a *g) | |||
233 | pboardobjgrp->pmudatainstget = _therm_channel_pmudata_instget; | 235 | pboardobjgrp->pmudatainstget = _therm_channel_pmudata_instget; |
234 | 236 | ||
235 | status = devinit_get_therm_channel_table(g, pthermchannelobjs); | 237 | status = devinit_get_therm_channel_table(g, pthermchannelobjs); |
236 | if (status) | 238 | if (status) { |
237 | goto done; | 239 | goto done; |
240 | } | ||
238 | 241 | ||
239 | BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, THERM, THERM_CHANNEL); | 242 | BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, THERM, THERM_CHANNEL); |
240 | 243 | ||
diff --git a/drivers/gpu/nvgpu/therm/thrmdev.c b/drivers/gpu/nvgpu/therm/thrmdev.c index ddd1f280..b0e65af7 100644 --- a/drivers/gpu/nvgpu/therm/thrmdev.c +++ b/drivers/gpu/nvgpu/therm/thrmdev.c | |||
@@ -43,8 +43,9 @@ static int _therm_device_pmudata_instget(struct gk20a *g, | |||
43 | 43 | ||
44 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 44 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
45 | if (((u32)BIT(idx) & | 45 | if (((u32)BIT(idx) & |
46 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) | 46 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { |
47 | return -EINVAL; | 47 | return -EINVAL; |
48 | } | ||
48 | 49 | ||
49 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 50 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
50 | &pgrp_set->objects[idx].data; | 51 | &pgrp_set->objects[idx].data; |
@@ -208,8 +209,9 @@ static struct boardobj *therm_device_construct(struct gk20a *g, | |||
208 | board_obj_ptr = NULL; | 209 | board_obj_ptr = NULL; |
209 | nvgpu_err(g, | 210 | nvgpu_err(g, |
210 | "could not allocate memory for therm_device"); | 211 | "could not allocate memory for therm_device"); |
211 | if (board_obj_ptr != NULL) | 212 | if (board_obj_ptr != NULL) { |
212 | nvgpu_kfree(g, board_obj_ptr); | 213 | nvgpu_kfree(g, board_obj_ptr); |
214 | } | ||
213 | } | 215 | } |
214 | 216 | ||
215 | 217 | ||
@@ -347,8 +349,9 @@ int therm_device_sw_setup(struct gk20a *g) | |||
347 | pboardobjgrp->pmudatainstget = _therm_device_pmudata_instget; | 349 | pboardobjgrp->pmudatainstget = _therm_device_pmudata_instget; |
348 | 350 | ||
349 | status = devinit_get_therm_device_table(g, pthermdeviceobjs); | 351 | status = devinit_get_therm_device_table(g, pthermdeviceobjs); |
350 | if (status) | 352 | if (status) { |
351 | goto done; | 353 | goto done; |
354 | } | ||
352 | 355 | ||
353 | BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, THERM, THERM_DEVICE); | 356 | BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, THERM, THERM_DEVICE); |
354 | 357 | ||
diff --git a/drivers/gpu/nvgpu/therm/thrmpmu.c b/drivers/gpu/nvgpu/therm/thrmpmu.c index 7814cf5e..e23d1d63 100644 --- a/drivers/gpu/nvgpu/therm/thrmpmu.c +++ b/drivers/gpu/nvgpu/therm/thrmpmu.c | |||
@@ -43,11 +43,12 @@ static void therm_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, | |||
43 | return; | 43 | return; |
44 | } | 44 | } |
45 | 45 | ||
46 | if (!phandlerparams->prpccall->b_supported) | 46 | if (!phandlerparams->prpccall->b_supported) { |
47 | nvgpu_err(g, "RPC msg %x failed", | 47 | nvgpu_err(g, "RPC msg %x failed", |
48 | msg->msg.pmgr.msg_type); | 48 | msg->msg.pmgr.msg_type); |
49 | else | 49 | } else { |
50 | phandlerparams->success = 1; | 50 | phandlerparams->success = 1; |
51 | } | ||
51 | } | 52 | } |
52 | 53 | ||
53 | int therm_send_pmgr_tables_to_pmu(struct gk20a *g) | 54 | int therm_send_pmgr_tables_to_pmu(struct gk20a *g) |