diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h | 8 |
5 files changed, 27 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 170bfc7f..d3b91a50 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -8740,7 +8740,7 @@ void gk20a_resume_single_sm(struct gk20a *g, | |||
8740 | gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(), | 8740 | gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(), |
8741 | gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f()); | 8741 | gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f()); |
8742 | gk20a_writel(g, | 8742 | gk20a_writel(g, |
8743 | gr_gpcs_tpcs_sm_dbgr_control0_r() + offset, dbgr_control0); | 8743 | gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0); |
8744 | 8744 | ||
8745 | /* Run trigger */ | 8745 | /* Run trigger */ |
8746 | dbgr_control0 |= gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(); | 8746 | dbgr_control0 |= gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(); |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 0e0d3f62..0375d71f 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1259,9 +1259,9 @@ static int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc) | |||
1259 | gr->sm_error_states[sm_id].hww_warp_esr_pc = gk20a_readl(g, | 1259 | gr->sm_error_states[sm_id].hww_warp_esr_pc = gk20a_readl(g, |
1260 | gr_gpc0_tpc0_sm_hww_warp_esr_pc_r() + offset); | 1260 | gr_gpc0_tpc0_sm_hww_warp_esr_pc_r() + offset); |
1261 | gr->sm_error_states[sm_id].hww_global_esr_report_mask = gk20a_readl(g, | 1261 | gr->sm_error_states[sm_id].hww_global_esr_report_mask = gk20a_readl(g, |
1262 | gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r() + offset); | 1262 | gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r() + offset); |
1263 | gr->sm_error_states[sm_id].hww_warp_esr_report_mask = gk20a_readl(g, | 1263 | gr->sm_error_states[sm_id].hww_warp_esr_report_mask = gk20a_readl(g, |
1264 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() + offset); | 1264 | gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r() + offset); |
1265 | 1265 | ||
1266 | mutex_unlock(&g->dbg_sessions_lock); | 1266 | mutex_unlock(&g->dbg_sessions_lock); |
1267 | 1267 | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h index 9f7fea45..30436fb1 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_gr_gm20b.h | |||
@@ -3062,6 +3062,10 @@ static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(vo | |||
3062 | { | 3062 | { |
3063 | return 0x100000; | 3063 | return 0x100000; |
3064 | } | 3064 | } |
3065 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r(void) | ||
3066 | { | ||
3067 | return 0x00504644; | ||
3068 | } | ||
3065 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) | 3069 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) |
3066 | { | 3070 | { |
3067 | return 0x00419e4c; | 3071 | return 0x00419e4c; |
@@ -3094,6 +3098,10 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complet | |||
3094 | { | 3098 | { |
3095 | return 0x40; | 3099 | return 0x40; |
3096 | } | 3100 | } |
3101 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r(void) | ||
3102 | { | ||
3103 | return 0x0050464c; | ||
3104 | } | ||
3097 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) | 3105 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) |
3098 | { | 3106 | { |
3099 | return 0x00419d0c; | 3107 | return 0x00419d0c; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h index 22b1142f..c20da067 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_gr_gp106.h | |||
@@ -3298,6 +3298,10 @@ static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(vo | |||
3298 | { | 3298 | { |
3299 | return 0x100000; | 3299 | return 0x100000; |
3300 | } | 3300 | } |
3301 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r(void) | ||
3302 | { | ||
3303 | return 0x00504644; | ||
3304 | } | ||
3301 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) | 3305 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) |
3302 | { | 3306 | { |
3303 | return 0x00419e4c; | 3307 | return 0x00419e4c; |
@@ -3338,6 +3342,10 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complet | |||
3338 | { | 3342 | { |
3339 | return 0x40; | 3343 | return 0x40; |
3340 | } | 3344 | } |
3345 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r(void) | ||
3346 | { | ||
3347 | return 0x0050464c; | ||
3348 | } | ||
3341 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) | 3349 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) |
3342 | { | 3350 | { |
3343 | return 0x00419d0c; | 3351 | return 0x00419d0c; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h index 6bef30e0..7989337c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_gr_gp10b.h | |||
@@ -3418,6 +3418,10 @@ static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(vo | |||
3418 | { | 3418 | { |
3419 | return 0x100000; | 3419 | return 0x100000; |
3420 | } | 3420 | } |
3421 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r(void) | ||
3422 | { | ||
3423 | return 0x00504644; | ||
3424 | } | ||
3421 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) | 3425 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) |
3422 | { | 3426 | { |
3423 | return 0x00419e4c; | 3427 | return 0x00419e4c; |
@@ -3458,6 +3462,10 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complet | |||
3458 | { | 3462 | { |
3459 | return 0x40; | 3463 | return 0x40; |
3460 | } | 3464 | } |
3465 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r(void) | ||
3466 | { | ||
3467 | return 0x0050464c; | ||
3468 | } | ||
3461 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) | 3469 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) |
3462 | { | 3470 | { |
3463 | return 0x00419d0c; | 3471 | return 0x00419d0c; |