diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile.nvgpu | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/debug.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/ltc.c | 42 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/ltc_gm20b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ltc_gp10b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/ltc.h | 21 |
16 files changed, 101 insertions, 75 deletions
diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu index ffe78097..2aa76497 100644 --- a/drivers/gpu/nvgpu/Makefile.nvgpu +++ b/drivers/gpu/nvgpu/Makefile.nvgpu | |||
@@ -66,6 +66,7 @@ nvgpu-y := \ | |||
66 | common/pmu/pmu_fw.o \ | 66 | common/pmu/pmu_fw.o \ |
67 | common/pmu/pmu_pg.o \ | 67 | common/pmu/pmu_pg.o \ |
68 | common/pmu/pmu_perfmon.o \ | 68 | common/pmu/pmu_perfmon.o \ |
69 | common/ltc.o \ | ||
69 | gk20a/gk20a.o \ | 70 | gk20a/gk20a.o \ |
70 | gk20a/bus_gk20a.o \ | 71 | gk20a/bus_gk20a.o \ |
71 | gk20a/pramin_gk20a.o \ | 72 | gk20a/pramin_gk20a.o \ |
diff --git a/drivers/gpu/nvgpu/common/linux/debug.c b/drivers/gpu/nvgpu/common/linux/debug.c index e085aed4..a846493e 100644 --- a/drivers/gpu/nvgpu/common/linux/debug.c +++ b/drivers/gpu/nvgpu/common/linux/debug.c | |||
@@ -275,15 +275,10 @@ void gk20a_debug_init(struct gk20a *g, const char *debugfs_symlink) | |||
275 | debugfs_create_u32("log_trace", S_IRUGO|S_IWUSR, | 275 | debugfs_create_u32("log_trace", S_IRUGO|S_IWUSR, |
276 | platform->debugfs, &g->log_trace); | 276 | platform->debugfs, &g->log_trace); |
277 | 277 | ||
278 | nvgpu_spinlock_init(&g->debugfs_lock); | ||
279 | |||
280 | g->mm.ltc_enabled = true; | ||
281 | g->mm.ltc_enabled_debug = true; | ||
282 | |||
283 | g->debugfs_ltc_enabled = | 278 | g->debugfs_ltc_enabled = |
284 | debugfs_create_bool("ltc_enabled", S_IRUGO|S_IWUSR, | 279 | debugfs_create_bool("ltc_enabled", S_IRUGO|S_IWUSR, |
285 | platform->debugfs, | 280 | platform->debugfs, |
286 | &g->mm.ltc_enabled_debug); | 281 | &g->mm.ltc_enabled_target); |
287 | 282 | ||
288 | g->debugfs_gr_idle_timeout_default = | 283 | g->debugfs_gr_idle_timeout_default = |
289 | debugfs_create_u32("gr_idle_timeout_default_us", | 284 | debugfs_create_u32("gr_idle_timeout_default_us", |
diff --git a/drivers/gpu/nvgpu/common/ltc.c b/drivers/gpu/nvgpu/common/ltc.c new file mode 100644 index 00000000..0965caa3 --- /dev/null +++ b/drivers/gpu/nvgpu/common/ltc.c | |||
@@ -0,0 +1,42 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <nvgpu/ltc.h> | ||
18 | |||
19 | #include "gk20a/gk20a.h" | ||
20 | |||
21 | int nvgpu_init_ltc_support(struct gk20a *g) | ||
22 | { | ||
23 | nvgpu_spinlock_init(&g->ltc_enabled_lock); | ||
24 | |||
25 | g->mm.ltc_enabled_current = true; | ||
26 | g->mm.ltc_enabled_target = true; | ||
27 | |||
28 | if (g->ops.ltc.init_fs_state) | ||
29 | g->ops.ltc.init_fs_state(g); | ||
30 | |||
31 | return 0; | ||
32 | } | ||
33 | |||
34 | void nvgpu_ltc_sync_enabled(struct gk20a *g) | ||
35 | { | ||
36 | nvgpu_spinlock_acquire(&g->ltc_enabled_lock); | ||
37 | if (g->mm.ltc_enabled_current != g->mm.ltc_enabled_target) { | ||
38 | g->ops.ltc.set_enabled(g, g->mm.ltc_enabled_target); | ||
39 | g->mm.ltc_enabled_current = g->mm.ltc_enabled_target; | ||
40 | } | ||
41 | nvgpu_spinlock_release(&g->ltc_enabled_lock); | ||
42 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 87923537..62b312b2 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -34,6 +34,7 @@ | |||
34 | #include <nvgpu/cond.h> | 34 | #include <nvgpu/cond.h> |
35 | #include <nvgpu/enabled.h> | 35 | #include <nvgpu/enabled.h> |
36 | #include <nvgpu/debug.h> | 36 | #include <nvgpu/debug.h> |
37 | #include <nvgpu/ltc.h> | ||
37 | 38 | ||
38 | #include "gk20a.h" | 39 | #include "gk20a.h" |
39 | #include "ctxsw_trace_gk20a.h" | 40 | #include "ctxsw_trace_gk20a.h" |
@@ -2490,11 +2491,8 @@ int gk20a_submit_channel_gpfifo(struct channel_gk20a *c, | |||
2490 | if (profile) | 2491 | if (profile) |
2491 | profile->timestamp[PROFILE_ENTRY] = sched_clock(); | 2492 | profile->timestamp[PROFILE_ENTRY] = sched_clock(); |
2492 | 2493 | ||
2493 | #ifdef CONFIG_DEBUG_FS | ||
2494 | /* update debug settings */ | 2494 | /* update debug settings */ |
2495 | if (g->ops.ltc.sync_debugfs) | 2495 | nvgpu_ltc_sync_enabled(g); |
2496 | g->ops.ltc.sync_debugfs(g); | ||
2497 | #endif | ||
2498 | 2496 | ||
2499 | gk20a_dbg_info("channel %d", c->chid); | 2497 | gk20a_dbg_info("channel %d", c->chid); |
2500 | 2498 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 6350bcf5..7d577cda 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <nvgpu/enabled.h> | 26 | #include <nvgpu/enabled.h> |
27 | #include <nvgpu/pmu.h> | 27 | #include <nvgpu/pmu.h> |
28 | #include <nvgpu/gmmu.h> | 28 | #include <nvgpu/gmmu.h> |
29 | #include <nvgpu/ltc.h> | ||
29 | 30 | ||
30 | #include <trace/events/gk20a.h> | 31 | #include <trace/events/gk20a.h> |
31 | 32 | ||
@@ -216,8 +217,11 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
216 | goto done; | 217 | goto done; |
217 | } | 218 | } |
218 | 219 | ||
219 | if (g->ops.ltc.init_fs_state) | 220 | err = nvgpu_init_ltc_support(g); |
220 | g->ops.ltc.init_fs_state(g); | 221 | if (err) { |
222 | nvgpu_err(g, "failed to init ltc"); | ||
223 | goto done; | ||
224 | } | ||
221 | 225 | ||
222 | err = gk20a_init_mm_support(g); | 226 | err = gk20a_init_mm_support(g); |
223 | if (err) { | 227 | if (err) { |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 8d9318b2..f7b714f2 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -144,9 +144,7 @@ struct gpu_ops { | |||
144 | struct zbc_entry *s_val, | 144 | struct zbc_entry *s_val, |
145 | u32 index); | 145 | u32 index); |
146 | void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr); | 146 | void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr); |
147 | #ifdef CONFIG_DEBUG_FS | 147 | void (*set_enabled)(struct gk20a *g, bool enabled); |
148 | void (*sync_debugfs)(struct gk20a *g); | ||
149 | #endif | ||
150 | void (*init_fs_state)(struct gk20a *g); | 148 | void (*init_fs_state)(struct gk20a *g); |
151 | void (*isr)(struct gk20a *g); | 149 | void (*isr)(struct gk20a *g); |
152 | u32 (*cbc_fix_config)(struct gk20a *g, int base); | 150 | u32 (*cbc_fix_config)(struct gk20a *g, int base); |
@@ -1147,8 +1145,9 @@ struct gk20a { | |||
1147 | 1145 | ||
1148 | u32 emc3d_ratio; | 1146 | u32 emc3d_ratio; |
1149 | 1147 | ||
1148 | struct nvgpu_spinlock ltc_enabled_lock; | ||
1149 | |||
1150 | #ifdef CONFIG_DEBUG_FS | 1150 | #ifdef CONFIG_DEBUG_FS |
1151 | struct nvgpu_spinlock debugfs_lock; | ||
1152 | struct dentry *debugfs_ltc_enabled; | 1151 | struct dentry *debugfs_ltc_enabled; |
1153 | struct dentry *debugfs_timeouts_enabled; | 1152 | struct dentry *debugfs_timeouts_enabled; |
1154 | struct dentry *debugfs_gr_idle_timeout_default; | 1153 | struct dentry *debugfs_gr_idle_timeout_default; |
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c index a543a0d3..1b834a47 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | |||
@@ -21,8 +21,6 @@ | |||
21 | #include "gk20a.h" | 21 | #include "gk20a.h" |
22 | #include "gr_gk20a.h" | 22 | #include "gr_gk20a.h" |
23 | 23 | ||
24 | /* Non HW reg dependent stuff: */ | ||
25 | |||
26 | int gk20a_ltc_alloc_phys_cbc(struct gk20a *g, size_t compbit_backing_size) | 24 | int gk20a_ltc_alloc_phys_cbc(struct gk20a *g, size_t compbit_backing_size) |
27 | { | 25 | { |
28 | struct gr_gk20a *gr = &g->gr; | 26 | struct gr_gk20a *gr = &g->gr; |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index 2f35df71..c56b28bb 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h | |||
@@ -245,14 +245,8 @@ struct mm_gk20a { | |||
245 | bool sw_ready; | 245 | bool sw_ready; |
246 | int physical_bits; | 246 | int physical_bits; |
247 | bool use_full_comp_tag_line; | 247 | bool use_full_comp_tag_line; |
248 | #ifdef CONFIG_DEBUG_FS | 248 | bool ltc_enabled_current; |
249 | u32 ltc_enabled; | 249 | bool ltc_enabled_target; |
250 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0) | ||
251 | u32 ltc_enabled_debug; | ||
252 | #else | ||
253 | bool ltc_enabled_debug; | ||
254 | #endif | ||
255 | #endif | ||
256 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0) | 250 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4,4,0) |
257 | u32 bypass_smmu; | 251 | u32 bypass_smmu; |
258 | u32 disable_bigpage; | 252 | u32 disable_bigpage; |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index c16cd3e5..7861e438 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -155,9 +155,7 @@ static const struct gpu_ops gm20b_ops = { | |||
155 | .isr = gm20b_ltc_isr, | 155 | .isr = gm20b_ltc_isr, |
156 | .cbc_fix_config = gm20b_ltc_cbc_fix_config, | 156 | .cbc_fix_config = gm20b_ltc_cbc_fix_config, |
157 | .flush = gm20b_flush_ltc, | 157 | .flush = gm20b_flush_ltc, |
158 | #ifdef CONFIG_DEBUG_FS | 158 | .set_enabled = gm20b_ltc_set_enabled, |
159 | .sync_debugfs = gm20b_ltc_sync_debugfs, | ||
160 | #endif | ||
161 | }, | 159 | }, |
162 | .ce2 = { | 160 | .ce2 = { |
163 | .isr_stall = gk20a_ce2_isr, | 161 | .isr_stall = gk20a_ce2_isr, |
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c index 5e938141..6fef01ea 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | |||
@@ -437,25 +437,17 @@ void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) | |||
437 | 437 | ||
438 | } | 438 | } |
439 | 439 | ||
440 | #ifdef CONFIG_DEBUG_FS | 440 | void gm20b_ltc_set_enabled(struct gk20a *g, bool enabled) |
441 | void gm20b_ltc_sync_debugfs(struct gk20a *g) | ||
442 | { | 441 | { |
443 | u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(); | 442 | u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(); |
443 | u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r()); | ||
444 | 444 | ||
445 | nvgpu_spinlock_acquire(&g->debugfs_lock); | 445 | if (enabled) |
446 | if (g->mm.ltc_enabled != g->mm.ltc_enabled_debug) { | 446 | /* bypass disabled (normal caching ops)*/ |
447 | u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r()); | 447 | reg &= ~reg_f; |
448 | 448 | else | |
449 | if (g->mm.ltc_enabled_debug) | 449 | /* bypass enabled (no caching) */ |
450 | /* bypass disabled (normal caching ops)*/ | 450 | reg |= reg_f; |
451 | reg &= ~reg_f; | ||
452 | else | ||
453 | /* bypass enabled (no caching) */ | ||
454 | reg |= reg_f; | ||
455 | 451 | ||
456 | gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); | 452 | gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); |
457 | g->mm.ltc_enabled = g->mm.ltc_enabled_debug; | ||
458 | } | ||
459 | nvgpu_spinlock_release(&g->debugfs_lock); | ||
460 | } | 453 | } |
461 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h index 3b4b16e3..bfd501d6 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h | |||
@@ -26,9 +26,7 @@ void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g, | |||
26 | struct zbc_entry *depth_val, | 26 | struct zbc_entry *depth_val, |
27 | u32 index); | 27 | u32 index); |
28 | void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr); | 28 | void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr); |
29 | #ifdef CONFIG_DEBUG_FS | 29 | void gm20b_ltc_set_enabled(struct gk20a *g, bool enabled); |
30 | void gm20b_ltc_sync_debugfs(struct gk20a *g); | ||
31 | #endif | ||
32 | void gm20b_ltc_init_fs_state(struct gk20a *g); | 30 | void gm20b_ltc_init_fs_state(struct gk20a *g); |
33 | int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, | 31 | int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, |
34 | u32 min, u32 max); | 32 | u32 min, u32 max); |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 38778da7..4a891a82 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -204,9 +204,7 @@ static const struct gpu_ops gp106_ops = { | |||
204 | .isr = gp10b_ltc_isr, | 204 | .isr = gp10b_ltc_isr, |
205 | .cbc_fix_config = NULL, | 205 | .cbc_fix_config = NULL, |
206 | .flush = gm20b_flush_ltc, | 206 | .flush = gm20b_flush_ltc, |
207 | #ifdef CONFIG_DEBUG_FS | 207 | .set_enabled = gp10b_ltc_set_enabled, |
208 | .sync_debugfs = gp10b_ltc_sync_debugfs, | ||
209 | #endif | ||
210 | }, | 208 | }, |
211 | .ce2 = { | 209 | .ce2 = { |
212 | .isr_stall = gp10b_ce_isr, | 210 | .isr_stall = gp10b_ce_isr, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index e2479530..197c4fad 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -164,9 +164,7 @@ static const struct gpu_ops gp10b_ops = { | |||
164 | .isr = gp10b_ltc_isr, | 164 | .isr = gp10b_ltc_isr, |
165 | .cbc_fix_config = gm20b_ltc_cbc_fix_config, | 165 | .cbc_fix_config = gm20b_ltc_cbc_fix_config, |
166 | .flush = gm20b_flush_ltc, | 166 | .flush = gm20b_flush_ltc, |
167 | #ifdef CONFIG_DEBUG_FS | 167 | .set_enabled = gp10b_ltc_set_enabled, |
168 | .sync_debugfs = gp10b_ltc_sync_debugfs, | ||
169 | #endif | ||
170 | }, | 168 | }, |
171 | .ce2 = { | 169 | .ce2 = { |
172 | .isr_stall = gp10b_ce_isr, | 170 | .isr_stall = gp10b_ce_isr, |
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index baa275c7..43619f80 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | |||
@@ -205,25 +205,17 @@ void gp10b_ltc_init_fs_state(struct gk20a *g) | |||
205 | ltc_intr); | 205 | ltc_intr); |
206 | } | 206 | } |
207 | 207 | ||
208 | #ifdef CONFIG_DEBUG_FS | 208 | void gp10b_ltc_set_enabled(struct gk20a *g, bool enabled) |
209 | void gp10b_ltc_sync_debugfs(struct gk20a *g) | ||
210 | { | 209 | { |
211 | u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(); | 210 | u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(); |
211 | u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r()); | ||
212 | 212 | ||
213 | nvgpu_spinlock_acquire(&g->debugfs_lock); | 213 | if (enabled) |
214 | if (g->mm.ltc_enabled != g->mm.ltc_enabled_debug) { | 214 | /* bypass disabled (normal caching ops)*/ |
215 | u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r()); | 215 | reg &= ~reg_f; |
216 | 216 | else | |
217 | if (g->mm.ltc_enabled_debug) | 217 | /* bypass enabled (no caching) */ |
218 | /* bypass disabled (normal caching ops)*/ | 218 | reg |= reg_f; |
219 | reg &= ~reg_f; | ||
220 | else | ||
221 | /* bypass enabled (no caching) */ | ||
222 | reg |= reg_f; | ||
223 | 219 | ||
224 | gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); | 220 | gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); |
225 | g->mm.ltc_enabled = g->mm.ltc_enabled_debug; | ||
226 | } | ||
227 | nvgpu_spinlock_release(&g->debugfs_lock); | ||
228 | } | 221 | } |
229 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h index b5f2cda6..385754ba 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h | |||
@@ -20,7 +20,5 @@ void gp10b_ltc_isr(struct gk20a *g); | |||
20 | int gp10b_determine_L2_size_bytes(struct gk20a *g); | 20 | int gp10b_determine_L2_size_bytes(struct gk20a *g); |
21 | int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr); | 21 | int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr); |
22 | void gp10b_ltc_init_fs_state(struct gk20a *g); | 22 | void gp10b_ltc_init_fs_state(struct gk20a *g); |
23 | #ifdef CONFIG_DEBUG_FS | 23 | void gp10b_ltc_set_enabled(struct gk20a *g, bool enabled); |
24 | void gp10b_ltc_sync_debugfs(struct gk20a *g); | ||
25 | #endif | ||
26 | #endif | 24 | #endif |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/ltc.h b/drivers/gpu/nvgpu/include/nvgpu/ltc.h new file mode 100644 index 00000000..89721158 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/ltc.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef __NVGPU_LTC_H__ | ||
14 | #define __NVGPU_LTC_H__ | ||
15 | |||
16 | struct gk20a; | ||
17 | |||
18 | int nvgpu_init_ltc_support(struct gk20a *g); | ||
19 | void nvgpu_ltc_sync_enabled(struct gk20a *g); | ||
20 | |||
21 | #endif | ||