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-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h3
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c9
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.h3
-rw-r--r--drivers/gpu/nvgpu/gk20a/regops_gk20a.c6
-rw-r--r--drivers/gpu/nvgpu/gk20a/regops_gk20a.h5
-rw-r--r--drivers/gpu/nvgpu/gv11b/gr_gv11b.c2
-rw-r--r--drivers/gpu/nvgpu/os/linux/ioctl_dbg.c11
-rw-r--r--drivers/gpu/nvgpu/vgpu/dbg_vgpu.c3
-rw-r--r--drivers/gpu/nvgpu/vgpu/dbg_vgpu.h3
9 files changed, 31 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index c98fec48..03510a16 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1133,7 +1133,8 @@ struct gpu_ops {
1133 struct { 1133 struct {
1134 int (*exec_regops)(struct dbg_session_gk20a *dbg_s, 1134 int (*exec_regops)(struct dbg_session_gk20a *dbg_s,
1135 struct nvgpu_dbg_reg_op *ops, 1135 struct nvgpu_dbg_reg_op *ops,
1136 u64 num_ops); 1136 u64 num_ops,
1137 bool *is_current_ctx);
1137 const struct regop_offset_range* ( 1138 const struct regop_offset_range* (
1138 *get_global_whitelist_ranges)(void); 1139 *get_global_whitelist_ranges)(void);
1139 u64 (*get_global_whitelist_ranges_count)(void); 1140 u64 (*get_global_whitelist_ranges_count)(void);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index a40d93fd..f3b580e4 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -8358,7 +8358,8 @@ int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
8358 8358
8359int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, 8359int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
8360 struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops, 8360 struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
8361 u32 num_ctx_wr_ops, u32 num_ctx_rd_ops) 8361 u32 num_ctx_wr_ops, u32 num_ctx_rd_ops,
8362 bool *is_curr_ctx)
8362{ 8363{
8363 struct gk20a *g = ch->g; 8364 struct gk20a *g = ch->g;
8364 int err, tmp_err; 8365 int err, tmp_err;
@@ -8376,7 +8377,9 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
8376 } 8377 }
8377 8378
8378 ch_is_curr_ctx = gk20a_is_channel_ctx_resident(ch); 8379 ch_is_curr_ctx = gk20a_is_channel_ctx_resident(ch);
8379 8380 if (is_curr_ctx != NULL) {
8381 *is_curr_ctx = ch_is_curr_ctx;
8382 }
8380 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "is curr ctx=%d", 8383 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "is curr ctx=%d",
8381 ch_is_curr_ctx); 8384 ch_is_curr_ctx);
8382 8385
@@ -8694,7 +8697,7 @@ int gr_gk20a_set_sm_debug_mode(struct gk20a *g,
8694 i++; 8697 i++;
8695 } 8698 }
8696 8699
8697 err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0); 8700 err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0, NULL);
8698 if (err) { 8701 if (err) {
8699 nvgpu_err(g, "Failed to access register"); 8702 nvgpu_err(g, "Failed to access register");
8700 } 8703 }
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 4f83bba3..617aad34 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -616,7 +616,8 @@ int gk20a_gr_suspend(struct gk20a *g);
616struct nvgpu_dbg_reg_op; 616struct nvgpu_dbg_reg_op;
617int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, 617int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
618 struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops, 618 struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
619 u32 num_ctx_wr_ops, u32 num_ctx_rd_ops); 619 u32 num_ctx_wr_ops, u32 num_ctx_rd_ops,
620 bool *is_curr_ctx);
620int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, 621int __gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
621 struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops, 622 struct nvgpu_dbg_reg_op *ctx_ops, u32 num_ops,
622 u32 num_ctx_wr_ops, u32 num_ctx_rd_ops, 623 u32 num_ctx_wr_ops, u32 num_ctx_rd_ops,
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
index 80d27c25..0aec4f86 100644
--- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
@@ -89,7 +89,8 @@ static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s,
89 89
90int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, 90int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
91 struct nvgpu_dbg_reg_op *ops, 91 struct nvgpu_dbg_reg_op *ops,
92 u64 num_ops) 92 u64 num_ops,
93 bool *is_current_ctx)
93{ 94{
94 int err = 0; 95 int err = 0;
95 unsigned int i; 96 unsigned int i;
@@ -219,7 +220,8 @@ int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
219 220
220 if (ctx_wr_count | ctx_rd_count) { 221 if (ctx_wr_count | ctx_rd_count) {
221 err = gr_gk20a_exec_ctx_ops(ch, ops, num_ops, 222 err = gr_gk20a_exec_ctx_ops(ch, ops, num_ops,
222 ctx_wr_count, ctx_rd_count); 223 ctx_wr_count, ctx_rd_count,
224 is_current_ctx);
223 if (err) { 225 if (err) {
224 nvgpu_warn(g, "failed to perform ctx ops\n"); 226 nvgpu_warn(g, "failed to perform ctx ops\n");
225 goto clean_up; 227 goto clean_up;
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.h b/drivers/gpu/nvgpu/gk20a/regops_gk20a.h
index 0fb108a4..96705879 100644
--- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Tegra GK20A GPU Debugger Driver Register Ops 2 * Tegra GK20A GPU Debugger Driver Register Ops
3 * 3 *
4 * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -77,7 +77,8 @@ struct regop_offset_range {
77 77
78int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, 78int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s,
79 struct nvgpu_dbg_reg_op *ops, 79 struct nvgpu_dbg_reg_op *ops,
80 u64 num_ops); 80 u64 num_ops,
81 bool *is_current_ctx);
81 82
82/* turn seriously unwieldy names -> something shorter */ 83/* turn seriously unwieldy names -> something shorter */
83#define REGOP(x) NVGPU_DBG_REG_OP_##x 84#define REGOP(x) NVGPU_DBG_REG_OP_##x
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 0938e2ed..450775b1 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -3377,7 +3377,7 @@ int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
3377 i++; 3377 i++;
3378 } 3378 }
3379 3379
3380 err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0); 3380 err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0, NULL);
3381 if (err) { 3381 if (err) {
3382 nvgpu_err(g, "Failed to access register\n"); 3382 nvgpu_err(g, "Failed to access register\n");
3383 } 3383 }
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
index 9ea681b1..1eace94b 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
@@ -869,6 +869,9 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
869 struct gk20a *g = dbg_s->g; 869 struct gk20a *g = dbg_s->g;
870 struct channel_gk20a *ch; 870 struct channel_gk20a *ch;
871 871
872 bool is_current_ctx;
873
874
872 nvgpu_log_fn(g, "%d ops, max fragment %d", args->num_ops, g->dbg_regops_tmp_buf_ops); 875 nvgpu_log_fn(g, "%d ops, max fragment %d", args->num_ops, g->dbg_regops_tmp_buf_ops);
873 876
874 if (args->num_ops > NVGPU_IOCTL_DBG_REG_OPS_LIMIT) { 877 if (args->num_ops > NVGPU_IOCTL_DBG_REG_OPS_LIMIT) {
@@ -954,11 +957,15 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s,
954 break; 957 break;
955 958
956 err = g->ops.regops.exec_regops( 959 err = g->ops.regops.exec_regops(
957 dbg_s, g->dbg_regops_tmp_buf, num_ops); 960 dbg_s, g->dbg_regops_tmp_buf, num_ops, &is_current_ctx);
958 961
959 if (err) { 962 if (err) {
960 break; 963 break;
961 } 964 }
965
966 if (ops_offset == 0) {
967 args->gr_ctx_resident = is_current_ctx;
968 }
962 969
963 err = nvgpu_get_regops_data_linux(g->dbg_regops_tmp_buf, 970 err = nvgpu_get_regops_data_linux(g->dbg_regops_tmp_buf,
964 linux_fragment, num_ops); 971 linux_fragment, num_ops);
diff --git a/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c
index d188f540..ca8d2872 100644
--- a/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c
@@ -33,7 +33,8 @@
33 33
34int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s, 34int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s,
35 struct nvgpu_dbg_reg_op *ops, 35 struct nvgpu_dbg_reg_op *ops,
36 u64 num_ops) 36 u64 num_ops,
37 bool *is_current_ctx)
37{ 38{
38 struct channel_gk20a *ch; 39 struct channel_gk20a *ch;
39 struct tegra_vgpu_cmd_msg msg; 40 struct tegra_vgpu_cmd_msg msg;
diff --git a/drivers/gpu/nvgpu/vgpu/dbg_vgpu.h b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.h
index 90645e59..7a1050ce 100644
--- a/drivers/gpu/nvgpu/vgpu/dbg_vgpu.h
+++ b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.h
@@ -30,7 +30,8 @@ struct gk20a;
30 30
31int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s, 31int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s,
32 struct nvgpu_dbg_reg_op *ops, 32 struct nvgpu_dbg_reg_op *ops,
33 u64 num_ops); 33 u64 num_ops,
34 bool *is_current_ctx);
34int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, bool disable_powergate); 35int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, bool disable_powergate);
35bool vgpu_check_and_set_global_reservation( 36bool vgpu_check_and_set_global_reservation(
36 struct dbg_session_gk20a *dbg_s, 37 struct dbg_session_gk20a *dbg_s,