diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile.nvgpu | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/acr.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm206/acr_gm206.c | 338 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm206/acr_gm206.h | 82 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm206/hal_gm206.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/acr_gp106.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/acr_gp106.h | 41 |
7 files changed, 42 insertions, 427 deletions
diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu index a07289ce..4daf5adb 100644 --- a/drivers/gpu/nvgpu/Makefile.nvgpu +++ b/drivers/gpu/nvgpu/Makefile.nvgpu | |||
@@ -86,7 +86,6 @@ nvgpu-y := \ | |||
86 | gm206/fifo_gm206.o \ | 86 | gm206/fifo_gm206.o \ |
87 | gm206/hal_gm206.o \ | 87 | gm206/hal_gm206.o \ |
88 | gm206/gr_gm206.o \ | 88 | gm206/gr_gm206.o \ |
89 | gm206/acr_gm206.o \ | ||
90 | gm206/mm_gm206.o \ | 89 | gm206/mm_gm206.o \ |
91 | gm206/ce_gm206.o \ | 90 | gm206/ce_gm206.o \ |
92 | boardobj/boardobj.o \ | 91 | boardobj/boardobj.o \ |
diff --git a/drivers/gpu/nvgpu/acr.h b/drivers/gpu/nvgpu/acr.h index 2877ac38..df90c96e 100644 --- a/drivers/gpu/nvgpu/acr.h +++ b/drivers/gpu/nvgpu/acr.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -16,7 +16,7 @@ | |||
16 | 16 | ||
17 | #include "gm20b/mm_gm20b.h" | 17 | #include "gm20b/mm_gm20b.h" |
18 | #include "gm20b/acr_gm20b.h" | 18 | #include "gm20b/acr_gm20b.h" |
19 | #include "gm206/acr_gm206.h" | 19 | #include "gp106/acr_gp106.h" |
20 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | 20 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC |
21 | #include "acr_t18x.h" | 21 | #include "acr_t18x.h" |
22 | #endif | 22 | #endif |
diff --git a/drivers/gpu/nvgpu/gm206/acr_gm206.c b/drivers/gpu/nvgpu/gm206/acr_gm206.c deleted file mode 100644 index 3af59374..00000000 --- a/drivers/gpu/nvgpu/gm206/acr_gm206.c +++ /dev/null | |||
@@ -1,338 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #include <linux/delay.h> /* for mdelay */ | ||
15 | #include <linux/firmware.h> | ||
16 | #include <linux/clk.h> | ||
17 | #include <linux/module.h> | ||
18 | #include <linux/debugfs.h> | ||
19 | #include <linux/dma-mapping.h> | ||
20 | #include <linux/io.h> | ||
21 | |||
22 | #include "gk20a/gk20a.h" | ||
23 | #include "gk20a/pmu_gk20a.h" | ||
24 | |||
25 | #include "acr.h" | ||
26 | #include "acr_gm206.h" | ||
27 | |||
28 | #include <nvgpu/nvgpu_common.h> | ||
29 | |||
30 | #include <nvgpu/hw/gm206/hw_pwr_gm206.h> | ||
31 | |||
32 | /*Defines*/ | ||
33 | #define gm206_dbg_pmu(fmt, arg...) \ | ||
34 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) | ||
35 | |||
36 | /* Both size and address of WPR need to be 128K-aligned */ | ||
37 | #define WPR_ALIGNMENT 0x20000 | ||
38 | #define DGPU_WPR 0x10000000 /* start from 256MB location at VIDMEM */ | ||
39 | #define DGPU_WPR_SIZE 0x100000 | ||
40 | |||
41 | static int gm206_pmu_populate_loader_cfg(struct gk20a *g, | ||
42 | void *lsfm, u32 *p_bl_gen_desc_size); | ||
43 | static int gm206_flcn_populate_bl_dmem_desc(struct gk20a *g, | ||
44 | void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid); | ||
45 | static int gm206_bootstrap_hs_flcn(struct gk20a *g); | ||
46 | |||
47 | void gm206_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf) | ||
48 | { | ||
49 | inf->wpr_base = DGPU_WPR; | ||
50 | inf->size = DGPU_WPR_SIZE; | ||
51 | } | ||
52 | |||
53 | static void flcn64_set_dma(struct falc_u64 *dma_addr, u64 value) | ||
54 | { | ||
55 | dma_addr->lo |= u64_lo32(value); | ||
56 | dma_addr->hi |= u64_lo32(value); | ||
57 | } | ||
58 | |||
59 | int gm206_alloc_blob_space(struct gk20a *g, | ||
60 | size_t size, struct mem_desc *mem) | ||
61 | { | ||
62 | struct wpr_carveout_info wpr_inf; | ||
63 | |||
64 | if (mem->size) | ||
65 | return 0; | ||
66 | |||
67 | g->ops.pmu.get_wpr(g, &wpr_inf); | ||
68 | |||
69 | return gk20a_gmmu_alloc_attr_vid_at(g, 0, wpr_inf.size, mem, | ||
70 | wpr_inf.wpr_base); | ||
71 | } | ||
72 | |||
73 | void gm206_init_secure_pmu(struct gpu_ops *gops) | ||
74 | { | ||
75 | gm20b_init_secure_pmu(gops); | ||
76 | gops->pmu.prepare_ucode = prepare_ucode_blob; | ||
77 | gops->pmu.pmu_setup_hw_and_bootstrap = gm206_bootstrap_hs_flcn; | ||
78 | gops->pmu.get_wpr = gm206_wpr_info; | ||
79 | gops->pmu.alloc_blob_space = gm206_alloc_blob_space; | ||
80 | gops->pmu.pmu_populate_loader_cfg = gm206_pmu_populate_loader_cfg; | ||
81 | gops->pmu.flcn_populate_bl_dmem_desc = gm206_flcn_populate_bl_dmem_desc; | ||
82 | } | ||
83 | |||
84 | static int gm206_pmu_populate_loader_cfg(struct gk20a *g, | ||
85 | void *lsfm, u32 *p_bl_gen_desc_size) | ||
86 | { | ||
87 | struct wpr_carveout_info wpr_inf; | ||
88 | struct pmu_gk20a *pmu = &g->pmu; | ||
89 | struct lsfm_managed_ucode_img_v1 *p_lsfm = | ||
90 | (struct lsfm_managed_ucode_img_v1 *)lsfm; | ||
91 | struct flcn_ucode_img *p_img = &(p_lsfm->ucode_img); | ||
92 | struct loader_config_v1 *ldr_cfg = | ||
93 | &(p_lsfm->bl_gen_desc.loader_cfg_v1); | ||
94 | u64 addr_base; | ||
95 | struct pmu_ucode_desc *desc; | ||
96 | u64 addr_code, addr_data; | ||
97 | u32 addr_args; | ||
98 | |||
99 | if (p_img->desc == NULL) /*This means its a header based ucode, | ||
100 | and so we do not fill BL gen desc structure*/ | ||
101 | return -EINVAL; | ||
102 | desc = p_img->desc; | ||
103 | /* | ||
104 | Calculate physical and virtual addresses for various portions of | ||
105 | the PMU ucode image | ||
106 | Calculate the 32-bit addresses for the application code, application | ||
107 | data, and bootloader code. These values are all based on IM_BASE. | ||
108 | The 32-bit addresses will be the upper 32-bits of the virtual or | ||
109 | physical addresses of each respective segment. | ||
110 | */ | ||
111 | addr_base = p_lsfm->lsb_header.ucode_off; | ||
112 | g->ops.pmu.get_wpr(g, &wpr_inf); | ||
113 | addr_base += wpr_inf.wpr_base; | ||
114 | |||
115 | gm206_dbg_pmu("pmu loader cfg u32 addrbase %x\n", (u32)addr_base); | ||
116 | /*From linux*/ | ||
117 | addr_code = u64_lo32((addr_base + | ||
118 | desc->app_start_offset + | ||
119 | desc->app_resident_code_offset)); | ||
120 | gm206_dbg_pmu("app start %d app res code off %d\n", | ||
121 | desc->app_start_offset, desc->app_resident_code_offset); | ||
122 | addr_data = u64_lo32((addr_base + | ||
123 | desc->app_start_offset + | ||
124 | desc->app_resident_data_offset)); | ||
125 | gm206_dbg_pmu("app res data offset%d\n", | ||
126 | desc->app_resident_data_offset); | ||
127 | gm206_dbg_pmu("bl start off %d\n", desc->bootloader_start_offset); | ||
128 | |||
129 | addr_args = ((pwr_falcon_hwcfg_dmem_size_v( | ||
130 | gk20a_readl(g, pwr_falcon_hwcfg_r()))) | ||
131 | << GK20A_PMU_DMEM_BLKSIZE2); | ||
132 | |||
133 | addr_args -= g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu); | ||
134 | |||
135 | gm206_dbg_pmu("addr_args %x\n", addr_args); | ||
136 | |||
137 | /* Populate the loader_config state*/ | ||
138 | ldr_cfg->dma_idx = GK20A_PMU_DMAIDX_UCODE; | ||
139 | flcn64_set_dma(&ldr_cfg->code_dma_base, addr_code); | ||
140 | ldr_cfg->code_size_total = desc->app_size; | ||
141 | ldr_cfg->code_size_to_load = desc->app_resident_code_size; | ||
142 | ldr_cfg->code_entry_point = desc->app_imem_entry; | ||
143 | flcn64_set_dma(&ldr_cfg->data_dma_base, addr_data); | ||
144 | ldr_cfg->data_size = desc->app_resident_data_size; | ||
145 | flcn64_set_dma(&ldr_cfg->overlay_dma_base, addr_code); | ||
146 | |||
147 | /* Update the argc/argv members*/ | ||
148 | ldr_cfg->argc = 1; | ||
149 | ldr_cfg->argv = addr_args; | ||
150 | |||
151 | *p_bl_gen_desc_size = sizeof(struct loader_config_v1); | ||
152 | g->acr.pmu_args = addr_args; | ||
153 | return 0; | ||
154 | } | ||
155 | |||
156 | static int gm206_flcn_populate_bl_dmem_desc(struct gk20a *g, | ||
157 | void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid) | ||
158 | { | ||
159 | struct wpr_carveout_info wpr_inf; | ||
160 | struct lsfm_managed_ucode_img_v1 *p_lsfm = | ||
161 | (struct lsfm_managed_ucode_img_v1 *)lsfm; | ||
162 | struct flcn_ucode_img *p_img = &(p_lsfm->ucode_img); | ||
163 | struct flcn_bl_dmem_desc_v1 *ldr_cfg = | ||
164 | &(p_lsfm->bl_gen_desc.bl_dmem_desc_v1); | ||
165 | u64 addr_base; | ||
166 | struct pmu_ucode_desc *desc; | ||
167 | u64 addr_code, addr_data; | ||
168 | |||
169 | if (p_img->desc == NULL) /*This means its a header based ucode, | ||
170 | and so we do not fill BL gen desc structure*/ | ||
171 | return -EINVAL; | ||
172 | desc = p_img->desc; | ||
173 | |||
174 | /* | ||
175 | Calculate physical and virtual addresses for various portions of | ||
176 | the PMU ucode image | ||
177 | Calculate the 32-bit addresses for the application code, application | ||
178 | data, and bootloader code. These values are all based on IM_BASE. | ||
179 | The 32-bit addresses will be the upper 32-bits of the virtual or | ||
180 | physical addresses of each respective segment. | ||
181 | */ | ||
182 | addr_base = p_lsfm->lsb_header.ucode_off; | ||
183 | g->ops.pmu.get_wpr(g, &wpr_inf); | ||
184 | addr_base += wpr_inf.wpr_base; | ||
185 | |||
186 | gm206_dbg_pmu("gen loader cfg %x u32 addrbase %x ID\n", (u32)addr_base, | ||
187 | p_lsfm->wpr_header.falcon_id); | ||
188 | addr_code = u64_lo32((addr_base + | ||
189 | desc->app_start_offset + | ||
190 | desc->app_resident_code_offset)); | ||
191 | addr_data = u64_lo32((addr_base + | ||
192 | desc->app_start_offset + | ||
193 | desc->app_resident_data_offset)); | ||
194 | |||
195 | gm206_dbg_pmu("gen cfg %x u32 addrcode %x & data %x load offset %xID\n", | ||
196 | (u32)addr_code, (u32)addr_data, desc->bootloader_start_offset, | ||
197 | p_lsfm->wpr_header.falcon_id); | ||
198 | |||
199 | /* Populate the LOADER_CONFIG state */ | ||
200 | memset((void *) ldr_cfg, 0, sizeof(struct flcn_bl_dmem_desc_v1)); | ||
201 | ldr_cfg->ctx_dma = GK20A_PMU_DMAIDX_UCODE; | ||
202 | flcn64_set_dma(&ldr_cfg->code_dma_base, addr_code); | ||
203 | ldr_cfg->non_sec_code_size = desc->app_resident_code_size; | ||
204 | flcn64_set_dma(&ldr_cfg->data_dma_base, addr_data); | ||
205 | ldr_cfg->data_size = desc->app_resident_data_size; | ||
206 | ldr_cfg->code_entry_point = desc->app_imem_entry; | ||
207 | *p_bl_gen_desc_size = sizeof(struct flcn_bl_dmem_desc_v1); | ||
208 | return 0; | ||
209 | } | ||
210 | |||
211 | /*Loads ACR bin to FB mem and bootstraps PMU with bootloader code | ||
212 | * start and end are addresses of ucode blob in non-WPR region*/ | ||
213 | static int gm206_bootstrap_hs_flcn(struct gk20a *g) | ||
214 | { | ||
215 | struct mm_gk20a *mm = &g->mm; | ||
216 | struct vm_gk20a *vm = &mm->pmu.vm; | ||
217 | unsigned int i; | ||
218 | int err = 0; | ||
219 | u64 *acr_dmem; | ||
220 | u32 img_size_in_bytes = 0; | ||
221 | u32 status; | ||
222 | struct acr_desc *acr = &g->acr; | ||
223 | const struct firmware *acr_fw = acr->acr_fw; | ||
224 | struct flcn_bl_dmem_desc_v1 *bl_dmem_desc = &acr->bl_dmem_desc_v1; | ||
225 | u32 *acr_ucode_header_t210_load; | ||
226 | u32 *acr_ucode_data_t210_load; | ||
227 | struct wpr_carveout_info wpr_inf; | ||
228 | |||
229 | gm206_dbg_pmu(""); | ||
230 | |||
231 | if (!acr_fw) { | ||
232 | /*First time init case*/ | ||
233 | acr_fw = nvgpu_request_firmware(g, | ||
234 | GM20B_HSBIN_PMU_UCODE_IMAGE, | ||
235 | NVGPU_REQUEST_FIRMWARE_NO_SOC); | ||
236 | if (!acr_fw) { | ||
237 | gk20a_err(dev_from_gk20a(g), "pmu ucode get fail"); | ||
238 | return -ENOENT; | ||
239 | } | ||
240 | acr->acr_fw = acr_fw; | ||
241 | acr->hsbin_hdr = (struct bin_hdr *)acr_fw->data; | ||
242 | acr->fw_hdr = (struct acr_fw_header *)(acr_fw->data + | ||
243 | acr->hsbin_hdr->header_offset); | ||
244 | acr_ucode_data_t210_load = (u32 *)(acr_fw->data + | ||
245 | acr->hsbin_hdr->data_offset); | ||
246 | acr_ucode_header_t210_load = (u32 *)(acr_fw->data + | ||
247 | acr->fw_hdr->hdr_offset); | ||
248 | img_size_in_bytes = ALIGN((acr->hsbin_hdr->data_size), 256); | ||
249 | |||
250 | /* Lets patch the signatures first.. */ | ||
251 | if (acr_ucode_patch_sig(g, acr_ucode_data_t210_load, | ||
252 | (u32 *)(acr_fw->data + | ||
253 | acr->fw_hdr->sig_prod_offset), | ||
254 | (u32 *)(acr_fw->data + | ||
255 | acr->fw_hdr->sig_dbg_offset), | ||
256 | (u32 *)(acr_fw->data + | ||
257 | acr->fw_hdr->patch_loc), | ||
258 | (u32 *)(acr_fw->data + | ||
259 | acr->fw_hdr->patch_sig)) < 0) { | ||
260 | gk20a_err(dev_from_gk20a(g), "patch signatures fail"); | ||
261 | err = -1; | ||
262 | goto err_release_acr_fw; | ||
263 | } | ||
264 | err = gk20a_gmmu_alloc_map_sys(vm, img_size_in_bytes, | ||
265 | &acr->acr_ucode); | ||
266 | if (err) { | ||
267 | err = -ENOMEM; | ||
268 | goto err_release_acr_fw; | ||
269 | } | ||
270 | |||
271 | g->ops.pmu.get_wpr(g, &wpr_inf); | ||
272 | |||
273 | acr_dmem = (u64 *) | ||
274 | &(((u8 *)acr_ucode_data_t210_load)[ | ||
275 | acr_ucode_header_t210_load[2]]); | ||
276 | acr->acr_dmem_desc = (struct flcn_acr_desc *)((u8 *)( | ||
277 | acr->acr_ucode.cpu_va) + acr_ucode_header_t210_load[2]); | ||
278 | ((struct flcn_acr_desc *)acr_dmem)->nonwpr_ucode_blob_start = | ||
279 | wpr_inf.wpr_base; | ||
280 | ((struct flcn_acr_desc *)acr_dmem)->nonwpr_ucode_blob_size = | ||
281 | wpr_inf.size; | ||
282 | ((struct flcn_acr_desc *)acr_dmem)->regions.no_regions = 1; | ||
283 | ((struct flcn_acr_desc *)acr_dmem)->wpr_offset = 0; | ||
284 | |||
285 | ((struct flcn_acr_desc *)acr_dmem)->wpr_region_id = 1; | ||
286 | ((struct flcn_acr_desc *)acr_dmem)->regions.region_props[ | ||
287 | 0].region_id = 1; | ||
288 | ((struct flcn_acr_desc *)acr_dmem)->regions.region_props[ | ||
289 | 0].start_addr = wpr_inf.wpr_base >> 8; | ||
290 | ((struct flcn_acr_desc *)acr_dmem)->regions.region_props[ | ||
291 | 0].end_addr = (wpr_inf.wpr_base + wpr_inf.size) >> 8; | ||
292 | |||
293 | for (i = 0; i < (img_size_in_bytes/4); i++) { | ||
294 | ((u32 *)acr->acr_ucode.cpu_va)[i] = | ||
295 | acr_ucode_data_t210_load[i]; | ||
296 | } | ||
297 | |||
298 | /* | ||
299 | * In order to execute this binary, we will be using | ||
300 | * a bootloader which will load this image into PMU IMEM/DMEM. | ||
301 | * Fill up the bootloader descriptor for PMU HAL to use.. | ||
302 | * TODO: Use standard descriptor which the generic bootloader is | ||
303 | * checked in. | ||
304 | */ | ||
305 | |||
306 | bl_dmem_desc->signature[0] = 0; | ||
307 | bl_dmem_desc->signature[1] = 0; | ||
308 | bl_dmem_desc->signature[2] = 0; | ||
309 | bl_dmem_desc->signature[3] = 0; | ||
310 | bl_dmem_desc->ctx_dma = GK20A_PMU_DMAIDX_VIRT; | ||
311 | flcn64_set_dma(&bl_dmem_desc->code_dma_base, | ||
312 | acr->acr_ucode.gpu_va); | ||
313 | bl_dmem_desc->non_sec_code_off = acr_ucode_header_t210_load[0]; | ||
314 | bl_dmem_desc->non_sec_code_size = acr_ucode_header_t210_load[1]; | ||
315 | bl_dmem_desc->sec_code_off = acr_ucode_header_t210_load[5]; | ||
316 | bl_dmem_desc->sec_code_size = acr_ucode_header_t210_load[6]; | ||
317 | bl_dmem_desc->code_entry_point = 0; /* Start at 0th offset */ | ||
318 | flcn64_set_dma(&bl_dmem_desc->data_dma_base, | ||
319 | acr->acr_ucode.gpu_va + | ||
320 | (acr_ucode_header_t210_load[2])); | ||
321 | bl_dmem_desc->data_size = acr_ucode_header_t210_load[3]; | ||
322 | |||
323 | } else | ||
324 | acr->acr_dmem_desc->nonwpr_ucode_blob_size = 0; | ||
325 | |||
326 | status = pmu_exec_gen_bl(g, bl_dmem_desc, 1); | ||
327 | if (status != 0) { | ||
328 | err = status; | ||
329 | goto err_free_ucode_map; | ||
330 | } | ||
331 | return 0; | ||
332 | err_free_ucode_map: | ||
333 | gk20a_gmmu_unmap_free(vm, &acr->acr_ucode); | ||
334 | err_release_acr_fw: | ||
335 | release_firmware(acr_fw); | ||
336 | acr->acr_fw = NULL; | ||
337 | return err; | ||
338 | } | ||
diff --git a/drivers/gpu/nvgpu/gm206/acr_gm206.h b/drivers/gpu/nvgpu/gm206/acr_gm206.h deleted file mode 100644 index b0ccbf9c..00000000 --- a/drivers/gpu/nvgpu/gm206/acr_gm206.h +++ /dev/null | |||
@@ -1,82 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ACR_GM206_H_ | ||
15 | #define __ACR_GM206_H_ | ||
16 | |||
17 | #include "gm20b/acr_gm20b.h" | ||
18 | |||
19 | struct loader_config_v1 { | ||
20 | u32 reserved; | ||
21 | u32 dma_idx; | ||
22 | struct falc_u64 code_dma_base; | ||
23 | u32 code_size_total; | ||
24 | u32 code_size_to_load; | ||
25 | u32 code_entry_point; | ||
26 | struct falc_u64 data_dma_base; | ||
27 | u32 data_size; | ||
28 | struct falc_u64 overlay_dma_base; | ||
29 | u32 argc; | ||
30 | u32 argv; | ||
31 | }; | ||
32 | |||
33 | struct flcn_bl_dmem_desc_v1 { | ||
34 | u32 reserved[4]; /*Should be the first element..*/ | ||
35 | u32 signature[4]; /*Should be the first element..*/ | ||
36 | u32 ctx_dma; | ||
37 | struct falc_u64 code_dma_base; | ||
38 | u32 non_sec_code_off; | ||
39 | u32 non_sec_code_size; | ||
40 | u32 sec_code_off; | ||
41 | u32 sec_code_size; | ||
42 | u32 code_entry_point; | ||
43 | struct falc_u64 data_dma_base; | ||
44 | u32 data_size; | ||
45 | u32 argc; | ||
46 | u32 argv; | ||
47 | }; | ||
48 | |||
49 | /*! | ||
50 | * Union of all supported structures used by bootloaders. | ||
51 | */ | ||
52 | union flcn_bl_generic_desc_v1 { | ||
53 | struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1; | ||
54 | struct loader_config_v1 loader_cfg_v1; | ||
55 | }; | ||
56 | |||
57 | /*! | ||
58 | * LSFM Managed Ucode Image | ||
59 | * next : Next image the list, NULL if last. | ||
60 | * wpr_header : WPR header for this ucode image | ||
61 | * lsb_header : LSB header for this ucode image | ||
62 | * bl_gen_desc : Bootloader generic desc structure for this ucode image | ||
63 | * bl_gen_desc_size : Sizeof bootloader desc structure for this ucode image | ||
64 | * full_ucode_size : Surface size required for final ucode image | ||
65 | * ucode_img : Ucode image info | ||
66 | */ | ||
67 | struct lsfm_managed_ucode_img_v1 { | ||
68 | struct lsfm_managed_ucode_img_v1 *next; | ||
69 | struct lsf_wpr_header wpr_header; | ||
70 | struct lsf_lsb_header lsb_header; | ||
71 | union flcn_bl_generic_desc_v1 bl_gen_desc; | ||
72 | u32 bl_gen_desc_size; | ||
73 | u32 full_ucode_size; | ||
74 | struct flcn_ucode_img ucode_img; | ||
75 | }; | ||
76 | |||
77 | void gm206_init_secure_pmu(struct gpu_ops *gops); | ||
78 | int gm206_alloc_blob_space(struct gk20a *g, | ||
79 | size_t size, struct mem_desc *mem); | ||
80 | void gm206_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf); | ||
81 | |||
82 | #endif /*__ACR_GM206_H_*/ | ||
diff --git a/drivers/gpu/nvgpu/gm206/hal_gm206.c b/drivers/gpu/nvgpu/gm206/hal_gm206.c index d6c73b53..8ad5a397 100644 --- a/drivers/gpu/nvgpu/gm206/hal_gm206.c +++ b/drivers/gpu/nvgpu/gm206/hal_gm206.c | |||
@@ -37,7 +37,6 @@ | |||
37 | #include "gm20b/clk_gm20b.h" | 37 | #include "gm20b/clk_gm20b.h" |
38 | #include "gm20b/debug_gm20b.h" | 38 | #include "gm20b/debug_gm20b.h" |
39 | #include "gm206/mm_gm206.h" | 39 | #include "gm206/mm_gm206.h" |
40 | #include "gm206/acr_gm206.h" | ||
41 | 40 | ||
42 | #include <nvgpu/hw/gm206/hw_proj_gm206.h> | 41 | #include <nvgpu/hw/gm206/hw_proj_gm206.h> |
43 | 42 | ||
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c index f5a4053b..847a0b00 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c | |||
@@ -22,8 +22,8 @@ | |||
22 | #include "gk20a/gk20a.h" | 22 | #include "gk20a/gk20a.h" |
23 | #include "gk20a/pmu_gk20a.h" | 23 | #include "gk20a/pmu_gk20a.h" |
24 | 24 | ||
25 | #include "gm206/acr_gm206.h" | ||
26 | #include "gm20b/acr_gm20b.h" | 25 | #include "gm20b/acr_gm20b.h" |
26 | #include "gp106/acr_gp106.h" | ||
27 | #include "gp106/pmu_gp106.h" | 27 | #include "gp106/pmu_gp106.h" |
28 | 28 | ||
29 | #include "sec2_gp106.h" | 29 | #include "sec2_gp106.h" |
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.h b/drivers/gpu/nvgpu/gp106/acr_gp106.h index cd555eb8..dee01f6b 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.h +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -15,13 +15,50 @@ | |||
15 | #define __ACR_GP106_H_ | 15 | #define __ACR_GP106_H_ |
16 | 16 | ||
17 | #include "gm20b/acr_gm20b.h" | 17 | #include "gm20b/acr_gm20b.h" |
18 | #include "gm206/acr_gm206.h" | ||
19 | 18 | ||
20 | #define GP106_FECS_UCODE_SIG "gp106/fecs_sig.bin" | 19 | #define GP106_FECS_UCODE_SIG "gp106/fecs_sig.bin" |
21 | #define GP106_GPCCS_UCODE_SIG "gp106/gpccs_sig.bin" | 20 | #define GP106_GPCCS_UCODE_SIG "gp106/gpccs_sig.bin" |
22 | #define GP104_FECS_UCODE_SIG "gp104/fecs_sig.bin" | 21 | #define GP104_FECS_UCODE_SIG "gp104/fecs_sig.bin" |
23 | #define GP104_GPCCS_UCODE_SIG "gp104/gpccs_sig.bin" | 22 | #define GP104_GPCCS_UCODE_SIG "gp104/gpccs_sig.bin" |
24 | 23 | ||
24 | struct loader_config_v1 { | ||
25 | u32 reserved; | ||
26 | u32 dma_idx; | ||
27 | struct falc_u64 code_dma_base; | ||
28 | u32 code_size_total; | ||
29 | u32 code_size_to_load; | ||
30 | u32 code_entry_point; | ||
31 | struct falc_u64 data_dma_base; | ||
32 | u32 data_size; | ||
33 | struct falc_u64 overlay_dma_base; | ||
34 | u32 argc; | ||
35 | u32 argv; | ||
36 | }; | ||
37 | |||
38 | struct flcn_bl_dmem_desc_v1 { | ||
39 | u32 reserved[4]; /*Should be the first element..*/ | ||
40 | u32 signature[4]; /*Should be the first element..*/ | ||
41 | u32 ctx_dma; | ||
42 | struct falc_u64 code_dma_base; | ||
43 | u32 non_sec_code_off; | ||
44 | u32 non_sec_code_size; | ||
45 | u32 sec_code_off; | ||
46 | u32 sec_code_size; | ||
47 | u32 code_entry_point; | ||
48 | struct falc_u64 data_dma_base; | ||
49 | u32 data_size; | ||
50 | u32 argc; | ||
51 | u32 argv; | ||
52 | }; | ||
53 | |||
54 | /*! | ||
55 | * Union of all supported structures used by bootloaders. | ||
56 | */ | ||
57 | union flcn_bl_generic_desc_v1 { | ||
58 | struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1; | ||
59 | struct loader_config_v1 loader_cfg_v1; | ||
60 | }; | ||
61 | |||
25 | struct lsf_ucode_desc_v1 { | 62 | struct lsf_ucode_desc_v1 { |
26 | u8 prd_keys[2][16]; | 63 | u8 prd_keys[2][16]; |
27 | u8 dbg_keys[2][16]; | 64 | u8 dbg_keys[2][16]; |