diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/common/fifo/tsg.c | 48 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/channel.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/tsg.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 3 |
5 files changed, 64 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c index 6d6c322e..5883667f 100644 --- a/drivers/gpu/nvgpu/common/fifo/tsg.c +++ b/drivers/gpu/nvgpu/common/fifo/tsg.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -445,3 +445,49 @@ void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg, | |||
445 | tsg_sm_error_states->hww_warp_esr_report_mask = | 445 | tsg_sm_error_states->hww_warp_esr_report_mask = |
446 | sm_error_state->hww_warp_esr_report_mask; | 446 | sm_error_state->hww_warp_esr_report_mask; |
447 | } | 447 | } |
448 | |||
449 | int nvgpu_tsg_set_mmu_debug_mode(struct tsg_gk20a *tsg, | ||
450 | struct channel_gk20a *ch, bool enable) | ||
451 | { | ||
452 | struct gk20a *g; | ||
453 | int err = 0; | ||
454 | u32 tsg_refcnt; | ||
455 | |||
456 | if ((ch == NULL) || (tsg == NULL)) { | ||
457 | return -EINVAL; | ||
458 | } | ||
459 | g = ch->g; | ||
460 | |||
461 | if (g->ops.gr.set_mmu_debug_mode == NULL) { | ||
462 | return -ENOSYS; | ||
463 | } | ||
464 | |||
465 | if (enable) { | ||
466 | if (ch->mmu_debug_mode_enabled) { | ||
467 | /* already enabled for this channel */ | ||
468 | return 0; | ||
469 | } | ||
470 | tsg_refcnt = tsg->mmu_debug_mode_refcnt + 1U; | ||
471 | } else { | ||
472 | if (!ch->mmu_debug_mode_enabled) { | ||
473 | /* already disabled for this channel */ | ||
474 | return 0; | ||
475 | } | ||
476 | tsg_refcnt = tsg->mmu_debug_mode_refcnt - 1U; | ||
477 | } | ||
478 | |||
479 | /* | ||
480 | * enable GPC MMU debug mode if it was requested for at | ||
481 | * least one channel in the TSG | ||
482 | */ | ||
483 | err = g->ops.gr.set_mmu_debug_mode(g, ch, tsg_refcnt > 0U); | ||
484 | if (err != 0) { | ||
485 | nvgpu_err(g, "set mmu debug mode failed, err=%d", err); | ||
486 | return err; | ||
487 | } | ||
488 | |||
489 | ch->mmu_debug_mode_enabled = enable; | ||
490 | tsg->mmu_debug_mode_refcnt = tsg_refcnt; | ||
491 | |||
492 | return err; | ||
493 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index d00181af..dacef784 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1468,10 +1468,15 @@ int gm20b_gr_set_mmu_debug_mode(struct gk20a *g, | |||
1468 | gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(), | 1468 | gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(), |
1469 | }; | 1469 | }; |
1470 | int err; | 1470 | int err; |
1471 | struct tsg_gk20a *tsg = tsg_gk20a_from_ch(ch); | ||
1472 | |||
1473 | if (tsg == NULL) { | ||
1474 | return enable ? -EINVAL : 0; | ||
1475 | } | ||
1471 | 1476 | ||
1472 | err = gr_gk20a_exec_ctx_ops(ch, &ctx_ops, 1, 1, 0, NULL); | 1477 | err = gr_gk20a_exec_ctx_ops(ch, &ctx_ops, 1, 1, 0, NULL); |
1473 | if (err != 0) { | 1478 | if (err != 0) { |
1474 | nvgpu_err(g, "Failed to access register"); | 1479 | nvgpu_err(g, "update MMU debug mode failed"); |
1475 | } | 1480 | } |
1476 | return err; | 1481 | return err; |
1477 | } | 1482 | } |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel.h b/drivers/gpu/nvgpu/include/nvgpu/channel.h index 7ca60fe3..e98af09b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/channel.h +++ b/drivers/gpu/nvgpu/include/nvgpu/channel.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -328,6 +328,7 @@ struct channel_gk20a { | |||
328 | bool has_os_fence_framework_support; | 328 | bool has_os_fence_framework_support; |
329 | 329 | ||
330 | bool is_privileged_channel; | 330 | bool is_privileged_channel; |
331 | bool mmu_debug_mode_enabled; | ||
331 | }; | 332 | }; |
332 | 333 | ||
333 | static inline struct channel_gk20a * | 334 | static inline struct channel_gk20a * |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/tsg.h b/drivers/gpu/nvgpu/include/nvgpu/tsg.h index 212fb77c..b43a6b98 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/tsg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/tsg.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -76,6 +76,9 @@ struct tsg_gk20a { | |||
76 | bool tpc_num_initialized; | 76 | bool tpc_num_initialized; |
77 | bool in_use; | 77 | bool in_use; |
78 | 78 | ||
79 | /* MMU debug mode enabled if mmu_debug_mode_refcnt > 0 */ | ||
80 | u32 mmu_debug_mode_refcnt; | ||
81 | |||
79 | struct nvgpu_tsg_sm_error_state *sm_error_states; | 82 | struct nvgpu_tsg_sm_error_state *sm_error_states; |
80 | 83 | ||
81 | #define NVGPU_SM_EXCEPTION_TYPE_MASK_NONE (0x0U) | 84 | #define NVGPU_SM_EXCEPTION_TYPE_MASK_NONE (0x0U) |
@@ -124,4 +127,7 @@ gk20a_event_id_data_from_event_id_node(struct nvgpu_list_node *node) | |||
124 | ((uintptr_t)node - offsetof(struct gk20a_event_id_data, event_id_node)); | 127 | ((uintptr_t)node - offsetof(struct gk20a_event_id_data, event_id_node)); |
125 | }; | 128 | }; |
126 | 129 | ||
130 | int nvgpu_tsg_set_mmu_debug_mode(struct tsg_gk20a *tsg, | ||
131 | struct channel_gk20a *ch, bool enable); | ||
132 | |||
127 | #endif /* TSG_GK20A_H */ | 133 | #endif /* TSG_GK20A_H */ |
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index f7a65f2b..408bbc64 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | |||
@@ -1107,10 +1107,11 @@ static int nvgpu_dbg_gpu_ioctl_set_mmu_debug_mode( | |||
1107 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); | 1107 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); |
1108 | if (!ch) { | 1108 | if (!ch) { |
1109 | nvgpu_err(g, "no bound channel for mmu debug mode"); | 1109 | nvgpu_err(g, "no bound channel for mmu debug mode"); |
1110 | err = -EINVAL; | ||
1110 | goto clean_up; | 1111 | goto clean_up; |
1111 | } | 1112 | } |
1112 | 1113 | ||
1113 | err = g->ops.gr.set_mmu_debug_mode(g, ch, enable); | 1114 | err = nvgpu_tsg_set_mmu_debug_mode(tsg_gk20a_from_ch(ch), ch, enable); |
1114 | if (err) { | 1115 | if (err) { |
1115 | nvgpu_err(g, "set mmu debug mode failed, err=%d", err); | 1116 | nvgpu_err(g, "set mmu debug mode failed, err=%d", err); |
1116 | } | 1117 | } |