diff options
Diffstat (limited to 'drivers')
26 files changed, 185 insertions, 328 deletions
diff --git a/drivers/gpu/nvgpu/Kconfig b/drivers/gpu/nvgpu/Kconfig index 7a9a99c6..cab717bb 100644 --- a/drivers/gpu/nvgpu/Kconfig +++ b/drivers/gpu/nvgpu/Kconfig | |||
@@ -115,8 +115,7 @@ config TEGRA_USE_NA_GPCPLL | |||
115 | config GK20A_PCI | 115 | config GK20A_PCI |
116 | bool "Support PCIe NVIDIA GPUs on nvgpu" | 116 | bool "Support PCIe NVIDIA GPUs on nvgpu" |
117 | depends on PCI && GK20A | 117 | depends on PCI && GK20A |
118 | default y if ARCH_TEGRA_18x_SOC | 118 | default y |
119 | default n | ||
120 | help | 119 | help |
121 | Enable support for GPUs on PCIe bus. | 120 | Enable support for GPUs on PCIe bus. |
122 | 121 | ||
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index f8253e41..72946fc0 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -177,7 +177,6 @@ nvgpu-$(CONFIG_GK20A_DEVFREQ) += \ | |||
177 | nvgpu-$(CONFIG_GK20A_CYCLE_STATS) += \ | 177 | nvgpu-$(CONFIG_GK20A_CYCLE_STATS) += \ |
178 | gk20a/css_gr_gk20a.o | 178 | gk20a/css_gr_gk20a.o |
179 | 179 | ||
180 | ifeq ($(CONFIG_ARCH_TEGRA_18x_SOC),y) | ||
181 | nvgpu-y += \ | 180 | nvgpu-y += \ |
182 | gp10b/gr_gp10b.o \ | 181 | gp10b/gr_gp10b.o \ |
183 | gp10b/gr_ctx_gp10b.o \ | 182 | gp10b/gr_ctx_gp10b.o \ |
@@ -249,7 +248,6 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ | |||
249 | common/linux/vgpu/gp10b/vgpu_hal_gp10b.o \ | 248 | common/linux/vgpu/gp10b/vgpu_hal_gp10b.o \ |
250 | common/linux/vgpu/gp10b/vgpu_gr_gp10b.o \ | 249 | common/linux/vgpu/gp10b/vgpu_gr_gp10b.o \ |
251 | common/linux/vgpu/gp10b/vgpu_mm_gp10b.o | 250 | common/linux/vgpu/gp10b/vgpu_mm_gp10b.o |
252 | endif | ||
253 | 251 | ||
254 | ifeq ($(CONFIG_ARCH_TEGRA_19x_SOC),y) | 252 | ifeq ($(CONFIG_ARCH_TEGRA_19x_SOC),y) |
255 | nvgpu-y += \ | 253 | nvgpu-y += \ |
diff --git a/drivers/gpu/nvgpu/common/linux/debug.c b/drivers/gpu/nvgpu/common/linux/debug.c index 7a4e4e9f..fb07df5b 100644 --- a/drivers/gpu/nvgpu/common/linux/debug.c +++ b/drivers/gpu/nvgpu/common/linux/debug.c | |||
@@ -364,23 +364,20 @@ void gk20a_debug_init(struct gk20a *g, const char *debugfs_symlink) | |||
364 | S_IRUGO|S_IWUSR, | 364 | S_IRUGO|S_IWUSR, |
365 | l->debugfs, | 365 | l->debugfs, |
366 | &g->runlist_interleave); | 366 | &g->runlist_interleave); |
367 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
368 | l->debugfs_force_preemption_gfxp = | 367 | l->debugfs_force_preemption_gfxp = |
369 | debugfs_create_bool("force_preemption_gfxp", S_IRUGO|S_IWUSR, | 368 | debugfs_create_bool("force_preemption_gfxp", S_IRUGO|S_IWUSR, |
370 | l->debugfs, | 369 | l->debugfs, |
371 | &g->gr.t18x.ctx_vars.force_preemption_gfxp); | 370 | &g->gr.ctx_vars.force_preemption_gfxp); |
372 | 371 | ||
373 | l->debugfs_force_preemption_cilp = | 372 | l->debugfs_force_preemption_cilp = |
374 | debugfs_create_bool("force_preemption_cilp", S_IRUGO|S_IWUSR, | 373 | debugfs_create_bool("force_preemption_cilp", S_IRUGO|S_IWUSR, |
375 | l->debugfs, | 374 | l->debugfs, |
376 | &g->gr.t18x.ctx_vars.force_preemption_cilp); | 375 | &g->gr.ctx_vars.force_preemption_cilp); |
377 | 376 | ||
378 | l->debugfs_dump_ctxsw_stats = | 377 | l->debugfs_dump_ctxsw_stats = |
379 | debugfs_create_bool("dump_ctxsw_stats_on_channel_close", | 378 | debugfs_create_bool("dump_ctxsw_stats_on_channel_close", |
380 | S_IRUGO|S_IWUSR, l->debugfs, | 379 | S_IRUGO|S_IWUSR, l->debugfs, |
381 | &g->gr.t18x. | 380 | &g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close); |
382 | ctx_vars.dump_ctxsw_stats_on_channel_close); | ||
383 | #endif | ||
384 | 381 | ||
385 | gr_gk20a_debugfs_init(g); | 382 | gr_gk20a_debugfs_init(g); |
386 | gk20a_pmu_debugfs_init(g); | 383 | gk20a_pmu_debugfs_init(g); |
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c index 31651795..0ac50140 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c | |||
@@ -22,7 +22,6 @@ | |||
22 | #include <linux/dma-buf.h> | 22 | #include <linux/dma-buf.h> |
23 | #include <linux/poll.h> | 23 | #include <linux/poll.h> |
24 | #include <uapi/linux/nvgpu.h> | 24 | #include <uapi/linux/nvgpu.h> |
25 | #include <uapi/linux/nvgpu-t18x.h> | ||
26 | 25 | ||
27 | #include <nvgpu/semaphore.h> | 26 | #include <nvgpu/semaphore.h> |
28 | #include <nvgpu/timers.h> | 27 | #include <nvgpu/timers.h> |
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c index 2a91b87d..c28bdfdb 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c | |||
@@ -20,7 +20,6 @@ | |||
20 | #include <linux/anon_inodes.h> | 20 | #include <linux/anon_inodes.h> |
21 | #include <linux/fs.h> | 21 | #include <linux/fs.h> |
22 | #include <uapi/linux/nvgpu.h> | 22 | #include <uapi/linux/nvgpu.h> |
23 | #include <uapi/linux/nvgpu-t18x.h> | ||
24 | 23 | ||
25 | #include <nvgpu/bitops.h> | 24 | #include <nvgpu/bitops.h> |
26 | #include <nvgpu/kmem.h> | 25 | #include <nvgpu/kmem.h> |
@@ -54,9 +53,7 @@ | |||
54 | struct gk20a_ctrl_priv { | 53 | struct gk20a_ctrl_priv { |
55 | struct device *dev; | 54 | struct device *dev; |
56 | struct gk20a *g; | 55 | struct gk20a *g; |
57 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
58 | struct nvgpu_clk_session *clk_session; | 56 | struct nvgpu_clk_session *clk_session; |
59 | #endif | ||
60 | }; | 57 | }; |
61 | 58 | ||
62 | int gk20a_ctrl_dev_open(struct inode *inode, struct file *filp) | 59 | int gk20a_ctrl_dev_open(struct inode *inode, struct file *filp) |
@@ -95,9 +92,7 @@ int gk20a_ctrl_dev_open(struct inode *inode, struct file *filp) | |||
95 | gk20a_idle(g); | 92 | gk20a_idle(g); |
96 | } | 93 | } |
97 | 94 | ||
98 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
99 | err = nvgpu_clk_arb_init_session(g, &priv->clk_session); | 95 | err = nvgpu_clk_arb_init_session(g, &priv->clk_session); |
100 | #endif | ||
101 | free_ref: | 96 | free_ref: |
102 | if (err) | 97 | if (err) |
103 | gk20a_put(g); | 98 | gk20a_put(g); |
@@ -110,10 +105,8 @@ int gk20a_ctrl_dev_release(struct inode *inode, struct file *filp) | |||
110 | 105 | ||
111 | gk20a_dbg_fn(""); | 106 | gk20a_dbg_fn(""); |
112 | 107 | ||
113 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
114 | if (priv->clk_session) | 108 | if (priv->clk_session) |
115 | nvgpu_clk_arb_release_session(g, priv->clk_session); | 109 | nvgpu_clk_arb_release_session(g, priv->clk_session); |
116 | #endif | ||
117 | 110 | ||
118 | gk20a_put(g); | 111 | gk20a_put(g); |
119 | nvgpu_kfree(g, priv); | 112 | nvgpu_kfree(g, priv); |
@@ -944,7 +937,6 @@ static int nvgpu_gpu_get_memory_state(struct gk20a *g, | |||
944 | return err; | 937 | return err; |
945 | } | 938 | } |
946 | 939 | ||
947 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
948 | static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g, | 940 | static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g, |
949 | struct gk20a_ctrl_priv *priv, | 941 | struct gk20a_ctrl_priv *priv, |
950 | struct nvgpu_gpu_clk_vf_points_args *args) | 942 | struct nvgpu_gpu_clk_vf_points_args *args) |
@@ -1402,7 +1394,6 @@ static int nvgpu_gpu_get_temperature(struct gk20a *g, | |||
1402 | 1394 | ||
1403 | return err; | 1395 | return err; |
1404 | } | 1396 | } |
1405 | #endif | ||
1406 | 1397 | ||
1407 | static int nvgpu_gpu_set_therm_alert_limit(struct gk20a *g, | 1398 | static int nvgpu_gpu_set_therm_alert_limit(struct gk20a *g, |
1408 | struct nvgpu_gpu_set_therm_alert_limit_args *args) | 1399 | struct nvgpu_gpu_set_therm_alert_limit_args *args) |
@@ -1798,7 +1789,6 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg | |||
1798 | (struct nvgpu_gpu_get_memory_state_args *)buf); | 1789 | (struct nvgpu_gpu_get_memory_state_args *)buf); |
1799 | break; | 1790 | break; |
1800 | 1791 | ||
1801 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
1802 | case NVGPU_GPU_IOCTL_CLK_GET_RANGE: | 1792 | case NVGPU_GPU_IOCTL_CLK_GET_RANGE: |
1803 | err = nvgpu_gpu_clk_get_range(g, priv, | 1793 | err = nvgpu_gpu_clk_get_range(g, priv, |
1804 | (struct nvgpu_gpu_clk_range_args *)buf); | 1794 | (struct nvgpu_gpu_clk_range_args *)buf); |
@@ -1843,7 +1833,6 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg | |||
1843 | err = nvgpu_gpu_get_temperature(g, | 1833 | err = nvgpu_gpu_get_temperature(g, |
1844 | (struct nvgpu_gpu_get_temperature_args *)buf); | 1834 | (struct nvgpu_gpu_get_temperature_args *)buf); |
1845 | break; | 1835 | break; |
1846 | #endif | ||
1847 | 1836 | ||
1848 | case NVGPU_GPU_IOCTL_SET_THERM_ALERT_LIMIT: | 1837 | case NVGPU_GPU_IOCTL_SET_THERM_ALERT_LIMIT: |
1849 | err = nvgpu_gpu_set_therm_alert_limit(g, | 1838 | err = nvgpu_gpu_set_therm_alert_limit(g, |
diff --git a/drivers/gpu/nvgpu/common/linux/module.c b/drivers/gpu/nvgpu/common/linux/module.c index 76b9d4db..796507a9 100644 --- a/drivers/gpu/nvgpu/common/linux/module.c +++ b/drivers/gpu/nvgpu/common/linux/module.c | |||
@@ -339,10 +339,8 @@ static struct of_device_id tegra_gk20a_of_match[] = { | |||
339 | #ifdef CONFIG_TEGRA_GK20A | 339 | #ifdef CONFIG_TEGRA_GK20A |
340 | { .compatible = "nvidia,tegra210-gm20b", | 340 | { .compatible = "nvidia,tegra210-gm20b", |
341 | .data = &gm20b_tegra_platform }, | 341 | .data = &gm20b_tegra_platform }, |
342 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
343 | { .compatible = "nvidia,tegra186-gp10b", | 342 | { .compatible = "nvidia,tegra186-gp10b", |
344 | .data = &gp10b_tegra_platform }, | 343 | .data = &gp10b_tegra_platform }, |
345 | #endif | ||
346 | #ifdef CONFIG_TEGRA_19x_GPU | 344 | #ifdef CONFIG_TEGRA_19x_GPU |
347 | { .compatible = TEGRA_19x_GPU_COMPAT_TEGRA, | 345 | { .compatible = TEGRA_19x_GPU_COMPAT_TEGRA, |
348 | .data = &t19x_gpu_tegra_platform }, | 346 | .data = &t19x_gpu_tegra_platform }, |
@@ -1035,11 +1033,9 @@ static int nvgpu_read_fuse_overrides(struct gk20a *g) | |||
1035 | case GM20B_FUSE_OPT_TPC_DISABLE: | 1033 | case GM20B_FUSE_OPT_TPC_DISABLE: |
1036 | g->tpc_fs_mask_user = ~value; | 1034 | g->tpc_fs_mask_user = ~value; |
1037 | break; | 1035 | break; |
1038 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
1039 | case GP10B_FUSE_OPT_ECC_EN: | 1036 | case GP10B_FUSE_OPT_ECC_EN: |
1040 | g->gr.t18x.fecs_feature_override_ecc_val = value; | 1037 | g->gr.fecs_feature_override_ecc_val = value; |
1041 | break; | 1038 | break; |
1042 | #endif | ||
1043 | default: | 1039 | default: |
1044 | nvgpu_err(g, "ignore unknown fuse override %08x", fuse); | 1040 | nvgpu_err(g, "ignore unknown fuse override %08x", fuse); |
1045 | break; | 1041 | break; |
@@ -1184,9 +1180,7 @@ int nvgpu_remove(struct device *dev, struct class *class) | |||
1184 | if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) | 1180 | if (IS_ENABLED(CONFIG_GK20A_DEVFREQ)) |
1185 | gk20a_scale_exit(dev); | 1181 | gk20a_scale_exit(dev); |
1186 | 1182 | ||
1187 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
1188 | nvgpu_clk_arb_cleanup_arbiter(g); | 1183 | nvgpu_clk_arb_cleanup_arbiter(g); |
1189 | #endif | ||
1190 | 1184 | ||
1191 | gk20a_user_deinit(dev, class); | 1185 | gk20a_user_deinit(dev, class); |
1192 | 1186 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c index b944844e..b42c3698 100644 --- a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c | |||
@@ -135,13 +135,13 @@ static int gp10b_tegra_probe(struct device *dev) | |||
135 | platform->bypass_smmu = !device_is_iommuable(dev); | 135 | platform->bypass_smmu = !device_is_iommuable(dev); |
136 | platform->disable_bigpage = platform->bypass_smmu; | 136 | platform->disable_bigpage = platform->bypass_smmu; |
137 | 137 | ||
138 | platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close | 138 | platform->g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close |
139 | = false; | 139 | = false; |
140 | platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close | 140 | platform->g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close |
141 | = false; | 141 | = false; |
142 | 142 | ||
143 | platform->g->gr.t18x.ctx_vars.force_preemption_gfxp = false; | 143 | platform->g->gr.ctx_vars.force_preemption_gfxp = false; |
144 | platform->g->gr.t18x.ctx_vars.force_preemption_cilp = false; | 144 | platform->g->gr.ctx_vars.force_preemption_cilp = false; |
145 | 145 | ||
146 | gp10b_tegra_get_clocks(dev); | 146 | gp10b_tegra_get_clocks(dev); |
147 | nvgpu_linux_init_clk_support(platform->g); | 147 | nvgpu_linux_init_clk_support(platform->g); |
@@ -621,86 +621,86 @@ void gr_gp10b_create_sysfs(struct gk20a *g) | |||
621 | initialized multiple times but we only need to create the ECC | 621 | initialized multiple times but we only need to create the ECC |
622 | stats once. Therefore, add the following check to avoid | 622 | stats once. Therefore, add the following check to avoid |
623 | creating duplicate stat sysfs nodes. */ | 623 | creating duplicate stat sysfs nodes. */ |
624 | if (g->ecc.gr.t18x.sm_lrf_single_err_count.counters != NULL) | 624 | if (g->ecc.gr.sm_lrf_single_err_count.counters != NULL) |
625 | return; | 625 | return; |
626 | 626 | ||
627 | error |= gr_gp10b_ecc_stat_create(dev, | 627 | error |= gr_gp10b_ecc_stat_create(dev, |
628 | 0, | 628 | 0, |
629 | "sm_lrf_ecc_single_err_count", | 629 | "sm_lrf_ecc_single_err_count", |
630 | &g->ecc.gr.t18x.sm_lrf_single_err_count, | 630 | &g->ecc.gr.sm_lrf_single_err_count, |
631 | &dev_attr_sm_lrf_ecc_single_err_count_array); | 631 | &dev_attr_sm_lrf_ecc_single_err_count_array); |
632 | error |= gr_gp10b_ecc_stat_create(dev, | 632 | error |= gr_gp10b_ecc_stat_create(dev, |
633 | 0, | 633 | 0, |
634 | "sm_lrf_ecc_double_err_count", | 634 | "sm_lrf_ecc_double_err_count", |
635 | &g->ecc.gr.t18x.sm_lrf_double_err_count, | 635 | &g->ecc.gr.sm_lrf_double_err_count, |
636 | &dev_attr_sm_lrf_ecc_double_err_count_array); | 636 | &dev_attr_sm_lrf_ecc_double_err_count_array); |
637 | 637 | ||
638 | error |= gr_gp10b_ecc_stat_create(dev, | 638 | error |= gr_gp10b_ecc_stat_create(dev, |
639 | 0, | 639 | 0, |
640 | "sm_shm_ecc_sec_count", | 640 | "sm_shm_ecc_sec_count", |
641 | &g->ecc.gr.t18x.sm_shm_sec_count, | 641 | &g->ecc.gr.sm_shm_sec_count, |
642 | &dev_attr_sm_shm_ecc_sec_count_array); | 642 | &dev_attr_sm_shm_ecc_sec_count_array); |
643 | error |= gr_gp10b_ecc_stat_create(dev, | 643 | error |= gr_gp10b_ecc_stat_create(dev, |
644 | 0, | 644 | 0, |
645 | "sm_shm_ecc_sed_count", | 645 | "sm_shm_ecc_sed_count", |
646 | &g->ecc.gr.t18x.sm_shm_sed_count, | 646 | &g->ecc.gr.sm_shm_sed_count, |
647 | &dev_attr_sm_shm_ecc_sed_count_array); | 647 | &dev_attr_sm_shm_ecc_sed_count_array); |
648 | error |= gr_gp10b_ecc_stat_create(dev, | 648 | error |= gr_gp10b_ecc_stat_create(dev, |
649 | 0, | 649 | 0, |
650 | "sm_shm_ecc_ded_count", | 650 | "sm_shm_ecc_ded_count", |
651 | &g->ecc.gr.t18x.sm_shm_ded_count, | 651 | &g->ecc.gr.sm_shm_ded_count, |
652 | &dev_attr_sm_shm_ecc_ded_count_array); | 652 | &dev_attr_sm_shm_ecc_ded_count_array); |
653 | 653 | ||
654 | error |= gr_gp10b_ecc_stat_create(dev, | 654 | error |= gr_gp10b_ecc_stat_create(dev, |
655 | 0, | 655 | 0, |
656 | "tex_ecc_total_sec_pipe0_count", | 656 | "tex_ecc_total_sec_pipe0_count", |
657 | &g->ecc.gr.t18x.tex_total_sec_pipe0_count, | 657 | &g->ecc.gr.tex_total_sec_pipe0_count, |
658 | &dev_attr_tex_ecc_total_sec_pipe0_count_array); | 658 | &dev_attr_tex_ecc_total_sec_pipe0_count_array); |
659 | error |= gr_gp10b_ecc_stat_create(dev, | 659 | error |= gr_gp10b_ecc_stat_create(dev, |
660 | 0, | 660 | 0, |
661 | "tex_ecc_total_ded_pipe0_count", | 661 | "tex_ecc_total_ded_pipe0_count", |
662 | &g->ecc.gr.t18x.tex_total_ded_pipe0_count, | 662 | &g->ecc.gr.tex_total_ded_pipe0_count, |
663 | &dev_attr_tex_ecc_total_ded_pipe0_count_array); | 663 | &dev_attr_tex_ecc_total_ded_pipe0_count_array); |
664 | error |= gr_gp10b_ecc_stat_create(dev, | 664 | error |= gr_gp10b_ecc_stat_create(dev, |
665 | 0, | 665 | 0, |
666 | "tex_ecc_unique_sec_pipe0_count", | 666 | "tex_ecc_unique_sec_pipe0_count", |
667 | &g->ecc.gr.t18x.tex_unique_sec_pipe0_count, | 667 | &g->ecc.gr.tex_unique_sec_pipe0_count, |
668 | &dev_attr_tex_ecc_unique_sec_pipe0_count_array); | 668 | &dev_attr_tex_ecc_unique_sec_pipe0_count_array); |
669 | error |= gr_gp10b_ecc_stat_create(dev, | 669 | error |= gr_gp10b_ecc_stat_create(dev, |
670 | 0, | 670 | 0, |
671 | "tex_ecc_unique_ded_pipe0_count", | 671 | "tex_ecc_unique_ded_pipe0_count", |
672 | &g->ecc.gr.t18x.tex_unique_ded_pipe0_count, | 672 | &g->ecc.gr.tex_unique_ded_pipe0_count, |
673 | &dev_attr_tex_ecc_unique_ded_pipe0_count_array); | 673 | &dev_attr_tex_ecc_unique_ded_pipe0_count_array); |
674 | error |= gr_gp10b_ecc_stat_create(dev, | 674 | error |= gr_gp10b_ecc_stat_create(dev, |
675 | 0, | 675 | 0, |
676 | "tex_ecc_total_sec_pipe1_count", | 676 | "tex_ecc_total_sec_pipe1_count", |
677 | &g->ecc.gr.t18x.tex_total_sec_pipe1_count, | 677 | &g->ecc.gr.tex_total_sec_pipe1_count, |
678 | &dev_attr_tex_ecc_total_sec_pipe1_count_array); | 678 | &dev_attr_tex_ecc_total_sec_pipe1_count_array); |
679 | error |= gr_gp10b_ecc_stat_create(dev, | 679 | error |= gr_gp10b_ecc_stat_create(dev, |
680 | 0, | 680 | 0, |
681 | "tex_ecc_total_ded_pipe1_count", | 681 | "tex_ecc_total_ded_pipe1_count", |
682 | &g->ecc.gr.t18x.tex_total_ded_pipe1_count, | 682 | &g->ecc.gr.tex_total_ded_pipe1_count, |
683 | &dev_attr_tex_ecc_total_ded_pipe1_count_array); | 683 | &dev_attr_tex_ecc_total_ded_pipe1_count_array); |
684 | error |= gr_gp10b_ecc_stat_create(dev, | 684 | error |= gr_gp10b_ecc_stat_create(dev, |
685 | 0, | 685 | 0, |
686 | "tex_ecc_unique_sec_pipe1_count", | 686 | "tex_ecc_unique_sec_pipe1_count", |
687 | &g->ecc.gr.t18x.tex_unique_sec_pipe1_count, | 687 | &g->ecc.gr.tex_unique_sec_pipe1_count, |
688 | &dev_attr_tex_ecc_unique_sec_pipe1_count_array); | 688 | &dev_attr_tex_ecc_unique_sec_pipe1_count_array); |
689 | error |= gr_gp10b_ecc_stat_create(dev, | 689 | error |= gr_gp10b_ecc_stat_create(dev, |
690 | 0, | 690 | 0, |
691 | "tex_ecc_unique_ded_pipe1_count", | 691 | "tex_ecc_unique_ded_pipe1_count", |
692 | &g->ecc.gr.t18x.tex_unique_ded_pipe1_count, | 692 | &g->ecc.gr.tex_unique_ded_pipe1_count, |
693 | &dev_attr_tex_ecc_unique_ded_pipe1_count_array); | 693 | &dev_attr_tex_ecc_unique_ded_pipe1_count_array); |
694 | 694 | ||
695 | error |= gr_gp10b_ecc_stat_create(dev, | 695 | error |= gr_gp10b_ecc_stat_create(dev, |
696 | 1, | 696 | 1, |
697 | "lts0_ecc_sec_count", | 697 | "lts0_ecc_sec_count", |
698 | &g->ecc.gr.t18x.l2_sec_count, | 698 | &g->ecc.ltc.l2_sec_count, |
699 | &dev_attr_l2_ecc_sec_count_array); | 699 | &dev_attr_l2_ecc_sec_count_array); |
700 | error |= gr_gp10b_ecc_stat_create(dev, | 700 | error |= gr_gp10b_ecc_stat_create(dev, |
701 | 1, | 701 | 1, |
702 | "lts0_ecc_ded_count", | 702 | "lts0_ecc_ded_count", |
703 | &g->ecc.gr.t18x.l2_ded_count, | 703 | &g->ecc.ltc.l2_ded_count, |
704 | &dev_attr_l2_ecc_ded_count_array); | 704 | &dev_attr_l2_ecc_ded_count_array); |
705 | 705 | ||
706 | if (error) | 706 | if (error) |
@@ -713,65 +713,65 @@ static void gr_gp10b_remove_sysfs(struct device *dev) | |||
713 | 713 | ||
714 | gr_gp10b_ecc_stat_remove(dev, | 714 | gr_gp10b_ecc_stat_remove(dev, |
715 | 0, | 715 | 0, |
716 | &g->ecc.gr.t18x.sm_lrf_single_err_count, | 716 | &g->ecc.gr.sm_lrf_single_err_count, |
717 | dev_attr_sm_lrf_ecc_single_err_count_array); | 717 | dev_attr_sm_lrf_ecc_single_err_count_array); |
718 | gr_gp10b_ecc_stat_remove(dev, | 718 | gr_gp10b_ecc_stat_remove(dev, |
719 | 0, | 719 | 0, |
720 | &g->ecc.gr.t18x.sm_lrf_double_err_count, | 720 | &g->ecc.gr.sm_lrf_double_err_count, |
721 | dev_attr_sm_lrf_ecc_double_err_count_array); | 721 | dev_attr_sm_lrf_ecc_double_err_count_array); |
722 | 722 | ||
723 | gr_gp10b_ecc_stat_remove(dev, | 723 | gr_gp10b_ecc_stat_remove(dev, |
724 | 0, | 724 | 0, |
725 | &g->ecc.gr.t18x.sm_shm_sec_count, | 725 | &g->ecc.gr.sm_shm_sec_count, |
726 | dev_attr_sm_shm_ecc_sec_count_array); | 726 | dev_attr_sm_shm_ecc_sec_count_array); |
727 | gr_gp10b_ecc_stat_remove(dev, | 727 | gr_gp10b_ecc_stat_remove(dev, |
728 | 0, | 728 | 0, |
729 | &g->ecc.gr.t18x.sm_shm_sed_count, | 729 | &g->ecc.gr.sm_shm_sed_count, |
730 | dev_attr_sm_shm_ecc_sed_count_array); | 730 | dev_attr_sm_shm_ecc_sed_count_array); |
731 | gr_gp10b_ecc_stat_remove(dev, | 731 | gr_gp10b_ecc_stat_remove(dev, |
732 | 0, | 732 | 0, |
733 | &g->ecc.gr.t18x.sm_shm_ded_count, | 733 | &g->ecc.gr.sm_shm_ded_count, |
734 | dev_attr_sm_shm_ecc_ded_count_array); | 734 | dev_attr_sm_shm_ecc_ded_count_array); |
735 | 735 | ||
736 | gr_gp10b_ecc_stat_remove(dev, | 736 | gr_gp10b_ecc_stat_remove(dev, |
737 | 0, | 737 | 0, |
738 | &g->ecc.gr.t18x.tex_total_sec_pipe0_count, | 738 | &g->ecc.gr.tex_total_sec_pipe0_count, |
739 | dev_attr_tex_ecc_total_sec_pipe0_count_array); | 739 | dev_attr_tex_ecc_total_sec_pipe0_count_array); |
740 | gr_gp10b_ecc_stat_remove(dev, | 740 | gr_gp10b_ecc_stat_remove(dev, |
741 | 0, | 741 | 0, |
742 | &g->ecc.gr.t18x.tex_total_ded_pipe0_count, | 742 | &g->ecc.gr.tex_total_ded_pipe0_count, |
743 | dev_attr_tex_ecc_total_ded_pipe0_count_array); | 743 | dev_attr_tex_ecc_total_ded_pipe0_count_array); |
744 | gr_gp10b_ecc_stat_remove(dev, | 744 | gr_gp10b_ecc_stat_remove(dev, |
745 | 0, | 745 | 0, |
746 | &g->ecc.gr.t18x.tex_unique_sec_pipe0_count, | 746 | &g->ecc.gr.tex_unique_sec_pipe0_count, |
747 | dev_attr_tex_ecc_unique_sec_pipe0_count_array); | 747 | dev_attr_tex_ecc_unique_sec_pipe0_count_array); |
748 | gr_gp10b_ecc_stat_remove(dev, | 748 | gr_gp10b_ecc_stat_remove(dev, |
749 | 0, | 749 | 0, |
750 | &g->ecc.gr.t18x.tex_unique_ded_pipe0_count, | 750 | &g->ecc.gr.tex_unique_ded_pipe0_count, |
751 | dev_attr_tex_ecc_unique_ded_pipe0_count_array); | 751 | dev_attr_tex_ecc_unique_ded_pipe0_count_array); |
752 | gr_gp10b_ecc_stat_remove(dev, | 752 | gr_gp10b_ecc_stat_remove(dev, |
753 | 0, | 753 | 0, |
754 | &g->ecc.gr.t18x.tex_total_sec_pipe1_count, | 754 | &g->ecc.gr.tex_total_sec_pipe1_count, |
755 | dev_attr_tex_ecc_total_sec_pipe1_count_array); | 755 | dev_attr_tex_ecc_total_sec_pipe1_count_array); |
756 | gr_gp10b_ecc_stat_remove(dev, | 756 | gr_gp10b_ecc_stat_remove(dev, |
757 | 0, | 757 | 0, |
758 | &g->ecc.gr.t18x.tex_total_ded_pipe1_count, | 758 | &g->ecc.gr.tex_total_ded_pipe1_count, |
759 | dev_attr_tex_ecc_total_ded_pipe1_count_array); | 759 | dev_attr_tex_ecc_total_ded_pipe1_count_array); |
760 | gr_gp10b_ecc_stat_remove(dev, | 760 | gr_gp10b_ecc_stat_remove(dev, |
761 | 0, | 761 | 0, |
762 | &g->ecc.gr.t18x.tex_unique_sec_pipe1_count, | 762 | &g->ecc.gr.tex_unique_sec_pipe1_count, |
763 | dev_attr_tex_ecc_unique_sec_pipe1_count_array); | 763 | dev_attr_tex_ecc_unique_sec_pipe1_count_array); |
764 | gr_gp10b_ecc_stat_remove(dev, | 764 | gr_gp10b_ecc_stat_remove(dev, |
765 | 0, | 765 | 0, |
766 | &g->ecc.gr.t18x.tex_unique_ded_pipe1_count, | 766 | &g->ecc.gr.tex_unique_ded_pipe1_count, |
767 | dev_attr_tex_ecc_unique_ded_pipe1_count_array); | 767 | dev_attr_tex_ecc_unique_ded_pipe1_count_array); |
768 | 768 | ||
769 | gr_gp10b_ecc_stat_remove(dev, | 769 | gr_gp10b_ecc_stat_remove(dev, |
770 | 1, | 770 | 1, |
771 | &g->ecc.gr.t18x.l2_sec_count, | 771 | &g->ecc.ltc.l2_sec_count, |
772 | dev_attr_l2_ecc_sec_count_array); | 772 | dev_attr_l2_ecc_sec_count_array); |
773 | gr_gp10b_ecc_stat_remove(dev, | 773 | gr_gp10b_ecc_stat_remove(dev, |
774 | 1, | 774 | 1, |
775 | &g->ecc.gr.t18x.l2_ded_count, | 775 | &g->ecc.ltc.l2_ded_count, |
776 | dev_attr_l2_ecc_ded_count_array); | 776 | dev_attr_l2_ecc_ded_count_array); |
777 | } | 777 | } |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c index efc9c595..fe85e113 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_gr_gp10b.c | |||
@@ -21,6 +21,7 @@ | |||
21 | #include "common/linux/vgpu/vgpu.h" | 21 | #include "common/linux/vgpu/vgpu.h" |
22 | #include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h" | 22 | #include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h" |
23 | 23 | ||
24 | #include "gp10b/gr_gp10b.h" | ||
24 | #include "vgpu_gr_gp10b.h" | 25 | #include "vgpu_gr_gp10b.h" |
25 | 26 | ||
26 | #include <nvgpu/hw/gp10b/hw_gr_gp10b.h> | 27 | #include <nvgpu/hw/gp10b/hw_gr_gp10b.h> |
@@ -45,10 +46,10 @@ void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | |||
45 | 46 | ||
46 | __nvgpu_vm_free_va(vm, gr_ctx->mem.gpu_va, gmmu_page_size_kernel); | 47 | __nvgpu_vm_free_va(vm, gr_ctx->mem.gpu_va, gmmu_page_size_kernel); |
47 | 48 | ||
48 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); | 49 | nvgpu_dma_unmap_free(vm, &gr_ctx->pagepool_ctxsw_buffer); |
49 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); | 50 | nvgpu_dma_unmap_free(vm, &gr_ctx->betacb_ctxsw_buffer); |
50 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); | 51 | nvgpu_dma_unmap_free(vm, &gr_ctx->spill_ctxsw_buffer); |
51 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); | 52 | nvgpu_dma_unmap_free(vm, &gr_ctx->preempt_ctxsw_buffer); |
52 | 53 | ||
53 | nvgpu_kfree(g, gr_ctx); | 54 | nvgpu_kfree(g, gr_ctx); |
54 | } | 55 | } |
@@ -122,11 +123,11 @@ int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | |||
122 | int err = 0; | 123 | int err = 0; |
123 | 124 | ||
124 | if (g->ops.gr.is_valid_gfx_class(g, class) && | 125 | if (g->ops.gr.is_valid_gfx_class(g, class) && |
125 | g->gr.t18x.ctx_vars.force_preemption_gfxp) | 126 | g->gr.ctx_vars.force_preemption_gfxp) |
126 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; | 127 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; |
127 | 128 | ||
128 | if (g->ops.gr.is_valid_compute_class(g, class) && | 129 | if (g->ops.gr.is_valid_compute_class(g, class) && |
129 | g->gr.t18x.ctx_vars.force_preemption_cilp) | 130 | g->gr.ctx_vars.force_preemption_cilp) |
130 | compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; | 131 | compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; |
131 | 132 | ||
132 | /* check for invalid combinations */ | 133 | /* check for invalid combinations */ |
@@ -157,54 +158,54 @@ int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | |||
157 | attrib_cb_size = ALIGN(attrib_cb_size, 128); | 158 | attrib_cb_size = ALIGN(attrib_cb_size, 128); |
158 | 159 | ||
159 | gk20a_dbg_info("gfxp context preempt size=%d", | 160 | gk20a_dbg_info("gfxp context preempt size=%d", |
160 | g->gr.t18x.ctx_vars.preempt_image_size); | 161 | g->gr.ctx_vars.preempt_image_size); |
161 | gk20a_dbg_info("gfxp context spill size=%d", spill_size); | 162 | gk20a_dbg_info("gfxp context spill size=%d", spill_size); |
162 | gk20a_dbg_info("gfxp context pagepool size=%d", pagepool_size); | 163 | gk20a_dbg_info("gfxp context pagepool size=%d", pagepool_size); |
163 | gk20a_dbg_info("gfxp context attrib cb size=%d", | 164 | gk20a_dbg_info("gfxp context attrib cb size=%d", |
164 | attrib_cb_size); | 165 | attrib_cb_size); |
165 | 166 | ||
166 | err = gr_gp10b_alloc_buffer(vm, | 167 | err = gr_gp10b_alloc_buffer(vm, |
167 | g->gr.t18x.ctx_vars.preempt_image_size, | 168 | g->gr.ctx_vars.preempt_image_size, |
168 | &gr_ctx->t18x.preempt_ctxsw_buffer); | 169 | &gr_ctx->preempt_ctxsw_buffer); |
169 | if (err) { | 170 | if (err) { |
170 | err = -ENOMEM; | 171 | err = -ENOMEM; |
171 | goto fail; | 172 | goto fail; |
172 | } | 173 | } |
173 | desc = &gr_ctx->t18x.preempt_ctxsw_buffer; | 174 | desc = &gr_ctx->preempt_ctxsw_buffer; |
174 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va; | 175 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va; |
175 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size; | 176 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size; |
176 | 177 | ||
177 | err = gr_gp10b_alloc_buffer(vm, | 178 | err = gr_gp10b_alloc_buffer(vm, |
178 | spill_size, | 179 | spill_size, |
179 | &gr_ctx->t18x.spill_ctxsw_buffer); | 180 | &gr_ctx->spill_ctxsw_buffer); |
180 | if (err) { | 181 | if (err) { |
181 | err = -ENOMEM; | 182 | err = -ENOMEM; |
182 | goto fail; | 183 | goto fail; |
183 | } | 184 | } |
184 | desc = &gr_ctx->t18x.spill_ctxsw_buffer; | 185 | desc = &gr_ctx->spill_ctxsw_buffer; |
185 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va; | 186 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va; |
186 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size; | 187 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size; |
187 | 188 | ||
188 | err = gr_gp10b_alloc_buffer(vm, | 189 | err = gr_gp10b_alloc_buffer(vm, |
189 | pagepool_size, | 190 | pagepool_size, |
190 | &gr_ctx->t18x.pagepool_ctxsw_buffer); | 191 | &gr_ctx->pagepool_ctxsw_buffer); |
191 | if (err) { | 192 | if (err) { |
192 | err = -ENOMEM; | 193 | err = -ENOMEM; |
193 | goto fail; | 194 | goto fail; |
194 | } | 195 | } |
195 | desc = &gr_ctx->t18x.pagepool_ctxsw_buffer; | 196 | desc = &gr_ctx->pagepool_ctxsw_buffer; |
196 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = | 197 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = |
197 | desc->gpu_va; | 198 | desc->gpu_va; |
198 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size; | 199 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size; |
199 | 200 | ||
200 | err = gr_gp10b_alloc_buffer(vm, | 201 | err = gr_gp10b_alloc_buffer(vm, |
201 | attrib_cb_size, | 202 | attrib_cb_size, |
202 | &gr_ctx->t18x.betacb_ctxsw_buffer); | 203 | &gr_ctx->betacb_ctxsw_buffer); |
203 | if (err) { | 204 | if (err) { |
204 | err = -ENOMEM; | 205 | err = -ENOMEM; |
205 | goto fail; | 206 | goto fail; |
206 | } | 207 | } |
207 | desc = &gr_ctx->t18x.betacb_ctxsw_buffer; | 208 | desc = &gr_ctx->betacb_ctxsw_buffer; |
208 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = | 209 | p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = |
209 | desc->gpu_va; | 210 | desc->gpu_va; |
210 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size; | 211 | p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size; |
@@ -323,9 +324,9 @@ int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) | |||
323 | if (err) | 324 | if (err) |
324 | return err; | 325 | return err; |
325 | 326 | ||
326 | g->gr.t18x.ctx_vars.preempt_image_size = | 327 | g->gr.ctx_vars.preempt_image_size = |
327 | priv->constants.preempt_ctx_size; | 328 | priv->constants.preempt_ctx_size; |
328 | if (!g->gr.t18x.ctx_vars.preempt_image_size) | 329 | if (!g->gr.ctx_vars.preempt_image_size) |
329 | return -EINVAL; | 330 | return -EINVAL; |
330 | 331 | ||
331 | return 0; | 332 | return 0; |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c index da4ca10c..6806b318 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -40,6 +40,7 @@ | |||
40 | #include "gp10b/ce_gp10b.h" | 40 | #include "gp10b/ce_gp10b.h" |
41 | #include "gp10b/fb_gp10b.h" | 41 | #include "gp10b/fb_gp10b.h" |
42 | #include "gp10b/pmu_gp10b.h" | 42 | #include "gp10b/pmu_gp10b.h" |
43 | #include "gp10b/gr_gp10b.h" | ||
43 | #include "gp10b/gr_ctx_gp10b.h" | 44 | #include "gp10b/gr_ctx_gp10b.h" |
44 | #include "gp10b/fifo_gp10b.h" | 45 | #include "gp10b/fifo_gp10b.h" |
45 | #include "gp10b/gp10b_gating_reglist.h" | 46 | #include "gp10b/gp10b_gating_reglist.h" |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c index 6b5a1b0d..a7491b20 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -48,6 +48,7 @@ | |||
48 | #include <gp10b/mm_gp10b.h> | 48 | #include <gp10b/mm_gp10b.h> |
49 | #include <gp10b/mc_gp10b.h> | 49 | #include <gp10b/mc_gp10b.h> |
50 | #include <gp10b/ce_gp10b.h> | 50 | #include <gp10b/ce_gp10b.h> |
51 | #include "gp10b/gr_gp10b.h" | ||
51 | #include <gp10b/fifo_gp10b.h> | 52 | #include <gp10b/fifo_gp10b.h> |
52 | #include <gp10b/therm_gp10b.h> | 53 | #include <gp10b/therm_gp10b.h> |
53 | #include <gp10b/priv_ring_gp10b.h> | 54 | #include <gp10b/priv_ring_gp10b.h> |
diff --git a/drivers/gpu/nvgpu/ecc_t18x.h b/drivers/gpu/nvgpu/ecc_t18x.h deleted file mode 100644 index e1644fd1..00000000 --- a/drivers/gpu/nvgpu/ecc_t18x.h +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | /* | ||
2 | * NVIDIA T18x ECC | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | #ifndef _NVGPU_ECC_T18X_H_ | ||
25 | #define _NVGPU_ECC_T18X_H_ | ||
26 | |||
27 | #include "gp10b/ecc_gp10b.h" | ||
28 | |||
29 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h index f04ff56c..0d1ed5df 100644 --- a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h | |||
@@ -32,9 +32,6 @@ struct gk20a_ecc_stat { | |||
32 | #endif | 32 | #endif |
33 | }; | 33 | }; |
34 | 34 | ||
35 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
36 | #include "ecc_t18x.h" | ||
37 | #endif | ||
38 | #ifdef CONFIG_TEGRA_19x_GPU | 35 | #ifdef CONFIG_TEGRA_19x_GPU |
39 | #include "ecc_t19x.h" | 36 | #include "ecc_t19x.h" |
40 | #endif | 37 | #endif |
@@ -42,15 +39,30 @@ struct gk20a_ecc_stat { | |||
42 | struct ecc_gk20a { | 39 | struct ecc_gk20a { |
43 | /* Stats per engine */ | 40 | /* Stats per engine */ |
44 | struct { | 41 | struct { |
45 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | 42 | struct gk20a_ecc_stat sm_lrf_single_err_count; |
46 | struct ecc_gr_t18x t18x; | 43 | struct gk20a_ecc_stat sm_lrf_double_err_count; |
47 | #endif | 44 | |
45 | struct gk20a_ecc_stat sm_shm_sec_count; | ||
46 | struct gk20a_ecc_stat sm_shm_sed_count; | ||
47 | struct gk20a_ecc_stat sm_shm_ded_count; | ||
48 | |||
49 | struct gk20a_ecc_stat tex_total_sec_pipe0_count; | ||
50 | struct gk20a_ecc_stat tex_total_ded_pipe0_count; | ||
51 | struct gk20a_ecc_stat tex_unique_sec_pipe0_count; | ||
52 | struct gk20a_ecc_stat tex_unique_ded_pipe0_count; | ||
53 | struct gk20a_ecc_stat tex_total_sec_pipe1_count; | ||
54 | struct gk20a_ecc_stat tex_total_ded_pipe1_count; | ||
55 | struct gk20a_ecc_stat tex_unique_sec_pipe1_count; | ||
56 | struct gk20a_ecc_stat tex_unique_ded_pipe1_count; | ||
57 | |||
48 | #ifdef CONFIG_TEGRA_19x_GPU | 58 | #ifdef CONFIG_TEGRA_19x_GPU |
49 | struct ecc_gr_t19x t19x; | 59 | struct ecc_gr_t19x t19x; |
50 | #endif | 60 | #endif |
51 | } gr; | 61 | } gr; |
52 | 62 | ||
53 | struct { | 63 | struct { |
64 | struct gk20a_ecc_stat l2_sec_count; | ||
65 | struct gk20a_ecc_stat l2_ded_count; | ||
54 | #ifdef CONFIG_TEGRA_19x_GPU | 66 | #ifdef CONFIG_TEGRA_19x_GPU |
55 | struct ecc_ltc_t19x t19x; | 67 | struct ecc_ltc_t19x t19x; |
56 | #endif | 68 | #endif |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 5bdd81ac..c029e9e0 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -46,9 +46,7 @@ | |||
46 | #include "mc_gk20a.h" | 46 | #include "mc_gk20a.h" |
47 | #include "hal.h" | 47 | #include "hal.h" |
48 | #include "bus_gk20a.h" | 48 | #include "bus_gk20a.h" |
49 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
50 | #include "pstate/pstate.h" | 49 | #include "pstate/pstate.h" |
51 | #endif | ||
52 | 50 | ||
53 | #ifdef CONFIG_TEGRA_19x_GPU | 51 | #ifdef CONFIG_TEGRA_19x_GPU |
54 | #include "nvgpu_gpuid_t19x.h" | 52 | #include "nvgpu_gpuid_t19x.h" |
@@ -112,10 +110,9 @@ int gk20a_prepare_poweroff(struct gk20a *g) | |||
112 | if (g->ops.clk.suspend_clk_support) | 110 | if (g->ops.clk.suspend_clk_support) |
113 | ret |= g->ops.clk.suspend_clk_support(g); | 111 | ret |= g->ops.clk.suspend_clk_support(g); |
114 | 112 | ||
115 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
116 | if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) | 113 | if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) |
117 | gk20a_deinit_pstate_support(g); | 114 | gk20a_deinit_pstate_support(g); |
118 | #endif | 115 | |
119 | g->power_on = false; | 116 | g->power_on = false; |
120 | 117 | ||
121 | return ret; | 118 | return ret; |
@@ -240,7 +237,6 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
240 | } | 237 | } |
241 | } | 238 | } |
242 | 239 | ||
243 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
244 | if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) { | 240 | if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) { |
245 | err = gk20a_init_pstate_support(g); | 241 | err = gk20a_init_pstate_support(g); |
246 | if (err) { | 242 | if (err) { |
@@ -248,7 +244,6 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
248 | goto done; | 244 | goto done; |
249 | } | 245 | } |
250 | } | 246 | } |
251 | #endif | ||
252 | 247 | ||
253 | if (g->ops.pmu.is_pmu_supported(g)) { | 248 | if (g->ops.pmu.is_pmu_supported(g)) { |
254 | err = nvgpu_init_pmu_support(g); | 249 | err = nvgpu_init_pmu_support(g); |
@@ -264,7 +259,6 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
264 | goto done; | 259 | goto done; |
265 | } | 260 | } |
266 | 261 | ||
267 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
268 | if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) { | 262 | if (nvgpu_is_enabled(g, NVGPU_PMU_PSTATE)) { |
269 | err = gk20a_init_pstate_pmu_support(g); | 263 | err = gk20a_init_pstate_pmu_support(g); |
270 | if (err) { | 264 | if (err) { |
@@ -278,7 +272,6 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
278 | nvgpu_err(g, "failed to init clk arb"); | 272 | nvgpu_err(g, "failed to init clk arb"); |
279 | goto done; | 273 | goto done; |
280 | } | 274 | } |
281 | #endif | ||
282 | 275 | ||
283 | err = gk20a_init_therm_support(g); | 276 | err = gk20a_init_therm_support(g); |
284 | if (err) { | 277 | if (err) { |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index fef9f498..8d8bfbec 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -72,12 +72,10 @@ struct nvgpu_ctxsw_trace_filter; | |||
72 | #include "pmu_gk20a.h" | 72 | #include "pmu_gk20a.h" |
73 | #include "priv_ring_gk20a.h" | 73 | #include "priv_ring_gk20a.h" |
74 | #include "therm_gk20a.h" | 74 | #include "therm_gk20a.h" |
75 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
76 | #include "clk/clk.h" | 75 | #include "clk/clk.h" |
77 | #include "perf/perf.h" | 76 | #include "perf/perf.h" |
78 | #include "pmgr/pmgr.h" | 77 | #include "pmgr/pmgr.h" |
79 | #include "therm/thrm.h" | 78 | #include "therm/thrm.h" |
80 | #endif | ||
81 | #include "ecc_gk20a.h" | 79 | #include "ecc_gk20a.h" |
82 | 80 | ||
83 | /* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds. | 81 | /* PTIMER_REF_FREQ_HZ corresponds to a period of 32 nanoseconds. |
@@ -1128,12 +1126,10 @@ struct gk20a { | |||
1128 | struct nvgpu_pmu pmu; | 1126 | struct nvgpu_pmu pmu; |
1129 | struct acr_desc acr; | 1127 | struct acr_desc acr; |
1130 | struct ecc_gk20a ecc; | 1128 | struct ecc_gk20a ecc; |
1131 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
1132 | struct clk_pmupstate clk_pmu; | 1129 | struct clk_pmupstate clk_pmu; |
1133 | struct perf_pmupstate perf_pmu; | 1130 | struct perf_pmupstate perf_pmu; |
1134 | struct pmgr_pmupstate pmgr_pmu; | 1131 | struct pmgr_pmupstate pmgr_pmu; |
1135 | struct therm_pmupstate therm_pmu; | 1132 | struct therm_pmupstate therm_pmu; |
1136 | #endif | ||
1137 | 1133 | ||
1138 | #ifdef CONFIG_DEBUG_FS | 1134 | #ifdef CONFIG_DEBUG_FS |
1139 | struct railgate_stats pstats; | 1135 | struct railgate_stats pstats; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index f44e96a7..0df88988 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -24,9 +24,6 @@ | |||
24 | #ifndef GR_GK20A_H | 24 | #ifndef GR_GK20A_H |
25 | #define GR_GK20A_H | 25 | #define GR_GK20A_H |
26 | 26 | ||
27 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
28 | #include "gr_t18x.h" | ||
29 | #endif | ||
30 | #ifdef CONFIG_TEGRA_19x_GPU | 27 | #ifdef CONFIG_TEGRA_19x_GPU |
31 | #include "gr_t19x.h" | 28 | #include "gr_t19x.h" |
32 | #endif | 29 | #endif |
@@ -316,6 +313,11 @@ struct gr_gk20a { | |||
316 | } ctxsw_regs; | 313 | } ctxsw_regs; |
317 | int regs_base_index; | 314 | int regs_base_index; |
318 | bool valid; | 315 | bool valid; |
316 | |||
317 | u32 preempt_image_size; | ||
318 | bool force_preemption_gfxp; | ||
319 | bool force_preemption_cilp; | ||
320 | bool dump_ctxsw_stats_on_channel_close; | ||
319 | } ctx_vars; | 321 | } ctx_vars; |
320 | 322 | ||
321 | struct nvgpu_mutex ctx_mutex; /* protect golden ctx init */ | 323 | struct nvgpu_mutex ctx_mutex; /* protect golden ctx init */ |
@@ -409,9 +411,11 @@ struct gr_gk20a { | |||
409 | bool sw_ready; | 411 | bool sw_ready; |
410 | bool skip_ucode_init; | 412 | bool skip_ucode_init; |
411 | 413 | ||
412 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | 414 | struct nvgpu_preemption_modes_rec preemption_mode_rec; |
413 | struct gr_t18x t18x; | 415 | |
414 | #endif | 416 | u32 fecs_feature_override_ecc_val; |
417 | |||
418 | int cilp_preempt_pending_chid; | ||
415 | 419 | ||
416 | u32 fbp_en_mask; | 420 | u32 fbp_en_mask; |
417 | u32 *fbp_rop_l2_en_mask; | 421 | u32 *fbp_rop_l2_en_mask; |
@@ -433,9 +437,15 @@ struct gr_ctx_desc { | |||
433 | u32 graphics_preempt_mode; | 437 | u32 graphics_preempt_mode; |
434 | u32 compute_preempt_mode; | 438 | u32 compute_preempt_mode; |
435 | bool boosted_ctx; | 439 | bool boosted_ctx; |
436 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | 440 | |
437 | struct gr_ctx_desc_t18x t18x; | 441 | struct nvgpu_mem preempt_ctxsw_buffer; |
438 | #endif | 442 | struct nvgpu_mem spill_ctxsw_buffer; |
443 | struct nvgpu_mem betacb_ctxsw_buffer; | ||
444 | struct nvgpu_mem pagepool_ctxsw_buffer; | ||
445 | u32 ctx_id; | ||
446 | bool ctx_id_valid; | ||
447 | bool cilp_preempt_pending; | ||
448 | |||
439 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION | 449 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION |
440 | u64 virt_ctx; | 450 | u64 virt_ctx; |
441 | #endif | 451 | #endif |
diff --git a/drivers/gpu/nvgpu/gk20a/hal.c b/drivers/gpu/nvgpu/gk20a/hal.c index 13e6f374..d24d4bc5 100644 --- a/drivers/gpu/nvgpu/gk20a/hal.c +++ b/drivers/gpu/nvgpu/gk20a/hal.c | |||
@@ -44,7 +44,6 @@ int gpu_init_hal(struct gk20a *g) | |||
44 | if (gm20b_init_hal(g)) | 44 | if (gm20b_init_hal(g)) |
45 | return -ENODEV; | 45 | return -ENODEV; |
46 | break; | 46 | break; |
47 | #if defined(CONFIG_ARCH_TEGRA_18x_SOC) | ||
48 | case NVGPU_GPUID_GP10B: | 47 | case NVGPU_GPUID_GP10B: |
49 | if (gp10b_init_hal(g)) | 48 | if (gp10b_init_hal(g)) |
50 | return -ENODEV; | 49 | return -ENODEV; |
@@ -54,7 +53,6 @@ int gpu_init_hal(struct gk20a *g) | |||
54 | if (gp106_init_hal(g)) | 53 | if (gp106_init_hal(g)) |
55 | return -ENODEV; | 54 | return -ENODEV; |
56 | break; | 55 | break; |
57 | #endif | ||
58 | #ifdef CONFIG_TEGRA_19x_GPU | 56 | #ifdef CONFIG_TEGRA_19x_GPU |
59 | case TEGRA_19x_GPUID: | 57 | case TEGRA_19x_GPUID: |
60 | if (TEGRA_19x_GPUID_HAL(g)) | 58 | if (TEGRA_19x_GPUID_HAL(g)) |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index d8478b2d..4e3eeb51 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -589,12 +589,10 @@ int nvgpu_pmu_handle_therm_event(struct nvgpu_pmu *pmu, | |||
589 | 589 | ||
590 | switch (msg->msg_type) { | 590 | switch (msg->msg_type) { |
591 | case NV_PMU_THERM_MSG_ID_EVENT_HW_SLOWDOWN_NOTIFICATION: | 591 | case NV_PMU_THERM_MSG_ID_EVENT_HW_SLOWDOWN_NOTIFICATION: |
592 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
593 | if (msg->hw_slct_msg.mask == BIT(NV_PMU_THERM_EVENT_THERMAL_1)) | 592 | if (msg->hw_slct_msg.mask == BIT(NV_PMU_THERM_EVENT_THERMAL_1)) |
594 | nvgpu_clk_arb_schedule_alarm(gk20a_from_pmu(pmu), | 593 | nvgpu_clk_arb_schedule_alarm(gk20a_from_pmu(pmu), |
595 | (0x1UL << NVGPU_GPU_EVENT_ALARM_THERMAL_ABOVE_THRESHOLD)); | 594 | (0x1UL << NVGPU_GPU_EVENT_ALARM_THERMAL_ABOVE_THRESHOLD)); |
596 | else | 595 | else |
597 | #endif | ||
598 | gk20a_dbg_pmu("Unwanted/Unregistered thermal event received %d", | 596 | gk20a_dbg_pmu("Unwanted/Unregistered thermal event received %d", |
599 | msg->hw_slct_msg.mask); | 597 | msg->hw_slct_msg.mask); |
600 | break; | 598 | break; |
diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c index fea337e7..bed08fed 100644 --- a/drivers/gpu/nvgpu/gp106/gr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c | |||
@@ -140,11 +140,11 @@ int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g, | |||
140 | { | 140 | { |
141 | int err = 0; | 141 | int err = 0; |
142 | 142 | ||
143 | if (class == PASCAL_B && g->gr.t18x.ctx_vars.force_preemption_gfxp) | 143 | if (class == PASCAL_B && g->gr.ctx_vars.force_preemption_gfxp) |
144 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; | 144 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; |
145 | 145 | ||
146 | if (class == PASCAL_COMPUTE_B && | 146 | if (class == PASCAL_COMPUTE_B && |
147 | g->gr.t18x.ctx_vars.force_preemption_cilp) | 147 | g->gr.ctx_vars.force_preemption_cilp) |
148 | compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; | 148 | compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; |
149 | 149 | ||
150 | /* check for invalid combinations */ | 150 | /* check for invalid combinations */ |
@@ -178,8 +178,8 @@ int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g, | |||
178 | attrib_cb_size); | 178 | attrib_cb_size); |
179 | 179 | ||
180 | err = gr_gp10b_alloc_buffer(vm, | 180 | err = gr_gp10b_alloc_buffer(vm, |
181 | g->gr.t18x.ctx_vars.preempt_image_size, | 181 | g->gr.ctx_vars.preempt_image_size, |
182 | &gr_ctx->t18x.preempt_ctxsw_buffer); | 182 | &gr_ctx->preempt_ctxsw_buffer); |
183 | if (err) { | 183 | if (err) { |
184 | nvgpu_err(g, "cannot allocate preempt buffer"); | 184 | nvgpu_err(g, "cannot allocate preempt buffer"); |
185 | goto fail; | 185 | goto fail; |
@@ -187,7 +187,7 @@ int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g, | |||
187 | 187 | ||
188 | err = gr_gp10b_alloc_buffer(vm, | 188 | err = gr_gp10b_alloc_buffer(vm, |
189 | spill_size, | 189 | spill_size, |
190 | &gr_ctx->t18x.spill_ctxsw_buffer); | 190 | &gr_ctx->spill_ctxsw_buffer); |
191 | if (err) { | 191 | if (err) { |
192 | nvgpu_err(g, "cannot allocate spill buffer"); | 192 | nvgpu_err(g, "cannot allocate spill buffer"); |
193 | goto fail_free_preempt; | 193 | goto fail_free_preempt; |
@@ -195,7 +195,7 @@ int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g, | |||
195 | 195 | ||
196 | err = gr_gp10b_alloc_buffer(vm, | 196 | err = gr_gp10b_alloc_buffer(vm, |
197 | attrib_cb_size, | 197 | attrib_cb_size, |
198 | &gr_ctx->t18x.betacb_ctxsw_buffer); | 198 | &gr_ctx->betacb_ctxsw_buffer); |
199 | if (err) { | 199 | if (err) { |
200 | nvgpu_err(g, "cannot allocate beta buffer"); | 200 | nvgpu_err(g, "cannot allocate beta buffer"); |
201 | goto fail_free_spill; | 201 | goto fail_free_spill; |
@@ -203,7 +203,7 @@ int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g, | |||
203 | 203 | ||
204 | err = gr_gp10b_alloc_buffer(vm, | 204 | err = gr_gp10b_alloc_buffer(vm, |
205 | pagepool_size, | 205 | pagepool_size, |
206 | &gr_ctx->t18x.pagepool_ctxsw_buffer); | 206 | &gr_ctx->pagepool_ctxsw_buffer); |
207 | if (err) { | 207 | if (err) { |
208 | nvgpu_err(g, "cannot allocate page pool"); | 208 | nvgpu_err(g, "cannot allocate page pool"); |
209 | goto fail_free_betacb; | 209 | goto fail_free_betacb; |
@@ -236,11 +236,11 @@ int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g, | |||
236 | return 0; | 236 | return 0; |
237 | 237 | ||
238 | fail_free_betacb: | 238 | fail_free_betacb: |
239 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); | 239 | nvgpu_dma_unmap_free(vm, &gr_ctx->betacb_ctxsw_buffer); |
240 | fail_free_spill: | 240 | fail_free_spill: |
241 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); | 241 | nvgpu_dma_unmap_free(vm, &gr_ctx->spill_ctxsw_buffer); |
242 | fail_free_preempt: | 242 | fail_free_preempt: |
243 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); | 243 | nvgpu_dma_unmap_free(vm, &gr_ctx->preempt_ctxsw_buffer); |
244 | fail: | 244 | fail: |
245 | return err; | 245 | return err; |
246 | } | 246 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h b/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h deleted file mode 100644 index a4a6e35b..00000000 --- a/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h +++ /dev/null | |||
@@ -1,50 +0,0 @@ | |||
1 | /* | ||
2 | * GP10B ECC | ||
3 | * | ||
4 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef _NVGPU_ECC_GP10B_H_ | ||
26 | #define _NVGPU_ECC_GP10B_H_ | ||
27 | |||
28 | struct gk20a_ecc_stat; | ||
29 | |||
30 | struct ecc_gr_t18x { | ||
31 | struct gk20a_ecc_stat sm_lrf_single_err_count; | ||
32 | struct gk20a_ecc_stat sm_lrf_double_err_count; | ||
33 | |||
34 | struct gk20a_ecc_stat sm_shm_sec_count; | ||
35 | struct gk20a_ecc_stat sm_shm_sed_count; | ||
36 | struct gk20a_ecc_stat sm_shm_ded_count; | ||
37 | |||
38 | struct gk20a_ecc_stat tex_total_sec_pipe0_count; | ||
39 | struct gk20a_ecc_stat tex_total_ded_pipe0_count; | ||
40 | struct gk20a_ecc_stat tex_unique_sec_pipe0_count; | ||
41 | struct gk20a_ecc_stat tex_unique_ded_pipe0_count; | ||
42 | struct gk20a_ecc_stat tex_total_sec_pipe1_count; | ||
43 | struct gk20a_ecc_stat tex_total_ded_pipe1_count; | ||
44 | struct gk20a_ecc_stat tex_unique_sec_pipe1_count; | ||
45 | struct gk20a_ecc_stat tex_unique_ded_pipe1_count; | ||
46 | |||
47 | struct gk20a_ecc_stat l2_sec_count; | ||
48 | struct gk20a_ecc_stat l2_ded_count; | ||
49 | }; | ||
50 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 6ff1522b..f0b77ebd 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -180,7 +180,7 @@ int gr_gp10b_handle_sm_exception(struct gk20a *g, | |||
180 | lrf_ecc_ded_status, | 180 | lrf_ecc_ded_status, |
181 | &lrf_single_count_delta, | 181 | &lrf_single_count_delta, |
182 | lrf_double_count_delta); | 182 | lrf_double_count_delta); |
183 | g->ecc.gr.t18x.sm_lrf_single_err_count.counters[tpc] += | 183 | g->ecc.gr.sm_lrf_single_err_count.counters[tpc] += |
184 | lrf_single_count_delta; | 184 | lrf_single_count_delta; |
185 | } | 185 | } |
186 | if (lrf_ecc_ded_status) { | 186 | if (lrf_ecc_ded_status) { |
@@ -192,7 +192,7 @@ int gr_gp10b_handle_sm_exception(struct gk20a *g, | |||
192 | lrf_ecc_ded_status, | 192 | lrf_ecc_ded_status, |
193 | &lrf_double_count_delta, | 193 | &lrf_double_count_delta, |
194 | lrf_single_count_delta); | 194 | lrf_single_count_delta); |
195 | g->ecc.gr.t18x.sm_lrf_double_err_count.counters[tpc] += | 195 | g->ecc.gr.sm_lrf_double_err_count.counters[tpc] += |
196 | lrf_double_count_delta; | 196 | lrf_double_count_delta; |
197 | } | 197 | } |
198 | gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, | 198 | gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, |
@@ -217,9 +217,9 @@ int gr_gp10b_handle_sm_exception(struct gk20a *g, | |||
217 | ecc_stats_reg_val = | 217 | ecc_stats_reg_val = |
218 | gk20a_readl(g, | 218 | gk20a_readl(g, |
219 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); | 219 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); |
220 | g->ecc.gr.t18x.sm_shm_sec_count.counters[tpc] += | 220 | g->ecc.gr.sm_shm_sec_count.counters[tpc] += |
221 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val); | 221 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val); |
222 | g->ecc.gr.t18x.sm_shm_sed_count.counters[tpc] += | 222 | g->ecc.gr.sm_shm_sed_count.counters[tpc] += |
223 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val); | 223 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val); |
224 | ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() | | 224 | ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() | |
225 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m()); | 225 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m()); |
@@ -239,7 +239,7 @@ int gr_gp10b_handle_sm_exception(struct gk20a *g, | |||
239 | ecc_stats_reg_val = | 239 | ecc_stats_reg_val = |
240 | gk20a_readl(g, | 240 | gk20a_readl(g, |
241 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); | 241 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); |
242 | g->ecc.gr.t18x.sm_shm_ded_count.counters[tpc] += | 242 | g->ecc.gr.sm_shm_ded_count.counters[tpc] += |
243 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val); | 243 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val); |
244 | ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m()); | 244 | ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m()); |
245 | gk20a_writel(g, | 245 | gk20a_writel(g, |
@@ -280,7 +280,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
280 | 280 | ||
281 | ecc_stats_reg_val = gk20a_readl(g, | 281 | ecc_stats_reg_val = gk20a_readl(g, |
282 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | 282 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); |
283 | g->ecc.gr.t18x.tex_total_sec_pipe0_count.counters[tpc] += | 283 | g->ecc.gr.tex_total_sec_pipe0_count.counters[tpc] += |
284 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); | 284 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); |
285 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); | 285 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); |
286 | gk20a_writel(g, | 286 | gk20a_writel(g, |
@@ -289,7 +289,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
289 | 289 | ||
290 | ecc_stats_reg_val = gk20a_readl(g, | 290 | ecc_stats_reg_val = gk20a_readl(g, |
291 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | 291 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); |
292 | g->ecc.gr.t18x.tex_unique_sec_pipe0_count.counters[tpc] += | 292 | g->ecc.gr.tex_unique_sec_pipe0_count.counters[tpc] += |
293 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); | 293 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); |
294 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); | 294 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); |
295 | gk20a_writel(g, | 295 | gk20a_writel(g, |
@@ -304,7 +304,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
304 | 304 | ||
305 | ecc_stats_reg_val = gk20a_readl(g, | 305 | ecc_stats_reg_val = gk20a_readl(g, |
306 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | 306 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); |
307 | g->ecc.gr.t18x.tex_total_sec_pipe1_count.counters[tpc] += | 307 | g->ecc.gr.tex_total_sec_pipe1_count.counters[tpc] += |
308 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); | 308 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); |
309 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); | 309 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); |
310 | gk20a_writel(g, | 310 | gk20a_writel(g, |
@@ -313,7 +313,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
313 | 313 | ||
314 | ecc_stats_reg_val = gk20a_readl(g, | 314 | ecc_stats_reg_val = gk20a_readl(g, |
315 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | 315 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); |
316 | g->ecc.gr.t18x.tex_unique_sec_pipe1_count.counters[tpc] += | 316 | g->ecc.gr.tex_unique_sec_pipe1_count.counters[tpc] += |
317 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); | 317 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); |
318 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); | 318 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); |
319 | gk20a_writel(g, | 319 | gk20a_writel(g, |
@@ -336,7 +336,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
336 | 336 | ||
337 | ecc_stats_reg_val = gk20a_readl(g, | 337 | ecc_stats_reg_val = gk20a_readl(g, |
338 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | 338 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); |
339 | g->ecc.gr.t18x.tex_total_ded_pipe0_count.counters[tpc] += | 339 | g->ecc.gr.tex_total_ded_pipe0_count.counters[tpc] += |
340 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); | 340 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); |
341 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); | 341 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); |
342 | gk20a_writel(g, | 342 | gk20a_writel(g, |
@@ -345,7 +345,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
345 | 345 | ||
346 | ecc_stats_reg_val = gk20a_readl(g, | 346 | ecc_stats_reg_val = gk20a_readl(g, |
347 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | 347 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); |
348 | g->ecc.gr.t18x.tex_unique_ded_pipe0_count.counters[tpc] += | 348 | g->ecc.gr.tex_unique_ded_pipe0_count.counters[tpc] += |
349 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); | 349 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); |
350 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); | 350 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); |
351 | gk20a_writel(g, | 351 | gk20a_writel(g, |
@@ -360,7 +360,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
360 | 360 | ||
361 | ecc_stats_reg_val = gk20a_readl(g, | 361 | ecc_stats_reg_val = gk20a_readl(g, |
362 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | 362 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); |
363 | g->ecc.gr.t18x.tex_total_ded_pipe1_count.counters[tpc] += | 363 | g->ecc.gr.tex_total_ded_pipe1_count.counters[tpc] += |
364 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); | 364 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); |
365 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); | 365 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); |
366 | gk20a_writel(g, | 366 | gk20a_writel(g, |
@@ -369,7 +369,7 @@ int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
369 | 369 | ||
370 | ecc_stats_reg_val = gk20a_readl(g, | 370 | ecc_stats_reg_val = gk20a_readl(g, |
371 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | 371 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); |
372 | g->ecc.gr.t18x.tex_unique_ded_pipe1_count.counters[tpc] += | 372 | g->ecc.gr.tex_unique_ded_pipe1_count.counters[tpc] += |
373 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); | 373 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); |
374 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); | 374 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); |
375 | gk20a_writel(g, | 375 | gk20a_writel(g, |
@@ -881,10 +881,10 @@ int gr_gp10b_init_ctx_state(struct gk20a *g) | |||
881 | if (err) | 881 | if (err) |
882 | return err; | 882 | return err; |
883 | 883 | ||
884 | if (!g->gr.t18x.ctx_vars.preempt_image_size) { | 884 | if (!g->gr.ctx_vars.preempt_image_size) { |
885 | op.method.addr = | 885 | op.method.addr = |
886 | gr_fecs_method_push_adr_discover_preemption_image_size_v(); | 886 | gr_fecs_method_push_adr_discover_preemption_image_size_v(); |
887 | op.mailbox.ret = &g->gr.t18x.ctx_vars.preempt_image_size; | 887 | op.mailbox.ret = &g->gr.ctx_vars.preempt_image_size; |
888 | err = gr_gk20a_submit_fecs_method_op(g, op, false); | 888 | err = gr_gk20a_submit_fecs_method_op(g, op, false); |
889 | if (err) { | 889 | if (err) { |
890 | nvgpu_err(g, "query preempt image size failed"); | 890 | nvgpu_err(g, "query preempt image size failed"); |
@@ -893,7 +893,7 @@ int gr_gp10b_init_ctx_state(struct gk20a *g) | |||
893 | } | 893 | } |
894 | 894 | ||
895 | gk20a_dbg_info("preempt image size: %u", | 895 | gk20a_dbg_info("preempt image size: %u", |
896 | g->gr.t18x.ctx_vars.preempt_image_size); | 896 | g->gr.ctx_vars.preempt_image_size); |
897 | 897 | ||
898 | gk20a_dbg_fn("done"); | 898 | gk20a_dbg_fn("done"); |
899 | 899 | ||
@@ -940,11 +940,11 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | |||
940 | int err = 0; | 940 | int err = 0; |
941 | 941 | ||
942 | if (g->ops.gr.is_valid_gfx_class(g, class) && | 942 | if (g->ops.gr.is_valid_gfx_class(g, class) && |
943 | g->gr.t18x.ctx_vars.force_preemption_gfxp) | 943 | g->gr.ctx_vars.force_preemption_gfxp) |
944 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; | 944 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; |
945 | 945 | ||
946 | if (g->ops.gr.is_valid_compute_class(g, class) && | 946 | if (g->ops.gr.is_valid_compute_class(g, class) && |
947 | g->gr.t18x.ctx_vars.force_preemption_cilp) | 947 | g->gr.ctx_vars.force_preemption_cilp) |
948 | compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; | 948 | compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; |
949 | 949 | ||
950 | /* check for invalid combinations */ | 950 | /* check for invalid combinations */ |
@@ -987,8 +987,8 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | |||
987 | attrib_cb_size); | 987 | attrib_cb_size); |
988 | 988 | ||
989 | err = gr_gp10b_alloc_buffer(vm, | 989 | err = gr_gp10b_alloc_buffer(vm, |
990 | g->gr.t18x.ctx_vars.preempt_image_size, | 990 | g->gr.ctx_vars.preempt_image_size, |
991 | &gr_ctx->t18x.preempt_ctxsw_buffer); | 991 | &gr_ctx->preempt_ctxsw_buffer); |
992 | if (err) { | 992 | if (err) { |
993 | nvgpu_err(g, "cannot allocate preempt buffer"); | 993 | nvgpu_err(g, "cannot allocate preempt buffer"); |
994 | goto fail; | 994 | goto fail; |
@@ -996,7 +996,7 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | |||
996 | 996 | ||
997 | err = gr_gp10b_alloc_buffer(vm, | 997 | err = gr_gp10b_alloc_buffer(vm, |
998 | spill_size, | 998 | spill_size, |
999 | &gr_ctx->t18x.spill_ctxsw_buffer); | 999 | &gr_ctx->spill_ctxsw_buffer); |
1000 | if (err) { | 1000 | if (err) { |
1001 | nvgpu_err(g, "cannot allocate spill buffer"); | 1001 | nvgpu_err(g, "cannot allocate spill buffer"); |
1002 | goto fail_free_preempt; | 1002 | goto fail_free_preempt; |
@@ -1004,7 +1004,7 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | |||
1004 | 1004 | ||
1005 | err = gr_gp10b_alloc_buffer(vm, | 1005 | err = gr_gp10b_alloc_buffer(vm, |
1006 | attrib_cb_size, | 1006 | attrib_cb_size, |
1007 | &gr_ctx->t18x.betacb_ctxsw_buffer); | 1007 | &gr_ctx->betacb_ctxsw_buffer); |
1008 | if (err) { | 1008 | if (err) { |
1009 | nvgpu_err(g, "cannot allocate beta buffer"); | 1009 | nvgpu_err(g, "cannot allocate beta buffer"); |
1010 | goto fail_free_spill; | 1010 | goto fail_free_spill; |
@@ -1012,7 +1012,7 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | |||
1012 | 1012 | ||
1013 | err = gr_gp10b_alloc_buffer(vm, | 1013 | err = gr_gp10b_alloc_buffer(vm, |
1014 | pagepool_size, | 1014 | pagepool_size, |
1015 | &gr_ctx->t18x.pagepool_ctxsw_buffer); | 1015 | &gr_ctx->pagepool_ctxsw_buffer); |
1016 | if (err) { | 1016 | if (err) { |
1017 | nvgpu_err(g, "cannot allocate page pool"); | 1017 | nvgpu_err(g, "cannot allocate page pool"); |
1018 | goto fail_free_betacb; | 1018 | goto fail_free_betacb; |
@@ -1046,11 +1046,11 @@ int gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, | |||
1046 | return 0; | 1046 | return 0; |
1047 | 1047 | ||
1048 | fail_free_betacb: | 1048 | fail_free_betacb: |
1049 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); | 1049 | nvgpu_dma_unmap_free(vm, &gr_ctx->betacb_ctxsw_buffer); |
1050 | fail_free_spill: | 1050 | fail_free_spill: |
1051 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); | 1051 | nvgpu_dma_unmap_free(vm, &gr_ctx->spill_ctxsw_buffer); |
1052 | fail_free_preempt: | 1052 | fail_free_preempt: |
1053 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); | 1053 | nvgpu_dma_unmap_free(vm, &gr_ctx->preempt_ctxsw_buffer); |
1054 | fail: | 1054 | fail: |
1055 | return err; | 1055 | return err; |
1056 | } | 1056 | } |
@@ -1070,7 +1070,7 @@ int gr_gp10b_alloc_gr_ctx(struct gk20a *g, | |||
1070 | if (err) | 1070 | if (err) |
1071 | return err; | 1071 | return err; |
1072 | 1072 | ||
1073 | (*gr_ctx)->t18x.ctx_id_valid = false; | 1073 | (*gr_ctx)->ctx_id_valid = false; |
1074 | 1074 | ||
1075 | if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_GFXP) | 1075 | if (flags & NVGPU_OBJ_CTX_FLAGS_SUPPORT_GFXP) |
1076 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; | 1076 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; |
@@ -1160,13 +1160,13 @@ void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | |||
1160 | if (!gr_ctx) | 1160 | if (!gr_ctx) |
1161 | return; | 1161 | return; |
1162 | 1162 | ||
1163 | if (g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close) | 1163 | if (g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close) |
1164 | dump_ctx_switch_stats(g, vm, gr_ctx); | 1164 | dump_ctx_switch_stats(g, vm, gr_ctx); |
1165 | 1165 | ||
1166 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); | 1166 | nvgpu_dma_unmap_free(vm, &gr_ctx->pagepool_ctxsw_buffer); |
1167 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); | 1167 | nvgpu_dma_unmap_free(vm, &gr_ctx->betacb_ctxsw_buffer); |
1168 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); | 1168 | nvgpu_dma_unmap_free(vm, &gr_ctx->spill_ctxsw_buffer); |
1169 | nvgpu_dma_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); | 1169 | nvgpu_dma_unmap_free(vm, &gr_ctx->preempt_ctxsw_buffer); |
1170 | gr_gk20a_free_gr_ctx(g, vm, gr_ctx); | 1170 | gr_gk20a_free_gr_ctx(g, vm, gr_ctx); |
1171 | gk20a_dbg_fn("done"); | 1171 | gk20a_dbg_fn("done"); |
1172 | } | 1172 | } |
@@ -1211,7 +1211,7 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1211 | cta_preempt_option); | 1211 | cta_preempt_option); |
1212 | } | 1212 | } |
1213 | 1213 | ||
1214 | if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va) { | 1214 | if (gr_ctx->preempt_ctxsw_buffer.gpu_va) { |
1215 | u32 addr; | 1215 | u32 addr; |
1216 | u32 size; | 1216 | u32 size; |
1217 | u32 cbes_reserve; | 1217 | u32 cbes_reserve; |
@@ -1219,10 +1219,10 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1219 | if (g->ops.gr.set_preemption_buffer_va) { | 1219 | if (g->ops.gr.set_preemption_buffer_va) { |
1220 | if (ctxheader->gpu_va) | 1220 | if (ctxheader->gpu_va) |
1221 | g->ops.gr.set_preemption_buffer_va(g, ctxheader, | 1221 | g->ops.gr.set_preemption_buffer_va(g, ctxheader, |
1222 | gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va); | 1222 | gr_ctx->preempt_ctxsw_buffer.gpu_va); |
1223 | else | 1223 | else |
1224 | g->ops.gr.set_preemption_buffer_va(g, mem, | 1224 | g->ops.gr.set_preemption_buffer_va(g, mem, |
1225 | gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va); | 1225 | gr_ctx->preempt_ctxsw_buffer.gpu_va); |
1226 | } | 1226 | } |
1227 | 1227 | ||
1228 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, true); | 1228 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, true); |
@@ -1231,30 +1231,30 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1231 | goto out; | 1231 | goto out; |
1232 | } | 1232 | } |
1233 | 1233 | ||
1234 | addr = (u64_lo32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) >> | 1234 | addr = (u64_lo32(gr_ctx->betacb_ctxsw_buffer.gpu_va) >> |
1235 | gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()) | | 1235 | gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()) | |
1236 | (u64_hi32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) << | 1236 | (u64_hi32(gr_ctx->betacb_ctxsw_buffer.gpu_va) << |
1237 | (32 - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v())); | 1237 | (32 - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v())); |
1238 | 1238 | ||
1239 | gk20a_dbg_info("attrib cb addr : 0x%016x", addr); | 1239 | gk20a_dbg_info("attrib cb addr : 0x%016x", addr); |
1240 | g->ops.gr.commit_global_attrib_cb(g, ch_ctx, addr, true); | 1240 | g->ops.gr.commit_global_attrib_cb(g, ch_ctx, addr, true); |
1241 | 1241 | ||
1242 | addr = (u64_lo32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) >> | 1242 | addr = (u64_lo32(gr_ctx->pagepool_ctxsw_buffer.gpu_va) >> |
1243 | gr_scc_pagepool_base_addr_39_8_align_bits_v()) | | 1243 | gr_scc_pagepool_base_addr_39_8_align_bits_v()) | |
1244 | (u64_hi32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) << | 1244 | (u64_hi32(gr_ctx->pagepool_ctxsw_buffer.gpu_va) << |
1245 | (32 - gr_scc_pagepool_base_addr_39_8_align_bits_v())); | 1245 | (32 - gr_scc_pagepool_base_addr_39_8_align_bits_v())); |
1246 | size = gr_ctx->t18x.pagepool_ctxsw_buffer.size; | 1246 | size = gr_ctx->pagepool_ctxsw_buffer.size; |
1247 | 1247 | ||
1248 | if (size == g->ops.gr.pagepool_default_size(g)) | 1248 | if (size == g->ops.gr.pagepool_default_size(g)) |
1249 | size = gr_scc_pagepool_total_pages_hwmax_v(); | 1249 | size = gr_scc_pagepool_total_pages_hwmax_v(); |
1250 | 1250 | ||
1251 | g->ops.gr.commit_global_pagepool(g, ch_ctx, addr, size, true); | 1251 | g->ops.gr.commit_global_pagepool(g, ch_ctx, addr, size, true); |
1252 | 1252 | ||
1253 | addr = (u64_lo32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) >> | 1253 | addr = (u64_lo32(gr_ctx->spill_ctxsw_buffer.gpu_va) >> |
1254 | gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) | | 1254 | gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) | |
1255 | (u64_hi32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) << | 1255 | (u64_hi32(gr_ctx->spill_ctxsw_buffer.gpu_va) << |
1256 | (32 - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v())); | 1256 | (32 - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v())); |
1257 | size = gr_ctx->t18x.spill_ctxsw_buffer.size / | 1257 | size = gr_ctx->spill_ctxsw_buffer.size / |
1258 | gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); | 1258 | gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); |
1259 | 1259 | ||
1260 | gr_gk20a_ctx_patch_write(g, ch_ctx, | 1260 | gr_gk20a_ctx_patch_write(g, ch_ctx, |
@@ -1489,8 +1489,8 @@ void gr_gp10b_commit_global_attrib_cb(struct gk20a *g, | |||
1489 | struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; | 1489 | struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; |
1490 | int attrBufferSize; | 1490 | int attrBufferSize; |
1491 | 1491 | ||
1492 | if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va) | 1492 | if (gr_ctx->preempt_ctxsw_buffer.gpu_va) |
1493 | attrBufferSize = gr_ctx->t18x.betacb_ctxsw_buffer.size; | 1493 | attrBufferSize = gr_ctx->betacb_ctxsw_buffer.size; |
1494 | else | 1494 | else |
1495 | attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g); | 1495 | attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g); |
1496 | 1496 | ||
@@ -1606,10 +1606,10 @@ int gr_gp10b_init_fs_state(struct gk20a *g) | |||
1606 | gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f()); | 1606 | gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f()); |
1607 | gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data); | 1607 | gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data); |
1608 | 1608 | ||
1609 | if (g->gr.t18x.fecs_feature_override_ecc_val != 0) { | 1609 | if (g->gr.fecs_feature_override_ecc_val != 0) { |
1610 | gk20a_writel(g, | 1610 | gk20a_writel(g, |
1611 | gr_fecs_feature_override_ecc_r(), | 1611 | gr_fecs_feature_override_ecc_r(), |
1612 | g->gr.t18x.fecs_feature_override_ecc_val); | 1612 | g->gr.fecs_feature_override_ecc_val); |
1613 | } | 1613 | } |
1614 | 1614 | ||
1615 | return gr_gm20b_init_fs_state(g); | 1615 | return gr_gm20b_init_fs_state(g); |
@@ -1718,7 +1718,7 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, | |||
1718 | if (!gr_ctx) | 1718 | if (!gr_ctx) |
1719 | return -EINVAL; | 1719 | return -EINVAL; |
1720 | 1720 | ||
1721 | if (gr_ctx->t18x.cilp_preempt_pending) { | 1721 | if (gr_ctx->cilp_preempt_pending) { |
1722 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | 1722 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
1723 | "CILP is already pending for chid %d", | 1723 | "CILP is already pending for chid %d", |
1724 | fault_ch->chid); | 1724 | fault_ch->chid); |
@@ -1726,24 +1726,24 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, | |||
1726 | } | 1726 | } |
1727 | 1727 | ||
1728 | /* get ctx_id from the ucode image */ | 1728 | /* get ctx_id from the ucode image */ |
1729 | if (!gr_ctx->t18x.ctx_id_valid) { | 1729 | if (!gr_ctx->ctx_id_valid) { |
1730 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | 1730 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
1731 | "CILP: looking up ctx id"); | 1731 | "CILP: looking up ctx id"); |
1732 | ret = gr_gk20a_get_ctx_id(g, fault_ch, &gr_ctx->t18x.ctx_id); | 1732 | ret = gr_gk20a_get_ctx_id(g, fault_ch, &gr_ctx->ctx_id); |
1733 | if (ret) { | 1733 | if (ret) { |
1734 | nvgpu_err(g, "CILP: error looking up ctx id!"); | 1734 | nvgpu_err(g, "CILP: error looking up ctx id!"); |
1735 | return ret; | 1735 | return ret; |
1736 | } | 1736 | } |
1737 | gr_ctx->t18x.ctx_id_valid = true; | 1737 | gr_ctx->ctx_id_valid = true; |
1738 | } | 1738 | } |
1739 | 1739 | ||
1740 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | 1740 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
1741 | "CILP: ctx id is 0x%x", gr_ctx->t18x.ctx_id); | 1741 | "CILP: ctx id is 0x%x", gr_ctx->ctx_id); |
1742 | 1742 | ||
1743 | /* send ucode method to set ctxsw interrupt */ | 1743 | /* send ucode method to set ctxsw interrupt */ |
1744 | ret = gr_gk20a_submit_fecs_sideband_method_op(g, | 1744 | ret = gr_gk20a_submit_fecs_sideband_method_op(g, |
1745 | (struct fecs_method_op_gk20a) { | 1745 | (struct fecs_method_op_gk20a) { |
1746 | .method.data = gr_ctx->t18x.ctx_id, | 1746 | .method.data = gr_ctx->ctx_id, |
1747 | .method.addr = | 1747 | .method.addr = |
1748 | gr_fecs_method_push_adr_configure_interrupt_completion_option_v(), | 1748 | gr_fecs_method_push_adr_configure_interrupt_completion_option_v(), |
1749 | .mailbox = { | 1749 | .mailbox = { |
@@ -1773,8 +1773,8 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, | |||
1773 | } | 1773 | } |
1774 | 1774 | ||
1775 | /* set cilp_preempt_pending = true and record the channel */ | 1775 | /* set cilp_preempt_pending = true and record the channel */ |
1776 | gr_ctx->t18x.cilp_preempt_pending = true; | 1776 | gr_ctx->cilp_preempt_pending = true; |
1777 | g->gr.t18x.cilp_preempt_pending_chid = fault_ch->chid; | 1777 | g->gr.cilp_preempt_pending_chid = fault_ch->chid; |
1778 | 1778 | ||
1779 | if (gk20a_is_channel_marked_as_tsg(fault_ch)) { | 1779 | if (gk20a_is_channel_marked_as_tsg(fault_ch)) { |
1780 | struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid]; | 1780 | struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid]; |
@@ -1801,15 +1801,15 @@ static int gr_gp10b_clear_cilp_preempt_pending(struct gk20a *g, | |||
1801 | 1801 | ||
1802 | /* The ucode is self-clearing, so all we need to do here is | 1802 | /* The ucode is self-clearing, so all we need to do here is |
1803 | to clear cilp_preempt_pending. */ | 1803 | to clear cilp_preempt_pending. */ |
1804 | if (!gr_ctx->t18x.cilp_preempt_pending) { | 1804 | if (!gr_ctx->cilp_preempt_pending) { |
1805 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | 1805 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
1806 | "CILP is already cleared for chid %d\n", | 1806 | "CILP is already cleared for chid %d\n", |
1807 | fault_ch->chid); | 1807 | fault_ch->chid); |
1808 | return 0; | 1808 | return 0; |
1809 | } | 1809 | } |
1810 | 1810 | ||
1811 | gr_ctx->t18x.cilp_preempt_pending = false; | 1811 | gr_ctx->cilp_preempt_pending = false; |
1812 | g->gr.t18x.cilp_preempt_pending_chid = -1; | 1812 | g->gr.cilp_preempt_pending_chid = -1; |
1813 | 1813 | ||
1814 | return 0; | 1814 | return 0; |
1815 | } | 1815 | } |
@@ -1925,7 +1925,7 @@ static int gr_gp10b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid) | |||
1925 | int chid; | 1925 | int chid; |
1926 | int ret = -EINVAL; | 1926 | int ret = -EINVAL; |
1927 | 1927 | ||
1928 | chid = g->gr.t18x.cilp_preempt_pending_chid; | 1928 | chid = g->gr.cilp_preempt_pending_chid; |
1929 | 1929 | ||
1930 | ch = gk20a_channel_get(gk20a_fifo_channel_from_chid(g, chid)); | 1930 | ch = gk20a_channel_get(gk20a_fifo_channel_from_chid(g, chid)); |
1931 | if (!ch) | 1931 | if (!ch) |
@@ -1933,7 +1933,7 @@ static int gr_gp10b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid) | |||
1933 | 1933 | ||
1934 | gr_ctx = ch->ch_ctx.gr_ctx; | 1934 | gr_ctx = ch->ch_ctx.gr_ctx; |
1935 | 1935 | ||
1936 | if (gr_ctx->t18x.cilp_preempt_pending) { | 1936 | if (gr_ctx->cilp_preempt_pending) { |
1937 | *__chid = chid; | 1937 | *__chid = chid; |
1938 | ret = 0; | 1938 | ret = 0; |
1939 | } | 1939 | } |
@@ -2121,7 +2121,7 @@ int gr_gp10b_suspend_contexts(struct gk20a *g, | |||
2121 | nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), | 2121 | nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), |
2122 | NVGPU_TIMER_CPU_TIMER); | 2122 | NVGPU_TIMER_CPU_TIMER); |
2123 | do { | 2123 | do { |
2124 | if (!gr_ctx->t18x.cilp_preempt_pending) | 2124 | if (!gr_ctx->cilp_preempt_pending) |
2125 | break; | 2125 | break; |
2126 | 2126 | ||
2127 | nvgpu_usleep_range(delay, delay * 2); | 2127 | nvgpu_usleep_range(delay, delay * 2); |
@@ -2129,7 +2129,7 @@ int gr_gp10b_suspend_contexts(struct gk20a *g, | |||
2129 | } while (!nvgpu_timeout_expired(&timeout)); | 2129 | } while (!nvgpu_timeout_expired(&timeout)); |
2130 | 2130 | ||
2131 | /* If cilp is still pending at this point, timeout */ | 2131 | /* If cilp is still pending at this point, timeout */ |
2132 | if (gr_ctx->t18x.cilp_preempt_pending) | 2132 | if (gr_ctx->cilp_preempt_pending) |
2133 | err = -ETIMEDOUT; | 2133 | err = -ETIMEDOUT; |
2134 | } | 2134 | } |
2135 | 2135 | ||
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index 45ac5305..55117022 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h | |||
@@ -145,27 +145,4 @@ int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch); | |||
145 | void gr_gp10b_init_czf_bypass(struct gk20a *g); | 145 | void gr_gp10b_init_czf_bypass(struct gk20a *g); |
146 | void gr_gp10b_init_ctxsw_hdr_data(struct gk20a *g, struct nvgpu_mem *mem); | 146 | void gr_gp10b_init_ctxsw_hdr_data(struct gk20a *g, struct nvgpu_mem *mem); |
147 | 147 | ||
148 | struct gr_t18x { | ||
149 | struct { | ||
150 | u32 preempt_image_size; | ||
151 | bool force_preemption_gfxp; | ||
152 | bool force_preemption_cilp; | ||
153 | bool dump_ctxsw_stats_on_channel_close; | ||
154 | } ctx_vars; | ||
155 | |||
156 | u32 fecs_feature_override_ecc_val; | ||
157 | |||
158 | int cilp_preempt_pending_chid; | ||
159 | }; | ||
160 | |||
161 | struct gr_ctx_desc_t18x { | ||
162 | struct nvgpu_mem preempt_ctxsw_buffer; | ||
163 | struct nvgpu_mem spill_ctxsw_buffer; | ||
164 | struct nvgpu_mem betacb_ctxsw_buffer; | ||
165 | struct nvgpu_mem pagepool_ctxsw_buffer; | ||
166 | u32 ctx_id; | ||
167 | bool ctx_id_valid; | ||
168 | bool cilp_preempt_pending; | ||
169 | }; | ||
170 | |||
171 | #endif | 148 | #endif |
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index 92a899b8..6e8a53c5 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | |||
@@ -155,7 +155,7 @@ void gp10b_ltc_isr(struct gk20a *g) | |||
155 | ecc_stats_reg_val = | 155 | ecc_stats_reg_val = |
156 | gk20a_readl(g, | 156 | gk20a_readl(g, |
157 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset); | 157 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset); |
158 | g->ecc.gr.t18x.l2_sec_count.counters[ltc] += | 158 | g->ecc.ltc.l2_sec_count.counters[ltc] += |
159 | ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val); | 159 | ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val); |
160 | ecc_stats_reg_val &= | 160 | ecc_stats_reg_val &= |
161 | ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m()); | 161 | ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m()); |
@@ -175,7 +175,7 @@ void gp10b_ltc_isr(struct gk20a *g) | |||
175 | ecc_stats_reg_val = | 175 | ecc_stats_reg_val = |
176 | gk20a_readl(g, | 176 | gk20a_readl(g, |
177 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset); | 177 | ltc_ltc0_lts0_dstg_ecc_report_r() + offset); |
178 | g->ecc.gr.t18x.l2_ded_count.counters[ltc] += | 178 | g->ecc.ltc.l2_ded_count.counters[ltc] += |
179 | ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val); | 179 | ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val); |
180 | ecc_stats_reg_val &= | 180 | ecc_stats_reg_val &= |
181 | ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m()); | 181 | ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m()); |
diff --git a/drivers/gpu/nvgpu/gr_t18x.h b/drivers/gpu/nvgpu/gr_t18x.h deleted file mode 100644 index 23ec54f2..00000000 --- a/drivers/gpu/nvgpu/gr_t18x.h +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | /* | ||
2 | * NVIDIA T18x GR | ||
3 | * | ||
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | #ifndef _NVGPU_GR_T18X_H_ | ||
25 | #define _NVGPU_GR_T18X_H_ | ||
26 | |||
27 | #include "gp10b/gr_gp10b.h" | ||
28 | |||
29 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 68ac8f51..9e43941d 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -280,7 +280,7 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
280 | lrf_corrected_err_count_delta += | 280 | lrf_corrected_err_count_delta += |
281 | (is_lrf_ecc_corrected_total_err_overflow << | 281 | (is_lrf_ecc_corrected_total_err_overflow << |
282 | gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s()); | 282 | gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s()); |
283 | g->ecc.gr.t18x.sm_lrf_single_err_count.counters[tpc] += | 283 | g->ecc.gr.sm_lrf_single_err_count.counters[tpc] += |
284 | lrf_corrected_err_count_delta; | 284 | lrf_corrected_err_count_delta; |
285 | gk20a_writel(g, | 285 | gk20a_writel(g, |
286 | gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r() + offset, | 286 | gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r() + offset, |
@@ -295,7 +295,7 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
295 | lrf_uncorrected_err_count_delta += | 295 | lrf_uncorrected_err_count_delta += |
296 | (is_lrf_ecc_uncorrected_total_err_overflow << | 296 | (is_lrf_ecc_uncorrected_total_err_overflow << |
297 | gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s()); | 297 | gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s()); |
298 | g->ecc.gr.t18x.sm_lrf_double_err_count.counters[tpc] += | 298 | g->ecc.gr.sm_lrf_double_err_count.counters[tpc] += |
299 | lrf_uncorrected_err_count_delta; | 299 | lrf_uncorrected_err_count_delta; |
300 | gk20a_writel(g, | 300 | gk20a_writel(g, |
301 | gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r() + offset, | 301 | gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r() + offset, |
@@ -1664,8 +1664,8 @@ void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, | |||
1664 | struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; | 1664 | struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; |
1665 | int attrBufferSize; | 1665 | int attrBufferSize; |
1666 | 1666 | ||
1667 | if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va) | 1667 | if (gr_ctx->preempt_ctxsw_buffer.gpu_va) |
1668 | attrBufferSize = gr_ctx->t18x.betacb_ctxsw_buffer.size; | 1668 | attrBufferSize = gr_ctx->betacb_ctxsw_buffer.size; |
1669 | else | 1669 | else |
1670 | attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g); | 1670 | attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g); |
1671 | 1671 | ||
@@ -2385,10 +2385,10 @@ int gr_gv11b_init_fs_state(struct gk20a *g) | |||
2385 | gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f()); | 2385 | gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f()); |
2386 | gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data); | 2386 | gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data); |
2387 | 2387 | ||
2388 | if (g->gr.t18x.fecs_feature_override_ecc_val != 0) { | 2388 | if (g->gr.fecs_feature_override_ecc_val != 0) { |
2389 | gk20a_writel(g, | 2389 | gk20a_writel(g, |
2390 | gr_fecs_feature_override_ecc_r(), | 2390 | gr_fecs_feature_override_ecc_r(), |
2391 | g->gr.t18x.fecs_feature_override_ecc_val); | 2391 | g->gr.fecs_feature_override_ecc_val); |
2392 | } | 2392 | } |
2393 | 2393 | ||
2394 | return gr_gm20b_init_fs_state(g); | 2394 | return gr_gm20b_init_fs_state(g); |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index b6ba231e..1941f239 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -46,6 +46,8 @@ struct zbc_query_params; | |||
46 | struct channel_ctx_gk20a; | 46 | struct channel_ctx_gk20a; |
47 | struct nvgpu_warpstate; | 47 | struct nvgpu_warpstate; |
48 | struct nvgpu_gr_sm_error_state; | 48 | struct nvgpu_gr_sm_error_state; |
49 | struct gr_gk20a_isr_data; | ||
50 | struct gk20a_debug_output; | ||
49 | 51 | ||
50 | enum { | 52 | enum { |
51 | VOLTA_CHANNEL_GPFIFO_A = 0xC36F, | 53 | VOLTA_CHANNEL_GPFIFO_A = 0xC36F, |
diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 95d82254..723e2e80 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | |||
@@ -81,13 +81,13 @@ static int gv11b_tegra_probe(struct device *dev) | |||
81 | platform->bypass_smmu = !device_is_iommuable(dev); | 81 | platform->bypass_smmu = !device_is_iommuable(dev); |
82 | platform->disable_bigpage = platform->bypass_smmu; | 82 | platform->disable_bigpage = platform->bypass_smmu; |
83 | 83 | ||
84 | platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close | 84 | platform->g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close |
85 | = false; | 85 | = false; |
86 | platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close | 86 | platform->g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close |
87 | = false; | 87 | = false; |
88 | 88 | ||
89 | platform->g->gr.t18x.ctx_vars.force_preemption_gfxp = false; | 89 | platform->g->gr.ctx_vars.force_preemption_gfxp = false; |
90 | platform->g->gr.t18x.ctx_vars.force_preemption_cilp = false; | 90 | platform->g->gr.ctx_vars.force_preemption_cilp = false; |
91 | 91 | ||
92 | gp10b_tegra_get_clocks(dev); | 92 | gp10b_tegra_get_clocks(dev); |
93 | nvgpu_linux_init_clk_support(platform->g); | 93 | nvgpu_linux_init_clk_support(platform->g); |