diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 38 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 132 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 23 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 17 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/tsg_gk20a.h | 1 |
10 files changed, 232 insertions, 21 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 9e023e16..697861e2 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -184,8 +184,7 @@ int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, | |||
184 | return 0; | 184 | return 0; |
185 | } | 185 | } |
186 | 186 | ||
187 | static int channel_gk20a_set_schedule_params(struct channel_gk20a *c, | 187 | static int channel_gk20a_set_schedule_params(struct channel_gk20a *c) |
188 | u32 timeslice_period) | ||
189 | { | 188 | { |
190 | void *inst_ptr; | 189 | void *inst_ptr; |
191 | int shift = 0, value = 0; | 190 | int shift = 0, value = 0; |
@@ -194,8 +193,8 @@ static int channel_gk20a_set_schedule_params(struct channel_gk20a *c, | |||
194 | if (!inst_ptr) | 193 | if (!inst_ptr) |
195 | return -ENOMEM; | 194 | return -ENOMEM; |
196 | 195 | ||
197 | gk20a_channel_get_timescale_from_timeslice(c->g, timeslice_period, | 196 | gk20a_channel_get_timescale_from_timeslice(c->g, |
198 | &value, &shift); | 197 | c->timeslice_us, &value, &shift); |
199 | 198 | ||
200 | /* disable channel */ | 199 | /* disable channel */ |
201 | c->g->ops.fifo.disable_channel(c); | 200 | c->g->ops.fifo.disable_channel(c); |
@@ -1162,6 +1161,7 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g) | |||
1162 | ch->obj_class = 0; | 1161 | ch->obj_class = 0; |
1163 | ch->clean_up.scheduled = false; | 1162 | ch->clean_up.scheduled = false; |
1164 | ch->interleave_level = NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW; | 1163 | ch->interleave_level = NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW; |
1164 | ch->timeslice_us = g->timeslice_low_priority_us; | ||
1165 | 1165 | ||
1166 | /* The channel is *not* runnable at this point. It still needs to have | 1166 | /* The channel is *not* runnable at this point. It still needs to have |
1167 | * an address space bound and allocate a gpfifo and grctx. */ | 1167 | * an address space bound and allocate a gpfifo and grctx. */ |
@@ -1207,6 +1207,8 @@ static int __gk20a_channel_open(struct gk20a *g, struct file *filp) | |||
1207 | return -ENOMEM; | 1207 | return -ENOMEM; |
1208 | } | 1208 | } |
1209 | 1209 | ||
1210 | trace_gk20a_channel_sched_defaults(GK20A_TP_ARGS_SCHED(ch)); | ||
1211 | |||
1210 | filp->private_data = ch; | 1212 | filp->private_data = ch; |
1211 | return 0; | 1213 | return 0; |
1212 | } | 1214 | } |
@@ -2699,8 +2701,6 @@ static int gk20a_channel_event_id_ctrl(struct channel_gk20a *ch, | |||
2699 | 2701 | ||
2700 | int gk20a_channel_set_priority(struct channel_gk20a *ch, u32 priority) | 2702 | int gk20a_channel_set_priority(struct channel_gk20a *ch, u32 priority) |
2701 | { | 2703 | { |
2702 | u32 timeslice_timeout; | ||
2703 | |||
2704 | if (gk20a_is_channel_marked_as_tsg(ch)) { | 2704 | if (gk20a_is_channel_marked_as_tsg(ch)) { |
2705 | gk20a_err(dev_from_gk20a(ch->g), | 2705 | gk20a_err(dev_from_gk20a(ch->g), |
2706 | "invalid operation for TSG!\n"); | 2706 | "invalid operation for TSG!\n"); |
@@ -2710,21 +2710,20 @@ int gk20a_channel_set_priority(struct channel_gk20a *ch, u32 priority) | |||
2710 | /* set priority of graphics channel */ | 2710 | /* set priority of graphics channel */ |
2711 | switch (priority) { | 2711 | switch (priority) { |
2712 | case NVGPU_PRIORITY_LOW: | 2712 | case NVGPU_PRIORITY_LOW: |
2713 | timeslice_timeout = ch->g->timeslice_low_priority_us; | 2713 | ch->timeslice_us = ch->g->timeslice_low_priority_us; |
2714 | break; | 2714 | break; |
2715 | case NVGPU_PRIORITY_MEDIUM: | 2715 | case NVGPU_PRIORITY_MEDIUM: |
2716 | timeslice_timeout = ch->g->timeslice_medium_priority_us; | 2716 | ch->timeslice_us = ch->g->timeslice_medium_priority_us; |
2717 | break; | 2717 | break; |
2718 | case NVGPU_PRIORITY_HIGH: | 2718 | case NVGPU_PRIORITY_HIGH: |
2719 | timeslice_timeout = ch->g->timeslice_high_priority_us; | 2719 | ch->timeslice_us = ch->g->timeslice_high_priority_us; |
2720 | break; | 2720 | break; |
2721 | default: | 2721 | default: |
2722 | pr_err("Unsupported priority"); | 2722 | pr_err("Unsupported priority"); |
2723 | return -EINVAL; | 2723 | return -EINVAL; |
2724 | } | 2724 | } |
2725 | 2725 | ||
2726 | return channel_gk20a_set_schedule_params(ch, | 2726 | return channel_gk20a_set_schedule_params(ch); |
2727 | timeslice_timeout); | ||
2728 | } | 2727 | } |
2729 | 2728 | ||
2730 | int gk20a_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice) | 2729 | int gk20a_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice) |
@@ -2739,7 +2738,9 @@ int gk20a_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice) | |||
2739 | timeslice > NVGPU_CHANNEL_MAX_TIMESLICE_US) | 2738 | timeslice > NVGPU_CHANNEL_MAX_TIMESLICE_US) |
2740 | return -EINVAL; | 2739 | return -EINVAL; |
2741 | 2740 | ||
2742 | return channel_gk20a_set_schedule_params(ch, timeslice); | 2741 | ch->timeslice_us = timeslice; |
2742 | |||
2743 | return channel_gk20a_set_schedule_params(ch); | ||
2743 | } | 2744 | } |
2744 | 2745 | ||
2745 | static int gk20a_channel_zcull_bind(struct channel_gk20a *ch, | 2746 | static int gk20a_channel_zcull_bind(struct channel_gk20a *ch, |
@@ -3059,6 +3060,8 @@ long gk20a_channel_ioctl(struct file *filp, | |||
3059 | gk20a_dbg(gpu_dbg_gpu_dbg, "setting timeout (%d ms) for chid %d", | 3060 | gk20a_dbg(gpu_dbg_gpu_dbg, "setting timeout (%d ms) for chid %d", |
3060 | timeout, ch->hw_chid); | 3061 | timeout, ch->hw_chid); |
3061 | ch->timeout_ms_max = timeout; | 3062 | ch->timeout_ms_max = timeout; |
3063 | |||
3064 | trace_gk20a_channel_set_timeout(GK20A_TP_ARGS_SCHED(ch)); | ||
3062 | break; | 3065 | break; |
3063 | } | 3066 | } |
3064 | case NVGPU_IOCTL_CHANNEL_SET_TIMEOUT_EX: | 3067 | case NVGPU_IOCTL_CHANNEL_SET_TIMEOUT_EX: |
@@ -3072,6 +3075,8 @@ long gk20a_channel_ioctl(struct file *filp, | |||
3072 | timeout, ch->hw_chid); | 3075 | timeout, ch->hw_chid); |
3073 | ch->timeout_ms_max = timeout; | 3076 | ch->timeout_ms_max = timeout; |
3074 | ch->timeout_debug_dump = timeout_debug_dump; | 3077 | ch->timeout_debug_dump = timeout_debug_dump; |
3078 | |||
3079 | trace_gk20a_channel_set_timeout(GK20A_TP_ARGS_SCHED(ch)); | ||
3075 | break; | 3080 | break; |
3076 | } | 3081 | } |
3077 | case NVGPU_IOCTL_CHANNEL_GET_TIMEDOUT: | 3082 | case NVGPU_IOCTL_CHANNEL_GET_TIMEDOUT: |
@@ -3088,7 +3093,10 @@ long gk20a_channel_ioctl(struct file *filp, | |||
3088 | } | 3093 | } |
3089 | err = ch->g->ops.fifo.channel_set_priority(ch, | 3094 | err = ch->g->ops.fifo.channel_set_priority(ch, |
3090 | ((struct nvgpu_set_priority_args *)buf)->priority); | 3095 | ((struct nvgpu_set_priority_args *)buf)->priority); |
3096 | |||
3091 | gk20a_idle(dev); | 3097 | gk20a_idle(dev); |
3098 | |||
3099 | trace_gk20a_channel_set_priority(GK20A_TP_ARGS_SCHED(ch)); | ||
3092 | break; | 3100 | break; |
3093 | case NVGPU_IOCTL_CHANNEL_ENABLE: | 3101 | case NVGPU_IOCTL_CHANNEL_ENABLE: |
3094 | err = gk20a_busy(dev); | 3102 | err = gk20a_busy(dev); |
@@ -3172,7 +3180,10 @@ long gk20a_channel_ioctl(struct file *filp, | |||
3172 | } | 3180 | } |
3173 | err = gk20a_channel_set_runlist_interleave(ch, | 3181 | err = gk20a_channel_set_runlist_interleave(ch, |
3174 | ((struct nvgpu_runlist_interleave_args *)buf)->level); | 3182 | ((struct nvgpu_runlist_interleave_args *)buf)->level); |
3183 | |||
3175 | gk20a_idle(dev); | 3184 | gk20a_idle(dev); |
3185 | |||
3186 | trace_gk20a_channel_set_runlist_interleave(GK20A_TP_ARGS_SCHED(ch)); | ||
3176 | break; | 3187 | break; |
3177 | case NVGPU_IOCTL_CHANNEL_SET_TIMESLICE: | 3188 | case NVGPU_IOCTL_CHANNEL_SET_TIMESLICE: |
3178 | err = gk20a_busy(dev); | 3189 | err = gk20a_busy(dev); |
@@ -3184,7 +3195,10 @@ long gk20a_channel_ioctl(struct file *filp, | |||
3184 | } | 3195 | } |
3185 | err = ch->g->ops.fifo.channel_set_timeslice(ch, | 3196 | err = ch->g->ops.fifo.channel_set_timeslice(ch, |
3186 | ((struct nvgpu_timeslice_args *)buf)->timeslice_us); | 3197 | ((struct nvgpu_timeslice_args *)buf)->timeslice_us); |
3198 | |||
3187 | gk20a_idle(dev); | 3199 | gk20a_idle(dev); |
3200 | |||
3201 | trace_gk20a_channel_set_timeslice(GK20A_TP_ARGS_SCHED(ch)); | ||
3188 | break; | 3202 | break; |
3189 | default: | 3203 | default: |
3190 | dev_dbg(dev, "unrecognized ioctl cmd: 0x%x", cmd); | 3204 | dev_dbg(dev, "unrecognized ioctl cmd: 0x%x", cmd); |
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index 1e9341ae..8840a3ae 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h | |||
@@ -176,6 +176,7 @@ struct channel_gk20a { | |||
176 | bool has_timedout; | 176 | bool has_timedout; |
177 | u32 timeout_ms_max; | 177 | u32 timeout_ms_max; |
178 | bool timeout_debug_dump; | 178 | bool timeout_debug_dump; |
179 | u32 timeslice_us; | ||
179 | 180 | ||
180 | struct dma_buf *error_notifier_ref; | 181 | struct dma_buf *error_notifier_ref; |
181 | struct nvgpu_notification *error_notifier; | 182 | struct nvgpu_notification *error_notifier; |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 66dfa48a..fa8ab5b1 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -2550,6 +2550,138 @@ struct channel_gk20a *gk20a_fifo_channel_from_hw_chid(struct gk20a *g, | |||
2550 | return g->fifo.channel + hw_chid; | 2550 | return g->fifo.channel + hw_chid; |
2551 | } | 2551 | } |
2552 | 2552 | ||
2553 | #ifdef CONFIG_DEBUG_FS | ||
2554 | static void *gk20a_fifo_sched_debugfs_seq_start( | ||
2555 | struct seq_file *s, loff_t *pos) | ||
2556 | { | ||
2557 | struct gk20a *g = s->private; | ||
2558 | struct fifo_gk20a *f = &g->fifo; | ||
2559 | |||
2560 | if (*pos >= f->num_channels) | ||
2561 | return NULL; | ||
2562 | |||
2563 | return &f->channel[*pos]; | ||
2564 | } | ||
2565 | |||
2566 | static void *gk20a_fifo_sched_debugfs_seq_next( | ||
2567 | struct seq_file *s, void *v, loff_t *pos) | ||
2568 | { | ||
2569 | struct gk20a *g = s->private; | ||
2570 | struct fifo_gk20a *f = &g->fifo; | ||
2571 | |||
2572 | ++(*pos); | ||
2573 | if (*pos >= f->num_channels) | ||
2574 | return NULL; | ||
2575 | |||
2576 | return &f->channel[*pos]; | ||
2577 | } | ||
2578 | |||
2579 | static void gk20a_fifo_sched_debugfs_seq_stop( | ||
2580 | struct seq_file *s, void *v) | ||
2581 | { | ||
2582 | } | ||
2583 | |||
2584 | static int gk20a_fifo_sched_debugfs_seq_show( | ||
2585 | struct seq_file *s, void *v) | ||
2586 | { | ||
2587 | struct gk20a *g = s->private; | ||
2588 | struct fifo_gk20a *f = &g->fifo; | ||
2589 | struct channel_gk20a *ch = v; | ||
2590 | struct tsg_gk20a *tsg = NULL; | ||
2591 | |||
2592 | struct fifo_engine_info_gk20a *engine_info; | ||
2593 | struct fifo_runlist_info_gk20a *runlist; | ||
2594 | u32 runlist_id; | ||
2595 | int ret = SEQ_SKIP; | ||
2596 | |||
2597 | engine_info = f->engine_info + ENGINE_GR_GK20A; | ||
2598 | runlist_id = engine_info->runlist_id; | ||
2599 | runlist = &f->runlist_info[runlist_id]; | ||
2600 | |||
2601 | if (ch == f->channel) { | ||
2602 | seq_puts(s, "chid tsgid pid timeslice timeout interleave preempt\n"); | ||
2603 | seq_puts(s, " (usecs) (msecs)\n"); | ||
2604 | ret = 0; | ||
2605 | } | ||
2606 | |||
2607 | if (!test_bit(ch->hw_chid, runlist->active_channels)) | ||
2608 | return ret; | ||
2609 | |||
2610 | if (gk20a_channel_get(ch)) { | ||
2611 | if (gk20a_is_channel_marked_as_tsg(ch)) | ||
2612 | tsg = &f->tsg[ch->tsgid]; | ||
2613 | |||
2614 | seq_printf(s, "%-8d %-8d %-8d %-9d %-8d %-10d %-8d\n", | ||
2615 | ch->hw_chid, | ||
2616 | ch->tsgid, | ||
2617 | ch->pid, | ||
2618 | tsg ? tsg->timeslice_us : ch->timeslice_us, | ||
2619 | ch->timeout_ms_max, | ||
2620 | ch->interleave_level, | ||
2621 | ch->ch_ctx.gr_ctx ? | ||
2622 | ch->ch_ctx.gr_ctx->preempt_mode : -1); | ||
2623 | gk20a_channel_put(ch); | ||
2624 | } | ||
2625 | return 0; | ||
2626 | } | ||
2627 | |||
2628 | const struct seq_operations gk20a_fifo_sched_debugfs_seq_ops = { | ||
2629 | .start = gk20a_fifo_sched_debugfs_seq_start, | ||
2630 | .next = gk20a_fifo_sched_debugfs_seq_next, | ||
2631 | .stop = gk20a_fifo_sched_debugfs_seq_stop, | ||
2632 | .show = gk20a_fifo_sched_debugfs_seq_show | ||
2633 | }; | ||
2634 | |||
2635 | static int gk20a_fifo_sched_debugfs_open(struct inode *inode, | ||
2636 | struct file *file) | ||
2637 | { | ||
2638 | int err; | ||
2639 | |||
2640 | if (!capable(CAP_SYS_ADMIN)) | ||
2641 | return -EPERM; | ||
2642 | |||
2643 | err = seq_open(file, &gk20a_fifo_sched_debugfs_seq_ops); | ||
2644 | if (err) | ||
2645 | return err; | ||
2646 | |||
2647 | gk20a_dbg(gpu_dbg_info, "i_private=%p", inode->i_private); | ||
2648 | |||
2649 | ((struct seq_file *)file->private_data)->private = inode->i_private; | ||
2650 | return 0; | ||
2651 | }; | ||
2652 | |||
2653 | /* | ||
2654 | * The file operations structure contains our open function along with | ||
2655 | * set of the canned seq_ ops. | ||
2656 | */ | ||
2657 | const struct file_operations gk20a_fifo_sched_debugfs_fops = { | ||
2658 | .owner = THIS_MODULE, | ||
2659 | .open = gk20a_fifo_sched_debugfs_open, | ||
2660 | .read = seq_read, | ||
2661 | .llseek = seq_lseek, | ||
2662 | .release = seq_release | ||
2663 | }; | ||
2664 | |||
2665 | void gk20a_fifo_debugfs_init(struct device *dev) | ||
2666 | { | ||
2667 | struct gk20a_platform *platform = dev_get_drvdata(dev); | ||
2668 | struct gk20a *g = get_gk20a(dev); | ||
2669 | |||
2670 | struct dentry *gpu_root = platform->debugfs; | ||
2671 | struct dentry *fifo_root; | ||
2672 | |||
2673 | fifo_root = debugfs_create_dir("fifo", gpu_root); | ||
2674 | if (IS_ERR_OR_NULL(fifo_root)) | ||
2675 | return; | ||
2676 | |||
2677 | gk20a_dbg(gpu_dbg_info, "g=%p", g); | ||
2678 | |||
2679 | debugfs_create_file("sched", 0600, fifo_root, g, | ||
2680 | &gk20a_fifo_sched_debugfs_fops); | ||
2681 | |||
2682 | } | ||
2683 | #endif /* CONFIG_DEBUG_FS */ | ||
2684 | |||
2553 | void gk20a_init_fifo(struct gpu_ops *gops) | 2685 | void gk20a_init_fifo(struct gpu_ops *gops) |
2554 | { | 2686 | { |
2555 | gk20a_init_channel(gops); | 2687 | gk20a_init_channel(gops); |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 0979bf2b..c95ba71c 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -140,6 +140,23 @@ struct fifo_gk20a { | |||
140 | struct mutex deferred_reset_mutex; | 140 | struct mutex deferred_reset_mutex; |
141 | }; | 141 | }; |
142 | 142 | ||
143 | static inline const char *gk20a_fifo_interleave_level_name(u32 interleave_level) | ||
144 | { | ||
145 | switch (interleave_level) { | ||
146 | case NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW: | ||
147 | return "LOW"; | ||
148 | |||
149 | case NVGPU_RUNLIST_INTERLEAVE_LEVEL_MEDIUM: | ||
150 | return "MEDIUM"; | ||
151 | |||
152 | case NVGPU_RUNLIST_INTERLEAVE_LEVEL_HIGH: | ||
153 | return "HIGH"; | ||
154 | |||
155 | default: | ||
156 | return "?"; | ||
157 | } | ||
158 | } | ||
159 | |||
143 | int gk20a_init_fifo_support(struct gk20a *g); | 160 | int gk20a_init_fifo_support(struct gk20a *g); |
144 | 161 | ||
145 | void gk20a_fifo_isr(struct gk20a *g); | 162 | void gk20a_fifo_isr(struct gk20a *g); |
@@ -200,4 +217,10 @@ int gk20a_fifo_set_runlist_interleave(struct gk20a *g, | |||
200 | bool is_tsg, | 217 | bool is_tsg, |
201 | u32 runlist_id, | 218 | u32 runlist_id, |
202 | u32 new_level); | 219 | u32 new_level); |
220 | |||
221 | void gk20a_fifo_debugfs_init(struct device *dev); | ||
222 | |||
223 | const char *gk20a_fifo_interleave_level_name(u32 interleave_level); | ||
224 | |||
225 | |||
203 | #endif /*__GR_GK20A_H__*/ | 226 | #endif /*__GR_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index dd27ef64..fd226ee5 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -1608,6 +1608,7 @@ static int gk20a_probe(struct platform_device *dev) | |||
1608 | gk20a_cde_debugfs_init(&dev->dev); | 1608 | gk20a_cde_debugfs_init(&dev->dev); |
1609 | gk20a_alloc_debugfs_init(dev); | 1609 | gk20a_alloc_debugfs_init(dev); |
1610 | gk20a_mm_debugfs_init(&dev->dev); | 1610 | gk20a_mm_debugfs_init(&dev->dev); |
1611 | gk20a_fifo_debugfs_init(&dev->dev); | ||
1611 | #endif | 1612 | #endif |
1612 | 1613 | ||
1613 | gk20a_init_gr(gk20a); | 1614 | gk20a_init_gr(gk20a); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 15f838d9..0b15783b 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1074,4 +1074,30 @@ int gk20a_pm_init(struct device *dev); | |||
1074 | int gk20a_pm_finalize_poweron(struct device *dev); | 1074 | int gk20a_pm_finalize_poweron(struct device *dev); |
1075 | void gk20a_remove_support(struct device *dev); | 1075 | void gk20a_remove_support(struct device *dev); |
1076 | 1076 | ||
1077 | static inline struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch) | ||
1078 | { | ||
1079 | struct tsg_gk20a *tsg = NULL; | ||
1080 | |||
1081 | if (gk20a_is_channel_marked_as_tsg(ch)) | ||
1082 | { | ||
1083 | struct gk20a *g = ch->g; | ||
1084 | struct fifo_gk20a *f = &g->fifo; | ||
1085 | tsg = &f->tsg[ch->tsgid]; | ||
1086 | } | ||
1087 | |||
1088 | return tsg; | ||
1089 | } | ||
1090 | |||
1091 | |||
1092 | #define GK20A_TP_ARGS_SCHED(ch) \ | ||
1093 | ch->hw_chid, \ | ||
1094 | ch->tsgid, \ | ||
1095 | ch->pid, \ | ||
1096 | gk20a_is_channel_marked_as_tsg(ch) ? \ | ||
1097 | tsg_gk20a_from_ch(ch)->timeslice_us : ch->timeslice_us, \ | ||
1098 | ch->timeout_ms_max, \ | ||
1099 | gk20a_fifo_interleave_level_name(ch->interleave_level), \ | ||
1100 | gr_gk20a_preempt_mode_name(ch->ch_ctx.gr_ctx ? \ | ||
1101 | ch->ch_ctx.gr_ctx->preempt_mode : 0) | ||
1102 | |||
1077 | #endif /* GK20A_H */ | 1103 | #endif /* GK20A_H */ |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 681a0437..e1e6e262 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -626,4 +626,21 @@ int gr_gk20a_resume_contexts(struct gk20a *g, | |||
626 | struct dbg_session_gk20a *dbg_s, | 626 | struct dbg_session_gk20a *dbg_s, |
627 | int *ctx_resident_ch_fd); | 627 | int *ctx_resident_ch_fd); |
628 | 628 | ||
629 | #define NVGPU_GR_PREEMPTION_MODE_WFI 0 | ||
630 | #define NVGPU_GR_PREEMPTION_MODE_CTA 2 | ||
631 | |||
632 | static inline const char *gr_gk20a_preempt_mode_name(u32 preempt_mode) | ||
633 | { | ||
634 | switch (preempt_mode) { | ||
635 | case NVGPU_GR_PREEMPTION_MODE_WFI: | ||
636 | return "WFI"; | ||
637 | |||
638 | case NVGPU_GR_PREEMPTION_MODE_CTA: | ||
639 | return "CTA"; | ||
640 | |||
641 | default: | ||
642 | return "?"; | ||
643 | } | ||
644 | } | ||
645 | |||
629 | #endif /*__GR_GK20A_H__*/ | 646 | #endif /*__GR_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index 3bc568d6..29f32d8f 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h | |||
@@ -103,9 +103,6 @@ struct gr_ctx_desc { | |||
103 | #endif | 103 | #endif |
104 | }; | 104 | }; |
105 | 105 | ||
106 | #define NVGPU_GR_PREEMPTION_MODE_WFI 0 | ||
107 | #define NVGPU_GR_PREEMPTION_MODE_CTA 2 | ||
108 | |||
109 | struct compbit_store_desc { | 106 | struct compbit_store_desc { |
110 | struct mem_desc mem; | 107 | struct mem_desc mem; |
111 | 108 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c index 40c871ce..5f4cf931 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | |||
@@ -165,24 +165,22 @@ int gk20a_init_tsg_support(struct gk20a *g, u32 tsgid) | |||
165 | static int gk20a_tsg_set_priority(struct gk20a *g, struct tsg_gk20a *tsg, | 165 | static int gk20a_tsg_set_priority(struct gk20a *g, struct tsg_gk20a *tsg, |
166 | u32 priority) | 166 | u32 priority) |
167 | { | 167 | { |
168 | int timeslice_period; | ||
169 | |||
170 | switch (priority) { | 168 | switch (priority) { |
171 | case NVGPU_PRIORITY_LOW: | 169 | case NVGPU_PRIORITY_LOW: |
172 | timeslice_period = g->timeslice_low_priority_us; | 170 | tsg->timeslice_us = g->timeslice_low_priority_us; |
173 | break; | 171 | break; |
174 | case NVGPU_PRIORITY_MEDIUM: | 172 | case NVGPU_PRIORITY_MEDIUM: |
175 | timeslice_period = g->timeslice_medium_priority_us; | 173 | tsg->timeslice_us = g->timeslice_medium_priority_us; |
176 | break; | 174 | break; |
177 | case NVGPU_PRIORITY_HIGH: | 175 | case NVGPU_PRIORITY_HIGH: |
178 | timeslice_period = g->timeslice_high_priority_us; | 176 | tsg->timeslice_us = g->timeslice_high_priority_us; |
179 | break; | 177 | break; |
180 | default: | 178 | default: |
181 | pr_err("Unsupported priority"); | 179 | pr_err("Unsupported priority"); |
182 | return -EINVAL; | 180 | return -EINVAL; |
183 | } | 181 | } |
184 | 182 | ||
185 | gk20a_channel_get_timescale_from_timeslice(g, timeslice_period, | 183 | gk20a_channel_get_timescale_from_timeslice(g, tsg->timeslice_us, |
186 | &tsg->timeslice_timeout, &tsg->timeslice_scale); | 184 | &tsg->timeslice_timeout, &tsg->timeslice_scale); |
187 | 185 | ||
188 | g->ops.fifo.update_runlist(g, 0, ~0, true, true); | 186 | g->ops.fifo.update_runlist(g, 0, ~0, true, true); |
@@ -407,6 +405,7 @@ int gk20a_tsg_open(struct gk20a *g, struct file *filp) | |||
407 | tsg->tsg_gr_ctx = NULL; | 405 | tsg->tsg_gr_ctx = NULL; |
408 | tsg->vm = NULL; | 406 | tsg->vm = NULL; |
409 | tsg->interleave_level = NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW; | 407 | tsg->interleave_level = NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW; |
408 | tsg->timeslice_us = 0; | ||
410 | 409 | ||
411 | filp->private_data = tsg; | 410 | filp->private_data = tsg; |
412 | 411 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h index 9a23c973..9a8bfada 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h | |||
@@ -43,6 +43,7 @@ struct tsg_gk20a { | |||
43 | int num_active_channels; | 43 | int num_active_channels; |
44 | struct mutex ch_list_lock; | 44 | struct mutex ch_list_lock; |
45 | 45 | ||
46 | int timeslice_us; | ||
46 | int timeslice_timeout; | 47 | int timeslice_timeout; |
47 | int timeslice_scale; | 48 | int timeslice_scale; |
48 | 49 | ||