diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 4 |
3 files changed, 16 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 3a166e06..8d65f90a 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -5304,10 +5304,18 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch, | |||
5304 | nvgpu_err(g, "fecs watchdog triggered for channel %u, " | 5304 | nvgpu_err(g, "fecs watchdog triggered for channel %u, " |
5305 | "cannot ctxsw anymore !!", isr_data->chid); | 5305 | "cannot ctxsw anymore !!", isr_data->chid); |
5306 | gk20a_fecs_dump_falcon_stats(g); | 5306 | gk20a_fecs_dump_falcon_stats(g); |
5307 | } else if ((gr_fecs_intr & | ||
5308 | gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR0)) != 0U) { | ||
5309 | u32 mailbox_value = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6)); | ||
5310 | |||
5311 | nvgpu_err(g, "ctxsw intr0 set by ucode, error_code: 0x%08x", | ||
5312 | mailbox_value); | ||
5313 | ret = -1; | ||
5307 | } else { | 5314 | } else { |
5308 | nvgpu_err(g, | 5315 | nvgpu_err(g, |
5309 | "fecs error interrupt 0x%08x for channel %u", | 5316 | "unhandled fecs error interrupt 0x%08x for channel %u", |
5310 | gr_fecs_intr, isr_data->chid); | 5317 | gr_fecs_intr, ch->chid); |
5318 | gk20a_fecs_dump_falcon_stats(g); | ||
5311 | } | 5319 | } |
5312 | 5320 | ||
5313 | gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr); | 5321 | gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index c4ce49af..25850104 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -66,6 +66,9 @@ | |||
66 | #define NVGPU_PREEMPTION_MODE_COMPUTE_CTA (1 << 1) | 66 | #define NVGPU_PREEMPTION_MODE_COMPUTE_CTA (1 << 1) |
67 | #define NVGPU_PREEMPTION_MODE_COMPUTE_CILP (1 << 2) | 67 | #define NVGPU_PREEMPTION_MODE_COMPUTE_CILP (1 << 2) |
68 | 68 | ||
69 | #define CTXSW_INTR0 BIT32(0) | ||
70 | #define CTXSW_INTR1 BIT32(1) | ||
71 | |||
69 | struct tsg_gk20a; | 72 | struct tsg_gk20a; |
70 | struct channel_gk20a; | 73 | struct channel_gk20a; |
71 | struct nvgpu_warpstate; | 74 | struct nvgpu_warpstate; |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 913434ab..be1e2038 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1996,7 +1996,9 @@ int gr_gp10b_handle_fecs_error(struct gk20a *g, | |||
1996 | * INTR1 (bit 1 of the HOST_INT_STATUS_CTXSW_INTR) | 1996 | * INTR1 (bit 1 of the HOST_INT_STATUS_CTXSW_INTR) |
1997 | * indicates that a CILP ctxsw save has finished | 1997 | * indicates that a CILP ctxsw save has finished |
1998 | */ | 1998 | */ |
1999 | if (gr_fecs_intr & gr_fecs_host_int_status_ctxsw_intr_f(2)) { | 1999 | |
2000 | if ((gr_fecs_intr & | ||
2001 | gr_fecs_host_int_status_ctxsw_intr_f(CTXSW_INTR1)) != 0U) { | ||
2000 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | 2002 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
2001 | "CILP: ctxsw save completed!\n"); | 2003 | "CILP: ctxsw save completed!\n"); |
2002 | 2004 | ||