diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 19 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gr_vgpu.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 2 |
12 files changed, 39 insertions, 21 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 79aec7a2..576a7f81 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -1393,7 +1393,7 @@ void gk20a_fifo_set_ctx_mmu_error_ch(struct gk20a *g, | |||
1393 | { | 1393 | { |
1394 | nvgpu_err(g, | 1394 | nvgpu_err(g, |
1395 | "channel %d generated a mmu fault", refch->chid); | 1395 | "channel %d generated a mmu fault", refch->chid); |
1396 | nvgpu_set_error_notifier(refch, | 1396 | g->ops.fifo.set_error_notifier(refch, |
1397 | NVGPU_ERR_NOTIFIER_FIFO_ERROR_MMU_ERR_FLT); | 1397 | NVGPU_ERR_NOTIFIER_FIFO_ERROR_MMU_ERR_FLT); |
1398 | } | 1398 | } |
1399 | 1399 | ||
@@ -1938,7 +1938,8 @@ int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, | |||
1938 | nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list, | 1938 | nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list, |
1939 | channel_gk20a, ch_entry) { | 1939 | channel_gk20a, ch_entry) { |
1940 | if (gk20a_channel_get(ch_tsg)) { | 1940 | if (gk20a_channel_get(ch_tsg)) { |
1941 | nvgpu_set_error_notifier(ch_tsg, err_code); | 1941 | g->ops.fifo.set_error_notifier(ch_tsg, |
1942 | err_code); | ||
1942 | gk20a_channel_put(ch_tsg); | 1943 | gk20a_channel_put(ch_tsg); |
1943 | } | 1944 | } |
1944 | } | 1945 | } |
@@ -1946,7 +1947,7 @@ int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, | |||
1946 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); | 1947 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); |
1947 | gk20a_fifo_recover_tsg(g, ch->tsgid, verbose); | 1948 | gk20a_fifo_recover_tsg(g, ch->tsgid, verbose); |
1948 | } else { | 1949 | } else { |
1949 | nvgpu_set_error_notifier(ch, err_code); | 1950 | g->ops.fifo.set_error_notifier(ch, err_code); |
1950 | gk20a_fifo_recover_ch(g, ch->chid, verbose); | 1951 | gk20a_fifo_recover_ch(g, ch->chid, verbose); |
1951 | } | 1952 | } |
1952 | 1953 | ||
@@ -2108,7 +2109,7 @@ bool gk20a_fifo_check_ch_ctxsw_timeout(struct channel_gk20a *ch, | |||
2108 | *verbose = ch->timeout_debug_dump; | 2109 | *verbose = ch->timeout_debug_dump; |
2109 | *ms = ch->timeout_accumulated_ms; | 2110 | *ms = ch->timeout_accumulated_ms; |
2110 | if (recover) | 2111 | if (recover) |
2111 | nvgpu_set_error_notifier(ch, | 2112 | ch->g->ops.fifo.set_error_notifier(ch, |
2112 | NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT); | 2113 | NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT); |
2113 | 2114 | ||
2114 | gk20a_channel_put(ch); | 2115 | gk20a_channel_put(ch); |
@@ -2172,7 +2173,7 @@ bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg, | |||
2172 | nvgpu_list_for_each_entry(ch, &tsg->ch_list, | 2173 | nvgpu_list_for_each_entry(ch, &tsg->ch_list, |
2173 | channel_gk20a, ch_entry) { | 2174 | channel_gk20a, ch_entry) { |
2174 | if (gk20a_channel_get(ch)) { | 2175 | if (gk20a_channel_get(ch)) { |
2175 | nvgpu_set_error_notifier(ch, | 2176 | ch->g->ops.fifo.set_error_notifier(ch, |
2176 | NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT); | 2177 | NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT); |
2177 | *verbose |= ch->timeout_debug_dump; | 2178 | *verbose |= ch->timeout_debug_dump; |
2178 | gk20a_channel_put(ch); | 2179 | gk20a_channel_put(ch); |
@@ -2487,7 +2488,7 @@ static void gk20a_fifo_pbdma_fault_rc(struct gk20a *g, | |||
2487 | struct channel_gk20a *ch = &f->channel[id]; | 2488 | struct channel_gk20a *ch = &f->channel[id]; |
2488 | 2489 | ||
2489 | if (gk20a_channel_get(ch)) { | 2490 | if (gk20a_channel_get(ch)) { |
2490 | nvgpu_set_error_notifier(ch, error_notifier); | 2491 | g->ops.fifo.set_error_notifier(ch, error_notifier); |
2491 | gk20a_fifo_recover_ch(g, id, true); | 2492 | gk20a_fifo_recover_ch(g, id, true); |
2492 | gk20a_channel_put(ch); | 2493 | gk20a_channel_put(ch); |
2493 | } | 2494 | } |
@@ -2500,7 +2501,7 @@ static void gk20a_fifo_pbdma_fault_rc(struct gk20a *g, | |||
2500 | nvgpu_list_for_each_entry(ch, &tsg->ch_list, | 2501 | nvgpu_list_for_each_entry(ch, &tsg->ch_list, |
2501 | channel_gk20a, ch_entry) { | 2502 | channel_gk20a, ch_entry) { |
2502 | if (gk20a_channel_get(ch)) { | 2503 | if (gk20a_channel_get(ch)) { |
2503 | nvgpu_set_error_notifier(ch, | 2504 | g->ops.fifo.set_error_notifier(ch, |
2504 | error_notifier); | 2505 | error_notifier); |
2505 | gk20a_channel_put(ch); | 2506 | gk20a_channel_put(ch); |
2506 | } | 2507 | } |
@@ -2662,7 +2663,7 @@ void __locked_fifo_preempt_timeout_rc(struct gk20a *g, u32 id, | |||
2662 | channel_gk20a, ch_entry) { | 2663 | channel_gk20a, ch_entry) { |
2663 | if (!gk20a_channel_get(ch)) | 2664 | if (!gk20a_channel_get(ch)) |
2664 | continue; | 2665 | continue; |
2665 | nvgpu_set_error_notifier(ch, | 2666 | g->ops.fifo.set_error_notifier(ch, |
2666 | NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT); | 2667 | NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT); |
2667 | gk20a_channel_put(ch); | 2668 | gk20a_channel_put(ch); |
2668 | } | 2669 | } |
@@ -2675,7 +2676,7 @@ void __locked_fifo_preempt_timeout_rc(struct gk20a *g, u32 id, | |||
2675 | "preempt channel %d timeout", id); | 2676 | "preempt channel %d timeout", id); |
2676 | 2677 | ||
2677 | if (gk20a_channel_get(ch)) { | 2678 | if (gk20a_channel_get(ch)) { |
2678 | nvgpu_set_error_notifier(ch, | 2679 | g->ops.fifo.set_error_notifier(ch, |
2679 | NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT); | 2680 | NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT); |
2680 | gk20a_fifo_recover_ch(g, id, true); | 2681 | gk20a_fifo_recover_ch(g, id, true); |
2681 | gk20a_channel_put(ch); | 2682 | gk20a_channel_put(ch); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index c7653133..e8cfaf13 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -635,6 +635,7 @@ struct gpu_ops { | |||
635 | bool *verbose, u32 *ms); | 635 | bool *verbose, u32 *ms); |
636 | int (*channel_suspend)(struct gk20a *g); | 636 | int (*channel_suspend)(struct gk20a *g); |
637 | int (*channel_resume)(struct gk20a *g); | 637 | int (*channel_resume)(struct gk20a *g); |
638 | void (*set_error_notifier)(struct channel_gk20a *ch, u32 error); | ||
638 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | 639 | #ifdef CONFIG_TEGRA_GK20A_NVHOST |
639 | int (*alloc_syncpt_buf)(struct channel_gk20a *c, | 640 | int (*alloc_syncpt_buf)(struct channel_gk20a *c, |
640 | u32 syncpt_id, struct nvgpu_mem *syncpt_buf); | 641 | u32 syncpt_id, struct nvgpu_mem *syncpt_buf); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index cf63546b..e06d190e 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -5154,14 +5154,14 @@ void gk20a_gr_set_error_notifier(struct gk20a *g, | |||
5154 | nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list, | 5154 | nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list, |
5155 | channel_gk20a, ch_entry) { | 5155 | channel_gk20a, ch_entry) { |
5156 | if (gk20a_channel_get(ch_tsg)) { | 5156 | if (gk20a_channel_get(ch_tsg)) { |
5157 | nvgpu_set_error_notifier(ch_tsg, | 5157 | g->ops.fifo.set_error_notifier(ch_tsg, |
5158 | error_notifier); | 5158 | error_notifier); |
5159 | gk20a_channel_put(ch_tsg); | 5159 | gk20a_channel_put(ch_tsg); |
5160 | } | 5160 | } |
5161 | } | 5161 | } |
5162 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); | 5162 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); |
5163 | } else { | 5163 | } else { |
5164 | nvgpu_set_error_notifier(ch, error_notifier); | 5164 | g->ops.fifo.set_error_notifier(ch, error_notifier); |
5165 | } | 5165 | } |
5166 | } | 5166 | } |
5167 | } | 5167 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index b41e07f9..0aac68ff 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -60,6 +60,7 @@ | |||
60 | #include <nvgpu/bug.h> | 60 | #include <nvgpu/bug.h> |
61 | #include <nvgpu/enabled.h> | 61 | #include <nvgpu/enabled.h> |
62 | #include <nvgpu/bus.h> | 62 | #include <nvgpu/bus.h> |
63 | #include <nvgpu/error_notifier.h> | ||
63 | 64 | ||
64 | #include <nvgpu/hw/gm20b/hw_proj_gm20b.h> | 65 | #include <nvgpu/hw/gm20b/hw_proj_gm20b.h> |
65 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> | 66 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> |
@@ -443,6 +444,7 @@ static const struct gpu_ops gm20b_ops = { | |||
443 | .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, | 444 | .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, |
444 | .channel_suspend = gk20a_channel_suspend, | 445 | .channel_suspend = gk20a_channel_suspend, |
445 | .channel_resume = gk20a_channel_resume, | 446 | .channel_resume = gk20a_channel_resume, |
447 | .set_error_notifier = nvgpu_set_error_notifier, | ||
446 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | 448 | #ifdef CONFIG_TEGRA_GK20A_NVHOST |
447 | .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, | 449 | .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, |
448 | .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, | 450 | .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 2f3c1a5e..e77316d6 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -89,6 +89,7 @@ | |||
89 | #include <nvgpu/bus.h> | 89 | #include <nvgpu/bus.h> |
90 | #include <nvgpu/enabled.h> | 90 | #include <nvgpu/enabled.h> |
91 | #include <nvgpu/ctxsw_trace.h> | 91 | #include <nvgpu/ctxsw_trace.h> |
92 | #include <nvgpu/error_notifier.h> | ||
92 | 93 | ||
93 | #include <nvgpu/hw/gp106/hw_proj_gp106.h> | 94 | #include <nvgpu/hw/gp106/hw_proj_gp106.h> |
94 | #include <nvgpu/hw/gp106/hw_fifo_gp106.h> | 95 | #include <nvgpu/hw/gp106/hw_fifo_gp106.h> |
@@ -504,6 +505,7 @@ static const struct gpu_ops gp106_ops = { | |||
504 | .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, | 505 | .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, |
505 | .channel_suspend = gk20a_channel_suspend, | 506 | .channel_suspend = gk20a_channel_suspend, |
506 | .channel_resume = gk20a_channel_resume, | 507 | .channel_resume = gk20a_channel_resume, |
508 | .set_error_notifier = nvgpu_set_error_notifier, | ||
507 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | 509 | #ifdef CONFIG_TEGRA_GK20A_NVHOST |
508 | .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, | 510 | .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, |
509 | .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, | 511 | .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 9238c4d7..78633e9b 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -71,6 +71,7 @@ | |||
71 | #include <nvgpu/enabled.h> | 71 | #include <nvgpu/enabled.h> |
72 | #include <nvgpu/bus.h> | 72 | #include <nvgpu/bus.h> |
73 | #include <nvgpu/ctxsw_trace.h> | 73 | #include <nvgpu/ctxsw_trace.h> |
74 | #include <nvgpu/error_notifier.h> | ||
74 | 75 | ||
75 | #include <nvgpu/hw/gp10b/hw_proj_gp10b.h> | 76 | #include <nvgpu/hw/gp10b/hw_proj_gp10b.h> |
76 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | 77 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> |
@@ -475,6 +476,7 @@ static const struct gpu_ops gp10b_ops = { | |||
475 | .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, | 476 | .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, |
476 | .channel_suspend = gk20a_channel_suspend, | 477 | .channel_suspend = gk20a_channel_suspend, |
477 | .channel_resume = gk20a_channel_resume, | 478 | .channel_resume = gk20a_channel_resume, |
479 | .set_error_notifier = nvgpu_set_error_notifier, | ||
478 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | 480 | #ifdef CONFIG_TEGRA_GK20A_NVHOST |
479 | .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, | 481 | .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, |
480 | .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, | 482 | .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 2f2d278e..45325469 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -109,6 +109,7 @@ | |||
109 | #include <nvgpu/debug.h> | 109 | #include <nvgpu/debug.h> |
110 | #include <nvgpu/enabled.h> | 110 | #include <nvgpu/enabled.h> |
111 | #include <nvgpu/ctxsw_trace.h> | 111 | #include <nvgpu/ctxsw_trace.h> |
112 | #include <nvgpu/error_notifier.h> | ||
112 | 113 | ||
113 | #include <nvgpu/hw/gv100/hw_proj_gv100.h> | 114 | #include <nvgpu/hw/gv100/hw_proj_gv100.h> |
114 | #include <nvgpu/hw/gv100/hw_fifo_gv100.h> | 115 | #include <nvgpu/hw/gv100/hw_fifo_gv100.h> |
@@ -516,6 +517,7 @@ static const struct gpu_ops gv100_ops = { | |||
516 | .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, | 517 | .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, |
517 | .channel_suspend = gk20a_channel_suspend, | 518 | .channel_suspend = gk20a_channel_suspend, |
518 | .channel_resume = gk20a_channel_resume, | 519 | .channel_resume = gk20a_channel_resume, |
520 | .set_error_notifier = nvgpu_set_error_notifier, | ||
519 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | 521 | #ifdef CONFIG_TEGRA_GK20A_NVHOST |
520 | .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, | 522 | .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, |
521 | .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, | 523 | .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 67b3adbf..60effbf2 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -85,6 +85,7 @@ | |||
85 | #include <nvgpu/debug.h> | 85 | #include <nvgpu/debug.h> |
86 | #include <nvgpu/enabled.h> | 86 | #include <nvgpu/enabled.h> |
87 | #include <nvgpu/ctxsw_trace.h> | 87 | #include <nvgpu/ctxsw_trace.h> |
88 | #include <nvgpu/error_notifier.h> | ||
88 | 89 | ||
89 | #include <nvgpu/hw/gv11b/hw_proj_gv11b.h> | 90 | #include <nvgpu/hw/gv11b/hw_proj_gv11b.h> |
90 | #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h> | 91 | #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h> |
@@ -533,6 +534,7 @@ static const struct gpu_ops gv11b_ops = { | |||
533 | .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, | 534 | .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, |
534 | .channel_suspend = gk20a_channel_suspend, | 535 | .channel_suspend = gk20a_channel_suspend, |
535 | .channel_resume = gk20a_channel_resume, | 536 | .channel_resume = gk20a_channel_resume, |
537 | .set_error_notifier = nvgpu_set_error_notifier, | ||
536 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | 538 | #ifdef CONFIG_TEGRA_GK20A_NVHOST |
537 | .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, | 539 | .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, |
538 | .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, | 540 | .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, |
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 6406c0da..c8a8ce49 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -643,7 +643,8 @@ int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, | |||
643 | nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list, | 643 | nvgpu_list_for_each_entry(ch_tsg, &tsg->ch_list, |
644 | channel_gk20a, ch_entry) { | 644 | channel_gk20a, ch_entry) { |
645 | if (gk20a_channel_get(ch_tsg)) { | 645 | if (gk20a_channel_get(ch_tsg)) { |
646 | nvgpu_set_error_notifier(ch_tsg, err_code); | 646 | g->ops.fifo.set_error_notifier(ch_tsg, |
647 | err_code); | ||
647 | ch_tsg->has_timedout = true; | 648 | ch_tsg->has_timedout = true; |
648 | gk20a_channel_put(ch_tsg); | 649 | gk20a_channel_put(ch_tsg); |
649 | } | 650 | } |
@@ -651,7 +652,7 @@ int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, | |||
651 | 652 | ||
652 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); | 653 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); |
653 | } else { | 654 | } else { |
654 | nvgpu_set_error_notifier(ch, err_code); | 655 | g->ops.fifo.set_error_notifier(ch, err_code); |
655 | ch->has_timedout = true; | 656 | ch->has_timedout = true; |
656 | } | 657 | } |
657 | 658 | ||
@@ -726,10 +727,11 @@ int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info) | |||
726 | 727 | ||
727 | switch (info->type) { | 728 | switch (info->type) { |
728 | case TEGRA_VGPU_FIFO_INTR_PBDMA: | 729 | case TEGRA_VGPU_FIFO_INTR_PBDMA: |
729 | nvgpu_set_error_notifier(ch, NVGPU_ERR_NOTIFIER_PBDMA_ERROR); | 730 | g->ops.fifo.set_error_notifier(ch, |
731 | NVGPU_ERR_NOTIFIER_PBDMA_ERROR); | ||
730 | break; | 732 | break; |
731 | case TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT: | 733 | case TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT: |
732 | nvgpu_set_error_notifier(ch, | 734 | g->ops.fifo.set_error_notifier(ch, |
733 | NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT); | 735 | NVGPU_ERR_NOTIFIER_FIFO_ERROR_IDLE_TIMEOUT); |
734 | break; | 736 | break; |
735 | case TEGRA_VGPU_FIFO_INTR_MMU_FAULT: | 737 | case TEGRA_VGPU_FIFO_INTR_MMU_FAULT: |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index ab08e09d..8b9f04dd 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -65,6 +65,7 @@ | |||
65 | 65 | ||
66 | #include <nvgpu/enabled.h> | 66 | #include <nvgpu/enabled.h> |
67 | #include <nvgpu/vgpu/vgpu.h> | 67 | #include <nvgpu/vgpu/vgpu.h> |
68 | #include <nvgpu/error_notifier.h> | ||
68 | 69 | ||
69 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | 70 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> |
70 | #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h> | 71 | #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h> |
@@ -349,6 +350,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
349 | .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, | 350 | .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, |
350 | .channel_suspend = gk20a_channel_suspend, | 351 | .channel_suspend = gk20a_channel_suspend, |
351 | .channel_resume = gk20a_channel_resume, | 352 | .channel_resume = gk20a_channel_resume, |
353 | .set_error_notifier = nvgpu_set_error_notifier, | ||
352 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | 354 | #ifdef CONFIG_TEGRA_GK20A_NVHOST |
353 | .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, | 355 | .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, |
354 | .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, | 356 | .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, |
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index 1c72ca76..a6cb3828 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c | |||
@@ -926,30 +926,30 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info) | |||
926 | nvgpu_cond_broadcast_interruptible(&ch->semaphore_wq); | 926 | nvgpu_cond_broadcast_interruptible(&ch->semaphore_wq); |
927 | break; | 927 | break; |
928 | case TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT: | 928 | case TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT: |
929 | nvgpu_set_error_notifier(ch, | 929 | g->ops.fifo.set_error_notifier(ch, |
930 | NVGPU_ERR_NOTIFIER_GR_SEMAPHORE_TIMEOUT); | 930 | NVGPU_ERR_NOTIFIER_GR_SEMAPHORE_TIMEOUT); |
931 | break; | 931 | break; |
932 | case TEGRA_VGPU_GR_INTR_ILLEGAL_NOTIFY: | 932 | case TEGRA_VGPU_GR_INTR_ILLEGAL_NOTIFY: |
933 | nvgpu_set_error_notifier(ch, | 933 | g->ops.fifo.set_error_notifier(ch, |
934 | NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY); | 934 | NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY); |
935 | case TEGRA_VGPU_GR_INTR_ILLEGAL_METHOD: | 935 | case TEGRA_VGPU_GR_INTR_ILLEGAL_METHOD: |
936 | break; | 936 | break; |
937 | case TEGRA_VGPU_GR_INTR_ILLEGAL_CLASS: | 937 | case TEGRA_VGPU_GR_INTR_ILLEGAL_CLASS: |
938 | nvgpu_set_error_notifier(ch, | 938 | g->ops.fifo.set_error_notifier(ch, |
939 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); | 939 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); |
940 | break; | 940 | break; |
941 | case TEGRA_VGPU_GR_INTR_FECS_ERROR: | 941 | case TEGRA_VGPU_GR_INTR_FECS_ERROR: |
942 | break; | 942 | break; |
943 | case TEGRA_VGPU_GR_INTR_CLASS_ERROR: | 943 | case TEGRA_VGPU_GR_INTR_CLASS_ERROR: |
944 | nvgpu_set_error_notifier(ch, | 944 | g->ops.fifo.set_error_notifier(ch, |
945 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); | 945 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); |
946 | break; | 946 | break; |
947 | case TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD: | 947 | case TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD: |
948 | nvgpu_set_error_notifier(ch, | 948 | g->ops.fifo.set_error_notifier(ch, |
949 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); | 949 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); |
950 | break; | 950 | break; |
951 | case TEGRA_VGPU_GR_INTR_EXCEPTION: | 951 | case TEGRA_VGPU_GR_INTR_EXCEPTION: |
952 | nvgpu_set_error_notifier(ch, | 952 | g->ops.fifo.set_error_notifier(ch, |
953 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); | 953 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); |
954 | break; | 954 | break; |
955 | case TEGRA_VGPU_GR_INTR_SM_EXCEPTION: | 955 | case TEGRA_VGPU_GR_INTR_SM_EXCEPTION: |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 5e3af9d7..32edbd21 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include <gk20a/gk20a.h> | 23 | #include <gk20a/gk20a.h> |
24 | #include <gv11b/hal_gv11b.h> | 24 | #include <gv11b/hal_gv11b.h> |
25 | #include <nvgpu/vgpu/vgpu.h> | 25 | #include <nvgpu/vgpu/vgpu.h> |
26 | #include <nvgpu/error_notifier.h> | ||
26 | 27 | ||
27 | #include "vgpu/fifo_vgpu.h" | 28 | #include "vgpu/fifo_vgpu.h" |
28 | #include "vgpu/gr_vgpu.h" | 29 | #include "vgpu/gr_vgpu.h" |
@@ -392,6 +393,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
392 | .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, | 393 | .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, |
393 | .channel_suspend = gk20a_channel_suspend, | 394 | .channel_suspend = gk20a_channel_suspend, |
394 | .channel_resume = gk20a_channel_resume, | 395 | .channel_resume = gk20a_channel_resume, |
396 | .set_error_notifier = nvgpu_set_error_notifier, | ||
395 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | 397 | #ifdef CONFIG_TEGRA_GK20A_NVHOST |
396 | .alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf, | 398 | .alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf, |
397 | .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, | 399 | .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, |