diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu.c | 52 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 34 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 70 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 72 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/pmu_gp106.c | 58 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/pmu_gp106.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 39 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 6 |
18 files changed, 204 insertions, 163 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c index 6d1d5f00..ffc9ec39 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu.c | |||
@@ -290,7 +290,7 @@ skip_init: | |||
290 | int nvgpu_init_pmu_support(struct gk20a *g) | 290 | int nvgpu_init_pmu_support(struct gk20a *g) |
291 | { | 291 | { |
292 | struct nvgpu_pmu *pmu = &g->pmu; | 292 | struct nvgpu_pmu *pmu = &g->pmu; |
293 | u32 err; | 293 | int err = 0; |
294 | 294 | ||
295 | nvgpu_log_fn(g, " "); | 295 | nvgpu_log_fn(g, " "); |
296 | 296 | ||
@@ -298,24 +298,54 @@ int nvgpu_init_pmu_support(struct gk20a *g) | |||
298 | return 0; | 298 | return 0; |
299 | } | 299 | } |
300 | 300 | ||
301 | err = pmu_enable_hw(pmu, true); | ||
302 | if (err) { | ||
303 | return err; | ||
304 | } | ||
305 | |||
306 | if (g->support_pmu) { | 301 | if (g->support_pmu) { |
307 | err = nvgpu_init_pmu_setup_sw(g); | 302 | err = nvgpu_init_pmu_setup_sw(g); |
308 | if (err) { | 303 | if (err != 0) { |
309 | return err; | 304 | goto exit; |
310 | } | 305 | } |
311 | err = g->ops.pmu.pmu_setup_hw_and_bootstrap(g); | 306 | |
312 | if (err) { | 307 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |
313 | return err; | 308 | /* |
309 | * clear halt interrupt to avoid PMU-RTOS ucode | ||
310 | * hitting breakpoint due to PMU halt | ||
311 | */ | ||
312 | err = nvgpu_flcn_clear_halt_intr_status(&g->pmu_flcn, | ||
313 | gk20a_get_gr_idle_timeout(g)); | ||
314 | if (err != 0) { | ||
315 | goto exit; | ||
316 | } | ||
317 | |||
318 | if (g->ops.pmu.setup_apertures != NULL) { | ||
319 | g->ops.pmu.setup_apertures(g); | ||
320 | } | ||
321 | |||
322 | if (g->ops.pmu.update_lspmu_cmdline_args != NULL) { | ||
323 | g->ops.pmu.update_lspmu_cmdline_args(g); | ||
324 | } | ||
325 | |||
326 | if (g->ops.pmu.pmu_enable_irq != NULL) { | ||
327 | nvgpu_mutex_acquire(&g->pmu.isr_mutex); | ||
328 | g->ops.pmu.pmu_enable_irq(&g->pmu, true); | ||
329 | g->pmu.isr_enabled = true; | ||
330 | nvgpu_mutex_release(&g->pmu.isr_mutex); | ||
331 | } | ||
332 | |||
333 | /*Once in LS mode, cpuctl_alias is only accessible*/ | ||
334 | if (g->ops.pmu.secured_pmu_start != NULL) { | ||
335 | g->ops.pmu.secured_pmu_start(g); | ||
336 | } | ||
337 | } else { | ||
338 | /* Do non-secure PMU boot */ | ||
339 | err = g->ops.pmu.pmu_setup_hw_and_bootstrap(g); | ||
340 | if (err != 0) { | ||
341 | goto exit; | ||
342 | } | ||
314 | } | 343 | } |
315 | 344 | ||
316 | nvgpu_pmu_state_change(g, PMU_STATE_STARTING, false); | 345 | nvgpu_pmu_state_change(g, PMU_STATE_STARTING, false); |
317 | } | 346 | } |
318 | 347 | ||
348 | exit: | ||
319 | return err; | 349 | return err; |
320 | } | 350 | } |
321 | 351 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 86cb04d9..f231e088 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -490,40 +490,6 @@ void gk20a_pmu_msgq_tail(struct nvgpu_pmu *pmu, u32 *tail, bool set) | |||
490 | } | 490 | } |
491 | } | 491 | } |
492 | 492 | ||
493 | int gk20a_init_pmu_setup_hw1(struct gk20a *g) | ||
494 | { | ||
495 | struct nvgpu_pmu *pmu = &g->pmu; | ||
496 | int err = 0; | ||
497 | |||
498 | nvgpu_log_fn(g, " "); | ||
499 | |||
500 | nvgpu_mutex_acquire(&pmu->isr_mutex); | ||
501 | nvgpu_flcn_reset(pmu->flcn); | ||
502 | pmu->isr_enabled = true; | ||
503 | nvgpu_mutex_release(&pmu->isr_mutex); | ||
504 | |||
505 | /* setup apertures - virtual */ | ||
506 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | ||
507 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
508 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), | ||
509 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
510 | /* setup apertures - physical */ | ||
511 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), | ||
512 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
513 | pwr_fbif_transcfg_target_local_fb_f()); | ||
514 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), | ||
515 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
516 | pwr_fbif_transcfg_target_coherent_sysmem_f()); | ||
517 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), | ||
518 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
519 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); | ||
520 | |||
521 | err = g->ops.pmu.pmu_nsbootstrap(pmu); | ||
522 | |||
523 | return err; | ||
524 | |||
525 | } | ||
526 | |||
527 | void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr) | 493 | void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr) |
528 | { | 494 | { |
529 | gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr); | 495 | gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr); |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 700a3a0e..35b80eaf 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -58,7 +58,6 @@ void gk20a_pmu_msgq_tail(struct nvgpu_pmu *pmu, u32 *tail, bool set); | |||
58 | u32 gk20a_pmu_read_idle_counter(struct gk20a *g, u32 counter_id); | 58 | u32 gk20a_pmu_read_idle_counter(struct gk20a *g, u32 counter_id); |
59 | void gk20a_pmu_reset_idle_counter(struct gk20a *g, u32 counter_id); | 59 | void gk20a_pmu_reset_idle_counter(struct gk20a *g, u32 counter_id); |
60 | 60 | ||
61 | int gk20a_init_pmu_setup_hw1(struct gk20a *g); | ||
62 | void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr); | 61 | void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr); |
63 | bool gk20a_is_pmu_supported(struct gk20a *g); | 62 | bool gk20a_is_pmu_supported(struct gk20a *g); |
64 | 63 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index a4657ff3..e38e9a85 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -1045,76 +1045,6 @@ int acr_ucode_patch_sig(struct gk20a *g, | |||
1045 | return 0; | 1045 | return 0; |
1046 | } | 1046 | } |
1047 | 1047 | ||
1048 | int gm20b_init_nspmu_setup_hw1(struct gk20a *g) | ||
1049 | { | ||
1050 | struct nvgpu_pmu *pmu = &g->pmu; | ||
1051 | int err = 0; | ||
1052 | |||
1053 | nvgpu_log_fn(g, " "); | ||
1054 | |||
1055 | nvgpu_mutex_acquire(&pmu->isr_mutex); | ||
1056 | nvgpu_flcn_reset(pmu->flcn); | ||
1057 | pmu->isr_enabled = true; | ||
1058 | nvgpu_mutex_release(&pmu->isr_mutex); | ||
1059 | |||
1060 | /* setup apertures - virtual */ | ||
1061 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | ||
1062 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
1063 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), | ||
1064 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
1065 | /* setup apertures - physical */ | ||
1066 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), | ||
1067 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
1068 | pwr_fbif_transcfg_target_local_fb_f()); | ||
1069 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), | ||
1070 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
1071 | pwr_fbif_transcfg_target_coherent_sysmem_f()); | ||
1072 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), | ||
1073 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
1074 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); | ||
1075 | |||
1076 | err = g->ops.pmu.pmu_nsbootstrap(pmu); | ||
1077 | |||
1078 | return err; | ||
1079 | } | ||
1080 | |||
1081 | void gm20b_setup_apertures(struct gk20a *g) | ||
1082 | { | ||
1083 | /* setup apertures - virtual */ | ||
1084 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | ||
1085 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
1086 | pwr_fbif_transcfg_target_local_fb_f()); | ||
1087 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), | ||
1088 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
1089 | /* setup apertures - physical */ | ||
1090 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), | ||
1091 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
1092 | pwr_fbif_transcfg_target_local_fb_f()); | ||
1093 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), | ||
1094 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
1095 | pwr_fbif_transcfg_target_coherent_sysmem_f()); | ||
1096 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), | ||
1097 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
1098 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); | ||
1099 | } | ||
1100 | |||
1101 | void gm20b_update_lspmu_cmdline_args(struct gk20a *g) | ||
1102 | { | ||
1103 | struct nvgpu_pmu *pmu = &g->pmu; | ||
1104 | /*Copying pmu cmdline args*/ | ||
1105 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, | ||
1106 | g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK)); | ||
1107 | g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1); | ||
1108 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_size( | ||
1109 | pmu, GK20A_PMU_TRACE_BUFSIZE); | ||
1110 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu); | ||
1111 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( | ||
1112 | pmu, GK20A_PMU_DMAIDX_VIRT); | ||
1113 | nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, | ||
1114 | (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), | ||
1115 | g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); | ||
1116 | } | ||
1117 | |||
1118 | static int nvgpu_gm20b_acr_wait_for_completion(struct gk20a *g, | 1048 | static int nvgpu_gm20b_acr_wait_for_completion(struct gk20a *g, |
1119 | struct nvgpu_falcon *flcn, unsigned int timeout) | 1049 | struct nvgpu_falcon *flcn, unsigned int timeout) |
1120 | { | 1050 | { |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h index cae6ab6a..fad40081 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h | |||
@@ -41,10 +41,6 @@ int gm20b_pmu_populate_loader_cfg(struct gk20a *g, | |||
41 | void *lsfm, u32 *p_bl_gen_desc_size); | 41 | void *lsfm, u32 *p_bl_gen_desc_size); |
42 | int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, | 42 | int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, |
43 | void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid); | 43 | void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid); |
44 | void gm20b_update_lspmu_cmdline_args(struct gk20a *g); | ||
45 | void gm20b_setup_apertures(struct gk20a *g); | ||
46 | int gm20b_pmu_setup_sw(struct gk20a *g); | ||
47 | int gm20b_init_nspmu_setup_hw1(struct gk20a *g); | ||
48 | 44 | ||
49 | int acr_ucode_patch_sig(struct gk20a *g, | 45 | int acr_ucode_patch_sig(struct gk20a *g, |
50 | unsigned int *p_img, | 46 | unsigned int *p_img, |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 52f86dab..133428da 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -735,7 +735,8 @@ int gm20b_init_hal(struct gk20a *g) | |||
735 | gm20b_flcn_populate_bl_dmem_desc; | 735 | gm20b_flcn_populate_bl_dmem_desc; |
736 | gops->pmu.update_lspmu_cmdline_args = | 736 | gops->pmu.update_lspmu_cmdline_args = |
737 | gm20b_update_lspmu_cmdline_args; | 737 | gm20b_update_lspmu_cmdline_args; |
738 | gops->pmu.setup_apertures = gm20b_setup_apertures; | 738 | gops->pmu.setup_apertures = gm20b_pmu_setup_apertures; |
739 | gops->pmu.secured_pmu_start = gm20b_secured_pmu_start; | ||
739 | 740 | ||
740 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | 741 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; |
741 | gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode; | 742 | gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode; |
@@ -745,6 +746,8 @@ int gm20b_init_hal(struct gk20a *g) | |||
745 | /* Inherit from gk20a */ | 746 | /* Inherit from gk20a */ |
746 | gops->pmu.is_pmu_supported = gk20a_is_pmu_supported; | 747 | gops->pmu.is_pmu_supported = gk20a_is_pmu_supported; |
747 | gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob; | 748 | gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob; |
749 | gops->pmu.pmu_setup_hw_and_bootstrap = | ||
750 | gm20b_ns_pmu_setup_hw_and_bootstrap; | ||
748 | gops->pmu.pmu_nsbootstrap = pmu_bootstrap; | 751 | gops->pmu.pmu_nsbootstrap = pmu_bootstrap; |
749 | 752 | ||
750 | gops->pmu.load_lsfalcon_ucode = NULL; | 753 | gops->pmu.load_lsfalcon_ucode = NULL; |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 6e764ac5..df0ae58d 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -278,6 +278,72 @@ bool gm20b_pmu_is_debug_mode_en(struct gk20a *g) | |||
278 | return pwr_pmu_scpctl_stat_debug_mode_v(ctl_stat) != 0U; | 278 | return pwr_pmu_scpctl_stat_debug_mode_v(ctl_stat) != 0U; |
279 | } | 279 | } |
280 | 280 | ||
281 | int gm20b_ns_pmu_setup_hw_and_bootstrap(struct gk20a *g) | ||
282 | { | ||
283 | struct nvgpu_pmu *pmu = &g->pmu; | ||
284 | |||
285 | nvgpu_log_fn(g, " "); | ||
286 | |||
287 | nvgpu_mutex_acquire(&pmu->isr_mutex); | ||
288 | nvgpu_flcn_reset(pmu->flcn); | ||
289 | pmu->isr_enabled = true; | ||
290 | nvgpu_mutex_release(&pmu->isr_mutex); | ||
291 | |||
292 | /* setup apertures - virtual */ | ||
293 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | ||
294 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
295 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), | ||
296 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
297 | /* setup apertures - physical */ | ||
298 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), | ||
299 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
300 | pwr_fbif_transcfg_target_local_fb_f()); | ||
301 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), | ||
302 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
303 | pwr_fbif_transcfg_target_coherent_sysmem_f()); | ||
304 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), | ||
305 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
306 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); | ||
307 | |||
308 | return g->ops.pmu.pmu_nsbootstrap(pmu); | ||
309 | } | ||
310 | |||
311 | void gm20b_pmu_setup_apertures(struct gk20a *g) | ||
312 | { | ||
313 | /* setup apertures - virtual */ | ||
314 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | ||
315 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
316 | pwr_fbif_transcfg_target_local_fb_f()); | ||
317 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), | ||
318 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
319 | /* setup apertures - physical */ | ||
320 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), | ||
321 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
322 | pwr_fbif_transcfg_target_local_fb_f()); | ||
323 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), | ||
324 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
325 | pwr_fbif_transcfg_target_coherent_sysmem_f()); | ||
326 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), | ||
327 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
328 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); | ||
329 | } | ||
330 | |||
331 | void gm20b_update_lspmu_cmdline_args(struct gk20a *g) | ||
332 | { | ||
333 | struct nvgpu_pmu *pmu = &g->pmu; | ||
334 | /*Copying pmu cmdline args*/ | ||
335 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, | ||
336 | g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK)); | ||
337 | g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1); | ||
338 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_size( | ||
339 | pmu, GK20A_PMU_TRACE_BUFSIZE); | ||
340 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu); | ||
341 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( | ||
342 | pmu, GK20A_PMU_DMAIDX_VIRT); | ||
343 | nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, | ||
344 | (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), | ||
345 | g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); | ||
346 | } | ||
281 | 347 | ||
282 | static int gm20b_bl_bootstrap(struct gk20a *g, | 348 | static int gm20b_bl_bootstrap(struct gk20a *g, |
283 | struct nvgpu_falcon_bl_info *bl_info) | 349 | struct nvgpu_falcon_bl_info *bl_info) |
@@ -337,3 +403,9 @@ int gm20b_pmu_setup_hw_and_bl_bootstrap(struct gk20a *g, | |||
337 | exit: | 403 | exit: |
338 | return err; | 404 | return err; |
339 | } | 405 | } |
406 | |||
407 | void gm20b_secured_pmu_start(struct gk20a *g) | ||
408 | { | ||
409 | gk20a_writel(g, pwr_falcon_cpuctl_alias_r(), | ||
410 | pwr_falcon_cpuctl_startcpu_f(1)); | ||
411 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h index 37634783..0e4968fb 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h | |||
@@ -34,7 +34,11 @@ void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags); | |||
34 | int gm20b_pmu_init_acr(struct gk20a *g); | 34 | int gm20b_pmu_init_acr(struct gk20a *g); |
35 | void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr); | 35 | void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr); |
36 | bool gm20b_pmu_is_debug_mode_en(struct gk20a *g); | 36 | bool gm20b_pmu_is_debug_mode_en(struct gk20a *g); |
37 | int gm20b_ns_pmu_setup_hw_and_bootstrap(struct gk20a *g); | ||
38 | void gm20b_pmu_setup_apertures(struct gk20a *g); | ||
39 | void gm20b_update_lspmu_cmdline_args(struct gk20a *g); | ||
37 | int gm20b_pmu_setup_hw_and_bl_bootstrap(struct gk20a *g, | 40 | int gm20b_pmu_setup_hw_and_bl_bootstrap(struct gk20a *g, |
38 | struct hs_acr *acr_desc, | 41 | struct hs_acr *acr_desc, |
39 | struct nvgpu_falcon_bl_info *bl_info); | 42 | struct nvgpu_falcon_bl_info *bl_info); |
43 | void gm20b_secured_pmu_start(struct gk20a *g); | ||
40 | #endif /*NVGPU_GM20B_PMU_GM20B_H*/ | 44 | #endif /*NVGPU_GM20B_PMU_GM20B_H*/ |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 048c0a45..3a2fa71d 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -658,6 +658,10 @@ static const struct gpu_ops gp106_ops = { | |||
658 | .get_irqdest = gk20a_pmu_get_irqdest, | 658 | .get_irqdest = gk20a_pmu_get_irqdest, |
659 | .alloc_super_surface = NULL, | 659 | .alloc_super_surface = NULL, |
660 | .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, | 660 | .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, |
661 | .update_lspmu_cmdline_args = | ||
662 | gp106_update_lspmu_cmdline_args, | ||
663 | .setup_apertures = gp106_pmu_setup_apertures, | ||
664 | .secured_pmu_start = gm20b_secured_pmu_start, | ||
661 | }, | 665 | }, |
662 | .clk = { | 666 | .clk = { |
663 | .init_clk_support = gp106_init_clk_support, | 667 | .init_clk_support = gp106_init_clk_support, |
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c index 031ac7d8..3e4a7390 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c | |||
@@ -306,3 +306,61 @@ int gp106_load_falcon_ucode(struct gk20a *g, u32 falconidmask) | |||
306 | } | 306 | } |
307 | return 0; | 307 | return 0; |
308 | } | 308 | } |
309 | |||
310 | void gp106_update_lspmu_cmdline_args(struct gk20a *g) | ||
311 | { | ||
312 | struct nvgpu_pmu *pmu = &g->pmu; | ||
313 | |||
314 | /*Copying pmu cmdline args*/ | ||
315 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, 0); | ||
316 | g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1); | ||
317 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_size( | ||
318 | pmu, GK20A_PMU_TRACE_BUFSIZE); | ||
319 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu); | ||
320 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( | ||
321 | pmu, GK20A_PMU_DMAIDX_VIRT); | ||
322 | if (g->ops.pmu_ver.config_pmu_cmdline_args_super_surface) { | ||
323 | g->ops.pmu_ver.config_pmu_cmdline_args_super_surface(pmu); | ||
324 | } | ||
325 | |||
326 | nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, | ||
327 | (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), | ||
328 | g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); | ||
329 | |||
330 | } | ||
331 | |||
332 | void gp106_pmu_setup_apertures(struct gk20a *g) | ||
333 | { | ||
334 | struct mm_gk20a *mm = &g->mm; | ||
335 | |||
336 | /* PMU TRANSCFG */ | ||
337 | /* setup apertures - virtual */ | ||
338 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | ||
339 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
340 | pwr_fbif_transcfg_target_local_fb_f()); | ||
341 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), | ||
342 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
343 | /* setup apertures - physical */ | ||
344 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), | ||
345 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
346 | pwr_fbif_transcfg_target_local_fb_f()); | ||
347 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), | ||
348 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
349 | pwr_fbif_transcfg_target_coherent_sysmem_f()); | ||
350 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), | ||
351 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
352 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); | ||
353 | |||
354 | /* PMU Config */ | ||
355 | gk20a_writel(g, pwr_falcon_itfen_r(), | ||
356 | gk20a_readl(g, pwr_falcon_itfen_r()) | | ||
357 | pwr_falcon_itfen_ctxen_enable_f()); | ||
358 | gk20a_writel(g, pwr_pmu_new_instblk_r(), | ||
359 | pwr_pmu_new_instblk_ptr_f( | ||
360 | nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | | ||
361 | pwr_pmu_new_instblk_valid_f(1) | | ||
362 | nvgpu_aperture_mask(g, &mm->pmu.inst_block, | ||
363 | pwr_pmu_new_instblk_target_sys_ncoh_f(), | ||
364 | pwr_pmu_new_instblk_target_sys_coh_f(), | ||
365 | pwr_pmu_new_instblk_target_fb_f())); | ||
366 | } | ||
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.h b/drivers/gpu/nvgpu/gp106/pmu_gp106.h index 9cf1202e..c9392d7b 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.h +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.h | |||
@@ -41,5 +41,7 @@ void gp106_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, | |||
41 | struct pmu_pg_stats_data *pg_stat_data); | 41 | struct pmu_pg_stats_data *pg_stat_data); |
42 | bool gp106_pmu_is_engine_in_reset(struct gk20a *g); | 42 | bool gp106_pmu_is_engine_in_reset(struct gk20a *g); |
43 | int gp106_pmu_engine_reset(struct gk20a *g, bool do_reset); | 43 | int gp106_pmu_engine_reset(struct gk20a *g, bool do_reset); |
44 | void gp106_update_lspmu_cmdline_args(struct gk20a *g); | ||
45 | void gp106_pmu_setup_apertures(struct gk20a *g); | ||
44 | 46 | ||
45 | #endif /* NVGPU_PMU_GP106_H */ | 47 | #endif /* NVGPU_PMU_GP106_H */ |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 759d271e..740cb8b7 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -794,7 +794,8 @@ int gp10b_init_hal(struct gk20a *g) | |||
794 | gm20b_flcn_populate_bl_dmem_desc, | 794 | gm20b_flcn_populate_bl_dmem_desc, |
795 | gops->pmu.update_lspmu_cmdline_args = | 795 | gops->pmu.update_lspmu_cmdline_args = |
796 | gm20b_update_lspmu_cmdline_args; | 796 | gm20b_update_lspmu_cmdline_args; |
797 | gops->pmu.setup_apertures = gm20b_setup_apertures; | 797 | gops->pmu.setup_apertures = gm20b_pmu_setup_apertures; |
798 | gops->pmu.secured_pmu_start = gm20b_secured_pmu_start; | ||
798 | 799 | ||
799 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | 800 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; |
800 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; | 801 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; |
@@ -806,6 +807,8 @@ int gp10b_init_hal(struct gk20a *g) | |||
806 | /* Inherit from gk20a */ | 807 | /* Inherit from gk20a */ |
807 | gops->pmu.is_pmu_supported = gk20a_is_pmu_supported, | 808 | gops->pmu.is_pmu_supported = gk20a_is_pmu_supported, |
808 | gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, | 809 | gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, |
810 | gops->pmu.pmu_setup_hw_and_bootstrap = | ||
811 | gm20b_ns_pmu_setup_hw_and_bootstrap; | ||
809 | gops->pmu.pmu_nsbootstrap = pmu_bootstrap, | 812 | gops->pmu.pmu_nsbootstrap = pmu_bootstrap, |
810 | 813 | ||
811 | gops->pmu.load_lsfalcon_ucode = NULL; | 814 | gops->pmu.load_lsfalcon_ucode = NULL; |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 5c7d1523..d268ab88 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -304,45 +304,6 @@ void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr) | |||
304 | 0x0); | 304 | 0x0); |
305 | } | 305 | } |
306 | 306 | ||
307 | int gp10b_init_pmu_setup_hw1(struct gk20a *g) | ||
308 | { | ||
309 | struct nvgpu_pmu *pmu = &g->pmu; | ||
310 | int err; | ||
311 | |||
312 | nvgpu_log_fn(g, " "); | ||
313 | |||
314 | nvgpu_mutex_acquire(&pmu->isr_mutex); | ||
315 | nvgpu_flcn_reset(pmu->flcn); | ||
316 | pmu->isr_enabled = true; | ||
317 | nvgpu_mutex_release(&pmu->isr_mutex); | ||
318 | |||
319 | /* setup apertures - virtual */ | ||
320 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | ||
321 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
322 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), | ||
323 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
324 | |||
325 | /* setup apertures - physical */ | ||
326 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), | ||
327 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
328 | pwr_fbif_transcfg_target_local_fb_f()); | ||
329 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), | ||
330 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
331 | pwr_fbif_transcfg_target_coherent_sysmem_f()); | ||
332 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), | ||
333 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
334 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); | ||
335 | |||
336 | err = g->ops.pmu.pmu_nsbootstrap(pmu); | ||
337 | if (err) { | ||
338 | return err; | ||
339 | } | ||
340 | |||
341 | nvgpu_log_fn(g, "done"); | ||
342 | return 0; | ||
343 | |||
344 | } | ||
345 | |||
346 | bool gp10b_is_lazy_bootstrap(u32 falcon_id) | 307 | bool gp10b_is_lazy_bootstrap(u32 falcon_id) |
347 | { | 308 | { |
348 | bool enable_status = false; | 309 | bool enable_status = false; |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h index 87c3ba79..4fd4c7c4 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B PMU | 2 | * GP10B PMU |
3 | * | 3 | * |
4 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -31,7 +31,6 @@ struct gk20a; | |||
31 | bool gp10b_is_lazy_bootstrap(u32 falcon_id); | 31 | bool gp10b_is_lazy_bootstrap(u32 falcon_id); |
32 | bool gp10b_is_priv_load(u32 falcon_id); | 32 | bool gp10b_is_priv_load(u32 falcon_id); |
33 | bool gp10b_is_pmu_supported(struct gk20a *g); | 33 | bool gp10b_is_pmu_supported(struct gk20a *g); |
34 | int gp10b_init_pmu_setup_hw1(struct gk20a *g); | ||
35 | void gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, | 34 | void gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, |
36 | struct pmu_pg_stats_data *pg_stat_data); | 35 | struct pmu_pg_stats_data *pg_stat_data); |
37 | int gp10b_pmu_setup_elpg(struct gk20a *g); | 36 | int gp10b_pmu_setup_elpg(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 45c3adb3..99ee2d10 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -757,6 +757,10 @@ static const struct gpu_ops gv100_ops = { | |||
757 | .get_irqdest = gk20a_pmu_get_irqdest, | 757 | .get_irqdest = gk20a_pmu_get_irqdest, |
758 | .alloc_super_surface = nvgpu_pmu_super_surface_alloc, | 758 | .alloc_super_surface = nvgpu_pmu_super_surface_alloc, |
759 | .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, | 759 | .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en, |
760 | .update_lspmu_cmdline_args = | ||
761 | gp106_update_lspmu_cmdline_args, | ||
762 | .setup_apertures = gp106_pmu_setup_apertures, | ||
763 | .secured_pmu_start = gm20b_secured_pmu_start, | ||
760 | }, | 764 | }, |
761 | .clk = { | 765 | .clk = { |
762 | .init_clk_support = gp106_init_clk_support, | 766 | .init_clk_support = gp106_init_clk_support, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 18b00ea4..665e2ed1 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -888,6 +888,7 @@ int gv11b_init_hal(struct gk20a *g) | |||
888 | gops->pmu.update_lspmu_cmdline_args = | 888 | gops->pmu.update_lspmu_cmdline_args = |
889 | gm20b_update_lspmu_cmdline_args; | 889 | gm20b_update_lspmu_cmdline_args; |
890 | gops->pmu.setup_apertures = gv11b_setup_apertures; | 890 | gops->pmu.setup_apertures = gv11b_setup_apertures; |
891 | gops->pmu.secured_pmu_start = gm20b_secured_pmu_start; | ||
891 | 892 | ||
892 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | 893 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; |
893 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; | 894 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; |
@@ -898,6 +899,8 @@ int gv11b_init_hal(struct gk20a *g) | |||
898 | } else { | 899 | } else { |
899 | /* Inherit from gk20a */ | 900 | /* Inherit from gk20a */ |
900 | gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, | 901 | gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, |
902 | gops->pmu.pmu_setup_hw_and_bootstrap = | ||
903 | gm20b_ns_pmu_setup_hw_and_bootstrap; | ||
901 | 904 | ||
902 | gops->pmu.load_lsfalcon_ucode = NULL; | 905 | gops->pmu.load_lsfalcon_ucode = NULL; |
903 | gops->pmu.init_wpr_region = NULL; | 906 | gops->pmu.init_wpr_region = NULL; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 892aa9af..d0f51055 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h | |||
@@ -1066,6 +1066,7 @@ struct gpu_ops { | |||
1066 | int (*alloc_super_surface)(struct gk20a *g, | 1066 | int (*alloc_super_surface)(struct gk20a *g, |
1067 | struct nvgpu_mem *super_surface, u32 size); | 1067 | struct nvgpu_mem *super_surface, u32 size); |
1068 | bool (*is_debug_mode_enabled)(struct gk20a *g); | 1068 | bool (*is_debug_mode_enabled)(struct gk20a *g); |
1069 | void (*secured_pmu_start)(struct gk20a *g); | ||
1069 | } pmu; | 1070 | } pmu; |
1070 | struct { | 1071 | struct { |
1071 | int (*init_debugfs)(struct gk20a *g); | 1072 | int (*init_debugfs)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 9b3b4ed5..78aef699 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -614,6 +614,10 @@ int vgpu_gp10b_init_hal(struct gk20a *g) | |||
614 | gm20b_pmu_populate_loader_cfg, | 614 | gm20b_pmu_populate_loader_cfg, |
615 | gops->pmu.flcn_populate_bl_dmem_desc = | 615 | gops->pmu.flcn_populate_bl_dmem_desc = |
616 | gm20b_flcn_populate_bl_dmem_desc, | 616 | gm20b_flcn_populate_bl_dmem_desc, |
617 | gops->pmu.update_lspmu_cmdline_args = | ||
618 | gm20b_update_lspmu_cmdline_args; | ||
619 | gops->pmu.setup_apertures = gm20b_pmu_setup_apertures; | ||
620 | gops->pmu.secured_pmu_start = gm20b_secured_pmu_start; | ||
617 | 621 | ||
618 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | 622 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; |
619 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; | 623 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; |
@@ -625,6 +629,8 @@ int vgpu_gp10b_init_hal(struct gk20a *g) | |||
625 | /* Inherit from gk20a */ | 629 | /* Inherit from gk20a */ |
626 | gops->pmu.is_pmu_supported = gk20a_is_pmu_supported, | 630 | gops->pmu.is_pmu_supported = gk20a_is_pmu_supported, |
627 | gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, | 631 | gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, |
632 | gops->pmu.pmu_setup_hw_and_bootstrap = | ||
633 | gm20b_ns_pmu_setup_hw_and_bootstrap; | ||
628 | gops->pmu.pmu_nsbootstrap = pmu_bootstrap, | 634 | gops->pmu.pmu_nsbootstrap = pmu_bootstrap, |
629 | 635 | ||
630 | gops->pmu.load_lsfalcon_ucode = NULL; | 636 | gops->pmu.load_lsfalcon_ucode = NULL; |