diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 19 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c | 3 |
8 files changed, 20 insertions, 42 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 55d6f72c..4a1609d6 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -30,11 +30,6 @@ struct nvgpu_firmware; | |||
30 | 30 | ||
31 | #define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe) | 31 | #define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe) |
32 | 32 | ||
33 | /*Fuse defines*/ | ||
34 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) | ||
35 | #define FUSE_GCPLEX_CONFIG_FUSE_0 0x2C8 | ||
36 | #endif | ||
37 | |||
38 | bool gk20a_pmu_is_interrupted(struct nvgpu_pmu *pmu); | 33 | bool gk20a_pmu_is_interrupted(struct nvgpu_pmu *pmu); |
39 | void gk20a_pmu_isr(struct gk20a *g); | 34 | void gk20a_pmu_isr(struct gk20a *g); |
40 | 35 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index ceeb457a..8dfc5636 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -240,8 +240,6 @@ found_match: | |||
240 | 240 | ||
241 | /* GPCPLL NA/DVFS mode methods */ | 241 | /* GPCPLL NA/DVFS mode methods */ |
242 | 242 | ||
243 | #define FUSE_RESERVED_CALIB 0x204 | ||
244 | |||
245 | static inline int fuse_get_gpcpll_adc_rev(u32 val) | 243 | static inline int fuse_get_gpcpll_adc_rev(u32 val) |
246 | { | 244 | { |
247 | return (val >> 30) & 0x3; | 245 | return (val >> 30) & 0x3; |
@@ -264,7 +262,7 @@ static int nvgpu_fuse_calib_gpcpll_get_adc(int *slope_uv, int *intercept_uv) | |||
264 | u32 val; | 262 | u32 val; |
265 | int ret; | 263 | int ret; |
266 | 264 | ||
267 | ret = nvgpu_tegra_fuse_read(FUSE_RESERVED_CALIB, &val); | 265 | ret = nvgpu_tegra_fuse_read_reserved_calib(&val); |
268 | if (ret) | 266 | if (ret) |
269 | return ret; | 267 | return ret; |
270 | 268 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index c6e451e1..b7fb1ac5 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -13,14 +13,13 @@ | |||
13 | * more details. | 13 | * more details. |
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <soc/tegra/fuse.h> | ||
17 | |||
18 | #include <dt-bindings/soc/gm20b-fuse.h> | 16 | #include <dt-bindings/soc/gm20b-fuse.h> |
19 | 17 | ||
20 | #include <nvgpu/kmem.h> | 18 | #include <nvgpu/kmem.h> |
21 | #include <nvgpu/log.h> | 19 | #include <nvgpu/log.h> |
22 | #include <nvgpu/enabled.h> | 20 | #include <nvgpu/enabled.h> |
23 | #include <nvgpu/debug.h> | 21 | #include <nvgpu/debug.h> |
22 | #include <nvgpu/fuse.h> | ||
24 | 23 | ||
25 | #include "gk20a/gk20a.h" | 24 | #include "gk20a/gk20a.h" |
26 | #include "gk20a/gr_gk20a.h" | 25 | #include "gk20a/gr_gk20a.h" |
@@ -548,18 +547,18 @@ static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | |||
548 | 547 | ||
549 | static void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 548 | static void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
550 | { | 549 | { |
551 | tegra_fuse_control_write(0x1, FUSE_FUSEBYPASS_0); | 550 | nvgpu_tegra_fuse_write_bypass(0x1); |
552 | tegra_fuse_control_write(0x0, FUSE_WRITE_ACCESS_SW_0); | 551 | nvgpu_tegra_fuse_write_access_sw(0x0); |
553 | 552 | ||
554 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) { | 553 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) { |
555 | tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); | 554 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0); |
556 | tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC1_DISABLE_0); | 555 | nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x1); |
557 | } else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) { | 556 | } else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) { |
558 | tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0); | 557 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x1); |
559 | tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC1_DISABLE_0); | 558 | nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x0); |
560 | } else { | 559 | } else { |
561 | tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); | 560 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0); |
562 | tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC1_DISABLE_0); | 561 | nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x0); |
563 | } | 562 | } |
564 | } | 563 | } |
565 | 564 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index b94259c5..e7dd091a 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |||
@@ -28,14 +28,6 @@ enum { | |||
28 | MAXWELL_CHANNEL_GPFIFO_A= 0xB06F, | 28 | MAXWELL_CHANNEL_GPFIFO_A= 0xB06F, |
29 | }; | 29 | }; |
30 | 30 | ||
31 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) | ||
32 | #define tegra_fuse_control_write tegra_fuse_writel | ||
33 | #define FUSE_FUSEBYPASS_0 0x24 | ||
34 | #define FUSE_WRITE_ACCESS_SW_0 0x30 | ||
35 | #define FUSE_OPT_GPU_TPC0_DISABLE_0 0x30C | ||
36 | #define FUSE_OPT_GPU_TPC1_DISABLE_0 0x33C | ||
37 | #endif | ||
38 | |||
39 | #define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc | 31 | #define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc |
40 | #define NVB197_SET_CIRCULAR_BUFFER_SIZE 0x1280 | 32 | #define NVB197_SET_CIRCULAR_BUFFER_SIZE 0x1280 |
41 | #define NVB197_SET_SHADER_EXCEPTIONS 0x1528 | 33 | #define NVB197_SET_SHADER_EXCEPTIONS 0x1528 |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index d501163f..5609a8cc 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -13,10 +13,9 @@ | |||
13 | * more details. | 13 | * more details. |
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <soc/tegra/fuse.h> | ||
17 | |||
18 | #include <nvgpu/timers.h> | 16 | #include <nvgpu/timers.h> |
19 | #include <nvgpu/pmu.h> | 17 | #include <nvgpu/pmu.h> |
18 | #include <nvgpu/fuse.h> | ||
20 | 19 | ||
21 | #include "gk20a/gk20a.h" | 20 | #include "gk20a/gk20a.h" |
22 | #include "gk20a/pmu_gk20a.h" | 21 | #include "gk20a/pmu_gk20a.h" |
@@ -269,7 +268,7 @@ static void pmu_dump_security_fuses_gm20b(struct gk20a *g) | |||
269 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); | 268 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); |
270 | nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", | 269 | nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", |
271 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); | 270 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); |
272 | tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val); | 271 | nvgpu_tegra_fuse_read_gcplex_config_fuse(&val); |
273 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", | 272 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", |
274 | val); | 273 | val); |
275 | } | 274 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 9a30ad7c..3bddef4c 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -13,8 +13,6 @@ | |||
13 | * more details. | 13 | * more details. |
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <soc/tegra/fuse.h> | ||
17 | |||
18 | #include <dt-bindings/soc/gm20b-fuse.h> | 16 | #include <dt-bindings/soc/gm20b-fuse.h> |
19 | #include <dt-bindings/soc/gp10b-fuse.h> | 17 | #include <dt-bindings/soc/gp10b-fuse.h> |
20 | 18 | ||
@@ -24,6 +22,7 @@ | |||
24 | #include <nvgpu/dma.h> | 22 | #include <nvgpu/dma.h> |
25 | #include <nvgpu/bug.h> | 23 | #include <nvgpu/bug.h> |
26 | #include <nvgpu/debug.h> | 24 | #include <nvgpu/debug.h> |
25 | #include <nvgpu/fuse.h> | ||
27 | 26 | ||
28 | #include "gk20a/gk20a.h" | 27 | #include "gk20a/gk20a.h" |
29 | #include "gk20a/gr_gk20a.h" | 28 | #include "gk20a/gr_gk20a.h" |
@@ -1571,15 +1570,15 @@ static void gr_gp10b_init_cyclestats(struct gk20a *g) | |||
1571 | 1570 | ||
1572 | static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 1571 | static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
1573 | { | 1572 | { |
1574 | tegra_fuse_control_write(0x1, FUSE_FUSEBYPASS_0); | 1573 | nvgpu_tegra_fuse_write_bypass(0x1); |
1575 | tegra_fuse_control_write(0x0, FUSE_WRITE_ACCESS_SW_0); | 1574 | nvgpu_tegra_fuse_write_access_sw(0x0); |
1576 | 1575 | ||
1577 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) | 1576 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) |
1578 | tegra_fuse_control_write(0x2, FUSE_OPT_GPU_TPC0_DISABLE_0); | 1577 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x2); |
1579 | else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) | 1578 | else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) |
1580 | tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0); | 1579 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x1); |
1581 | else | 1580 | else |
1582 | tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); | 1581 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0); |
1583 | } | 1582 | } |
1584 | 1583 | ||
1585 | static void gr_gp10b_get_access_map(struct gk20a *g, | 1584 | static void gr_gp10b_get_access_map(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index cd6bf97a..2222cc17 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -13,10 +13,9 @@ | |||
13 | * more details. | 13 | * more details. |
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <soc/tegra/fuse.h> | ||
17 | |||
18 | #include <nvgpu/pmu.h> | 16 | #include <nvgpu/pmu.h> |
19 | #include <nvgpu/log.h> | 17 | #include <nvgpu/log.h> |
18 | #include <nvgpu/fuse.h> | ||
20 | 19 | ||
21 | #include "gk20a/gk20a.h" | 20 | #include "gk20a/gk20a.h" |
22 | #include "gk20a/pmu_gk20a.h" | 21 | #include "gk20a/pmu_gk20a.h" |
@@ -383,7 +382,7 @@ static void pmu_dump_security_fuses_gp10b(struct gk20a *g) | |||
383 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); | 382 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); |
384 | nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", | 383 | nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", |
385 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); | 384 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); |
386 | tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val); | 385 | nvgpu_tegra_fuse_read_gcplex_config_fuse(&val); |
387 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", | 386 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", |
388 | val); | 387 | val); |
389 | } | 388 | } |
diff --git a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c index f55ea6d2..3d5ea698 100644 --- a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c +++ b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c | |||
@@ -32,9 +32,6 @@ | |||
32 | #if defined(CONFIG_COMMON_CLK) | 32 | #if defined(CONFIG_COMMON_CLK) |
33 | #include <soc/tegra/tegra-dvfs.h> | 33 | #include <soc/tegra/tegra-dvfs.h> |
34 | #endif | 34 | #endif |
35 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) | ||
36 | #include <soc/tegra/fuse.h> | ||
37 | #endif | ||
38 | #ifdef CONFIG_TEGRA_BWMGR | 35 | #ifdef CONFIG_TEGRA_BWMGR |
39 | #include <linux/platform/tegra/emc_bwmgr.h> | 36 | #include <linux/platform/tegra/emc_bwmgr.h> |
40 | #endif | 37 | #endif |