diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/module.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/pci.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ltc_common.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/platform_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/therm_gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c | 17 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/vgpu.c | 5 |
17 files changed, 34 insertions, 56 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/module.c b/drivers/gpu/nvgpu/common/linux/module.c index 2cbf996b..8747c632 100644 --- a/drivers/gpu/nvgpu/common/linux/module.c +++ b/drivers/gpu/nvgpu/common/linux/module.c | |||
@@ -212,11 +212,6 @@ static int gk20a_pm_prepare_poweroff(struct device *dev) | |||
212 | if (g->irq_stall != g->irq_nonstall) | 212 | if (g->irq_stall != g->irq_nonstall) |
213 | disable_irq(g->irq_nonstall); | 213 | disable_irq(g->irq_nonstall); |
214 | 214 | ||
215 | /* | ||
216 | * is_fmodel needs to be in gk20a struct for deferred teardown | ||
217 | */ | ||
218 | g->is_fmodel = platform->is_fmodel; | ||
219 | |||
220 | /* Decrement platform power refcount */ | 215 | /* Decrement platform power refcount */ |
221 | if (platform->idle) | 216 | if (platform->idle) |
222 | platform->idle(dev); | 217 | platform->idle(dev); |
@@ -885,7 +880,7 @@ static int gk20a_probe(struct platform_device *dev) | |||
885 | gk20a->dev = &dev->dev; | 880 | gk20a->dev = &dev->dev; |
886 | 881 | ||
887 | if (nvgpu_platform_is_simulation(gk20a)) | 882 | if (nvgpu_platform_is_simulation(gk20a)) |
888 | platform->is_fmodel = true; | 883 | gk20a->is_fmodel = true; |
889 | 884 | ||
890 | nvgpu_kmem_init(gk20a); | 885 | nvgpu_kmem_init(gk20a); |
891 | 886 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/pci.c b/drivers/gpu/nvgpu/common/linux/pci.c index f90b3a6e..0bad2b67 100644 --- a/drivers/gpu/nvgpu/common/linux/pci.c +++ b/drivers/gpu/nvgpu/common/linux/pci.c | |||
@@ -402,11 +402,6 @@ static int nvgpu_pci_probe(struct pci_dev *pdev, | |||
402 | } | 402 | } |
403 | disable_irq(g->irq_stall); | 403 | disable_irq(g->irq_stall); |
404 | 404 | ||
405 | /* | ||
406 | * is_fmodel needs to be in gk20a struct for deferred teardown | ||
407 | */ | ||
408 | g->is_fmodel = platform->is_fmodel; | ||
409 | |||
410 | err = nvgpu_pci_init_support(pdev); | 405 | err = nvgpu_pci_init_support(pdev); |
411 | if (err) | 406 | if (err) |
412 | return err; | 407 | return err; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c index 3c6d8924..32c95e2f 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c | |||
@@ -442,9 +442,7 @@ done: | |||
442 | 442 | ||
443 | int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr) | 443 | int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr) |
444 | { | 444 | { |
445 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | 445 | if (g->is_fmodel) |
446 | |||
447 | if (platform->is_fmodel) | ||
448 | return gr_gk20a_init_ctx_vars_sim(g, gr); | 446 | return gr_gk20a_init_ctx_vars_sim(g, gr); |
449 | else | 447 | else |
450 | return gr_gk20a_init_ctx_vars_fw(g, gr); | 448 | return gr_gk20a_init_ctx_vars_fw(g, gr); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 0e787356..22093a34 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -380,10 +380,9 @@ int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long duration_ms, | |||
380 | { | 380 | { |
381 | u32 val; | 381 | u32 val; |
382 | u32 delay = expect_delay; | 382 | u32 delay = expect_delay; |
383 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
384 | struct nvgpu_timeout timeout; | 383 | struct nvgpu_timeout timeout; |
385 | 384 | ||
386 | if (platform->is_fmodel) | 385 | if (g->is_fmodel) |
387 | return 0; | 386 | return 0; |
388 | 387 | ||
389 | gk20a_dbg_fn(""); | 388 | gk20a_dbg_fn(""); |
@@ -1581,7 +1580,6 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1581 | struct aiv_list_gk20a *sw_ctx_load = &g->gr.ctx_vars.sw_ctx_load; | 1580 | struct aiv_list_gk20a *sw_ctx_load = &g->gr.ctx_vars.sw_ctx_load; |
1582 | struct av_list_gk20a *sw_method_init = &g->gr.ctx_vars.sw_method_init; | 1581 | struct av_list_gk20a *sw_method_init = &g->gr.ctx_vars.sw_method_init; |
1583 | u32 last_method_data = 0; | 1582 | u32 last_method_data = 0; |
1584 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
1585 | struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; | 1583 | struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; |
1586 | struct nvgpu_mem *ctxheader = &ctx->mem; | 1584 | struct nvgpu_mem *ctxheader = &ctx->mem; |
1587 | 1585 | ||
@@ -1595,7 +1593,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1595 | if (gr->ctx_vars.golden_image_initialized) { | 1593 | if (gr->ctx_vars.golden_image_initialized) { |
1596 | goto clean_up; | 1594 | goto clean_up; |
1597 | } | 1595 | } |
1598 | if (!platform->is_fmodel) { | 1596 | if (!g->is_fmodel) { |
1599 | struct nvgpu_timeout timeout; | 1597 | struct nvgpu_timeout timeout; |
1600 | 1598 | ||
1601 | nvgpu_timeout_init(g, &timeout, FE_PWR_MODE_TIMEOUT_MAX / 1000, | 1599 | nvgpu_timeout_init(g, &timeout, FE_PWR_MODE_TIMEOUT_MAX / 1000, |
@@ -1638,7 +1636,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1638 | gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r()); | 1636 | gk20a_readl(g, gr_fecs_ctxsw_reset_ctl_r()); |
1639 | nvgpu_udelay(10); | 1637 | nvgpu_udelay(10); |
1640 | 1638 | ||
1641 | if (!platform->is_fmodel) { | 1639 | if (!g->is_fmodel) { |
1642 | struct nvgpu_timeout timeout; | 1640 | struct nvgpu_timeout timeout; |
1643 | 1641 | ||
1644 | nvgpu_timeout_init(g, &timeout, FE_PWR_MODE_TIMEOUT_MAX / 1000, | 1642 | nvgpu_timeout_init(g, &timeout, FE_PWR_MODE_TIMEOUT_MAX / 1000, |
@@ -2580,11 +2578,10 @@ static void gr_gk20a_load_falcon_with_bootloader(struct gk20a *g) | |||
2580 | int gr_gk20a_load_ctxsw_ucode(struct gk20a *g) | 2578 | int gr_gk20a_load_ctxsw_ucode(struct gk20a *g) |
2581 | { | 2579 | { |
2582 | int err; | 2580 | int err; |
2583 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
2584 | 2581 | ||
2585 | gk20a_dbg_fn(""); | 2582 | gk20a_dbg_fn(""); |
2586 | 2583 | ||
2587 | if (platform->is_fmodel) { | 2584 | if (g->is_fmodel) { |
2588 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7), | 2585 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7), |
2589 | gr_fecs_ctxsw_mailbox_value_f(0xc0de7777)); | 2586 | gr_fecs_ctxsw_mailbox_value_f(0xc0de7777)); |
2590 | gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7), | 2587 | gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7), |
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_common.c b/drivers/gpu/nvgpu/gk20a/ltc_common.c index 6162d420..b92dda6d 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_common.c +++ b/drivers/gpu/nvgpu/gk20a/ltc_common.c | |||
@@ -91,9 +91,8 @@ static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) | |||
91 | u64 compbit_base_post_multiply64; | 91 | u64 compbit_base_post_multiply64; |
92 | u64 compbit_store_iova; | 92 | u64 compbit_store_iova; |
93 | u64 compbit_base_post_divide64; | 93 | u64 compbit_base_post_divide64; |
94 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
95 | 94 | ||
96 | if (platform->is_fmodel) | 95 | if (g->is_fmodel) |
97 | compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem); | 96 | compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem); |
98 | else | 97 | else |
99 | compbit_store_iova = g->ops.mm.get_iova_addr(g, | 98 | compbit_store_iova = g->ops.mm.get_iova_addr(g, |
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c index d8d9226c..4bd8f816 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | |||
@@ -49,7 +49,6 @@ static int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
49 | u32 compbit_backing_size; | 49 | u32 compbit_backing_size; |
50 | 50 | ||
51 | int err; | 51 | int err; |
52 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
53 | 52 | ||
54 | gk20a_dbg_fn(""); | 53 | gk20a_dbg_fn(""); |
55 | 54 | ||
@@ -83,7 +82,7 @@ static int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
83 | gk20a_dbg_info("max comptag lines : %d", | 82 | gk20a_dbg_info("max comptag lines : %d", |
84 | max_comptag_lines); | 83 | max_comptag_lines); |
85 | 84 | ||
86 | if (platform->is_fmodel) | 85 | if (g->is_fmodel) |
87 | err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); | 86 | err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); |
88 | else | 87 | else |
89 | err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); | 88 | err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); |
diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h index 4bdbda43..1115a5fb 100644 --- a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h | |||
@@ -39,9 +39,6 @@ struct gk20a_platform { | |||
39 | struct gk20a *g; | 39 | struct gk20a *g; |
40 | 40 | ||
41 | /* Should be populated at probe. */ | 41 | /* Should be populated at probe. */ |
42 | bool is_fmodel; | ||
43 | |||
44 | /* Should be populated at probe. */ | ||
45 | bool can_railgate; | 42 | bool can_railgate; |
46 | 43 | ||
47 | /* Set by User while disabling railgating */ | 44 | /* Set by User while disabling railgating */ |
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c index 07cdc9e5..1584ffda 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | |||
@@ -28,9 +28,7 @@ | |||
28 | 28 | ||
29 | void gk20a_enable_priv_ring(struct gk20a *g) | 29 | void gk20a_enable_priv_ring(struct gk20a *g) |
30 | { | 30 | { |
31 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | 31 | if (g->is_fmodel) |
32 | |||
33 | if (platform->is_fmodel) | ||
34 | return; | 32 | return; |
35 | 33 | ||
36 | if (g->ops.clock_gating.slcg_priring_load_gating_prod) | 34 | if (g->ops.clock_gating.slcg_priring_load_gating_prod) |
@@ -75,9 +73,8 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
75 | s32 retry = 100; | 73 | s32 retry = 100; |
76 | u32 gpc; | 74 | u32 gpc; |
77 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | 75 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); |
78 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
79 | 76 | ||
80 | if (platform->is_fmodel) | 77 | if (g->is_fmodel) |
81 | return; | 78 | return; |
82 | 79 | ||
83 | status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); | 80 | status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); |
diff --git a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c b/drivers/gpu/nvgpu/gk20a/therm_gk20a.c index 234c2937..0d2f1281 100644 --- a/drivers/gpu/nvgpu/gk20a/therm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/therm_gk20a.c | |||
@@ -117,7 +117,6 @@ int gk20a_elcg_init_idle_filters(struct gk20a *g) | |||
117 | u32 engine_id; | 117 | u32 engine_id; |
118 | u32 active_engine_id = 0; | 118 | u32 active_engine_id = 0; |
119 | struct fifo_gk20a *f = &g->fifo; | 119 | struct fifo_gk20a *f = &g->fifo; |
120 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
121 | 120 | ||
122 | gk20a_dbg_fn(""); | 121 | gk20a_dbg_fn(""); |
123 | 122 | ||
@@ -125,7 +124,7 @@ int gk20a_elcg_init_idle_filters(struct gk20a *g) | |||
125 | active_engine_id = f->active_engines_list[engine_id]; | 124 | active_engine_id = f->active_engines_list[engine_id]; |
126 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id)); | 125 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id)); |
127 | 126 | ||
128 | if (platform->is_fmodel) { | 127 | if (g->is_fmodel) { |
129 | gate_ctrl = set_field(gate_ctrl, | 128 | gate_ctrl = set_field(gate_ctrl, |
130 | therm_gate_ctrl_eng_delay_after_m(), | 129 | therm_gate_ctrl_eng_delay_after_m(), |
131 | therm_gate_ctrl_eng_delay_after_f(4)); | 130 | therm_gate_ctrl_eng_delay_after_f(4)); |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 7400a9e4..717e5487 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -725,11 +725,10 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
725 | u32 reg_offset = gr_gpcs_gpccs_falcon_hwcfg_r() - | 725 | u32 reg_offset = gr_gpcs_gpccs_falcon_hwcfg_r() - |
726 | gr_fecs_falcon_hwcfg_r(); | 726 | gr_fecs_falcon_hwcfg_r(); |
727 | u8 falcon_id_mask = 0; | 727 | u8 falcon_id_mask = 0; |
728 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
729 | 728 | ||
730 | gk20a_dbg_fn(""); | 729 | gk20a_dbg_fn(""); |
731 | 730 | ||
732 | if (platform->is_fmodel) { | 731 | if (g->is_fmodel) { |
733 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7), | 732 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7), |
734 | gr_fecs_ctxsw_mailbox_value_f(0xc0de7777)); | 733 | gr_fecs_ctxsw_mailbox_value_f(0xc0de7777)); |
735 | gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7), | 734 | gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7), |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 24acf29c..c190a83c 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -183,14 +183,13 @@ int gm20b_init_hal(struct gk20a *g) | |||
183 | { | 183 | { |
184 | struct gpu_ops *gops = &g->ops; | 184 | struct gpu_ops *gops = &g->ops; |
185 | struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; | 185 | struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; |
186 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
187 | u32 val; | 186 | u32 val; |
188 | 187 | ||
189 | gops->clock_gating = gm20b_ops.clock_gating; | 188 | gops->clock_gating = gm20b_ops.clock_gating; |
190 | gops->securegpccs = false; | 189 | gops->securegpccs = false; |
191 | gops->pmupstate = false; | 190 | gops->pmupstate = false; |
192 | #ifdef CONFIG_TEGRA_ACR | 191 | #ifdef CONFIG_TEGRA_ACR |
193 | if (platform->is_fmodel) { | 192 | if (g->is_fmodel) { |
194 | gops->privsecurity = 1; | 193 | gops->privsecurity = 1; |
195 | } else { | 194 | } else { |
196 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | 195 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); |
@@ -202,7 +201,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
202 | } | 201 | } |
203 | } | 202 | } |
204 | #else | 203 | #else |
205 | if (platform->is_fmodel) { | 204 | if (g->is_fmodel) { |
206 | gk20a_dbg_info("running ASIM with PRIV security disabled"); | 205 | gk20a_dbg_info("running ASIM with PRIV security disabled"); |
207 | gops->privsecurity = 0; | 206 | gops->privsecurity = 0; |
208 | } else { | 207 | } else { |
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c index 17882e72..90504e52 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | |||
@@ -49,7 +49,6 @@ static int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
49 | u32 compbit_backing_size; | 49 | u32 compbit_backing_size; |
50 | 50 | ||
51 | int err; | 51 | int err; |
52 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
53 | 52 | ||
54 | gk20a_dbg_fn(""); | 53 | gk20a_dbg_fn(""); |
55 | 54 | ||
@@ -82,7 +81,7 @@ static int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
82 | gk20a_dbg_info("max comptag lines : %d", | 81 | gk20a_dbg_info("max comptag lines : %d", |
83 | max_comptag_lines); | 82 | max_comptag_lines); |
84 | 83 | ||
85 | if (platform->is_fmodel) | 84 | if (g->is_fmodel) |
86 | err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); | 85 | err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); |
87 | else | 86 | else |
88 | err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); | 87 | err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 6990b4ef..0332897e 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -189,13 +189,12 @@ int gp10b_init_hal(struct gk20a *g) | |||
189 | { | 189 | { |
190 | struct gpu_ops *gops = &g->ops; | 190 | struct gpu_ops *gops = &g->ops; |
191 | struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; | 191 | struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; |
192 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
193 | u32 val; | 192 | u32 val; |
194 | 193 | ||
195 | gops->clock_gating = gp10b_ops.clock_gating; | 194 | gops->clock_gating = gp10b_ops.clock_gating; |
196 | gops->pmupstate = false; | 195 | gops->pmupstate = false; |
197 | #ifdef CONFIG_TEGRA_ACR | 196 | #ifdef CONFIG_TEGRA_ACR |
198 | if (platform->is_fmodel) { | 197 | if (g->is_fmodel) { |
199 | gops->privsecurity = 0; | 198 | gops->privsecurity = 0; |
200 | gops->securegpccs = 0; | 199 | gops->securegpccs = 0; |
201 | } else if (gk20a_gpu_is_virtual(g->dev)) { | 200 | } else if (gk20a_gpu_is_virtual(g->dev)) { |
@@ -213,7 +212,7 @@ int gp10b_init_hal(struct gk20a *g) | |||
213 | } | 212 | } |
214 | } | 213 | } |
215 | #else | 214 | #else |
216 | if (platform->is_fmodel) { | 215 | if (g->is_fmodel) { |
217 | gk20a_dbg_info("running simulator with PRIV security disabled"); | 216 | gk20a_dbg_info("running simulator with PRIV security disabled"); |
218 | gops->privsecurity = 0; | 217 | gops->privsecurity = 0; |
219 | gops->securegpccs = 0; | 218 | gops->securegpccs = 0; |
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index 42bfbf29..9ca5f46e 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | |||
@@ -71,7 +71,6 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
71 | u32 compbit_backing_size; | 71 | u32 compbit_backing_size; |
72 | 72 | ||
73 | int err; | 73 | int err; |
74 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
75 | 74 | ||
76 | gk20a_dbg_fn(""); | 75 | gk20a_dbg_fn(""); |
77 | 76 | ||
@@ -102,7 +101,7 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
102 | gk20a_dbg_info("gobs_per_comptagline_per_slice: %d", | 101 | gk20a_dbg_info("gobs_per_comptagline_per_slice: %d", |
103 | gobs_per_comptagline_per_slice); | 102 | gobs_per_comptagline_per_slice); |
104 | 103 | ||
105 | if (platform->is_fmodel) | 104 | if (g->is_fmodel) |
106 | err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); | 105 | err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); |
107 | else | 106 | else |
108 | err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); | 107 | err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); |
diff --git a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c index 4f799a82..3e2a0adf 100644 --- a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c +++ b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c | |||
@@ -112,12 +112,13 @@ static void gk20a_tegra_secure_page_destroy(struct device *dev, | |||
112 | int gk20a_tegra_secure_page_alloc(struct device *dev) | 112 | int gk20a_tegra_secure_page_alloc(struct device *dev) |
113 | { | 113 | { |
114 | struct gk20a_platform *platform = dev_get_drvdata(dev); | 114 | struct gk20a_platform *platform = dev_get_drvdata(dev); |
115 | struct gk20a *g = get_gk20a(dev); | ||
115 | struct secure_page_buffer *secure_buffer = &platform->secure_buffer; | 116 | struct secure_page_buffer *secure_buffer = &platform->secure_buffer; |
116 | DEFINE_DMA_ATTRS(attrs); | 117 | DEFINE_DMA_ATTRS(attrs); |
117 | dma_addr_t iova; | 118 | dma_addr_t iova; |
118 | size_t size = PAGE_SIZE; | 119 | size_t size = PAGE_SIZE; |
119 | 120 | ||
120 | if (platform->is_fmodel) | 121 | if (g->is_fmodel) |
121 | return -EINVAL; | 122 | return -EINVAL; |
122 | 123 | ||
123 | (void)dma_alloc_attrs(&tegra_vpr_dev, size, &iova, | 124 | (void)dma_alloc_attrs(&tegra_vpr_dev, size, &iova, |
@@ -389,10 +390,11 @@ done: | |||
389 | 390 | ||
390 | static int gk20a_tegra_railgate(struct device *dev) | 391 | static int gk20a_tegra_railgate(struct device *dev) |
391 | { | 392 | { |
393 | struct gk20a *g = get_gk20a(dev); | ||
392 | struct gk20a_platform *platform = dev_get_drvdata(dev); | 394 | struct gk20a_platform *platform = dev_get_drvdata(dev); |
393 | int ret = 0; | 395 | int ret = 0; |
394 | 396 | ||
395 | if (platform->is_fmodel || | 397 | if (g->is_fmodel || |
396 | !tegra_dvfs_is_rail_up(platform->gpu_rail)) | 398 | !tegra_dvfs_is_rail_up(platform->gpu_rail)) |
397 | return 0; | 399 | return 0; |
398 | 400 | ||
@@ -442,11 +444,12 @@ err_power_off: | |||
442 | 444 | ||
443 | static int gk20a_tegra_unrailgate(struct device *dev) | 445 | static int gk20a_tegra_unrailgate(struct device *dev) |
444 | { | 446 | { |
447 | struct gk20a *g = get_gk20a(dev); | ||
445 | struct gk20a_platform *platform = dev_get_drvdata(dev); | 448 | struct gk20a_platform *platform = dev_get_drvdata(dev); |
446 | int ret = 0; | 449 | int ret = 0; |
447 | bool first = false; | 450 | bool first = false; |
448 | 451 | ||
449 | if (platform->is_fmodel) | 452 | if (g->is_fmodel) |
450 | return 0; | 453 | return 0; |
451 | 454 | ||
452 | if (!platform->gpu_rail) { | 455 | if (!platform->gpu_rail) { |
@@ -517,10 +520,11 @@ err_clk_on: | |||
517 | 520 | ||
518 | static bool gk20a_tegra_is_railgated(struct device *dev) | 521 | static bool gk20a_tegra_is_railgated(struct device *dev) |
519 | { | 522 | { |
523 | struct gk20a *g = get_gk20a(dev); | ||
520 | struct gk20a_platform *platform = dev_get_drvdata(dev); | 524 | struct gk20a_platform *platform = dev_get_drvdata(dev); |
521 | bool ret = false; | 525 | bool ret = false; |
522 | 526 | ||
523 | if (!platform->is_fmodel) | 527 | if (!g->is_fmodel) |
524 | ret = !tegra_dvfs_is_rail_up(platform->gpu_rail); | 528 | ret = !tegra_dvfs_is_rail_up(platform->gpu_rail); |
525 | 529 | ||
526 | return ret; | 530 | return ret; |
@@ -534,10 +538,11 @@ static bool gk20a_tegra_is_railgated(struct device *dev) | |||
534 | 538 | ||
535 | static int gm20b_tegra_railgate(struct device *dev) | 539 | static int gm20b_tegra_railgate(struct device *dev) |
536 | { | 540 | { |
541 | struct gk20a *g = get_gk20a(dev); | ||
537 | struct gk20a_platform *platform = dev_get_drvdata(dev); | 542 | struct gk20a_platform *platform = dev_get_drvdata(dev); |
538 | int ret = 0; | 543 | int ret = 0; |
539 | 544 | ||
540 | if (platform->is_fmodel || | 545 | if (g->is_fmodel || |
541 | !tegra_dvfs_is_rail_up(platform->gpu_rail)) | 546 | !tegra_dvfs_is_rail_up(platform->gpu_rail)) |
542 | return 0; | 547 | return 0; |
543 | 548 | ||
@@ -601,7 +606,7 @@ static int gm20b_tegra_unrailgate(struct device *dev) | |||
601 | int ret = 0; | 606 | int ret = 0; |
602 | bool first = false; | 607 | bool first = false; |
603 | 608 | ||
604 | if (platform->is_fmodel) | 609 | if (g->is_fmodel) |
605 | return 0; | 610 | return 0; |
606 | 611 | ||
607 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | 612 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK |
diff --git a/drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.c index 26ac44a3..d04a2885 100644 --- a/drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.c | |||
@@ -72,10 +72,11 @@ static void gr_gp10b_remove_sysfs(struct device *dev); | |||
72 | 72 | ||
73 | int gp10b_tegra_get_clocks(struct device *dev) | 73 | int gp10b_tegra_get_clocks(struct device *dev) |
74 | { | 74 | { |
75 | struct gk20a *g = get_gk20a(dev); | ||
75 | struct gk20a_platform *platform = dev_get_drvdata(dev); | 76 | struct gk20a_platform *platform = dev_get_drvdata(dev); |
76 | unsigned int i; | 77 | unsigned int i; |
77 | 78 | ||
78 | if (platform->is_fmodel) | 79 | if (g->is_fmodel) |
79 | return 0; | 80 | return 0; |
80 | 81 | ||
81 | platform->num_clks = 0; | 82 | platform->num_clks = 0; |
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c index 75fdd369..cc672b1e 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/vgpu.c | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <linux/dma-mapping.h> | 18 | #include <linux/dma-mapping.h> |
19 | #include <linux/pm_runtime.h> | 19 | #include <linux/pm_runtime.h> |
20 | #include <linux/pm_qos.h> | 20 | #include <linux/pm_qos.h> |
21 | #include <soc/tegra/chip-id.h> | ||
21 | 22 | ||
22 | #include <nvgpu/kmem.h> | 23 | #include <nvgpu/kmem.h> |
23 | #include <nvgpu/bug.h> | 24 | #include <nvgpu/bug.h> |
@@ -574,8 +575,8 @@ int vgpu_probe(struct platform_device *pdev) | |||
574 | } | 575 | } |
575 | 576 | ||
576 | gk20a->dev = dev; | 577 | gk20a->dev = dev; |
577 | 578 | if (tegra_platform_is_linsim() || tegra_platform_is_vdk()) | |
578 | gk20a->is_fmodel = platform->is_fmodel; | 579 | gk20a->is_fmodel = true; |
579 | 580 | ||
580 | nvgpu_kmem_init(gk20a); | 581 | nvgpu_kmem_init(gk20a); |
581 | 582 | ||