diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/channel_t19x.h | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c | 87 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.h | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gv11b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 90 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/subctx_gv11b.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/tsg_t19x.h | 21 |
10 files changed, 228 insertions, 42 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 8a7c768e..33391a80 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -1,6 +1,7 @@ | |||
1 | nvgpu-t19x := ../../../../nvgpu-t19x/drivers/gpu/nvgpu | 1 | nvgpu-t19x := ../../../../nvgpu-t19x/drivers/gpu/nvgpu |
2 | 2 | ||
3 | nvgpu-y += \ | 3 | nvgpu-y += \ |
4 | $(nvgpu-t19x)/common/linux/ioctl_tsg_t19x.o \ | ||
4 | $(nvgpu-t19x)/gv11b/gv11b.o \ | 5 | $(nvgpu-t19x)/gv11b/gv11b.o \ |
5 | $(nvgpu-t19x)/gv11b/bus_gv11b.o \ | 6 | $(nvgpu-t19x)/gv11b/bus_gv11b.o \ |
6 | $(nvgpu-t19x)/gv11b/mc_gv11b.o \ | 7 | $(nvgpu-t19x)/gv11b/mc_gv11b.o \ |
diff --git a/drivers/gpu/nvgpu/channel_t19x.h b/drivers/gpu/nvgpu/channel_t19x.h new file mode 100644 index 00000000..bb324426 --- /dev/null +++ b/drivers/gpu/nvgpu/channel_t19x.h | |||
@@ -0,0 +1,24 @@ | |||
1 | /* | ||
2 | * NVIDIA T19x Channel info | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef _NVGPU_CHANNEL_T19X_H_ | ||
17 | #define _NVGPU_CHANNEL_T19X_H_ | ||
18 | |||
19 | struct channel_t19x { | ||
20 | u32 subctx_id; | ||
21 | u32 runqueue_sel; | ||
22 | }; | ||
23 | |||
24 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c new file mode 100644 index 00000000..bf6088ab --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c | |||
@@ -0,0 +1,87 @@ | |||
1 | /* | ||
2 | * GV11B TSG IOCTL Handler | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #include <linux/types.h> | ||
17 | |||
18 | #include "gk20a/gk20a.h" | ||
19 | |||
20 | #include "gv11b/fifo_gv11b.h" | ||
21 | #include "gv11b/subctx_gv11b.h" | ||
22 | #include "ioctl_tsg_t19x.h" | ||
23 | |||
24 | static int gv11b_tsg_ioctl_bind_channel_ex(struct gk20a *g, | ||
25 | struct tsg_gk20a *tsg, struct nvgpu_tsg_bind_channel_ex_args *arg) | ||
26 | { | ||
27 | struct gk20a_sched_ctrl *sched = &g->sched_ctrl; | ||
28 | struct channel_gk20a *ch; | ||
29 | int err = 0; | ||
30 | |||
31 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid); | ||
32 | |||
33 | nvgpu_mutex_acquire(&sched->control_lock); | ||
34 | if (sched->control_locked) { | ||
35 | err = -EPERM; | ||
36 | goto done; | ||
37 | } | ||
38 | err = gk20a_busy(g); | ||
39 | if (err) { | ||
40 | nvgpu_err(g, "failed to power on gpu"); | ||
41 | goto done; | ||
42 | } | ||
43 | |||
44 | ch = gk20a_get_channel_from_file(arg->channel_fd); | ||
45 | if (!ch) | ||
46 | return -EINVAL; | ||
47 | if (arg->subcontext_id < gv11b_get_max_subctx_count(g)) | ||
48 | ch->t19x.subctx_id = arg->subcontext_id; | ||
49 | else | ||
50 | return -EINVAL; | ||
51 | nvgpu_log(g, gpu_dbg_info, "channel id : %d : subctx: %d", | ||
52 | ch->chid, ch->t19x.subctx_id); | ||
53 | |||
54 | /* Use runqueue selector 1 for all ASYNC ids */ | ||
55 | if (ch->t19x.subctx_id > CHANNEL_INFO_VEID0) | ||
56 | ch->t19x.runqueue_sel = 1; | ||
57 | |||
58 | err = ch->g->ops.fifo.tsg_bind_channel(tsg, ch); | ||
59 | gk20a_idle(g); | ||
60 | done: | ||
61 | nvgpu_mutex_release(&sched->control_lock); | ||
62 | return err; | ||
63 | } | ||
64 | |||
65 | int t19x_tsg_ioctl_handler(struct gk20a *g, struct tsg_gk20a *tsg, | ||
66 | unsigned int cmd, u8 *buf) | ||
67 | { | ||
68 | int err = 0; | ||
69 | |||
70 | nvgpu_log(g, gpu_dbg_fn, "t19x_tsg_ioctl_handler"); | ||
71 | |||
72 | switch (cmd) { | ||
73 | case NVGPU_TSG_IOCTL_BIND_CHANNEL_EX: | ||
74 | { | ||
75 | err = gv11b_tsg_ioctl_bind_channel_ex(g, tsg, | ||
76 | (struct nvgpu_tsg_bind_channel_ex_args *)buf); | ||
77 | break; | ||
78 | } | ||
79 | |||
80 | default: | ||
81 | nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x", | ||
82 | cmd); | ||
83 | err = -ENOTTY; | ||
84 | break; | ||
85 | } | ||
86 | return err; | ||
87 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.h b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.h new file mode 100644 index 00000000..3376ffce --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * GV11B TSG IOCTL handler | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef _NVGPU_IOCTL_TSG_T19X | ||
17 | #define _NVGPU_IOCTL_TSG_T19X | ||
18 | |||
19 | int t19x_tsg_ioctl_handler(struct gk20a *g, struct tsg_gk20a *tsg, | ||
20 | unsigned int cmd, u8 *arg); | ||
21 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index a1f6d258..ace873e9 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -45,7 +45,6 @@ | |||
45 | #include "subctx_gv11b.h" | 45 | #include "subctx_gv11b.h" |
46 | #include "gr_gv11b.h" | 46 | #include "gr_gv11b.h" |
47 | 47 | ||
48 | #define CHANNEL_INFO_VEID0 0 | ||
49 | #define PBDMA_SUBDEVICE_ID 1 | 48 | #define PBDMA_SUBDEVICE_ID 1 |
50 | 49 | ||
51 | static void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g, | 50 | static void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g, |
@@ -94,7 +93,8 @@ static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) | |||
94 | 93 | ||
95 | /* Time being use 0 pbdma sequencer */ | 94 | /* Time being use 0 pbdma sequencer */ |
96 | runlist_entry = ram_rl_entry_type_channel_v() | | 95 | runlist_entry = ram_rl_entry_type_channel_v() | |
97 | ram_rl_entry_chan_runqueue_selector_f(0) | | 96 | ram_rl_entry_chan_runqueue_selector_f( |
97 | c->t19x.runqueue_sel) | | ||
98 | ram_rl_entry_chan_userd_target_f( | 98 | ram_rl_entry_chan_userd_target_f( |
99 | ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()) | | 99 | ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()) | |
100 | ram_rl_entry_chan_inst_target_f( | 100 | ram_rl_entry_chan_inst_target_f( |
@@ -178,10 +178,14 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, | |||
178 | 178 | ||
179 | nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); | 179 | nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); |
180 | 180 | ||
181 | /* Until full subcontext is supported, always use VEID0 */ | 181 | if (c->t19x.subctx_id == CHANNEL_INFO_VEID0) |
182 | nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), | 182 | nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), |
183 | pbdma_set_channel_info_scg_type_graphics_compute0_f() | | 183 | pbdma_set_channel_info_scg_type_graphics_compute0_f() | |
184 | pbdma_set_channel_info_veid_f(CHANNEL_INFO_VEID0)); | 184 | pbdma_set_channel_info_veid_f(c->t19x.subctx_id)); |
185 | else | ||
186 | nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), | ||
187 | pbdma_set_channel_info_scg_type_compute1_f() | | ||
188 | pbdma_set_channel_info_veid_f(c->t19x.subctx_id)); | ||
185 | 189 | ||
186 | gv11b_fifo_init_ramfc_eng_method_buffer(g, c, mem); | 190 | gv11b_fifo_init_ramfc_eng_method_buffer(g, c, mem); |
187 | 191 | ||
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 03cca839..032342b2 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV11B Fifo | 2 | * GV11B Fifo |
3 | * | 3 | * |
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -36,6 +36,8 @@ | |||
36 | #define GR_RUNQUE 0 /* pbdma 0 */ | 36 | #define GR_RUNQUE 0 /* pbdma 0 */ |
37 | #define ASYNC_CE_RUNQUE 2 /* pbdma 2 */ | 37 | #define ASYNC_CE_RUNQUE 2 /* pbdma 2 */ |
38 | 38 | ||
39 | #define CHANNEL_INFO_VEID0 0 | ||
40 | |||
39 | struct gpu_ops; | 41 | struct gpu_ops; |
40 | void gv11b_init_fifo(struct gpu_ops *gops); | 42 | void gv11b_init_fifo(struct gpu_ops *gops); |
41 | void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g, | 43 | void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.c b/drivers/gpu/nvgpu/gv11b/gv11b.c index 09628940..69fd0cf4 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV11B Graphics | 2 | * GV11B Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -23,5 +23,7 @@ | |||
23 | int gv11b_init_gpu_characteristics(struct gk20a *g) | 23 | int gv11b_init_gpu_characteristics(struct gk20a *g) |
24 | { | 24 | { |
25 | gk20a_init_gpu_characteristics(g); | 25 | gk20a_init_gpu_characteristics(g); |
26 | g->gpu_characteristics.flags |= | ||
27 | NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS; | ||
26 | return 0; | 28 | return 0; |
27 | } | 29 | } |
diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 79ed0d1e..cb042f87 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | |||
@@ -31,12 +31,17 @@ | |||
31 | static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, | 31 | static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, |
32 | struct nvgpu_mem *inst_block); | 32 | struct nvgpu_mem *inst_block); |
33 | 33 | ||
34 | static void gv11b_subctx_commit_valid_mask(struct channel_gk20a *c, | ||
35 | struct nvgpu_mem *inst_block); | ||
36 | static void gv11b_subctx_commit_pdb(struct channel_gk20a *c, | ||
37 | struct nvgpu_mem *inst_block); | ||
38 | |||
34 | void gv11b_free_subctx_header(struct channel_gk20a *c) | 39 | void gv11b_free_subctx_header(struct channel_gk20a *c) |
35 | { | 40 | { |
36 | struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; | 41 | struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; |
37 | struct gk20a *g = c->g; | 42 | struct gk20a *g = c->g; |
38 | 43 | ||
39 | gk20a_dbg_fn(""); | 44 | nvgpu_log(g, gpu_dbg_fn, "gv11b_free_subctx_header"); |
40 | 45 | ||
41 | if (ctx->mem.gpu_va) { | 46 | if (ctx->mem.gpu_va) { |
42 | nvgpu_gmmu_unmap(c->vm, &ctx->mem, ctx->mem.gpu_va); | 47 | nvgpu_gmmu_unmap(c->vm, &ctx->mem, ctx->mem.gpu_va); |
@@ -52,7 +57,7 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) | |||
52 | struct gr_gk20a *gr = &g->gr; | 57 | struct gr_gk20a *gr = &g->gr; |
53 | int ret = 0; | 58 | int ret = 0; |
54 | 59 | ||
55 | gk20a_dbg_fn(""); | 60 | nvgpu_log(g, gpu_dbg_fn, "gv11b_alloc_subctx_header"); |
56 | 61 | ||
57 | if (ctx->mem.gpu_va == 0) { | 62 | if (ctx->mem.gpu_va == 0) { |
58 | ret = nvgpu_dma_alloc_flags_sys(g, | 63 | ret = nvgpu_dma_alloc_flags_sys(g, |
@@ -82,7 +87,6 @@ int gv11b_alloc_subctx_header(struct channel_gk20a *c) | |||
82 | nvgpu_mem_end(g, &ctx->mem); | 87 | nvgpu_mem_end(g, &ctx->mem); |
83 | 88 | ||
84 | gv11b_init_subcontext_pdb(c, &c->inst_block); | 89 | gv11b_init_subcontext_pdb(c, &c->inst_block); |
85 | |||
86 | } | 90 | } |
87 | return ret; | 91 | return ret; |
88 | } | 92 | } |
@@ -91,37 +95,13 @@ static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, | |||
91 | struct nvgpu_mem *inst_block) | 95 | struct nvgpu_mem *inst_block) |
92 | { | 96 | { |
93 | struct gk20a *g = c->g; | 97 | struct gk20a *g = c->g; |
94 | struct vm_gk20a *vm; | ||
95 | u64 pdb_addr, pdb_addr_lo, pdb_addr_hi; | ||
96 | u32 format_word; | ||
97 | u32 lo, hi; | ||
98 | 98 | ||
99 | gk20a_dbg_fn(""); | 99 | gv11b_subctx_commit_pdb(c, inst_block); |
100 | /* load main pdb as veid0 pdb also */ | 100 | gv11b_subctx_commit_valid_mask(c, inst_block); |
101 | vm = c->vm; | 101 | |
102 | pdb_addr = g->ops.mm.get_iova_addr(g, vm->pdb.mem.priv.sgt->sgl, 0); | 102 | nvgpu_log(g, gpu_dbg_info, " subctx %d instblk set", c->t19x.subctx_id); |
103 | pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); | ||
104 | pdb_addr_hi = u64_hi32(pdb_addr); | ||
105 | format_word = ram_in_sc_page_dir_base_target_f( | ||
106 | ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(), 0) | | ||
107 | ram_in_sc_page_dir_base_vol_f( | ||
108 | ram_in_sc_page_dir_base_vol_true_v(), 0) | | ||
109 | ram_in_sc_page_dir_base_fault_replay_tex_f(0, 0) | | ||
110 | ram_in_sc_page_dir_base_fault_replay_gcc_f(0, 0) | | ||
111 | ram_in_sc_use_ver2_pt_format_f(1, 0) | | ||
112 | ram_in_sc_big_page_size_f(1, 0) | | ||
113 | ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); | ||
114 | lo = ram_in_sc_page_dir_base_vol_0_w(); | ||
115 | hi = ram_in_sc_page_dir_base_hi_0_w(); | ||
116 | nvgpu_mem_wr32(g, inst_block, lo, format_word); | ||
117 | nvgpu_mem_wr32(g, inst_block, hi, pdb_addr_hi); | ||
118 | |||
119 | /* make subcontext0 address space to valid */ | ||
120 | /* TODO fix proper hw register definations */ | ||
121 | nvgpu_mem_wr32(g, inst_block, 166, 0x1); | ||
122 | nvgpu_mem_wr32(g, inst_block, 167, 0); | ||
123 | nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(), | 103 | nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(), |
124 | ram_in_engine_wfi_veid_f(0)); | 104 | ram_in_engine_wfi_veid_f(c->t19x.subctx_id)); |
125 | 105 | ||
126 | } | 106 | } |
127 | 107 | ||
@@ -149,7 +129,51 @@ int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) | |||
149 | return ret; | 129 | return ret; |
150 | } | 130 | } |
151 | 131 | ||
152 | int gv11b_get_max_subctx_count(struct gk20a *g) | 132 | void gv11b_subctx_commit_valid_mask(struct channel_gk20a *c, |
133 | struct nvgpu_mem *inst_block) | ||
134 | { | ||
135 | struct gk20a *g = c->g; | ||
136 | |||
137 | /* Make all subctx pdbs valid */ | ||
138 | nvgpu_mem_wr32(g, inst_block, 166, 0xffffffff); | ||
139 | nvgpu_mem_wr32(g, inst_block, 167, 0xffffffff); | ||
140 | } | ||
141 | |||
142 | void gv11b_subctx_commit_pdb(struct channel_gk20a *c, | ||
143 | struct nvgpu_mem *inst_block) | ||
144 | { | ||
145 | struct gk20a *g = c->g; | ||
146 | u32 lo, hi; | ||
147 | u32 subctx_id = 0; | ||
148 | u32 format_word; | ||
149 | u32 pdb_addr_lo, pdb_addr_hi; | ||
150 | u64 pdb_addr; | ||
151 | |||
152 | pdb_addr = g->ops.mm.get_iova_addr(g, c->vm->pdb.mem.priv.sgt->sgl, 0); | ||
153 | pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); | ||
154 | pdb_addr_hi = u64_hi32(pdb_addr); | ||
155 | format_word = ram_in_sc_page_dir_base_target_f( | ||
156 | ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(), 0) | | ||
157 | ram_in_sc_page_dir_base_vol_f( | ||
158 | ram_in_sc_page_dir_base_vol_true_v(), 0) | | ||
159 | ram_in_sc_page_dir_base_fault_replay_tex_f(0, 0) | | ||
160 | ram_in_sc_page_dir_base_fault_replay_gcc_f(0, 0) | | ||
161 | ram_in_sc_use_ver2_pt_format_f(1, 0) | | ||
162 | ram_in_sc_big_page_size_f(1, 0) | | ||
163 | ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); | ||
164 | nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x", | ||
165 | format_word, pdb_addr_hi); | ||
166 | for (subctx_id = 0; subctx_id < gv11b_get_max_subctx_count(g); | ||
167 | subctx_id++) { | ||
168 | lo = ram_in_sc_page_dir_base_vol_0_w() + (4 * subctx_id); | ||
169 | hi = ram_in_sc_page_dir_base_hi_0_w() + (4 * subctx_id); | ||
170 | nvgpu_mem_wr32(g, inst_block, lo, format_word); | ||
171 | nvgpu_mem_wr32(g, inst_block, hi, pdb_addr_hi); | ||
172 | } | ||
173 | } | ||
174 | |||
175 | |||
176 | u32 gv11b_get_max_subctx_count(struct gk20a *g) | ||
153 | { | 177 | { |
154 | u32 data = gk20a_readl(g, gr_pri_fe_chip_def_info_r()); | 178 | u32 data = gk20a_readl(g, gr_pri_fe_chip_def_info_r()); |
155 | 179 | ||
diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h index fdfe9e3b..5e4e99f5 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.h | |||
@@ -25,5 +25,5 @@ void gv11b_free_subctx_header(struct channel_gk20a *c); | |||
25 | 25 | ||
26 | int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va); | 26 | int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va); |
27 | 27 | ||
28 | int gv11b_get_max_subctx_count(struct gk20a *g); | 28 | u32 gv11b_get_max_subctx_count(struct gk20a *g); |
29 | #endif /* __SUBCONTEXT_GV11B_H__ */ | 29 | #endif /* __SUBCONTEXT_GV11B_H__ */ |
diff --git a/drivers/gpu/nvgpu/tsg_t19x.h b/drivers/gpu/nvgpu/tsg_t19x.h new file mode 100644 index 00000000..2f359668 --- /dev/null +++ b/drivers/gpu/nvgpu/tsg_t19x.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * NVIDIA T19x TSG | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef _NVGPU_TSG_T19X_H_ | ||
17 | #define _NVGPU_TSG_T19X_H_ | ||
18 | |||
19 | #include "common/linux/ioctl_tsg_t19x.h" | ||
20 | |||
21 | #endif | ||