diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/tsg_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 71 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 66 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/fifo_gp106.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/fifo_gp106.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 68 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 28 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fifo_gp10b.h | 17 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 68 |
11 files changed, 238 insertions, 117 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c index a0dcd622..99d72292 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | |||
@@ -342,9 +342,3 @@ struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch) | |||
342 | 342 | ||
343 | return tsg; | 343 | return tsg; |
344 | } | 344 | } |
345 | |||
346 | void gk20a_init_tsg_ops(struct gpu_ops *gops) | ||
347 | { | ||
348 | gops->fifo.tsg_bind_channel = gk20a_tsg_bind_channel; | ||
349 | gops->fifo.tsg_unbind_channel = gk20a_tsg_unbind_channel; | ||
350 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h index e6a4a3cc..40e12105 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h | |||
@@ -22,14 +22,12 @@ | |||
22 | #define NVGPU_INVALID_TSG_ID (-1) | 22 | #define NVGPU_INVALID_TSG_ID (-1) |
23 | 23 | ||
24 | struct channel_gk20a; | 24 | struct channel_gk20a; |
25 | struct gpu_ops; | ||
26 | 25 | ||
27 | bool gk20a_is_channel_marked_as_tsg(struct channel_gk20a *ch); | 26 | bool gk20a_is_channel_marked_as_tsg(struct channel_gk20a *ch); |
28 | struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g); | 27 | struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g); |
29 | void gk20a_tsg_release(struct kref *ref); | 28 | void gk20a_tsg_release(struct kref *ref); |
30 | 29 | ||
31 | int gk20a_init_tsg_support(struct gk20a *g, u32 tsgid); | 30 | int gk20a_init_tsg_support(struct gk20a *g, u32 tsgid); |
32 | void gk20a_init_tsg_ops(struct gpu_ops *gops); | ||
33 | struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch); | 31 | struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch); |
34 | 32 | ||
35 | struct tsg_gk20a { | 33 | struct tsg_gk20a { |
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 19782412..afdfba91 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | |||
@@ -28,7 +28,7 @@ | |||
28 | #include <nvgpu/hw/gm20b/hw_top_gm20b.h> | 28 | #include <nvgpu/hw/gm20b/hw_top_gm20b.h> |
29 | #include <nvgpu/hw/gm20b/hw_pbdma_gm20b.h> | 29 | #include <nvgpu/hw/gm20b/hw_pbdma_gm20b.h> |
30 | 30 | ||
31 | static void channel_gm20b_bind(struct channel_gk20a *c) | 31 | void channel_gm20b_bind(struct channel_gk20a *c) |
32 | { | 32 | { |
33 | struct gk20a *g = c->g; | 33 | struct gk20a *g = c->g; |
34 | 34 | ||
@@ -69,7 +69,7 @@ static inline u32 gm20b_engine_id_to_mmu_id(struct gk20a *g, u32 engine_id) | |||
69 | return fault_id; | 69 | return fault_id; |
70 | } | 70 | } |
71 | 71 | ||
72 | static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, | 72 | void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, |
73 | unsigned long engine_ids) | 73 | unsigned long engine_ids) |
74 | { | 74 | { |
75 | unsigned long delay = GR_IDLE_CHECK_DEFAULT; | 75 | unsigned long delay = GR_IDLE_CHECK_DEFAULT; |
@@ -113,12 +113,12 @@ static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, | |||
113 | gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id), 0); | 113 | gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id), 0); |
114 | } | 114 | } |
115 | 115 | ||
116 | static u32 gm20b_fifo_get_num_fifos(struct gk20a *g) | 116 | u32 gm20b_fifo_get_num_fifos(struct gk20a *g) |
117 | { | 117 | { |
118 | return ccsr_channel__size_1_v(); | 118 | return ccsr_channel__size_1_v(); |
119 | } | 119 | } |
120 | 120 | ||
121 | static void gm20b_device_info_data_parse(struct gk20a *g, | 121 | void gm20b_device_info_data_parse(struct gk20a *g, |
122 | u32 table_entry, u32 *inst_id, | 122 | u32 table_entry, u32 *inst_id, |
123 | u32 *pri_base, u32 *fault_id) | 123 | u32 *pri_base, u32 *fault_id) |
124 | { | 124 | { |
@@ -139,7 +139,7 @@ static void gm20b_device_info_data_parse(struct gk20a *g, | |||
139 | top_device_info_data_type_v(table_entry)); | 139 | top_device_info_data_type_v(table_entry)); |
140 | } | 140 | } |
141 | 141 | ||
142 | static void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) | 142 | void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) |
143 | { | 143 | { |
144 | /* | 144 | /* |
145 | * These are all errors which indicate something really wrong | 145 | * These are all errors which indicate something really wrong |
@@ -182,64 +182,3 @@ static void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) | |||
182 | f->intr.pbdma.restartable_0 = | 182 | f->intr.pbdma.restartable_0 = |
183 | pbdma_intr_0_device_pending_f(); | 183 | pbdma_intr_0_device_pending_f(); |
184 | } | 184 | } |
185 | |||
186 | void gm20b_init_fifo(struct gpu_ops *gops) | ||
187 | { | ||
188 | gops->fifo.init_fifo_setup_hw = gk20a_init_fifo_setup_hw; | ||
189 | gops->fifo.bind_channel = channel_gm20b_bind; | ||
190 | gops->fifo.unbind_channel = gk20a_fifo_channel_unbind; | ||
191 | gops->fifo.disable_channel = gk20a_fifo_disable_channel; | ||
192 | gops->fifo.enable_channel = gk20a_fifo_enable_channel; | ||
193 | gops->fifo.alloc_inst = gk20a_fifo_alloc_inst; | ||
194 | gops->fifo.free_inst = gk20a_fifo_free_inst; | ||
195 | gops->fifo.setup_ramfc = gk20a_fifo_setup_ramfc; | ||
196 | gops->fifo.channel_set_priority = gk20a_fifo_set_priority; | ||
197 | gops->fifo.channel_set_timeslice = gk20a_fifo_set_timeslice; | ||
198 | gops->fifo.default_timeslice_us = gk20a_fifo_default_timeslice_us; | ||
199 | gops->fifo.setup_userd = gk20a_fifo_setup_userd; | ||
200 | gops->fifo.userd_gp_get = gk20a_fifo_userd_gp_get; | ||
201 | gops->fifo.userd_gp_put = gk20a_fifo_userd_gp_put; | ||
202 | gops->fifo.userd_pb_get = gk20a_fifo_userd_pb_get; | ||
203 | gops->fifo.pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val; | ||
204 | |||
205 | gops->fifo.preempt_channel = gk20a_fifo_preempt_channel; | ||
206 | gops->fifo.preempt_tsg = gk20a_fifo_preempt_tsg; | ||
207 | gops->fifo.update_runlist = gk20a_fifo_update_runlist; | ||
208 | gops->fifo.trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault; | ||
209 | gops->fifo.get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info; | ||
210 | gops->fifo.wait_engine_idle = gk20a_fifo_wait_engine_idle; | ||
211 | gops->fifo.get_num_fifos = gm20b_fifo_get_num_fifos; | ||
212 | gops->fifo.get_pbdma_signature = gk20a_fifo_get_pbdma_signature; | ||
213 | gops->fifo.set_runlist_interleave = gk20a_fifo_set_runlist_interleave; | ||
214 | gops->fifo.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice; | ||
215 | gops->fifo.force_reset_ch = gk20a_fifo_force_reset_ch; | ||
216 | gops->fifo.engine_enum_from_type = gk20a_fifo_engine_enum_from_type; | ||
217 | gops->fifo.device_info_data_parse = gm20b_device_info_data_parse; | ||
218 | gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; | ||
219 | gops->fifo.init_engine_info = gk20a_fifo_init_engine_info; | ||
220 | gops->fifo.runlist_entry_size = ram_rl_entry_size_v; | ||
221 | gops->fifo.get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry; | ||
222 | gops->fifo.get_ch_runlist_entry = gk20a_get_ch_runlist_entry; | ||
223 | gops->fifo.is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc; | ||
224 | gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status; | ||
225 | gops->fifo.dump_eng_status = gk20a_dump_eng_status; | ||
226 | gops->fifo.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc; | ||
227 | gops->fifo.intr_0_error_mask = gk20a_fifo_intr_0_error_mask; | ||
228 | gops->fifo.is_preempt_pending = gk20a_fifo_is_preempt_pending; | ||
229 | gops->fifo.init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs; | ||
230 | gops->fifo.reset_enable_hw = gk20a_init_fifo_reset_enable_hw; | ||
231 | gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg; | ||
232 | gops->fifo.handle_sched_error = gk20a_fifo_handle_sched_error; | ||
233 | gops->fifo.handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0; | ||
234 | gops->fifo.handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1; | ||
235 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
236 | gops->fifo.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf; | ||
237 | gops->fifo.free_syncpt_buf = gk20a_fifo_free_syncpt_buf; | ||
238 | gops->fifo.add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd; | ||
239 | gops->fifo.get_syncpt_wait_cmd_size = | ||
240 | gk20a_fifo_get_syncpt_wait_cmd_size; | ||
241 | gops->fifo.add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd; | ||
242 | gops->fifo.get_syncpt_incr_cmd_size = | ||
243 | gk20a_fifo_get_syncpt_incr_cmd_size; | ||
244 | #endif | ||
245 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h index ca452d21..1b1b8cc1 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B Fifo | 2 | * GM20B Fifo |
3 | * | 3 | * |
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -17,5 +17,13 @@ | |||
17 | #define _NVHOST_GM20B_FIFO | 17 | #define _NVHOST_GM20B_FIFO |
18 | struct gk20a; | 18 | struct gk20a; |
19 | 19 | ||
20 | void gm20b_init_fifo(struct gpu_ops *gops); | 20 | void channel_gm20b_bind(struct channel_gk20a *c); |
21 | void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, | ||
22 | unsigned long engine_ids); | ||
23 | u32 gm20b_fifo_get_num_fifos(struct gk20a *g); | ||
24 | void gm20b_device_info_data_parse(struct gk20a *g, | ||
25 | u32 table_entry, u32 *inst_id, | ||
26 | u32 *pri_base, u32 *fault_id); | ||
27 | void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f); | ||
28 | |||
21 | #endif | 29 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 87acb25c..bdee1149 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -15,6 +15,7 @@ | |||
15 | 15 | ||
16 | #include "gk20a/gk20a.h" | 16 | #include "gk20a/gk20a.h" |
17 | #include "gk20a/dbg_gpu_gk20a.h" | 17 | #include "gk20a/dbg_gpu_gk20a.h" |
18 | #include "gk20a/fifo_gk20a.h" | ||
18 | #include "gk20a/css_gr_gk20a.h" | 19 | #include "gk20a/css_gr_gk20a.h" |
19 | #include "gk20a/mc_gk20a.h" | 20 | #include "gk20a/mc_gk20a.h" |
20 | #include "gk20a/bus_gk20a.h" | 21 | #include "gk20a/bus_gk20a.h" |
@@ -46,6 +47,9 @@ | |||
46 | 47 | ||
47 | #include <nvgpu/hw/gm20b/hw_proj_gm20b.h> | 48 | #include <nvgpu/hw/gm20b/hw_proj_gm20b.h> |
48 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> | 49 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> |
50 | #include <nvgpu/hw/gm20b/hw_fifo_gm20b.h> | ||
51 | #include <nvgpu/hw/gm20b/hw_ram_gm20b.h> | ||
52 | #include <nvgpu/hw/gm20b/hw_top_gm20b.h> | ||
49 | 53 | ||
50 | #define PRIV_SECURITY_DISABLE 0x01 | 54 | #define PRIV_SECURITY_DISABLE 0x01 |
51 | 55 | ||
@@ -202,6 +206,64 @@ static const struct gpu_ops gm20b_ops = { | |||
202 | .pg_gr_load_gating_prod = | 206 | .pg_gr_load_gating_prod = |
203 | gr_gm20b_pg_gr_load_gating_prod, | 207 | gr_gm20b_pg_gr_load_gating_prod, |
204 | }, | 208 | }, |
209 | .fifo = { | ||
210 | .init_fifo_setup_hw = gk20a_init_fifo_setup_hw, | ||
211 | .bind_channel = channel_gm20b_bind, | ||
212 | .unbind_channel = gk20a_fifo_channel_unbind, | ||
213 | .disable_channel = gk20a_fifo_disable_channel, | ||
214 | .enable_channel = gk20a_fifo_enable_channel, | ||
215 | .alloc_inst = gk20a_fifo_alloc_inst, | ||
216 | .free_inst = gk20a_fifo_free_inst, | ||
217 | .setup_ramfc = gk20a_fifo_setup_ramfc, | ||
218 | .channel_set_priority = gk20a_fifo_set_priority, | ||
219 | .channel_set_timeslice = gk20a_fifo_set_timeslice, | ||
220 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, | ||
221 | .setup_userd = gk20a_fifo_setup_userd, | ||
222 | .userd_gp_get = gk20a_fifo_userd_gp_get, | ||
223 | .userd_gp_put = gk20a_fifo_userd_gp_put, | ||
224 | .userd_pb_get = gk20a_fifo_userd_pb_get, | ||
225 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, | ||
226 | .preempt_channel = gk20a_fifo_preempt_channel, | ||
227 | .preempt_tsg = gk20a_fifo_preempt_tsg, | ||
228 | .update_runlist = gk20a_fifo_update_runlist, | ||
229 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, | ||
230 | .get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info, | ||
231 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, | ||
232 | .get_num_fifos = gm20b_fifo_get_num_fifos, | ||
233 | .get_pbdma_signature = gk20a_fifo_get_pbdma_signature, | ||
234 | .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, | ||
235 | .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, | ||
236 | .force_reset_ch = gk20a_fifo_force_reset_ch, | ||
237 | .engine_enum_from_type = gk20a_fifo_engine_enum_from_type, | ||
238 | .device_info_data_parse = gm20b_device_info_data_parse, | ||
239 | .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, | ||
240 | .init_engine_info = gk20a_fifo_init_engine_info, | ||
241 | .runlist_entry_size = ram_rl_entry_size_v, | ||
242 | .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry, | ||
243 | .get_ch_runlist_entry = gk20a_get_ch_runlist_entry, | ||
244 | .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, | ||
245 | .dump_pbdma_status = gk20a_dump_pbdma_status, | ||
246 | .dump_eng_status = gk20a_dump_eng_status, | ||
247 | .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc, | ||
248 | .intr_0_error_mask = gk20a_fifo_intr_0_error_mask, | ||
249 | .is_preempt_pending = gk20a_fifo_is_preempt_pending, | ||
250 | .init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs, | ||
251 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, | ||
252 | .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, | ||
253 | .handle_sched_error = gk20a_fifo_handle_sched_error, | ||
254 | .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, | ||
255 | .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, | ||
256 | .tsg_bind_channel = gk20a_tsg_bind_channel, | ||
257 | .tsg_unbind_channel = gk20a_tsg_unbind_channel, | ||
258 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
259 | .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, | ||
260 | .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, | ||
261 | .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd, | ||
262 | .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size, | ||
263 | .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd, | ||
264 | .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, | ||
265 | #endif | ||
266 | }, | ||
205 | .mc = { | 267 | .mc = { |
206 | .intr_enable = mc_gk20a_intr_enable, | 268 | .intr_enable = mc_gk20a_intr_enable, |
207 | .intr_unit_config = mc_gk20a_intr_unit_config, | 269 | .intr_unit_config = mc_gk20a_intr_unit_config, |
@@ -271,6 +333,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
271 | 333 | ||
272 | gops->ltc = gm20b_ops.ltc; | 334 | gops->ltc = gm20b_ops.ltc; |
273 | gops->clock_gating = gm20b_ops.clock_gating; | 335 | gops->clock_gating = gm20b_ops.clock_gating; |
336 | gops->fifo = gm20b_ops.fifo; | ||
274 | gops->mc = gm20b_ops.mc; | 337 | gops->mc = gm20b_ops.mc; |
275 | gops->dbg_session_ops = gm20b_ops.dbg_session_ops; | 338 | gops->dbg_session_ops = gm20b_ops.dbg_session_ops; |
276 | gops->debug = gm20b_ops.debug; | 339 | gops->debug = gm20b_ops.debug; |
@@ -320,7 +383,6 @@ int gm20b_init_hal(struct gk20a *g) | |||
320 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | 383 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; |
321 | gm20b_init_gr(gops); | 384 | gm20b_init_gr(gops); |
322 | gm20b_init_fb(gops); | 385 | gm20b_init_fb(gops); |
323 | gm20b_init_fifo(gops); | ||
324 | gm20b_init_ce2(gops); | 386 | gm20b_init_ce2(gops); |
325 | gm20b_init_gr_ctx(gops); | 387 | gm20b_init_gr_ctx(gops); |
326 | gm20b_init_mm(gops); | 388 | gm20b_init_mm(gops); |
@@ -328,7 +390,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
328 | gm20b_init_clk_ops(gops); | 390 | gm20b_init_clk_ops(gops); |
329 | gm20b_init_regops(gops); | 391 | gm20b_init_regops(gops); |
330 | gm20b_init_therm_ops(gops); | 392 | gm20b_init_therm_ops(gops); |
331 | gk20a_init_tsg_ops(gops); | 393 | |
332 | g->name = "gm20b"; | 394 | g->name = "gm20b"; |
333 | 395 | ||
334 | c->twod_class = FERMI_TWOD_A; | 396 | c->twod_class = FERMI_TWOD_A; |
diff --git a/drivers/gpu/nvgpu/gp106/fifo_gp106.c b/drivers/gpu/nvgpu/gp106/fifo_gp106.c index 5fa03d6f..22a49260 100644 --- a/drivers/gpu/nvgpu/gp106/fifo_gp106.c +++ b/drivers/gpu/nvgpu/gp106/fifo_gp106.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -19,14 +19,7 @@ | |||
19 | #include <nvgpu/hw/gp106/hw_ccsr_gp106.h> | 19 | #include <nvgpu/hw/gp106/hw_ccsr_gp106.h> |
20 | #include <nvgpu/hw/gp106/hw_fifo_gp106.h> | 20 | #include <nvgpu/hw/gp106/hw_fifo_gp106.h> |
21 | 21 | ||
22 | static u32 gp106_fifo_get_num_fifos(struct gk20a *g) | 22 | u32 gp106_fifo_get_num_fifos(struct gk20a *g) |
23 | { | 23 | { |
24 | return ccsr_channel__size_1_v(); | 24 | return ccsr_channel__size_1_v(); |
25 | } | 25 | } |
26 | |||
27 | void gp106_init_fifo(struct gpu_ops *gops) | ||
28 | { | ||
29 | gp10b_init_fifo(gops); | ||
30 | gops->fifo.get_num_fifos = gp106_fifo_get_num_fifos; | ||
31 | gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; | ||
32 | } | ||
diff --git a/drivers/gpu/nvgpu/gp106/fifo_gp106.h b/drivers/gpu/nvgpu/gp106/fifo_gp106.h index 1bcec9ef..c70c0995 100644 --- a/drivers/gpu/nvgpu/gp106/fifo_gp106.h +++ b/drivers/gpu/nvgpu/gp106/fifo_gp106.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -13,6 +13,6 @@ | |||
13 | 13 | ||
14 | #ifndef NVGPU_FIFO_GP106_H | 14 | #ifndef NVGPU_FIFO_GP106_H |
15 | #define NVGPU_FIFO_GP106_H | 15 | #define NVGPU_FIFO_GP106_H |
16 | struct gpu_ops; | 16 | struct gk20a; |
17 | void gp106_init_fifo(struct gpu_ops *gops); | 17 | u32 gp106_fifo_get_num_fifos(struct gk20a *g); |
18 | #endif | 18 | #endif |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 1690c42b..fa767c3b 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -14,6 +14,7 @@ | |||
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include "gk20a/gk20a.h" | 16 | #include "gk20a/gk20a.h" |
17 | #include "gk20a/fifo_gk20a.h" | ||
17 | #include "gk20a/dbg_gpu_gk20a.h" | 18 | #include "gk20a/dbg_gpu_gk20a.h" |
18 | #include "gk20a/css_gr_gk20a.h" | 19 | #include "gk20a/css_gr_gk20a.h" |
19 | #include "gk20a/bus_gk20a.h" | 20 | #include "gk20a/bus_gk20a.h" |
@@ -31,6 +32,7 @@ | |||
31 | #include "gp10b/regops_gp10b.h" | 32 | #include "gp10b/regops_gp10b.h" |
32 | #include "gp10b/cde_gp10b.h" | 33 | #include "gp10b/cde_gp10b.h" |
33 | #include "gp10b/priv_ring_gp10b.h" | 34 | #include "gp10b/priv_ring_gp10b.h" |
35 | #include "gp10b/fifo_gp10b.h" | ||
34 | 36 | ||
35 | #include "gp106/fifo_gp106.h" | 37 | #include "gp106/fifo_gp106.h" |
36 | #include "gp106/regops_gp106.h" | 38 | #include "gp106/regops_gp106.h" |
@@ -62,6 +64,9 @@ | |||
62 | #include <nvgpu/bus.h> | 64 | #include <nvgpu/bus.h> |
63 | 65 | ||
64 | #include <nvgpu/hw/gp106/hw_proj_gp106.h> | 66 | #include <nvgpu/hw/gp106/hw_proj_gp106.h> |
67 | #include <nvgpu/hw/gp106/hw_fifo_gp106.h> | ||
68 | #include <nvgpu/hw/gp106/hw_ram_gp106.h> | ||
69 | #include <nvgpu/hw/gp106/hw_top_gp106.h> | ||
65 | 70 | ||
66 | static int gp106_get_litter_value(struct gk20a *g, int value) | 71 | static int gp106_get_litter_value(struct gk20a *g, int value) |
67 | { | 72 | { |
@@ -243,6 +248,66 @@ static const struct gpu_ops gp106_ops = { | |||
243 | .pg_gr_load_gating_prod = | 248 | .pg_gr_load_gating_prod = |
244 | gr_gp106_pg_gr_load_gating_prod, | 249 | gr_gp106_pg_gr_load_gating_prod, |
245 | }, | 250 | }, |
251 | .fifo = { | ||
252 | .init_fifo_setup_hw = gk20a_init_fifo_setup_hw, | ||
253 | .bind_channel = channel_gm20b_bind, | ||
254 | .unbind_channel = gk20a_fifo_channel_unbind, | ||
255 | .disable_channel = gk20a_fifo_disable_channel, | ||
256 | .enable_channel = gk20a_fifo_enable_channel, | ||
257 | .alloc_inst = gk20a_fifo_alloc_inst, | ||
258 | .free_inst = gk20a_fifo_free_inst, | ||
259 | .setup_ramfc = channel_gp10b_setup_ramfc, | ||
260 | .channel_set_priority = gk20a_fifo_set_priority, | ||
261 | .channel_set_timeslice = gk20a_fifo_set_timeslice, | ||
262 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, | ||
263 | .setup_userd = gk20a_fifo_setup_userd, | ||
264 | .userd_gp_get = gk20a_fifo_userd_gp_get, | ||
265 | .userd_gp_put = gk20a_fifo_userd_gp_put, | ||
266 | .userd_pb_get = gk20a_fifo_userd_pb_get, | ||
267 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, | ||
268 | .preempt_channel = gk20a_fifo_preempt_channel, | ||
269 | .preempt_tsg = gk20a_fifo_preempt_tsg, | ||
270 | .update_runlist = gk20a_fifo_update_runlist, | ||
271 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, | ||
272 | .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info, | ||
273 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, | ||
274 | .get_num_fifos = gp106_fifo_get_num_fifos, | ||
275 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, | ||
276 | .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, | ||
277 | .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, | ||
278 | .force_reset_ch = gk20a_fifo_force_reset_ch, | ||
279 | .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, | ||
280 | .device_info_data_parse = gp10b_device_info_data_parse, | ||
281 | .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, | ||
282 | .init_engine_info = gk20a_fifo_init_engine_info, | ||
283 | .runlist_entry_size = ram_rl_entry_size_v, | ||
284 | .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry, | ||
285 | .get_ch_runlist_entry = gk20a_get_ch_runlist_entry, | ||
286 | .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, | ||
287 | .dump_pbdma_status = gk20a_dump_pbdma_status, | ||
288 | .dump_eng_status = gk20a_dump_eng_status, | ||
289 | .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc, | ||
290 | .intr_0_error_mask = gk20a_fifo_intr_0_error_mask, | ||
291 | .is_preempt_pending = gk20a_fifo_is_preempt_pending, | ||
292 | .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs, | ||
293 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, | ||
294 | .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, | ||
295 | .handle_sched_error = gk20a_fifo_handle_sched_error, | ||
296 | .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, | ||
297 | .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, | ||
298 | .tsg_bind_channel = gk20a_tsg_bind_channel, | ||
299 | .tsg_unbind_channel = gk20a_tsg_unbind_channel, | ||
300 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
301 | .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, | ||
302 | .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, | ||
303 | .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd, | ||
304 | .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size, | ||
305 | .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd, | ||
306 | .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, | ||
307 | #endif | ||
308 | .resetup_ramfc = gp10b_fifo_resetup_ramfc, | ||
309 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, | ||
310 | }, | ||
246 | .mc = { | 311 | .mc = { |
247 | .intr_enable = mc_gp10b_intr_enable, | 312 | .intr_enable = mc_gp10b_intr_enable, |
248 | .intr_unit_config = mc_gp10b_intr_unit_config, | 313 | .intr_unit_config = mc_gp10b_intr_unit_config, |
@@ -331,6 +396,7 @@ int gp106_init_hal(struct gk20a *g) | |||
331 | 396 | ||
332 | gops->ltc = gp106_ops.ltc; | 397 | gops->ltc = gp106_ops.ltc; |
333 | gops->clock_gating = gp106_ops.clock_gating; | 398 | gops->clock_gating = gp106_ops.clock_gating; |
399 | gops->fifo = gp106_ops.fifo; | ||
334 | gops->mc = gp106_ops.mc; | 400 | gops->mc = gp106_ops.mc; |
335 | gops->debug = gp106_ops.debug; | 401 | gops->debug = gp106_ops.debug; |
336 | gops->dbg_session_ops = gp106_ops.dbg_session_ops; | 402 | gops->dbg_session_ops = gp106_ops.dbg_session_ops; |
@@ -358,7 +424,6 @@ int gp106_init_hal(struct gk20a *g) | |||
358 | gp106_init_gr(gops); | 424 | gp106_init_gr(gops); |
359 | gp10b_init_fecs_trace_ops(gops); | 425 | gp10b_init_fecs_trace_ops(gops); |
360 | gp106_init_fb(gops); | 426 | gp106_init_fb(gops); |
361 | gp106_init_fifo(gops); | ||
362 | gp10b_init_ce(gops); | 427 | gp10b_init_ce(gops); |
363 | gp106_init_gr_ctx(gops); | 428 | gp106_init_gr_ctx(gops); |
364 | gp106_init_mm(gops); | 429 | gp106_init_mm(gops); |
@@ -366,7 +431,6 @@ int gp106_init_hal(struct gk20a *g) | |||
366 | gp106_init_clk_ops(gops); | 431 | gp106_init_clk_ops(gops); |
367 | gp106_init_clk_arb_ops(gops); | 432 | gp106_init_clk_arb_ops(gops); |
368 | gp106_init_regops(gops); | 433 | gp106_init_regops(gops); |
369 | gk20a_init_tsg_ops(gops); | ||
370 | gk20a_init_pramin_ops(gops); | 434 | gk20a_init_pramin_ops(gops); |
371 | gp106_init_therm_ops(gops); | 435 | gp106_init_therm_ops(gops); |
372 | 436 | ||
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index 633fbfb7..99d9d744 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | |||
@@ -80,7 +80,7 @@ int channel_gp10b_commit_userd(struct channel_gk20a *c) | |||
80 | return 0; | 80 | return 0; |
81 | } | 81 | } |
82 | 82 | ||
83 | static int channel_gp10b_setup_ramfc(struct channel_gk20a *c, | 83 | int channel_gp10b_setup_ramfc(struct channel_gk20a *c, |
84 | u64 gpfifo_base, u32 gpfifo_entries, | 84 | u64 gpfifo_base, u32 gpfifo_entries, |
85 | unsigned long acquire_timeout, u32 flags) | 85 | unsigned long acquire_timeout, u32 flags) |
86 | { | 86 | { |
@@ -147,13 +147,13 @@ static int channel_gp10b_setup_ramfc(struct channel_gk20a *c, | |||
147 | return channel_gp10b_commit_userd(c); | 147 | return channel_gp10b_commit_userd(c); |
148 | } | 148 | } |
149 | 149 | ||
150 | static u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g) | 150 | u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g) |
151 | { | 151 | { |
152 | return g->gpu_characteristics.gpfifo_class | 152 | return g->gpu_characteristics.gpfifo_class |
153 | | pbdma_signature_sw_zero_f(); | 153 | | pbdma_signature_sw_zero_f(); |
154 | } | 154 | } |
155 | 155 | ||
156 | static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c) | 156 | int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c) |
157 | { | 157 | { |
158 | u32 new_syncpt = 0, old_syncpt; | 158 | u32 new_syncpt = 0, old_syncpt; |
159 | u32 v; | 159 | u32 v; |
@@ -192,7 +192,7 @@ static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c) | |||
192 | return 0; | 192 | return 0; |
193 | } | 193 | } |
194 | 194 | ||
195 | static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type, | 195 | int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type, |
196 | u32 *inst_id) | 196 | u32 *inst_id) |
197 | { | 197 | { |
198 | int ret = ENGINE_INVAL_GK20A; | 198 | int ret = ENGINE_INVAL_GK20A; |
@@ -208,7 +208,7 @@ static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type, | |||
208 | return ret; | 208 | return ret; |
209 | } | 209 | } |
210 | 210 | ||
211 | static void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry, | 211 | void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry, |
212 | u32 *inst_id, u32 *pri_base, u32 *fault_id) | 212 | u32 *inst_id, u32 *pri_base, u32 *fault_id) |
213 | { | 213 | { |
214 | if (top_device_info_data_type_v(table_entry) == | 214 | if (top_device_info_data_type_v(table_entry) == |
@@ -232,7 +232,7 @@ static void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry, | |||
232 | top_device_info_data_type_v(table_entry)); | 232 | top_device_info_data_type_v(table_entry)); |
233 | } | 233 | } |
234 | 234 | ||
235 | static void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) | 235 | void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) |
236 | { | 236 | { |
237 | /* | 237 | /* |
238 | * These are all errors which indicate something really wrong | 238 | * These are all errors which indicate something really wrong |
@@ -277,7 +277,7 @@ static void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) | |||
277 | pbdma_intr_0_device_pending_f(); | 277 | pbdma_intr_0_device_pending_f(); |
278 | } | 278 | } |
279 | 279 | ||
280 | static void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, | 280 | void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, |
281 | struct mmu_fault_info *mmfault) | 281 | struct mmu_fault_info *mmfault) |
282 | { | 282 | { |
283 | u32 fault_info; | 283 | u32 fault_info; |
@@ -307,17 +307,3 @@ static void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, | |||
307 | /* note: inst_ptr is a 40b phys addr. */ | 307 | /* note: inst_ptr is a 40b phys addr. */ |
308 | mmfault->inst_ptr <<= fifo_intr_mmu_fault_inst_ptr_align_shift_v(); | 308 | mmfault->inst_ptr <<= fifo_intr_mmu_fault_inst_ptr_align_shift_v(); |
309 | } | 309 | } |
310 | |||
311 | void gp10b_init_fifo(struct gpu_ops *gops) | ||
312 | { | ||
313 | gm20b_init_fifo(gops); | ||
314 | gops->fifo.get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info; | ||
315 | gops->fifo.setup_ramfc = channel_gp10b_setup_ramfc; | ||
316 | gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature; | ||
317 | gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc; | ||
318 | gops->fifo.engine_enum_from_type = gp10b_fifo_engine_enum_from_type; | ||
319 | gops->fifo.device_info_data_parse = gp10b_device_info_data_parse; | ||
320 | gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; | ||
321 | gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v; | ||
322 | gops->fifo.init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs; | ||
323 | } | ||
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h index da0e82a9..369bed9a 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B Fifo | 2 | * GP10B Fifo |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -18,8 +18,21 @@ | |||
18 | 18 | ||
19 | struct gpu_ops; | 19 | struct gpu_ops; |
20 | struct channel_gk20a; | 20 | struct channel_gk20a; |
21 | struct fifo_gk20a; | ||
22 | struct mmu_fault_info; | ||
21 | 23 | ||
22 | void gp10b_init_fifo(struct gpu_ops *gops); | 24 | int channel_gp10b_setup_ramfc(struct channel_gk20a *c, |
25 | u64 gpfifo_base, u32 gpfifo_entries, | ||
26 | unsigned long acquire_timeout, u32 flags); | ||
27 | u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g); | ||
28 | int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c); | ||
29 | int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type, | ||
30 | u32 *inst_id); | ||
31 | void gp10b_device_info_data_parse(struct gk20a *g, u32 table_entry, | ||
32 | u32 *inst_id, u32 *pri_base, u32 *fault_id); | ||
33 | void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f); | ||
34 | void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, | ||
35 | struct mmu_fault_info *mmfault); | ||
23 | int channel_gp10b_commit_userd(struct channel_gk20a *c); | 36 | int channel_gp10b_commit_userd(struct channel_gk20a *c); |
24 | 37 | ||
25 | #endif | 38 | #endif |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 4479be42..d603703b 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -14,6 +14,7 @@ | |||
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include "gk20a/gk20a.h" | 16 | #include "gk20a/gk20a.h" |
17 | #include "gk20a/fifo_gk20a.h" | ||
17 | #include "gk20a/dbg_gpu_gk20a.h" | 18 | #include "gk20a/dbg_gpu_gk20a.h" |
18 | #include "gk20a/css_gr_gk20a.h" | 19 | #include "gk20a/css_gr_gk20a.h" |
19 | #include "gk20a/bus_gk20a.h" | 20 | #include "gk20a/bus_gk20a.h" |
@@ -43,6 +44,7 @@ | |||
43 | #include "gm20b/fifo_gm20b.h" | 44 | #include "gm20b/fifo_gm20b.h" |
44 | #include "gm20b/pmu_gm20b.h" | 45 | #include "gm20b/pmu_gm20b.h" |
45 | #include "gm20b/clk_gm20b.h" | 46 | #include "gm20b/clk_gm20b.h" |
47 | #include "gm20b/fifo_gm20b.h" | ||
46 | 48 | ||
47 | #include "gp10b.h" | 49 | #include "gp10b.h" |
48 | #include "hal_gp10b.h" | 50 | #include "hal_gp10b.h" |
@@ -54,6 +56,9 @@ | |||
54 | 56 | ||
55 | #include <nvgpu/hw/gp10b/hw_proj_gp10b.h> | 57 | #include <nvgpu/hw/gp10b/hw_proj_gp10b.h> |
56 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | 58 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> |
59 | #include <nvgpu/hw/gp10b/hw_fifo_gp10b.h> | ||
60 | #include <nvgpu/hw/gp10b/hw_ram_gp10b.h> | ||
61 | #include <nvgpu/hw/gp10b/hw_top_gp10b.h> | ||
57 | 62 | ||
58 | static int gp10b_get_litter_value(struct gk20a *g, int value) | 63 | static int gp10b_get_litter_value(struct gk20a *g, int value) |
59 | { | 64 | { |
@@ -210,6 +215,66 @@ static const struct gpu_ops gp10b_ops = { | |||
210 | .pg_gr_load_gating_prod = | 215 | .pg_gr_load_gating_prod = |
211 | gr_gp10b_pg_gr_load_gating_prod, | 216 | gr_gp10b_pg_gr_load_gating_prod, |
212 | }, | 217 | }, |
218 | .fifo = { | ||
219 | .init_fifo_setup_hw = gk20a_init_fifo_setup_hw, | ||
220 | .bind_channel = channel_gm20b_bind, | ||
221 | .unbind_channel = gk20a_fifo_channel_unbind, | ||
222 | .disable_channel = gk20a_fifo_disable_channel, | ||
223 | .enable_channel = gk20a_fifo_enable_channel, | ||
224 | .alloc_inst = gk20a_fifo_alloc_inst, | ||
225 | .free_inst = gk20a_fifo_free_inst, | ||
226 | .setup_ramfc = channel_gp10b_setup_ramfc, | ||
227 | .channel_set_priority = gk20a_fifo_set_priority, | ||
228 | .channel_set_timeslice = gk20a_fifo_set_timeslice, | ||
229 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, | ||
230 | .setup_userd = gk20a_fifo_setup_userd, | ||
231 | .userd_gp_get = gk20a_fifo_userd_gp_get, | ||
232 | .userd_gp_put = gk20a_fifo_userd_gp_put, | ||
233 | .userd_pb_get = gk20a_fifo_userd_pb_get, | ||
234 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, | ||
235 | .preempt_channel = gk20a_fifo_preempt_channel, | ||
236 | .preempt_tsg = gk20a_fifo_preempt_tsg, | ||
237 | .update_runlist = gk20a_fifo_update_runlist, | ||
238 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, | ||
239 | .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info, | ||
240 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, | ||
241 | .get_num_fifos = gm20b_fifo_get_num_fifos, | ||
242 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, | ||
243 | .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, | ||
244 | .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, | ||
245 | .force_reset_ch = gk20a_fifo_force_reset_ch, | ||
246 | .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, | ||
247 | .device_info_data_parse = gp10b_device_info_data_parse, | ||
248 | .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, | ||
249 | .init_engine_info = gk20a_fifo_init_engine_info, | ||
250 | .runlist_entry_size = ram_rl_entry_size_v, | ||
251 | .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry, | ||
252 | .get_ch_runlist_entry = gk20a_get_ch_runlist_entry, | ||
253 | .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, | ||
254 | .dump_pbdma_status = gk20a_dump_pbdma_status, | ||
255 | .dump_eng_status = gk20a_dump_eng_status, | ||
256 | .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc, | ||
257 | .intr_0_error_mask = gk20a_fifo_intr_0_error_mask, | ||
258 | .is_preempt_pending = gk20a_fifo_is_preempt_pending, | ||
259 | .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs, | ||
260 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, | ||
261 | .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, | ||
262 | .handle_sched_error = gk20a_fifo_handle_sched_error, | ||
263 | .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, | ||
264 | .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, | ||
265 | .tsg_bind_channel = gk20a_tsg_bind_channel, | ||
266 | .tsg_unbind_channel = gk20a_tsg_unbind_channel, | ||
267 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
268 | .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, | ||
269 | .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, | ||
270 | .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd, | ||
271 | .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size, | ||
272 | .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd, | ||
273 | .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, | ||
274 | #endif | ||
275 | .resetup_ramfc = gp10b_fifo_resetup_ramfc, | ||
276 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, | ||
277 | }, | ||
213 | .mc = { | 278 | .mc = { |
214 | .intr_enable = mc_gp10b_intr_enable, | 279 | .intr_enable = mc_gp10b_intr_enable, |
215 | .intr_unit_config = mc_gp10b_intr_unit_config, | 280 | .intr_unit_config = mc_gp10b_intr_unit_config, |
@@ -281,6 +346,7 @@ int gp10b_init_hal(struct gk20a *g) | |||
281 | 346 | ||
282 | gops->ltc = gp10b_ops.ltc; | 347 | gops->ltc = gp10b_ops.ltc; |
283 | gops->clock_gating = gp10b_ops.clock_gating; | 348 | gops->clock_gating = gp10b_ops.clock_gating; |
349 | gops->fifo = gp10b_ops.fifo; | ||
284 | gops->mc = gp10b_ops.mc; | 350 | gops->mc = gp10b_ops.mc; |
285 | gops->debug = gp10b_ops.debug; | 351 | gops->debug = gp10b_ops.debug; |
286 | gops->dbg_session_ops = gp10b_ops.dbg_session_ops; | 352 | gops->dbg_session_ops = gp10b_ops.dbg_session_ops; |
@@ -340,14 +406,12 @@ int gp10b_init_hal(struct gk20a *g) | |||
340 | gp10b_init_gr(gops); | 406 | gp10b_init_gr(gops); |
341 | gp10b_init_fecs_trace_ops(gops); | 407 | gp10b_init_fecs_trace_ops(gops); |
342 | gp10b_init_fb(gops); | 408 | gp10b_init_fb(gops); |
343 | gp10b_init_fifo(gops); | ||
344 | gp10b_init_ce(gops); | 409 | gp10b_init_ce(gops); |
345 | gp10b_init_gr_ctx(gops); | 410 | gp10b_init_gr_ctx(gops); |
346 | gp10b_init_mm(gops); | 411 | gp10b_init_mm(gops); |
347 | gp10b_init_pmu_ops(gops); | 412 | gp10b_init_pmu_ops(gops); |
348 | gp10b_init_regops(gops); | 413 | gp10b_init_regops(gops); |
349 | gp10b_init_therm_ops(gops); | 414 | gp10b_init_therm_ops(gops); |
350 | gk20a_init_tsg_ops(gops); | ||
351 | gk20a_init_pramin_ops(gops); | 415 | gk20a_init_pramin_ops(gops); |
352 | 416 | ||
353 | g->name = "gp10b"; | 417 | g->name = "gp10b"; |