diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fb_vgpu.c | 45 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fb_vgpu.h | 28 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gr_vgpu.c | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 5 |
9 files changed, 116 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index aad186ec..472bf32c 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -279,6 +279,7 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ | |||
279 | vgpu/css_vgpu.o \ | 279 | vgpu/css_vgpu.o \ |
280 | vgpu/ecc_vgpu.o \ | 280 | vgpu/ecc_vgpu.o \ |
281 | vgpu/clk_vgpu.o \ | 281 | vgpu/clk_vgpu.o \ |
282 | vgpu/fb_vgpu.o \ | ||
282 | vgpu/gm20b/vgpu_gr_gm20b.o \ | 283 | vgpu/gm20b/vgpu_gr_gm20b.o \ |
283 | vgpu/gp10b/vgpu_hal_gp10b.o \ | 284 | vgpu/gp10b/vgpu_hal_gp10b.o \ |
284 | vgpu/gp10b/vgpu_gr_gp10b.o \ | 285 | vgpu/gp10b/vgpu_gr_gp10b.o \ |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h index 6abb5e33..e33dce94 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | |||
@@ -123,6 +123,8 @@ enum { | |||
123 | TEGRA_VGPU_CMD_RESUME = 83, | 123 | TEGRA_VGPU_CMD_RESUME = 83, |
124 | TEGRA_VGPU_CMD_GET_ECC_INFO = 84, | 124 | TEGRA_VGPU_CMD_GET_ECC_INFO = 84, |
125 | TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE = 85, | 125 | TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE = 85, |
126 | TEGRA_VGPU_CMD_FB_SET_MMU_DEBUG_MODE = 88, | ||
127 | TEGRA_VGPU_CMD_GR_SET_MMU_DEBUG_MODE = 89, | ||
126 | }; | 128 | }; |
127 | 129 | ||
128 | struct tegra_vgpu_connect_params { | 130 | struct tegra_vgpu_connect_params { |
@@ -617,6 +619,15 @@ struct tegra_vgpu_tsg_bind_channel_ex_params { | |||
617 | u32 runqueue_sel; | 619 | u32 runqueue_sel; |
618 | }; | 620 | }; |
619 | 621 | ||
622 | struct tegra_vgpu_fb_set_mmu_debug_mode_params { | ||
623 | u8 enable; | ||
624 | }; | ||
625 | |||
626 | struct tegra_vgpu_gr_set_mmu_debug_mode_params { | ||
627 | u64 ch_handle; | ||
628 | u8 enable; | ||
629 | }; | ||
630 | |||
620 | struct tegra_vgpu_cmd_msg { | 631 | struct tegra_vgpu_cmd_msg { |
621 | u32 cmd; | 632 | u32 cmd; |
622 | int ret; | 633 | int ret; |
@@ -679,6 +690,8 @@ struct tegra_vgpu_cmd_msg { | |||
679 | struct tegra_vgpu_channel_update_pc_sampling update_pc_sampling; | 690 | struct tegra_vgpu_channel_update_pc_sampling update_pc_sampling; |
680 | struct tegra_vgpu_ecc_info_params ecc_info; | 691 | struct tegra_vgpu_ecc_info_params ecc_info; |
681 | struct tegra_vgpu_ecc_counter_params ecc_counter; | 692 | struct tegra_vgpu_ecc_counter_params ecc_counter; |
693 | struct tegra_vgpu_fb_set_mmu_debug_mode_params fb_set_mmu_debug_mode; | ||
694 | struct tegra_vgpu_gr_set_mmu_debug_mode_params gr_set_mmu_debug_mode; | ||
682 | char padding[192]; | 695 | char padding[192]; |
683 | } params; | 696 | } params; |
684 | }; | 697 | }; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h index 15ab879e..ecdb8964 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/vgpu.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -39,6 +39,7 @@ struct vm_gk20a; | |||
39 | struct nvgpu_gr_ctx; | 39 | struct nvgpu_gr_ctx; |
40 | struct nvgpu_cpu_time_correlation_sample; | 40 | struct nvgpu_cpu_time_correlation_sample; |
41 | struct vgpu_ecc_stat; | 41 | struct vgpu_ecc_stat; |
42 | struct channel_gk20a; | ||
42 | 43 | ||
43 | struct vgpu_priv_data { | 44 | struct vgpu_priv_data { |
44 | u64 virt_handle; | 45 | u64 virt_handle; |
@@ -104,4 +105,6 @@ int vgpu_gv11b_init_hal(struct gk20a *g); | |||
104 | 105 | ||
105 | bool vgpu_is_reduced_bar1(struct gk20a *g); | 106 | bool vgpu_is_reduced_bar1(struct gk20a *g); |
106 | 107 | ||
108 | int vgpu_gr_set_mmu_debug_mode(struct gk20a *g, | ||
109 | struct channel_gk20a *ch, bool enable); | ||
107 | #endif | 110 | #endif |
diff --git a/drivers/gpu/nvgpu/vgpu/fb_vgpu.c b/drivers/gpu/nvgpu/vgpu/fb_vgpu.c new file mode 100644 index 00000000..cb7ea861 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/fb_vgpu.c | |||
@@ -0,0 +1,45 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/gk20a.h> | ||
24 | #include <nvgpu/vgpu/tegra_vgpu.h> | ||
25 | #include <nvgpu/vgpu/vgpu.h> | ||
26 | |||
27 | #include "fb_vgpu.h" | ||
28 | |||
29 | void vgpu_fb_set_mmu_debug_mode(struct gk20a *g, bool enable) | ||
30 | { | ||
31 | struct tegra_vgpu_cmd_msg msg = {}; | ||
32 | struct tegra_vgpu_fb_set_mmu_debug_mode_params *p = | ||
33 | &msg.params.fb_set_mmu_debug_mode; | ||
34 | int err; | ||
35 | |||
36 | msg.cmd = TEGRA_VGPU_CMD_FB_SET_MMU_DEBUG_MODE; | ||
37 | msg.handle = vgpu_get_handle(g); | ||
38 | p->enable = enable ? 1U : 0U; | ||
39 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
40 | err = err != 0 ? err : msg.ret; | ||
41 | if (err != 0) { | ||
42 | nvgpu_err(g, | ||
43 | "fb set mmu debug mode failed err %d", err); | ||
44 | } | ||
45 | } | ||
diff --git a/drivers/gpu/nvgpu/vgpu/fb_vgpu.h b/drivers/gpu/nvgpu/vgpu/fb_vgpu.h new file mode 100644 index 00000000..dc98e012 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/fb_vgpu.h | |||
@@ -0,0 +1,28 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef FB_VGPU_H | ||
24 | #define FB_VGPU_H | ||
25 | |||
26 | void vgpu_fb_set_mmu_debug_mode(struct gk20a *g, bool enable); | ||
27 | |||
28 | #endif | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index a4f02faa..fe89dcfb 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -41,6 +41,7 @@ | |||
41 | #include "vgpu/dbg_vgpu.h" | 41 | #include "vgpu/dbg_vgpu.h" |
42 | #include "vgpu/fecs_trace_vgpu.h" | 42 | #include "vgpu/fecs_trace_vgpu.h" |
43 | #include "vgpu/css_vgpu.h" | 43 | #include "vgpu/css_vgpu.h" |
44 | #include "vgpu/fb_vgpu.h" | ||
44 | #include "gp10b/gp10b.h" | 45 | #include "gp10b/gp10b.h" |
45 | #include "gp10b/hal_gp10b.h" | 46 | #include "gp10b/hal_gp10b.h" |
46 | #include "vgpu/gm20b/vgpu_gr_gm20b.h" | 47 | #include "vgpu/gm20b/vgpu_gr_gm20b.h" |
@@ -250,7 +251,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
250 | .read_wpr_info = NULL, | 251 | .read_wpr_info = NULL, |
251 | .is_debug_mode_enabled = NULL, | 252 | .is_debug_mode_enabled = NULL, |
252 | .set_debug_mode = vgpu_mm_mmu_set_debug_mode, | 253 | .set_debug_mode = vgpu_mm_mmu_set_debug_mode, |
253 | .set_mmu_debug_mode = NULL, | 254 | .set_mmu_debug_mode = vgpu_fb_set_mmu_debug_mode, |
254 | .tlb_invalidate = vgpu_mm_tlb_invalidate, | 255 | .tlb_invalidate = vgpu_mm_tlb_invalidate, |
255 | }, | 256 | }, |
256 | .clock_gating = { | 257 | .clock_gating = { |
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index e3b1888e..cb4a441a 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Virtualized GPU Graphics | 2 | * Virtualized GPU Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -1378,3 +1378,21 @@ int vgpu_gr_update_pc_sampling(struct channel_gk20a *ch, bool enable) | |||
1378 | 1378 | ||
1379 | return err ? err : msg.ret; | 1379 | return err ? err : msg.ret; |
1380 | } | 1380 | } |
1381 | |||
1382 | int vgpu_gr_set_mmu_debug_mode(struct gk20a *g, | ||
1383 | struct channel_gk20a *ch, bool enable) | ||
1384 | { | ||
1385 | struct tegra_vgpu_cmd_msg msg = {}; | ||
1386 | struct tegra_vgpu_gr_set_mmu_debug_mode_params *p = | ||
1387 | &msg.params.gr_set_mmu_debug_mode; | ||
1388 | int err; | ||
1389 | |||
1390 | msg.cmd = TEGRA_VGPU_CMD_GR_SET_MMU_DEBUG_MODE; | ||
1391 | msg.handle = vgpu_get_handle(g); | ||
1392 | p->ch_handle = ch->virt_ctx; | ||
1393 | p->enable = enable ? 1U : 0U; | ||
1394 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
1395 | WARN_ON(err || msg.ret); | ||
1396 | |||
1397 | return err ? err : msg.ret; | ||
1398 | } | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c index 2190478e..a6c11719 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c | |||
@@ -44,7 +44,7 @@ int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g) | |||
44 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true); | 44 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true); |
45 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true); | 45 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true); |
46 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true); | 46 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true); |
47 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); | 47 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, true); |
48 | 48 | ||
49 | return 0; | 49 | return 0; |
50 | } | 50 | } |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index f51d4c35..cfd4e385 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -49,6 +49,7 @@ | |||
49 | #include "vgpu/dbg_vgpu.h" | 49 | #include "vgpu/dbg_vgpu.h" |
50 | #include "vgpu/fecs_trace_vgpu.h" | 50 | #include "vgpu/fecs_trace_vgpu.h" |
51 | #include "vgpu/css_vgpu.h" | 51 | #include "vgpu/css_vgpu.h" |
52 | #include "vgpu/fb_vgpu.h" | ||
52 | #include "vgpu/gm20b/vgpu_gr_gm20b.h" | 53 | #include "vgpu/gm20b/vgpu_gr_gm20b.h" |
53 | #include "vgpu/gp10b/vgpu_mm_gp10b.h" | 54 | #include "vgpu/gp10b/vgpu_mm_gp10b.h" |
54 | #include "vgpu/gp10b/vgpu_gr_gp10b.h" | 55 | #include "vgpu/gp10b/vgpu_gr_gp10b.h" |
@@ -189,7 +190,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
189 | .get_hw_accessor_stream_out_mode = | 190 | .get_hw_accessor_stream_out_mode = |
190 | gr_gv100_get_hw_accessor_stream_out_mode, | 191 | gr_gv100_get_hw_accessor_stream_out_mode, |
191 | .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, | 192 | .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, |
192 | .set_mmu_debug_mode = NULL, | 193 | .set_mmu_debug_mode = vgpu_gr_set_mmu_debug_mode, |
193 | .record_sm_error_state = gv11b_gr_record_sm_error_state, | 194 | .record_sm_error_state = gv11b_gr_record_sm_error_state, |
194 | .clear_sm_error_state = vgpu_gr_clear_sm_error_state, | 195 | .clear_sm_error_state = vgpu_gr_clear_sm_error_state, |
195 | .suspend_contexts = vgpu_gr_suspend_contexts, | 196 | .suspend_contexts = vgpu_gr_suspend_contexts, |
@@ -291,7 +292,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
291 | .read_wpr_info = NULL, | 292 | .read_wpr_info = NULL, |
292 | .is_debug_mode_enabled = NULL, | 293 | .is_debug_mode_enabled = NULL, |
293 | .set_debug_mode = vgpu_mm_mmu_set_debug_mode, | 294 | .set_debug_mode = vgpu_mm_mmu_set_debug_mode, |
294 | .set_mmu_debug_mode = NULL, | 295 | .set_mmu_debug_mode = vgpu_fb_set_mmu_debug_mode, |
295 | .tlb_invalidate = vgpu_mm_tlb_invalidate, | 296 | .tlb_invalidate = vgpu_mm_tlb_invalidate, |
296 | .hub_isr = gv11b_fb_hub_isr, | 297 | .hub_isr = gv11b_fb_hub_isr, |
297 | .enable_hub_intr = gv11b_fb_enable_hub_intr, | 298 | .enable_hub_intr = gv11b_fb_enable_hub_intr, |