diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 53 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gr_vgpu.c | 71 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/vgpu.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/vgpu.h | 12 |
4 files changed, 107 insertions, 33 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 24b9f4be..45d956a2 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Virtualized GPU Fifo | 2 | * Virtualized GPU Fifo |
3 | * | 3 | * |
4 | * Copyright (c) 2014 NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -551,6 +551,57 @@ static int vgpu_fifo_wait_engine_idle(struct gk20a *g) | |||
551 | return 0; | 551 | return 0; |
552 | } | 552 | } |
553 | 553 | ||
554 | static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g, | ||
555 | struct channel_gk20a *ch) | ||
556 | { | ||
557 | if (ch->error_notifier) { | ||
558 | if (ch->error_notifier->status == 0xffff) { | ||
559 | /* If error code is already set, this mmu fault | ||
560 | * was triggered as part of recovery from other | ||
561 | * error condition. | ||
562 | * Don't overwrite error flag. */ | ||
563 | } else { | ||
564 | gk20a_set_error_notifier(ch, | ||
565 | NVGPU_CHANNEL_FIFO_ERROR_MMU_ERR_FLT); | ||
566 | } | ||
567 | } | ||
568 | /* mark channel as faulted */ | ||
569 | ch->has_timedout = true; | ||
570 | wmb(); | ||
571 | /* unblock pending waits */ | ||
572 | wake_up(&ch->semaphore_wq); | ||
573 | wake_up(&ch->notifier_wq); | ||
574 | wake_up(&ch->submit_wq); | ||
575 | } | ||
576 | |||
577 | int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info) | ||
578 | { | ||
579 | struct fifo_gk20a *f = &g->fifo; | ||
580 | struct channel_gk20a *ch = &f->channel[info->chid]; | ||
581 | |||
582 | gk20a_err(dev_from_gk20a(g), "fifo intr (%d) on ch %u", | ||
583 | info->type, info->chid); | ||
584 | |||
585 | switch (info->type) { | ||
586 | case TEGRA_VGPU_FIFO_INTR_PBDMA: | ||
587 | gk20a_set_error_notifier(ch, NVGPU_CHANNEL_PBDMA_ERROR); | ||
588 | break; | ||
589 | case TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT: | ||
590 | gk20a_set_error_notifier(ch, | ||
591 | NVGPU_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT); | ||
592 | break; | ||
593 | case TEGRA_VGPU_FIFO_INTR_MMU_FAULT: | ||
594 | gk20a_channel_abort(ch); | ||
595 | vgpu_fifo_set_ctx_mmu_error(g, ch); | ||
596 | break; | ||
597 | default: | ||
598 | WARN_ON(1); | ||
599 | break; | ||
600 | } | ||
601 | |||
602 | return 0; | ||
603 | } | ||
604 | |||
554 | void vgpu_init_fifo_ops(struct gpu_ops *gops) | 605 | void vgpu_init_fifo_ops(struct gpu_ops *gops) |
555 | { | 606 | { |
556 | gops->fifo.bind_channel = vgpu_channel_bind; | 607 | gops->fifo.bind_channel = vgpu_channel_bind; |
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index b1a8027e..aac097d9 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Virtualized GPU Graphics | 2 | * Virtualized GPU Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2014 NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -668,38 +668,51 @@ int vgpu_init_gr_support(struct gk20a *g) | |||
668 | return vgpu_gr_init_gr_setup_sw(g); | 668 | return vgpu_gr_init_gr_setup_sw(g); |
669 | } | 669 | } |
670 | 670 | ||
671 | struct gr_isr_data { | ||
672 | u32 addr; | ||
673 | u32 data_lo; | ||
674 | u32 data_hi; | ||
675 | u32 curr_ctx; | ||
676 | u32 chid; | ||
677 | u32 offset; | ||
678 | u32 sub_chan; | ||
679 | u32 class_num; | ||
680 | }; | ||
681 | |||
682 | static int vgpu_gr_handle_notify_pending(struct gk20a *g, | ||
683 | struct gr_isr_data *isr_data) | ||
684 | { | ||
685 | struct fifo_gk20a *f = &g->fifo; | ||
686 | struct channel_gk20a *ch = &f->channel[isr_data->chid]; | ||
687 | |||
688 | gk20a_dbg_fn(""); | ||
689 | wake_up(&ch->notifier_wq); | ||
690 | return 0; | ||
691 | } | ||
692 | |||
693 | int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info) | 671 | int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info) |
694 | { | 672 | { |
695 | struct gr_isr_data isr_data; | 673 | struct fifo_gk20a *f = &g->fifo; |
674 | struct channel_gk20a *ch = &f->channel[info->chid]; | ||
696 | 675 | ||
697 | gk20a_dbg_fn(""); | 676 | gk20a_dbg_fn(""); |
698 | 677 | if (info->type != TEGRA_VGPU_GR_INTR_NOTIFY) | |
699 | isr_data.chid = info->chid; | 678 | gk20a_err(dev_from_gk20a(g), "gr intr (%d) on ch %u", |
700 | 679 | info->type, info->chid); | |
701 | if (info->type == TEGRA_VGPU_GR_INTR_NOTIFY) | 680 | |
702 | vgpu_gr_handle_notify_pending(g, &isr_data); | 681 | switch (info->type) { |
682 | case TEGRA_VGPU_GR_INTR_NOTIFY: | ||
683 | wake_up(&ch->notifier_wq); | ||
684 | break; | ||
685 | case TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT: | ||
686 | gk20a_set_error_notifier(ch, | ||
687 | NVGPU_CHANNEL_GR_SEMAPHORE_TIMEOUT); | ||
688 | break; | ||
689 | case TEGRA_VGPU_GR_INTR_ILLEGAL_NOTIFY: | ||
690 | gk20a_set_error_notifier(ch, | ||
691 | NVGPU_CHANNEL_GR_ILLEGAL_NOTIFY); | ||
692 | case TEGRA_VGPU_GR_INTR_ILLEGAL_METHOD: | ||
693 | break; | ||
694 | case TEGRA_VGPU_GR_INTR_ILLEGAL_CLASS: | ||
695 | gk20a_set_error_notifier(ch, | ||
696 | NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY); | ||
697 | break; | ||
698 | case TEGRA_VGPU_GR_INTR_FECS_ERROR: | ||
699 | break; | ||
700 | case TEGRA_VGPU_GR_INTR_CLASS_ERROR: | ||
701 | gk20a_set_error_notifier(ch, | ||
702 | NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY); | ||
703 | break; | ||
704 | case TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD: | ||
705 | gk20a_set_error_notifier(ch, | ||
706 | NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY); | ||
707 | break; | ||
708 | case TEGRA_VGPU_GR_INTR_EXCEPTION: | ||
709 | gk20a_set_error_notifier(ch, | ||
710 | NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY); | ||
711 | break; | ||
712 | default: | ||
713 | WARN_ON(1); | ||
714 | break; | ||
715 | } | ||
703 | 716 | ||
704 | return 0; | 717 | return 0; |
705 | } | 718 | } |
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c index 36d65ee8..d3d793d1 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/vgpu.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Virtualized GPU | 2 | * Virtualized GPU |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -114,6 +114,8 @@ static int vgpu_intr_thread(void *dev_id) | |||
114 | 114 | ||
115 | if (msg->unit == TEGRA_VGPU_INTR_GR) | 115 | if (msg->unit == TEGRA_VGPU_INTR_GR) |
116 | vgpu_gr_isr(g, &msg->info.gr_intr); | 116 | vgpu_gr_isr(g, &msg->info.gr_intr); |
117 | else if (msg->unit == TEGRA_VGPU_INTR_FIFO) | ||
118 | vgpu_fifo_isr(g, &msg->info.fifo_intr); | ||
117 | 119 | ||
118 | tegra_gr_comm_release(handle); | 120 | tegra_gr_comm_release(handle); |
119 | } | 121 | } |
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.h b/drivers/gpu/nvgpu/vgpu/vgpu.h index 4677b36c..1a7ef7ba 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/vgpu.h | |||
@@ -27,6 +27,7 @@ int vgpu_probe(struct platform_device *dev); | |||
27 | int vgpu_remove(struct platform_device *dev); | 27 | int vgpu_remove(struct platform_device *dev); |
28 | u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt, u64 size); | 28 | u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt, u64 size); |
29 | int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info); | 29 | int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info); |
30 | int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info); | ||
30 | void vgpu_init_fifo_ops(struct gpu_ops *gops); | 31 | void vgpu_init_fifo_ops(struct gpu_ops *gops); |
31 | void vgpu_init_gr_ops(struct gpu_ops *gops); | 32 | void vgpu_init_gr_ops(struct gpu_ops *gops); |
32 | void vgpu_init_ltc_ops(struct gpu_ops *gops); | 33 | void vgpu_init_ltc_ops(struct gpu_ops *gops); |
@@ -56,11 +57,18 @@ static inline int vgpu_remove(struct platform_device *dev) | |||
56 | { | 57 | { |
57 | return -ENOSYS; | 58 | return -ENOSYS; |
58 | } | 59 | } |
59 | static inline u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt, u64 size) | 60 | static inline u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt, |
61 | u64 size) | ||
60 | { | 62 | { |
61 | return 0; | 63 | return 0; |
62 | } | 64 | } |
63 | static inline int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info) | 65 | static inline int vgpu_gr_isr(struct gk20a *g, |
66 | struct tegra_vgpu_gr_intr_info *info) | ||
67 | { | ||
68 | return 0; | ||
69 | } | ||
70 | static inline int vgpu_fifo_isr(struct gk20a *g, | ||
71 | struct tegra_vgpu_fifo_intr_info *info) | ||
64 | { | 72 | { |
65 | return 0; | 73 | return 0; |
66 | } | 74 | } |