diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c | 37 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 3 |
6 files changed, 46 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c index 88c8debf..4bb79375 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c | |||
@@ -429,15 +429,24 @@ static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g, | |||
429 | struct nvgpu_gpu_wait_pause_args *args) | 429 | struct nvgpu_gpu_wait_pause_args *args) |
430 | { | 430 | { |
431 | int err; | 431 | int err; |
432 | struct warpstate *w_state; | 432 | struct warpstate *ioctl_w_state; |
433 | u32 sm_count, size; | 433 | struct nvgpu_warpstate *w_state = NULL; |
434 | u32 sm_count, ioctl_size, size, sm_id; | ||
434 | 435 | ||
435 | sm_count = g->gr.gpc_count * g->gr.tpc_count; | 436 | sm_count = g->gr.gpc_count * g->gr.tpc_count; |
436 | size = sm_count * sizeof(struct warpstate); | 437 | |
437 | w_state = nvgpu_kzalloc(g, size); | 438 | ioctl_size = sm_count * sizeof(struct warpstate); |
438 | if (!w_state) | 439 | ioctl_w_state = nvgpu_kzalloc(g, ioctl_size); |
440 | if (!ioctl_w_state) | ||
439 | return -ENOMEM; | 441 | return -ENOMEM; |
440 | 442 | ||
443 | size = sm_count * sizeof(struct nvgpu_warpstate); | ||
444 | w_state = nvgpu_kzalloc(g, size); | ||
445 | if (!w_state) { | ||
446 | err = -ENOMEM; | ||
447 | goto out_free; | ||
448 | } | ||
449 | |||
441 | err = gk20a_busy(g); | 450 | err = gk20a_busy(g); |
442 | if (err) | 451 | if (err) |
443 | goto out_free; | 452 | goto out_free; |
@@ -445,8 +454,23 @@ static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g, | |||
445 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | 454 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); |
446 | g->ops.gr.wait_for_pause(g, w_state); | 455 | g->ops.gr.wait_for_pause(g, w_state); |
447 | 456 | ||
457 | for (sm_id = 0; sm_id < g->gr.no_of_sm; sm_id++) { | ||
458 | ioctl_w_state[sm_id].valid_warps[0] = | ||
459 | w_state[sm_id].valid_warps[0]; | ||
460 | ioctl_w_state[sm_id].valid_warps[1] = | ||
461 | w_state[sm_id].valid_warps[1]; | ||
462 | ioctl_w_state[sm_id].trapped_warps[0] = | ||
463 | w_state[sm_id].trapped_warps[0]; | ||
464 | ioctl_w_state[sm_id].trapped_warps[1] = | ||
465 | w_state[sm_id].trapped_warps[1]; | ||
466 | ioctl_w_state[sm_id].paused_warps[0] = | ||
467 | w_state[sm_id].paused_warps[0]; | ||
468 | ioctl_w_state[sm_id].paused_warps[1] = | ||
469 | w_state[sm_id].paused_warps[1]; | ||
470 | } | ||
448 | /* Copy to user space - pointed by "args->pwarpstate" */ | 471 | /* Copy to user space - pointed by "args->pwarpstate" */ |
449 | if (copy_to_user((void __user *)(uintptr_t)args->pwarpstate, w_state, size)) { | 472 | if (copy_to_user((void __user *)(uintptr_t)args->pwarpstate, |
473 | w_state, ioctl_size)) { | ||
450 | gk20a_dbg_fn("copy_to_user failed!"); | 474 | gk20a_dbg_fn("copy_to_user failed!"); |
451 | err = -EFAULT; | 475 | err = -EFAULT; |
452 | } | 476 | } |
@@ -457,6 +481,7 @@ static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g, | |||
457 | 481 | ||
458 | out_free: | 482 | out_free: |
459 | nvgpu_kfree(g, w_state); | 483 | nvgpu_kfree(g, w_state); |
484 | nvgpu_kfree(g, ioctl_w_state); | ||
460 | 485 | ||
461 | return err; | 486 | return err; |
462 | } | 487 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 8efb009a..ead1f69e 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -41,6 +41,7 @@ struct nvgpu_clk_pll_debug_data; | |||
41 | struct nvgpu_nvhost_dev; | 41 | struct nvgpu_nvhost_dev; |
42 | struct nvgpu_cpu_time_correlation_sample; | 42 | struct nvgpu_cpu_time_correlation_sample; |
43 | struct nvgpu_mem_sgt; | 43 | struct nvgpu_mem_sgt; |
44 | struct nvgpu_warpstate; | ||
44 | 45 | ||
45 | #include <nvgpu/lock.h> | 46 | #include <nvgpu/lock.h> |
46 | #include <nvgpu/thread.h> | 47 | #include <nvgpu/thread.h> |
@@ -308,7 +309,7 @@ struct gpu_ops { | |||
308 | int (*set_sm_debug_mode)(struct gk20a *g, struct channel_gk20a *ch, | 309 | int (*set_sm_debug_mode)(struct gk20a *g, struct channel_gk20a *ch, |
309 | u64 sms, bool enable); | 310 | u64 sms, bool enable); |
310 | void (*bpt_reg_info)(struct gk20a *g, | 311 | void (*bpt_reg_info)(struct gk20a *g, |
311 | struct warpstate *w_state); | 312 | struct nvgpu_warpstate *w_state); |
312 | void (*get_access_map)(struct gk20a *g, | 313 | void (*get_access_map)(struct gk20a *g, |
313 | u32 **whitelist, int *num_entries); | 314 | u32 **whitelist, int *num_entries); |
314 | int (*handle_fecs_error)(struct gk20a *g, | 315 | int (*handle_fecs_error)(struct gk20a *g, |
@@ -407,7 +408,7 @@ struct gpu_ops { | |||
407 | void (*load_tpc_mask)(struct gk20a *g); | 408 | void (*load_tpc_mask)(struct gk20a *g); |
408 | int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch); | 409 | int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch); |
409 | int (*trigger_suspend)(struct gk20a *g); | 410 | int (*trigger_suspend)(struct gk20a *g); |
410 | int (*wait_for_pause)(struct gk20a *g, struct warpstate *w_state); | 411 | int (*wait_for_pause)(struct gk20a *g, struct nvgpu_warpstate *w_state); |
411 | int (*resume_from_pause)(struct gk20a *g); | 412 | int (*resume_from_pause)(struct gk20a *g); |
412 | int (*clear_sm_errors)(struct gk20a *g); | 413 | int (*clear_sm_errors)(struct gk20a *g); |
413 | u32 (*tpc_enabled_exceptions)(struct gk20a *g); | 414 | u32 (*tpc_enabled_exceptions)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 6f829282..1ade6b6a 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -8488,7 +8488,7 @@ int gr_gk20a_trigger_suspend(struct gk20a *g) | |||
8488 | return err; | 8488 | return err; |
8489 | } | 8489 | } |
8490 | 8490 | ||
8491 | int gr_gk20a_wait_for_pause(struct gk20a *g, struct warpstate *w_state) | 8491 | int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state) |
8492 | { | 8492 | { |
8493 | int err = 0; | 8493 | int err = 0; |
8494 | struct gr_gk20a *gr = &g->gr; | 8494 | struct gr_gk20a *gr = &g->gr; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index a78f0498..5fab43ca 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -51,6 +51,7 @@ | |||
51 | #define GK20A_TIMEOUT_FPGA 100000 /* 100 sec */ | 51 | #define GK20A_TIMEOUT_FPGA 100000 /* 100 sec */ |
52 | 52 | ||
53 | struct channel_gk20a; | 53 | struct channel_gk20a; |
54 | struct nvgpu_warpstate; | ||
54 | 55 | ||
55 | enum /* global_ctx_buffer */ { | 56 | enum /* global_ctx_buffer */ { |
56 | CIRCULAR = 0, | 57 | CIRCULAR = 0, |
@@ -488,6 +489,12 @@ struct fecs_method_op_gk20a { | |||
488 | 489 | ||
489 | }; | 490 | }; |
490 | 491 | ||
492 | struct nvgpu_warpstate { | ||
493 | u64 valid_warps[2]; | ||
494 | u64 trapped_warps[2]; | ||
495 | u64 paused_warps[2]; | ||
496 | }; | ||
497 | |||
491 | struct gpu_ops; | 498 | struct gpu_ops; |
492 | int gr_gk20a_load_golden_ctx_image(struct gk20a *g, | 499 | int gr_gk20a_load_golden_ctx_image(struct gk20a *g, |
493 | struct channel_gk20a *c); | 500 | struct channel_gk20a *c); |
@@ -718,7 +725,7 @@ void gk20a_gr_enable_gpc_exceptions(struct gk20a *g); | |||
718 | void gk20a_gr_enable_exceptions(struct gk20a *g); | 725 | void gk20a_gr_enable_exceptions(struct gk20a *g); |
719 | int gr_gk20a_inval_icache(struct gk20a *g, struct channel_gk20a *ch); | 726 | int gr_gk20a_inval_icache(struct gk20a *g, struct channel_gk20a *ch); |
720 | int gr_gk20a_trigger_suspend(struct gk20a *g); | 727 | int gr_gk20a_trigger_suspend(struct gk20a *g); |
721 | int gr_gk20a_wait_for_pause(struct gk20a *g, struct warpstate *w_state); | 728 | int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state); |
722 | int gr_gk20a_resume_from_pause(struct gk20a *g); | 729 | int gr_gk20a_resume_from_pause(struct gk20a *g); |
723 | int gr_gk20a_clear_sm_errors(struct gk20a *g); | 730 | int gr_gk20a_clear_sm_errors(struct gk20a *g); |
724 | u32 gr_gk20a_tpc_enabled_exceptions(struct gk20a *g); | 731 | u32 gr_gk20a_tpc_enabled_exceptions(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 05c6dc5f..92096cfa 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1140,7 +1140,7 @@ void gr_gm20b_enable_cde_in_fecs(struct gk20a *g, struct nvgpu_mem *mem) | |||
1140 | nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_ctl_o(), cde_v); | 1140 | nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_ctl_o(), cde_v); |
1141 | } | 1141 | } |
1142 | 1142 | ||
1143 | void gr_gm20b_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) | 1143 | void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state) |
1144 | { | 1144 | { |
1145 | /* Check if we have at least one valid warp */ | 1145 | /* Check if we have at least one valid warp */ |
1146 | /* get paused state on maxwell */ | 1146 | /* get paused state on maxwell */ |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index c7a84b0a..67f1ea29 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |||
@@ -26,6 +26,7 @@ | |||
26 | #define _NVHOST_GM20B_GR_MMU_H | 26 | #define _NVHOST_GM20B_GR_MMU_H |
27 | 27 | ||
28 | struct gk20a; | 28 | struct gk20a; |
29 | struct nvgpu_warpstate; | ||
29 | 30 | ||
30 | enum { | 31 | enum { |
31 | MAXWELL_B = 0xB197, | 32 | MAXWELL_B = 0xB197, |
@@ -112,7 +113,7 @@ u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g); | |||
112 | u32 gr_gm20b_get_max_fbps_count(struct gk20a *g); | 113 | u32 gr_gm20b_get_max_fbps_count(struct gk20a *g); |
113 | void gr_gm20b_init_cyclestats(struct gk20a *g); | 114 | void gr_gm20b_init_cyclestats(struct gk20a *g); |
114 | void gr_gm20b_enable_cde_in_fecs(struct gk20a *g, struct nvgpu_mem *mem); | 115 | void gr_gm20b_enable_cde_in_fecs(struct gk20a *g, struct nvgpu_mem *mem); |
115 | void gr_gm20b_bpt_reg_info(struct gk20a *g, struct warpstate *w_state); | 116 | void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state); |
116 | void gr_gm20b_get_access_map(struct gk20a *g, | 117 | void gr_gm20b_get_access_map(struct gk20a *g, |
117 | u32 **whitelist, int *num_entries); | 118 | u32 **whitelist, int *num_entries); |
118 | int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc); | 119 | int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc); |