diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 11 |
4 files changed, 19 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 8b144864..bd4e2ff8 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -256,7 +256,7 @@ void gk20a_disable_channel(struct channel_gk20a *ch) | |||
256 | channel_gk20a_update_runlist(ch, false); | 256 | channel_gk20a_update_runlist(ch, false); |
257 | } | 257 | } |
258 | 258 | ||
259 | static void gk20a_wait_until_counter_is_N( | 259 | void gk20a_wait_until_counter_is_N( |
260 | struct channel_gk20a *ch, nvgpu_atomic_t *counter, int wait_value, | 260 | struct channel_gk20a *ch, nvgpu_atomic_t *counter, int wait_value, |
261 | struct nvgpu_cond *c, const char *caller, const char *counter_name) | 261 | struct nvgpu_cond *c, const char *caller, const char *counter_name) |
262 | { | 262 | { |
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index 473248ec..f2cb2ab8 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h | |||
@@ -340,6 +340,9 @@ int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, | |||
340 | unsigned int timeslice_period, | 340 | unsigned int timeslice_period, |
341 | unsigned int *__timeslice_timeout, unsigned int *__timeslice_scale); | 341 | unsigned int *__timeslice_timeout, unsigned int *__timeslice_scale); |
342 | 342 | ||
343 | void gk20a_wait_until_counter_is_N( | ||
344 | struct channel_gk20a *ch, nvgpu_atomic_t *counter, int wait_value, | ||
345 | struct nvgpu_cond *c, const char *caller, const char *counter_name); | ||
343 | int channel_gk20a_alloc_job(struct channel_gk20a *c, | 346 | int channel_gk20a_alloc_job(struct channel_gk20a *c, |
344 | struct channel_gk20a_job **job_out); | 347 | struct channel_gk20a_job **job_out); |
345 | void channel_gk20a_free_job(struct channel_gk20a *c, | 348 | void channel_gk20a_free_job(struct channel_gk20a *c, |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 5bd4dc57..6a7afad7 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -862,7 +862,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) | |||
862 | return 0; | 862 | return 0; |
863 | } | 863 | } |
864 | 864 | ||
865 | static int gk20a_init_fifo_setup_sw(struct gk20a *g) | 865 | int gk20a_init_fifo_setup_sw(struct gk20a *g) |
866 | { | 866 | { |
867 | struct fifo_gk20a *f = &g->fifo; | 867 | struct fifo_gk20a *f = &g->fifo; |
868 | unsigned int chid, i; | 868 | unsigned int chid, i; |
@@ -2093,7 +2093,7 @@ u32 gk20a_fifo_get_failing_engine_data(struct gk20a *g, | |||
2093 | return active_engine_id; | 2093 | return active_engine_id; |
2094 | } | 2094 | } |
2095 | 2095 | ||
2096 | static bool gk20a_fifo_check_ch_ctxsw_timeout(struct channel_gk20a *ch, | 2096 | bool gk20a_fifo_check_ch_ctxsw_timeout(struct channel_gk20a *ch, |
2097 | bool *verbose, u32 *ms) | 2097 | bool *verbose, u32 *ms) |
2098 | { | 2098 | { |
2099 | bool recover = false; | 2099 | bool recover = false; |
@@ -2971,7 +2971,7 @@ static void gk20a_fifo_runlist_reset_engines(struct gk20a *g, u32 runlist_id) | |||
2971 | gk20a_fifo_recover(g, engines, ~(u32)0, false, false, true); | 2971 | gk20a_fifo_recover(g, engines, ~(u32)0, false, false, true); |
2972 | } | 2972 | } |
2973 | 2973 | ||
2974 | static int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id) | 2974 | int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id) |
2975 | { | 2975 | { |
2976 | struct nvgpu_timeout timeout; | 2976 | struct nvgpu_timeout timeout; |
2977 | unsigned long delay = GR_IDLE_CHECK_DEFAULT; | 2977 | unsigned long delay = GR_IDLE_CHECK_DEFAULT; |
@@ -3032,7 +3032,7 @@ void gk20a_get_ch_runlist_entry(struct channel_gk20a *ch, u32 *runlist) | |||
3032 | } | 3032 | } |
3033 | 3033 | ||
3034 | /* recursively construct a runlist with interleaved bare channels and TSGs */ | 3034 | /* recursively construct a runlist with interleaved bare channels and TSGs */ |
3035 | static u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f, | 3035 | u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f, |
3036 | struct fifo_runlist_info_gk20a *runlist, | 3036 | struct fifo_runlist_info_gk20a *runlist, |
3037 | u32 cur_level, | 3037 | u32 cur_level, |
3038 | u32 *runlist_entry, | 3038 | u32 *runlist_entry, |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 8a3bd4b9..e2febbf8 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -378,6 +378,15 @@ int gk20a_fifo_setup_userd(struct channel_gk20a *c); | |||
378 | u32 gk20a_fifo_pbdma_acquire_val(u64 timeout); | 378 | u32 gk20a_fifo_pbdma_acquire_val(u64 timeout); |
379 | 379 | ||
380 | 380 | ||
381 | u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f, | ||
382 | struct fifo_runlist_info_gk20a *runlist, | ||
383 | u32 cur_level, | ||
384 | u32 *runlist_entry, | ||
385 | bool interleave_enabled, | ||
386 | bool prev_empty, | ||
387 | u32 *entries_left); | ||
388 | int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id); | ||
389 | int gk20a_init_fifo_setup_sw(struct gk20a *g); | ||
381 | void gk20a_fifo_handle_runlist_event(struct gk20a *g); | 390 | void gk20a_fifo_handle_runlist_event(struct gk20a *g); |
382 | bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id, | 391 | bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id, |
383 | u32 engine_subid, bool fake_fault); | 392 | u32 engine_subid, bool fake_fault); |
@@ -386,6 +395,8 @@ void gk20a_fifo_teardown_ch_tsg(struct gk20a *g, u32 __engine_ids, | |||
386 | u32 hw_id, unsigned int id_type, unsigned int rc_type, | 395 | u32 hw_id, unsigned int id_type, unsigned int rc_type, |
387 | struct mmu_fault_info *mmfault); | 396 | struct mmu_fault_info *mmfault); |
388 | 397 | ||
398 | bool gk20a_fifo_check_ch_ctxsw_timeout(struct channel_gk20a *ch, | ||
399 | bool *verbose, u32 *ms); | ||
389 | bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg, | 400 | bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg, |
390 | bool *verbose, u32 *ms); | 401 | bool *verbose, u32 *ms); |
391 | bool gk20a_fifo_handle_sched_error(struct gk20a *g); | 402 | bool gk20a_fifo_handle_sched_error(struct gk20a *g); |