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-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h82
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h64
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h24
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h198
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h884
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h314
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h64
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h46
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h716
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h2428
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h372
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h96
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h296
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h76
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h54
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h10
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h16
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h64
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h446
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h354
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h176
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h28
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h88
24 files changed, 3449 insertions, 3449 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h
index 9fe7e591..d1d9b34a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_bus_gv11b.h
@@ -58,166 +58,166 @@
58 58
59static inline u32 bus_bar0_window_r(void) 59static inline u32 bus_bar0_window_r(void)
60{ 60{
61 return 0x00001700; 61 return 0x00001700U;
62} 62}
63static inline u32 bus_bar0_window_base_f(u32 v) 63static inline u32 bus_bar0_window_base_f(u32 v)
64{ 64{
65 return (v & 0xffffff) << 0; 65 return (v & 0xffffffU) << 0U;
66} 66}
67static inline u32 bus_bar0_window_target_vid_mem_f(void) 67static inline u32 bus_bar0_window_target_vid_mem_f(void)
68{ 68{
69 return 0x0; 69 return 0x0U;
70} 70}
71static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) 71static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
72{ 72{
73 return 0x2000000; 73 return 0x2000000U;
74} 74}
75static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) 75static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
76{ 76{
77 return 0x3000000; 77 return 0x3000000U;
78} 78}
79static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) 79static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
80{ 80{
81 return 0x00000010; 81 return 0x00000010U;
82} 82}
83static inline u32 bus_bar1_block_r(void) 83static inline u32 bus_bar1_block_r(void)
84{ 84{
85 return 0x00001704; 85 return 0x00001704U;
86} 86}
87static inline u32 bus_bar1_block_ptr_f(u32 v) 87static inline u32 bus_bar1_block_ptr_f(u32 v)
88{ 88{
89 return (v & 0xfffffff) << 0; 89 return (v & 0xfffffffU) << 0U;
90} 90}
91static inline u32 bus_bar1_block_target_vid_mem_f(void) 91static inline u32 bus_bar1_block_target_vid_mem_f(void)
92{ 92{
93 return 0x0; 93 return 0x0U;
94} 94}
95static inline u32 bus_bar1_block_target_sys_mem_coh_f(void) 95static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
96{ 96{
97 return 0x20000000; 97 return 0x20000000U;
98} 98}
99static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void) 99static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
100{ 100{
101 return 0x30000000; 101 return 0x30000000U;
102} 102}
103static inline u32 bus_bar1_block_mode_virtual_f(void) 103static inline u32 bus_bar1_block_mode_virtual_f(void)
104{ 104{
105 return 0x80000000; 105 return 0x80000000U;
106} 106}
107static inline u32 bus_bar2_block_r(void) 107static inline u32 bus_bar2_block_r(void)
108{ 108{
109 return 0x00001714; 109 return 0x00001714U;
110} 110}
111static inline u32 bus_bar2_block_ptr_f(u32 v) 111static inline u32 bus_bar2_block_ptr_f(u32 v)
112{ 112{
113 return (v & 0xfffffff) << 0; 113 return (v & 0xfffffffU) << 0U;
114} 114}
115static inline u32 bus_bar2_block_target_vid_mem_f(void) 115static inline u32 bus_bar2_block_target_vid_mem_f(void)
116{ 116{
117 return 0x0; 117 return 0x0U;
118} 118}
119static inline u32 bus_bar2_block_target_sys_mem_coh_f(void) 119static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
120{ 120{
121 return 0x20000000; 121 return 0x20000000U;
122} 122}
123static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void) 123static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
124{ 124{
125 return 0x30000000; 125 return 0x30000000U;
126} 126}
127static inline u32 bus_bar2_block_mode_virtual_f(void) 127static inline u32 bus_bar2_block_mode_virtual_f(void)
128{ 128{
129 return 0x80000000; 129 return 0x80000000U;
130} 130}
131static inline u32 bus_bar1_block_ptr_shift_v(void) 131static inline u32 bus_bar1_block_ptr_shift_v(void)
132{ 132{
133 return 0x0000000c; 133 return 0x0000000cU;
134} 134}
135static inline u32 bus_bar2_block_ptr_shift_v(void) 135static inline u32 bus_bar2_block_ptr_shift_v(void)
136{ 136{
137 return 0x0000000c; 137 return 0x0000000cU;
138} 138}
139static inline u32 bus_bind_status_r(void) 139static inline u32 bus_bind_status_r(void)
140{ 140{
141 return 0x00001710; 141 return 0x00001710U;
142} 142}
143static inline u32 bus_bind_status_bar1_pending_v(u32 r) 143static inline u32 bus_bind_status_bar1_pending_v(u32 r)
144{ 144{
145 return (r >> 0) & 0x1; 145 return (r >> 0U) & 0x1U;
146} 146}
147static inline u32 bus_bind_status_bar1_pending_empty_f(void) 147static inline u32 bus_bind_status_bar1_pending_empty_f(void)
148{ 148{
149 return 0x0; 149 return 0x0U;
150} 150}
151static inline u32 bus_bind_status_bar1_pending_busy_f(void) 151static inline u32 bus_bind_status_bar1_pending_busy_f(void)
152{ 152{
153 return 0x1; 153 return 0x1U;
154} 154}
155static inline u32 bus_bind_status_bar1_outstanding_v(u32 r) 155static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
156{ 156{
157 return (r >> 1) & 0x1; 157 return (r >> 1U) & 0x1U;
158} 158}
159static inline u32 bus_bind_status_bar1_outstanding_false_f(void) 159static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
160{ 160{
161 return 0x0; 161 return 0x0U;
162} 162}
163static inline u32 bus_bind_status_bar1_outstanding_true_f(void) 163static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
164{ 164{
165 return 0x2; 165 return 0x2U;
166} 166}
167static inline u32 bus_bind_status_bar2_pending_v(u32 r) 167static inline u32 bus_bind_status_bar2_pending_v(u32 r)
168{ 168{
169 return (r >> 2) & 0x1; 169 return (r >> 2U) & 0x1U;
170} 170}
171static inline u32 bus_bind_status_bar2_pending_empty_f(void) 171static inline u32 bus_bind_status_bar2_pending_empty_f(void)
172{ 172{
173 return 0x0; 173 return 0x0U;
174} 174}
175static inline u32 bus_bind_status_bar2_pending_busy_f(void) 175static inline u32 bus_bind_status_bar2_pending_busy_f(void)
176{ 176{
177 return 0x4; 177 return 0x4U;
178} 178}
179static inline u32 bus_bind_status_bar2_outstanding_v(u32 r) 179static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
180{ 180{
181 return (r >> 3) & 0x1; 181 return (r >> 3U) & 0x1U;
182} 182}
183static inline u32 bus_bind_status_bar2_outstanding_false_f(void) 183static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
184{ 184{
185 return 0x0; 185 return 0x0U;
186} 186}
187static inline u32 bus_bind_status_bar2_outstanding_true_f(void) 187static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
188{ 188{
189 return 0x8; 189 return 0x8U;
190} 190}
191static inline u32 bus_intr_0_r(void) 191static inline u32 bus_intr_0_r(void)
192{ 192{
193 return 0x00001100; 193 return 0x00001100U;
194} 194}
195static inline u32 bus_intr_0_pri_squash_m(void) 195static inline u32 bus_intr_0_pri_squash_m(void)
196{ 196{
197 return 0x1 << 1; 197 return 0x1U << 1U;
198} 198}
199static inline u32 bus_intr_0_pri_fecserr_m(void) 199static inline u32 bus_intr_0_pri_fecserr_m(void)
200{ 200{
201 return 0x1 << 2; 201 return 0x1U << 2U;
202} 202}
203static inline u32 bus_intr_0_pri_timeout_m(void) 203static inline u32 bus_intr_0_pri_timeout_m(void)
204{ 204{
205 return 0x1 << 3; 205 return 0x1U << 3U;
206} 206}
207static inline u32 bus_intr_en_0_r(void) 207static inline u32 bus_intr_en_0_r(void)
208{ 208{
209 return 0x00001140; 209 return 0x00001140U;
210} 210}
211static inline u32 bus_intr_en_0_pri_squash_m(void) 211static inline u32 bus_intr_en_0_pri_squash_m(void)
212{ 212{
213 return 0x1 << 1; 213 return 0x1U << 1U;
214} 214}
215static inline u32 bus_intr_en_0_pri_fecserr_m(void) 215static inline u32 bus_intr_en_0_pri_fecserr_m(void)
216{ 216{
217 return 0x1 << 2; 217 return 0x1U << 2U;
218} 218}
219static inline u32 bus_intr_en_0_pri_timeout_m(void) 219static inline u32 bus_intr_en_0_pri_timeout_m(void)
220{ 220{
221 return 0x1 << 3; 221 return 0x1U << 3U;
222} 222}
223#endif 223#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h
index 3243e3e2..e21a4738 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h
@@ -58,130 +58,130 @@
58 58
59static inline u32 ccsr_channel_inst_r(u32 i) 59static inline u32 ccsr_channel_inst_r(u32 i)
60{ 60{
61 return 0x00800000 + i*8; 61 return 0x00800000U + i*8U;
62} 62}
63static inline u32 ccsr_channel_inst__size_1_v(void) 63static inline u32 ccsr_channel_inst__size_1_v(void)
64{ 64{
65 return 0x00000200; 65 return 0x00000200U;
66} 66}
67static inline u32 ccsr_channel_inst_ptr_f(u32 v) 67static inline u32 ccsr_channel_inst_ptr_f(u32 v)
68{ 68{
69 return (v & 0xfffffff) << 0; 69 return (v & 0xfffffffU) << 0U;
70} 70}
71static inline u32 ccsr_channel_inst_target_vid_mem_f(void) 71static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
72{ 72{
73 return 0x0; 73 return 0x0U;
74} 74}
75static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) 75static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
76{ 76{
77 return 0x20000000; 77 return 0x20000000U;
78} 78}
79static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) 79static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
80{ 80{
81 return 0x30000000; 81 return 0x30000000U;
82} 82}
83static inline u32 ccsr_channel_inst_bind_false_f(void) 83static inline u32 ccsr_channel_inst_bind_false_f(void)
84{ 84{
85 return 0x0; 85 return 0x0U;
86} 86}
87static inline u32 ccsr_channel_inst_bind_true_f(void) 87static inline u32 ccsr_channel_inst_bind_true_f(void)
88{ 88{
89 return 0x80000000; 89 return 0x80000000U;
90} 90}
91static inline u32 ccsr_channel_r(u32 i) 91static inline u32 ccsr_channel_r(u32 i)
92{ 92{
93 return 0x00800004 + i*8; 93 return 0x00800004U + i*8U;
94} 94}
95static inline u32 ccsr_channel__size_1_v(void) 95static inline u32 ccsr_channel__size_1_v(void)
96{ 96{
97 return 0x00000200; 97 return 0x00000200U;
98} 98}
99static inline u32 ccsr_channel_enable_v(u32 r) 99static inline u32 ccsr_channel_enable_v(u32 r)
100{ 100{
101 return (r >> 0) & 0x1; 101 return (r >> 0U) & 0x1U;
102} 102}
103static inline u32 ccsr_channel_enable_set_f(u32 v) 103static inline u32 ccsr_channel_enable_set_f(u32 v)
104{ 104{
105 return (v & 0x1) << 10; 105 return (v & 0x1U) << 10U;
106} 106}
107static inline u32 ccsr_channel_enable_set_true_f(void) 107static inline u32 ccsr_channel_enable_set_true_f(void)
108{ 108{
109 return 0x400; 109 return 0x400U;
110} 110}
111static inline u32 ccsr_channel_enable_clr_true_f(void) 111static inline u32 ccsr_channel_enable_clr_true_f(void)
112{ 112{
113 return 0x800; 113 return 0x800U;
114} 114}
115static inline u32 ccsr_channel_status_v(u32 r) 115static inline u32 ccsr_channel_status_v(u32 r)
116{ 116{
117 return (r >> 24) & 0xf; 117 return (r >> 24U) & 0xfU;
118} 118}
119static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) 119static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
120{ 120{
121 return 0x00000002; 121 return 0x00000002U;
122} 122}
123static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) 123static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
124{ 124{
125 return 0x00000004; 125 return 0x00000004U;
126} 126}
127static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) 127static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
128{ 128{
129 return 0x0000000a; 129 return 0x0000000aU;
130} 130}
131static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) 131static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
132{ 132{
133 return 0x0000000b; 133 return 0x0000000bU;
134} 134}
135static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) 135static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
136{ 136{
137 return 0x0000000c; 137 return 0x0000000cU;
138} 138}
139static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) 139static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
140{ 140{
141 return 0x0000000d; 141 return 0x0000000dU;
142} 142}
143static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) 143static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
144{ 144{
145 return 0x0000000e; 145 return 0x0000000eU;
146} 146}
147static inline u32 ccsr_channel_next_v(u32 r) 147static inline u32 ccsr_channel_next_v(u32 r)
148{ 148{
149 return (r >> 1) & 0x1; 149 return (r >> 1U) & 0x1U;
150} 150}
151static inline u32 ccsr_channel_next_true_v(void) 151static inline u32 ccsr_channel_next_true_v(void)
152{ 152{
153 return 0x00000001; 153 return 0x00000001U;
154} 154}
155static inline u32 ccsr_channel_force_ctx_reload_true_f(void) 155static inline u32 ccsr_channel_force_ctx_reload_true_f(void)
156{ 156{
157 return 0x100; 157 return 0x100U;
158} 158}
159static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) 159static inline u32 ccsr_channel_pbdma_faulted_f(u32 v)
160{ 160{
161 return (v & 0x1) << 22; 161 return (v & 0x1U) << 22U;
162} 162}
163static inline u32 ccsr_channel_pbdma_faulted_reset_f(void) 163static inline u32 ccsr_channel_pbdma_faulted_reset_f(void)
164{ 164{
165 return 0x400000; 165 return 0x400000U;
166} 166}
167static inline u32 ccsr_channel_eng_faulted_f(u32 v) 167static inline u32 ccsr_channel_eng_faulted_f(u32 v)
168{ 168{
169 return (v & 0x1) << 23; 169 return (v & 0x1U) << 23U;
170} 170}
171static inline u32 ccsr_channel_eng_faulted_v(u32 r) 171static inline u32 ccsr_channel_eng_faulted_v(u32 r)
172{ 172{
173 return (r >> 23) & 0x1; 173 return (r >> 23U) & 0x1U;
174} 174}
175static inline u32 ccsr_channel_eng_faulted_reset_f(void) 175static inline u32 ccsr_channel_eng_faulted_reset_f(void)
176{ 176{
177 return 0x800000; 177 return 0x800000U;
178} 178}
179static inline u32 ccsr_channel_eng_faulted_true_v(void) 179static inline u32 ccsr_channel_eng_faulted_true_v(void)
180{ 180{
181 return 0x00000001; 181 return 0x00000001U;
182} 182}
183static inline u32 ccsr_channel_busy_v(u32 r) 183static inline u32 ccsr_channel_busy_v(u32 r)
184{ 184{
185 return (r >> 28) & 0x1; 185 return (r >> 28U) & 0x1U;
186} 186}
187#endif 187#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h
index 8a0a9206..efc14d00 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ce_gv11b.h
@@ -58,50 +58,50 @@
58 58
59static inline u32 ce_intr_status_r(u32 i) 59static inline u32 ce_intr_status_r(u32 i)
60{ 60{
61 return 0x00104410 + i*128; 61 return 0x00104410U + i*128U;
62} 62}
63static inline u32 ce_intr_status_blockpipe_pending_f(void) 63static inline u32 ce_intr_status_blockpipe_pending_f(void)
64{ 64{
65 return 0x1; 65 return 0x1U;
66} 66}
67static inline u32 ce_intr_status_blockpipe_reset_f(void) 67static inline u32 ce_intr_status_blockpipe_reset_f(void)
68{ 68{
69 return 0x1; 69 return 0x1U;
70} 70}
71static inline u32 ce_intr_status_nonblockpipe_pending_f(void) 71static inline u32 ce_intr_status_nonblockpipe_pending_f(void)
72{ 72{
73 return 0x2; 73 return 0x2U;
74} 74}
75static inline u32 ce_intr_status_nonblockpipe_reset_f(void) 75static inline u32 ce_intr_status_nonblockpipe_reset_f(void)
76{ 76{
77 return 0x2; 77 return 0x2U;
78} 78}
79static inline u32 ce_intr_status_launcherr_pending_f(void) 79static inline u32 ce_intr_status_launcherr_pending_f(void)
80{ 80{
81 return 0x4; 81 return 0x4U;
82} 82}
83static inline u32 ce_intr_status_launcherr_reset_f(void) 83static inline u32 ce_intr_status_launcherr_reset_f(void)
84{ 84{
85 return 0x4; 85 return 0x4U;
86} 86}
87static inline u32 ce_intr_status_invalid_config_pending_f(void) 87static inline u32 ce_intr_status_invalid_config_pending_f(void)
88{ 88{
89 return 0x8; 89 return 0x8U;
90} 90}
91static inline u32 ce_intr_status_invalid_config_reset_f(void) 91static inline u32 ce_intr_status_invalid_config_reset_f(void)
92{ 92{
93 return 0x8; 93 return 0x8U;
94} 94}
95static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void) 95static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void)
96{ 96{
97 return 0x10; 97 return 0x10U;
98} 98}
99static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void) 99static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void)
100{ 100{
101 return 0x10; 101 return 0x10U;
102} 102}
103static inline u32 ce_pce_map_r(void) 103static inline u32 ce_pce_map_r(void)
104{ 104{
105 return 0x00104028; 105 return 0x00104028U;
106} 106}
107#endif 107#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h
index 27ac297c..623a8c15 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h
@@ -58,398 +58,398 @@
58 58
59static inline u32 ctxsw_prog_fecs_header_v(void) 59static inline u32 ctxsw_prog_fecs_header_v(void)
60{ 60{
61 return 0x00000100; 61 return 0x00000100U;
62} 62}
63static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) 63static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
64{ 64{
65 return 0x00000008; 65 return 0x00000008U;
66} 66}
67static inline u32 ctxsw_prog_main_image_ctl_o(void) 67static inline u32 ctxsw_prog_main_image_ctl_o(void)
68{ 68{
69 return 0x0000000c; 69 return 0x0000000cU;
70} 70}
71static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v) 71static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v)
72{ 72{
73 return (v & 0x3f) << 0; 73 return (v & 0x3fU) << 0U;
74} 74}
75static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void) 75static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void)
76{ 76{
77 return 0x00000000; 77 return 0x00000000U;
78} 78}
79static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void) 79static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void)
80{ 80{
81 return 0x00000008; 81 return 0x00000008U;
82} 82}
83static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void) 83static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void)
84{ 84{
85 return 0x00000010; 85 return 0x00000010U;
86} 86}
87static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void) 87static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void)
88{ 88{
89 return 0x00000011; 89 return 0x00000011U;
90} 90}
91static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void) 91static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void)
92{ 92{
93 return 0x00000012; 93 return 0x00000012U;
94} 94}
95static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void) 95static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void)
96{ 96{
97 return 0x00000020; 97 return 0x00000020U;
98} 98}
99static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void) 99static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void)
100{ 100{
101 return 0x00000021; 101 return 0x00000021U;
102} 102}
103static inline u32 ctxsw_prog_main_image_patch_count_o(void) 103static inline u32 ctxsw_prog_main_image_patch_count_o(void)
104{ 104{
105 return 0x00000010; 105 return 0x00000010U;
106} 106}
107static inline u32 ctxsw_prog_main_image_context_id_o(void) 107static inline u32 ctxsw_prog_main_image_context_id_o(void)
108{ 108{
109 return 0x000000f0; 109 return 0x000000f0U;
110} 110}
111static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) 111static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
112{ 112{
113 return 0x00000014; 113 return 0x00000014U;
114} 114}
115static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) 115static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
116{ 116{
117 return 0x00000018; 117 return 0x00000018U;
118} 118}
119static inline u32 ctxsw_prog_main_image_zcull_o(void) 119static inline u32 ctxsw_prog_main_image_zcull_o(void)
120{ 120{
121 return 0x0000001c; 121 return 0x0000001cU;
122} 122}
123static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) 123static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
124{ 124{
125 return 0x00000001; 125 return 0x00000001U;
126} 126}
127static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) 127static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
128{ 128{
129 return 0x00000002; 129 return 0x00000002U;
130} 130}
131static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) 131static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
132{ 132{
133 return 0x00000020; 133 return 0x00000020U;
134} 134}
135static inline u32 ctxsw_prog_main_image_pm_o(void) 135static inline u32 ctxsw_prog_main_image_pm_o(void)
136{ 136{
137 return 0x00000028; 137 return 0x00000028U;
138} 138}
139static inline u32 ctxsw_prog_main_image_pm_mode_m(void) 139static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
140{ 140{
141 return 0x7 << 0; 141 return 0x7U << 0U;
142} 142}
143static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) 143static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
144{ 144{
145 return 0x0; 145 return 0x0U;
146} 146}
147static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) 147static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
148{ 148{
149 return 0x7 << 3; 149 return 0x7U << 3U;
150} 150}
151static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) 151static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
152{ 152{
153 return 0x8; 153 return 0x8U;
154} 154}
155static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) 155static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
156{ 156{
157 return 0x0; 157 return 0x0U;
158} 158}
159static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) 159static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
160{ 160{
161 return 0x0000002c; 161 return 0x0000002cU;
162} 162}
163static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) 163static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
164{ 164{
165 return 0x000000f4; 165 return 0x000000f4U;
166} 166}
167static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) 167static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void)
168{ 168{
169 return 0x000000d0; 169 return 0x000000d0U;
170} 170}
171static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) 171static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void)
172{ 172{
173 return 0x000000d4; 173 return 0x000000d4U;
174} 174}
175static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) 175static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void)
176{ 176{
177 return 0x000000d8; 177 return 0x000000d8U;
178} 178}
179static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) 179static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void)
180{ 180{
181 return 0x000000dc; 181 return 0x000000dcU;
182} 182}
183static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) 183static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
184{ 184{
185 return 0x000000f8; 185 return 0x000000f8U;
186} 186}
187static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void) 187static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void)
188{ 188{
189 return 0x00000060; 189 return 0x00000060U;
190} 190}
191static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v) 191static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v)
192{ 192{
193 return (v & 0x1ffff) << 0; 193 return (v & 0x1ffffU) << 0U;
194} 194}
195static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void) 195static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void)
196{ 196{
197 return 0x00000094; 197 return 0x00000094U;
198} 198}
199static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void) 199static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void)
200{ 200{
201 return 0x00000064; 201 return 0x00000064U;
202} 202}
203static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v) 203static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v)
204{ 204{
205 return (v & 0x1ffff) << 0; 205 return (v & 0x1ffffU) << 0U;
206} 206}
207static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) 207static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void)
208{ 208{
209 return 0x00000068; 209 return 0x00000068U;
210} 210}
211static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v) 211static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v)
212{ 212{
213 return (v & 0xffffffff) << 0; 213 return (v & 0xffffffffU) << 0U;
214} 214}
215static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void) 215static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void)
216{ 216{
217 return 0x00000070; 217 return 0x00000070U;
218} 218}
219static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v) 219static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v)
220{ 220{
221 return (v & 0x1ffff) << 0; 221 return (v & 0x1ffffU) << 0U;
222} 222}
223static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void) 223static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void)
224{ 224{
225 return 0x00000074; 225 return 0x00000074U;
226} 226}
227static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v) 227static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v)
228{ 228{
229 return (v & 0xffffffff) << 0; 229 return (v & 0xffffffffU) << 0U;
230} 230}
231static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void) 231static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void)
232{ 232{
233 return 0x00000078; 233 return 0x00000078U;
234} 234}
235static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v) 235static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v)
236{ 236{
237 return (v & 0x1ffff) << 0; 237 return (v & 0x1ffffU) << 0U;
238} 238}
239static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void) 239static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void)
240{ 240{
241 return 0x0000007c; 241 return 0x0000007cU;
242} 242}
243static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v) 243static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v)
244{ 244{
245 return (v & 0xffffffff) << 0; 245 return (v & 0xffffffffU) << 0U;
246} 246}
247static inline u32 ctxsw_prog_main_image_magic_value_o(void) 247static inline u32 ctxsw_prog_main_image_magic_value_o(void)
248{ 248{
249 return 0x000000fc; 249 return 0x000000fcU;
250} 250}
251static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) 251static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
252{ 252{
253 return 0x600dc0de; 253 return 0x600dc0deU;
254} 254}
255static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) 255static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
256{ 256{
257 return 0x0000000c; 257 return 0x0000000cU;
258} 258}
259static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) 259static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
260{ 260{
261 return (r >> 0) & 0xffff; 261 return (r >> 0U) & 0xffffU;
262} 262}
263static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void) 263static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void)
264{ 264{
265 return 0x000000b8; 265 return 0x000000b8U;
266} 266}
267static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v) 267static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v)
268{ 268{
269 return (v & 0xffffffff) << 0; 269 return (v & 0xffffffffU) << 0U;
270} 270}
271static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void) 271static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void)
272{ 272{
273 return 0x000000bc; 273 return 0x000000bcU;
274} 274}
275static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v) 275static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v)
276{ 276{
277 return (v & 0x1ffff) << 0; 277 return (v & 0x1ffffU) << 0U;
278} 278}
279static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void) 279static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void)
280{ 280{
281 return 0x000000c0; 281 return 0x000000c0U;
282} 282}
283static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v) 283static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v)
284{ 284{
285 return (v & 0xffffffff) << 0; 285 return (v & 0xffffffffU) << 0U;
286} 286}
287static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void) 287static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void)
288{ 288{
289 return 0x000000c4; 289 return 0x000000c4U;
290} 290}
291static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v) 291static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v)
292{ 292{
293 return (v & 0x1ffff) << 0; 293 return (v & 0x1ffffU) << 0U;
294} 294}
295static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void) 295static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void)
296{ 296{
297 return 0x000000c8; 297 return 0x000000c8U;
298} 298}
299static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v) 299static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v)
300{ 300{
301 return (v & 0xffffffff) << 0; 301 return (v & 0xffffffffU) << 0U;
302} 302}
303static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void) 303static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void)
304{ 304{
305 return 0x000000cc; 305 return 0x000000ccU;
306} 306}
307static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v) 307static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v)
308{ 308{
309 return (v & 0x1ffff) << 0; 309 return (v & 0x1ffffU) << 0U;
310} 310}
311static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void) 311static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void)
312{ 312{
313 return 0x000000e0; 313 return 0x000000e0U;
314} 314}
315static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v) 315static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v)
316{ 316{
317 return (v & 0xffffffff) << 0; 317 return (v & 0xffffffffU) << 0U;
318} 318}
319static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void) 319static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void)
320{ 320{
321 return 0x000000e4; 321 return 0x000000e4U;
322} 322}
323static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v) 323static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v)
324{ 324{
325 return (v & 0x1ffff) << 0; 325 return (v & 0x1ffffU) << 0U;
326} 326}
327static inline u32 ctxsw_prog_local_image_ppc_info_o(void) 327static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
328{ 328{
329 return 0x000000f4; 329 return 0x000000f4U;
330} 330}
331static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) 331static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
332{ 332{
333 return (r >> 0) & 0xffff; 333 return (r >> 0U) & 0xffffU;
334} 334}
335static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) 335static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
336{ 336{
337 return (r >> 16) & 0xffff; 337 return (r >> 16U) & 0xffffU;
338} 338}
339static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) 339static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
340{ 340{
341 return 0x000000f8; 341 return 0x000000f8U;
342} 342}
343static inline u32 ctxsw_prog_local_magic_value_o(void) 343static inline u32 ctxsw_prog_local_magic_value_o(void)
344{ 344{
345 return 0x000000fc; 345 return 0x000000fcU;
346} 346}
347static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) 347static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
348{ 348{
349 return 0xad0becab; 349 return 0xad0becabU;
350} 350}
351static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) 351static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
352{ 352{
353 return 0x000000ec; 353 return 0x000000ecU;
354} 354}
355static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) 355static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
356{ 356{
357 return (r >> 0) & 0xffff; 357 return (r >> 0U) & 0xffffU;
358} 358}
359static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) 359static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
360{ 360{
361 return (r >> 16) & 0xff; 361 return (r >> 16U) & 0xffU;
362} 362}
363static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) 363static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
364{ 364{
365 return 0x00000100; 365 return 0x00000100U;
366} 366}
367static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) 367static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
368{ 368{
369 return 0x00000004; 369 return 0x00000004U;
370} 370}
371static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) 371static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
372{ 372{
373 return 0x00000000; 373 return 0x00000000U;
374} 374}
375static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) 375static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
376{ 376{
377 return 0x00000002; 377 return 0x00000002U;
378} 378}
379static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) 379static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
380{ 380{
381 return 0x000000a0; 381 return 0x000000a0U;
382} 382}
383static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) 383static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
384{ 384{
385 return 2; 385 return 2U;
386} 386}
387static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) 387static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
388{ 388{
389 return (v & 0x3) << 0; 389 return (v & 0x3U) << 0U;
390} 390}
391static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) 391static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
392{ 392{
393 return 0x3 << 0; 393 return 0x3U << 0U;
394} 394}
395static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) 395static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
396{ 396{
397 return (r >> 0) & 0x3; 397 return (r >> 0U) & 0x3U;
398} 398}
399static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) 399static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
400{ 400{
401 return 0x0; 401 return 0x0U;
402} 402}
403static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) 403static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
404{ 404{
405 return 0x2; 405 return 0x2U;
406} 406}
407static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) 407static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
408{ 408{
409 return 0x000000a4; 409 return 0x000000a4U;
410} 410}
411static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) 411static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
412{ 412{
413 return 0x000000a8; 413 return 0x000000a8U;
414} 414}
415static inline u32 ctxsw_prog_main_image_misc_options_o(void) 415static inline u32 ctxsw_prog_main_image_misc_options_o(void)
416{ 416{
417 return 0x0000003c; 417 return 0x0000003cU;
418} 418}
419static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) 419static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
420{ 420{
421 return 0x1 << 3; 421 return 0x1U << 3U;
422} 422}
423static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) 423static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
424{ 424{
425 return 0x0; 425 return 0x0U;
426} 426}
427static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) 427static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void)
428{ 428{
429 return 0x00000080; 429 return 0x00000080U;
430} 430}
431static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) 431static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v)
432{ 432{
433 return (v & 0x3) << 0; 433 return (v & 0x3U) << 0U;
434} 434}
435static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) 435static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void)
436{ 436{
437 return 0x1; 437 return 0x1U;
438} 438}
439static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) 439static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void)
440{ 440{
441 return 0x00000084; 441 return 0x00000084U;
442} 442}
443static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) 443static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v)
444{ 444{
445 return (v & 0x3) << 0; 445 return (v & 0x3U) << 0U;
446} 446}
447static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) 447static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void)
448{ 448{
449 return 0x1; 449 return 0x1U;
450} 450}
451static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) 451static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void)
452{ 452{
453 return 0x2; 453 return 0x2U;
454} 454}
455#endif 455#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
index f902ae6c..ea3c7939 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fb_gv11b.h
@@ -58,1770 +58,1770 @@
58 58
59static inline u32 fb_fbhub_num_active_ltcs_r(void) 59static inline u32 fb_fbhub_num_active_ltcs_r(void)
60{ 60{
61 return 0x00100800; 61 return 0x00100800U;
62} 62}
63static inline u32 fb_mmu_ctrl_r(void) 63static inline u32 fb_mmu_ctrl_r(void)
64{ 64{
65 return 0x00100c80; 65 return 0x00100c80U;
66} 66}
67static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) 67static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v)
68{ 68{
69 return (v & 0x1) << 0; 69 return (v & 0x1U) << 0U;
70} 70}
71static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) 71static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void)
72{ 72{
73 return 0x0; 73 return 0x0U;
74} 74}
75static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) 75static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void)
76{ 76{
77 return 0x1; 77 return 0x1U;
78} 78}
79static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) 79static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
80{ 80{
81 return (r >> 15) & 0x1; 81 return (r >> 15U) & 0x1U;
82} 82}
83static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) 83static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
84{ 84{
85 return 0x0; 85 return 0x0U;
86} 86}
87static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) 87static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
88{ 88{
89 return (r >> 16) & 0xff; 89 return (r >> 16U) & 0xffU;
90} 90}
91static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) 91static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r)
92{ 92{
93 return (r >> 11) & 0x1; 93 return (r >> 11U) & 0x1U;
94} 94}
95static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) 95static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void)
96{ 96{
97 return 0x800; 97 return 0x800U;
98} 98}
99static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) 99static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
100{ 100{
101 return 0x0; 101 return 0x0U;
102} 102}
103static inline u32 fb_priv_mmu_phy_secure_r(void) 103static inline u32 fb_priv_mmu_phy_secure_r(void)
104{ 104{
105 return 0x00100ce4; 105 return 0x00100ce4U;
106} 106}
107static inline u32 fb_mmu_invalidate_pdb_r(void) 107static inline u32 fb_mmu_invalidate_pdb_r(void)
108{ 108{
109 return 0x00100cb8; 109 return 0x00100cb8U;
110} 110}
111static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) 111static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
112{ 112{
113 return 0x0; 113 return 0x0U;
114} 114}
115static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void) 115static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
116{ 116{
117 return 0x2; 117 return 0x2U;
118} 118}
119static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) 119static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
120{ 120{
121 return (v & 0xfffffff) << 4; 121 return (v & 0xfffffffU) << 4U;
122} 122}
123static inline u32 fb_mmu_invalidate_r(void) 123static inline u32 fb_mmu_invalidate_r(void)
124{ 124{
125 return 0x00100cbc; 125 return 0x00100cbcU;
126} 126}
127static inline u32 fb_mmu_invalidate_all_va_true_f(void) 127static inline u32 fb_mmu_invalidate_all_va_true_f(void)
128{ 128{
129 return 0x1; 129 return 0x1U;
130} 130}
131static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) 131static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
132{ 132{
133 return 0x2; 133 return 0x2U;
134} 134}
135static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) 135static inline u32 fb_mmu_invalidate_hubtlb_only_s(void)
136{ 136{
137 return 1; 137 return 1U;
138} 138}
139static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) 139static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v)
140{ 140{
141 return (v & 0x1) << 2; 141 return (v & 0x1U) << 2U;
142} 142}
143static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) 143static inline u32 fb_mmu_invalidate_hubtlb_only_m(void)
144{ 144{
145 return 0x1 << 2; 145 return 0x1U << 2U;
146} 146}
147static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) 147static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r)
148{ 148{
149 return (r >> 2) & 0x1; 149 return (r >> 2U) & 0x1U;
150} 150}
151static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) 151static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void)
152{ 152{
153 return 0x4; 153 return 0x4U;
154} 154}
155static inline u32 fb_mmu_invalidate_replay_s(void) 155static inline u32 fb_mmu_invalidate_replay_s(void)
156{ 156{
157 return 3; 157 return 3U;
158} 158}
159static inline u32 fb_mmu_invalidate_replay_f(u32 v) 159static inline u32 fb_mmu_invalidate_replay_f(u32 v)
160{ 160{
161 return (v & 0x7) << 3; 161 return (v & 0x7U) << 3U;
162} 162}
163static inline u32 fb_mmu_invalidate_replay_m(void) 163static inline u32 fb_mmu_invalidate_replay_m(void)
164{ 164{
165 return 0x7 << 3; 165 return 0x7U << 3U;
166} 166}
167static inline u32 fb_mmu_invalidate_replay_v(u32 r) 167static inline u32 fb_mmu_invalidate_replay_v(u32 r)
168{ 168{
169 return (r >> 3) & 0x7; 169 return (r >> 3U) & 0x7U;
170} 170}
171static inline u32 fb_mmu_invalidate_replay_none_f(void) 171static inline u32 fb_mmu_invalidate_replay_none_f(void)
172{ 172{
173 return 0x0; 173 return 0x0U;
174} 174}
175static inline u32 fb_mmu_invalidate_replay_start_f(void) 175static inline u32 fb_mmu_invalidate_replay_start_f(void)
176{ 176{
177 return 0x8; 177 return 0x8U;
178} 178}
179static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) 179static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void)
180{ 180{
181 return 0x10; 181 return 0x10U;
182} 182}
183static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) 183static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void)
184{ 184{
185 return 0x20; 185 return 0x20U;
186} 186}
187static inline u32 fb_mmu_invalidate_sys_membar_s(void) 187static inline u32 fb_mmu_invalidate_sys_membar_s(void)
188{ 188{
189 return 1; 189 return 1U;
190} 190}
191static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) 191static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v)
192{ 192{
193 return (v & 0x1) << 6; 193 return (v & 0x1U) << 6U;
194} 194}
195static inline u32 fb_mmu_invalidate_sys_membar_m(void) 195static inline u32 fb_mmu_invalidate_sys_membar_m(void)
196{ 196{
197 return 0x1 << 6; 197 return 0x1U << 6U;
198} 198}
199static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) 199static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r)
200{ 200{
201 return (r >> 6) & 0x1; 201 return (r >> 6U) & 0x1U;
202} 202}
203static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) 203static inline u32 fb_mmu_invalidate_sys_membar_true_f(void)
204{ 204{
205 return 0x40; 205 return 0x40U;
206} 206}
207static inline u32 fb_mmu_invalidate_ack_s(void) 207static inline u32 fb_mmu_invalidate_ack_s(void)
208{ 208{
209 return 2; 209 return 2U;
210} 210}
211static inline u32 fb_mmu_invalidate_ack_f(u32 v) 211static inline u32 fb_mmu_invalidate_ack_f(u32 v)
212{ 212{
213 return (v & 0x3) << 7; 213 return (v & 0x3U) << 7U;
214} 214}
215static inline u32 fb_mmu_invalidate_ack_m(void) 215static inline u32 fb_mmu_invalidate_ack_m(void)
216{ 216{
217 return 0x3 << 7; 217 return 0x3U << 7U;
218} 218}
219static inline u32 fb_mmu_invalidate_ack_v(u32 r) 219static inline u32 fb_mmu_invalidate_ack_v(u32 r)
220{ 220{
221 return (r >> 7) & 0x3; 221 return (r >> 7U) & 0x3U;
222} 222}
223static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) 223static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void)
224{ 224{
225 return 0x0; 225 return 0x0U;
226} 226}
227static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) 227static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void)
228{ 228{
229 return 0x100; 229 return 0x100U;
230} 230}
231static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) 231static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void)
232{ 232{
233 return 0x80; 233 return 0x80U;
234} 234}
235static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) 235static inline u32 fb_mmu_invalidate_cancel_client_id_s(void)
236{ 236{
237 return 6; 237 return 6U;
238} 238}
239static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) 239static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v)
240{ 240{
241 return (v & 0x3f) << 9; 241 return (v & 0x3fU) << 9U;
242} 242}
243static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) 243static inline u32 fb_mmu_invalidate_cancel_client_id_m(void)
244{ 244{
245 return 0x3f << 9; 245 return 0x3fU << 9U;
246} 246}
247static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) 247static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r)
248{ 248{
249 return (r >> 9) & 0x3f; 249 return (r >> 9U) & 0x3fU;
250} 250}
251static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) 251static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void)
252{ 252{
253 return 5; 253 return 5U;
254} 254}
255static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) 255static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v)
256{ 256{
257 return (v & 0x1f) << 15; 257 return (v & 0x1fU) << 15U;
258} 258}
259static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) 259static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void)
260{ 260{
261 return 0x1f << 15; 261 return 0x1fU << 15U;
262} 262}
263static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) 263static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r)
264{ 264{
265 return (r >> 15) & 0x1f; 265 return (r >> 15U) & 0x1fU;
266} 266}
267static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) 267static inline u32 fb_mmu_invalidate_cancel_client_type_s(void)
268{ 268{
269 return 1; 269 return 1U;
270} 270}
271static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) 271static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v)
272{ 272{
273 return (v & 0x1) << 20; 273 return (v & 0x1U) << 20U;
274} 274}
275static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) 275static inline u32 fb_mmu_invalidate_cancel_client_type_m(void)
276{ 276{
277 return 0x1 << 20; 277 return 0x1U << 20U;
278} 278}
279static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) 279static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r)
280{ 280{
281 return (r >> 20) & 0x1; 281 return (r >> 20U) & 0x1U;
282} 282}
283static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) 283static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void)
284{ 284{
285 return 0x0; 285 return 0x0U;
286} 286}
287static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) 287static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void)
288{ 288{
289 return 0x100000; 289 return 0x100000U;
290} 290}
291static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) 291static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void)
292{ 292{
293 return 3; 293 return 3U;
294} 294}
295static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) 295static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v)
296{ 296{
297 return (v & 0x7) << 24; 297 return (v & 0x7U) << 24U;
298} 298}
299static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) 299static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void)
300{ 300{
301 return 0x7 << 24; 301 return 0x7U << 24U;
302} 302}
303static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) 303static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r)
304{ 304{
305 return (r >> 24) & 0x7; 305 return (r >> 24U) & 0x7U;
306} 306}
307static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) 307static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void)
308{ 308{
309 return 0x0; 309 return 0x0U;
310} 310}
311static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) 311static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void)
312{ 312{
313 return 0x1000000; 313 return 0x1000000U;
314} 314}
315static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) 315static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void)
316{ 316{
317 return 0x2000000; 317 return 0x2000000U;
318} 318}
319static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) 319static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void)
320{ 320{
321 return 0x3000000; 321 return 0x3000000U;
322} 322}
323static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) 323static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void)
324{ 324{
325 return 0x4000000; 325 return 0x4000000U;
326} 326}
327static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) 327static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void)
328{ 328{
329 return 0x5000000; 329 return 0x5000000U;
330} 330}
331static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) 331static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void)
332{ 332{
333 return 0x6000000; 333 return 0x6000000U;
334} 334}
335static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) 335static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void)
336{ 336{
337 return 0x7000000; 337 return 0x7000000U;
338} 338}
339static inline u32 fb_mmu_invalidate_trigger_s(void) 339static inline u32 fb_mmu_invalidate_trigger_s(void)
340{ 340{
341 return 1; 341 return 1U;
342} 342}
343static inline u32 fb_mmu_invalidate_trigger_f(u32 v) 343static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
344{ 344{
345 return (v & 0x1) << 31; 345 return (v & 0x1U) << 31U;
346} 346}
347static inline u32 fb_mmu_invalidate_trigger_m(void) 347static inline u32 fb_mmu_invalidate_trigger_m(void)
348{ 348{
349 return 0x1 << 31; 349 return 0x1U << 31U;
350} 350}
351static inline u32 fb_mmu_invalidate_trigger_v(u32 r) 351static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
352{ 352{
353 return (r >> 31) & 0x1; 353 return (r >> 31U) & 0x1U;
354} 354}
355static inline u32 fb_mmu_invalidate_trigger_true_f(void) 355static inline u32 fb_mmu_invalidate_trigger_true_f(void)
356{ 356{
357 return 0x80000000; 357 return 0x80000000U;
358} 358}
359static inline u32 fb_mmu_debug_wr_r(void) 359static inline u32 fb_mmu_debug_wr_r(void)
360{ 360{
361 return 0x00100cc8; 361 return 0x00100cc8U;
362} 362}
363static inline u32 fb_mmu_debug_wr_aperture_s(void) 363static inline u32 fb_mmu_debug_wr_aperture_s(void)
364{ 364{
365 return 2; 365 return 2U;
366} 366}
367static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) 367static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
368{ 368{
369 return (v & 0x3) << 0; 369 return (v & 0x3U) << 0U;
370} 370}
371static inline u32 fb_mmu_debug_wr_aperture_m(void) 371static inline u32 fb_mmu_debug_wr_aperture_m(void)
372{ 372{
373 return 0x3 << 0; 373 return 0x3U << 0U;
374} 374}
375static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) 375static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
376{ 376{
377 return (r >> 0) & 0x3; 377 return (r >> 0U) & 0x3U;
378} 378}
379static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) 379static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
380{ 380{
381 return 0x0; 381 return 0x0U;
382} 382}
383static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void) 383static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
384{ 384{
385 return 0x2; 385 return 0x2U;
386} 386}
387static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void) 387static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
388{ 388{
389 return 0x3; 389 return 0x3U;
390} 390}
391static inline u32 fb_mmu_debug_wr_vol_false_f(void) 391static inline u32 fb_mmu_debug_wr_vol_false_f(void)
392{ 392{
393 return 0x0; 393 return 0x0U;
394} 394}
395static inline u32 fb_mmu_debug_wr_vol_true_v(void) 395static inline u32 fb_mmu_debug_wr_vol_true_v(void)
396{ 396{
397 return 0x00000001; 397 return 0x00000001U;
398} 398}
399static inline u32 fb_mmu_debug_wr_vol_true_f(void) 399static inline u32 fb_mmu_debug_wr_vol_true_f(void)
400{ 400{
401 return 0x4; 401 return 0x4U;
402} 402}
403static inline u32 fb_mmu_debug_wr_addr_f(u32 v) 403static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
404{ 404{
405 return (v & 0xfffffff) << 4; 405 return (v & 0xfffffffU) << 4U;
406} 406}
407static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) 407static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
408{ 408{
409 return 0x0000000c; 409 return 0x0000000cU;
410} 410}
411static inline u32 fb_mmu_debug_rd_r(void) 411static inline u32 fb_mmu_debug_rd_r(void)
412{ 412{
413 return 0x00100ccc; 413 return 0x00100cccU;
414} 414}
415static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) 415static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
416{ 416{
417 return 0x0; 417 return 0x0U;
418} 418}
419static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void) 419static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
420{ 420{
421 return 0x2; 421 return 0x2U;
422} 422}
423static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void) 423static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
424{ 424{
425 return 0x3; 425 return 0x3U;
426} 426}
427static inline u32 fb_mmu_debug_rd_vol_false_f(void) 427static inline u32 fb_mmu_debug_rd_vol_false_f(void)
428{ 428{
429 return 0x0; 429 return 0x0U;
430} 430}
431static inline u32 fb_mmu_debug_rd_addr_f(u32 v) 431static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
432{ 432{
433 return (v & 0xfffffff) << 4; 433 return (v & 0xfffffffU) << 4U;
434} 434}
435static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) 435static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
436{ 436{
437 return 0x0000000c; 437 return 0x0000000cU;
438} 438}
439static inline u32 fb_mmu_debug_ctrl_r(void) 439static inline u32 fb_mmu_debug_ctrl_r(void)
440{ 440{
441 return 0x00100cc4; 441 return 0x00100cc4U;
442} 442}
443static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) 443static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
444{ 444{
445 return (r >> 16) & 0x1; 445 return (r >> 16U) & 0x1U;
446} 446}
447static inline u32 fb_mmu_debug_ctrl_debug_m(void) 447static inline u32 fb_mmu_debug_ctrl_debug_m(void)
448{ 448{
449 return 0x1 << 16; 449 return 0x1U << 16U;
450} 450}
451static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) 451static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
452{ 452{
453 return 0x00000001; 453 return 0x00000001U;
454} 454}
455static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) 455static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
456{ 456{
457 return 0x00000000; 457 return 0x00000000U;
458} 458}
459static inline u32 fb_mmu_vpr_info_r(void) 459static inline u32 fb_mmu_vpr_info_r(void)
460{ 460{
461 return 0x00100cd0; 461 return 0x00100cd0U;
462} 462}
463static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) 463static inline u32 fb_mmu_vpr_info_fetch_v(u32 r)
464{ 464{
465 return (r >> 2) & 0x1; 465 return (r >> 2U) & 0x1U;
466} 466}
467static inline u32 fb_mmu_vpr_info_fetch_false_v(void) 467static inline u32 fb_mmu_vpr_info_fetch_false_v(void)
468{ 468{
469 return 0x00000000; 469 return 0x00000000U;
470} 470}
471static inline u32 fb_mmu_vpr_info_fetch_true_v(void) 471static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
472{ 472{
473 return 0x00000001; 473 return 0x00000001U;
474} 474}
475static inline u32 fb_mmu_l2tlb_ecc_status_r(void) 475static inline u32 fb_mmu_l2tlb_ecc_status_r(void)
476{ 476{
477 return 0x00100e70; 477 return 0x00100e70U;
478} 478}
479static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m(void) 479static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m(void)
480{ 480{
481 return 0x1 << 0; 481 return 0x1U << 0U;
482} 482}
483static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m(void) 483static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_l2tlb_sa_data_m(void)
484{ 484{
485 return 0x1 << 1; 485 return 0x1U << 1U;
486} 486}
487static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m(void) 487static inline u32 fb_mmu_l2tlb_ecc_status_corrected_err_total_counter_overflow_m(void)
488{ 488{
489 return 0x1 << 16; 489 return 0x1U << 16U;
490} 490}
491static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) 491static inline u32 fb_mmu_l2tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void)
492{ 492{
493 return 0x1 << 18; 493 return 0x1U << 18U;
494} 494}
495static inline u32 fb_mmu_l2tlb_ecc_status_reset_f(u32 v) 495static inline u32 fb_mmu_l2tlb_ecc_status_reset_f(u32 v)
496{ 496{
497 return (v & 0x1) << 30; 497 return (v & 0x1U) << 30U;
498} 498}
499static inline u32 fb_mmu_l2tlb_ecc_status_reset_clear_f(void) 499static inline u32 fb_mmu_l2tlb_ecc_status_reset_clear_f(void)
500{ 500{
501 return 0x40000000; 501 return 0x40000000U;
502} 502}
503static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_r(void) 503static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_r(void)
504{ 504{
505 return 0x00100e74; 505 return 0x00100e74U;
506} 506}
507static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_s(void) 507static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_s(void)
508{ 508{
509 return 16; 509 return 16U;
510} 510}
511static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_f(u32 v) 511static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_f(u32 v)
512{ 512{
513 return (v & 0xffff) << 0; 513 return (v & 0xffffU) << 0U;
514} 514}
515static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_m(void) 515static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_m(void)
516{ 516{
517 return 0xffff << 0; 517 return 0xffffU << 0U;
518} 518}
519static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_v(u32 r) 519static inline u32 fb_mmu_l2tlb_ecc_corrected_err_count_total_v(u32 r)
520{ 520{
521 return (r >> 0) & 0xffff; 521 return (r >> 0U) & 0xffffU;
522} 522}
523static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_r(void) 523static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_r(void)
524{ 524{
525 return 0x00100e78; 525 return 0x00100e78U;
526} 526}
527static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s(void) 527static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s(void)
528{ 528{
529 return 16; 529 return 16U;
530} 530}
531static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_f(u32 v) 531static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_f(u32 v)
532{ 532{
533 return (v & 0xffff) << 0; 533 return (v & 0xffffU) << 0U;
534} 534}
535static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_m(void) 535static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_m(void)
536{ 536{
537 return 0xffff << 0; 537 return 0xffffU << 0U;
538} 538}
539static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(u32 r) 539static inline u32 fb_mmu_l2tlb_ecc_uncorrected_err_count_total_v(u32 r)
540{ 540{
541 return (r >> 0) & 0xffff; 541 return (r >> 0U) & 0xffffU;
542} 542}
543static inline u32 fb_mmu_l2tlb_ecc_address_r(void) 543static inline u32 fb_mmu_l2tlb_ecc_address_r(void)
544{ 544{
545 return 0x00100e7c; 545 return 0x00100e7cU;
546} 546}
547static inline u32 fb_mmu_l2tlb_ecc_address_index_s(void) 547static inline u32 fb_mmu_l2tlb_ecc_address_index_s(void)
548{ 548{
549 return 32; 549 return 32U;
550} 550}
551static inline u32 fb_mmu_l2tlb_ecc_address_index_f(u32 v) 551static inline u32 fb_mmu_l2tlb_ecc_address_index_f(u32 v)
552{ 552{
553 return (v & 0xffffffff) << 0; 553 return (v & 0xffffffffU) << 0U;
554} 554}
555static inline u32 fb_mmu_l2tlb_ecc_address_index_m(void) 555static inline u32 fb_mmu_l2tlb_ecc_address_index_m(void)
556{ 556{
557 return 0xffffffff << 0; 557 return 0xffffffffU << 0U;
558} 558}
559static inline u32 fb_mmu_l2tlb_ecc_address_index_v(u32 r) 559static inline u32 fb_mmu_l2tlb_ecc_address_index_v(u32 r)
560{ 560{
561 return (r >> 0) & 0xffffffff; 561 return (r >> 0U) & 0xffffffffU;
562} 562}
563static inline u32 fb_mmu_hubtlb_ecc_status_r(void) 563static inline u32 fb_mmu_hubtlb_ecc_status_r(void)
564{ 564{
565 return 0x00100e84; 565 return 0x00100e84U;
566} 566}
567static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m(void) 567static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m(void)
568{ 568{
569 return 0x1 << 0; 569 return 0x1U << 0U;
570} 570}
571static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m(void) 571static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_sa_data_m(void)
572{ 572{
573 return 0x1 << 1; 573 return 0x1U << 1U;
574} 574}
575static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m(void) 575static inline u32 fb_mmu_hubtlb_ecc_status_corrected_err_total_counter_overflow_m(void)
576{ 576{
577 return 0x1 << 16; 577 return 0x1U << 16U;
578} 578}
579static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) 579static inline u32 fb_mmu_hubtlb_ecc_status_uncorrected_err_total_counter_overflow_m(void)
580{ 580{
581 return 0x1 << 18; 581 return 0x1U << 18U;
582} 582}
583static inline u32 fb_mmu_hubtlb_ecc_status_reset_f(u32 v) 583static inline u32 fb_mmu_hubtlb_ecc_status_reset_f(u32 v)
584{ 584{
585 return (v & 0x1) << 30; 585 return (v & 0x1U) << 30U;
586} 586}
587static inline u32 fb_mmu_hubtlb_ecc_status_reset_clear_f(void) 587static inline u32 fb_mmu_hubtlb_ecc_status_reset_clear_f(void)
588{ 588{
589 return 0x40000000; 589 return 0x40000000U;
590} 590}
591static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_r(void) 591static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_r(void)
592{ 592{
593 return 0x00100e88; 593 return 0x00100e88U;
594} 594}
595static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_s(void) 595static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_s(void)
596{ 596{
597 return 16; 597 return 16U;
598} 598}
599static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_f(u32 v) 599static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_f(u32 v)
600{ 600{
601 return (v & 0xffff) << 0; 601 return (v & 0xffffU) << 0U;
602} 602}
603static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_m(void) 603static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_m(void)
604{ 604{
605 return 0xffff << 0; 605 return 0xffffU << 0U;
606} 606}
607static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_v(u32 r) 607static inline u32 fb_mmu_hubtlb_ecc_corrected_err_count_total_v(u32 r)
608{ 608{
609 return (r >> 0) & 0xffff; 609 return (r >> 0U) & 0xffffU;
610} 610}
611static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_r(void) 611static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_r(void)
612{ 612{
613 return 0x00100e8c; 613 return 0x00100e8cU;
614} 614}
615static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s(void) 615static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s(void)
616{ 616{
617 return 16; 617 return 16U;
618} 618}
619static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_f(u32 v) 619static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_f(u32 v)
620{ 620{
621 return (v & 0xffff) << 0; 621 return (v & 0xffffU) << 0U;
622} 622}
623static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_m(void) 623static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_m(void)
624{ 624{
625 return 0xffff << 0; 625 return 0xffffU << 0U;
626} 626}
627static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(u32 r) 627static inline u32 fb_mmu_hubtlb_ecc_uncorrected_err_count_total_v(u32 r)
628{ 628{
629 return (r >> 0) & 0xffff; 629 return (r >> 0U) & 0xffffU;
630} 630}
631static inline u32 fb_mmu_hubtlb_ecc_address_r(void) 631static inline u32 fb_mmu_hubtlb_ecc_address_r(void)
632{ 632{
633 return 0x00100e90; 633 return 0x00100e90U;
634} 634}
635static inline u32 fb_mmu_hubtlb_ecc_address_index_s(void) 635static inline u32 fb_mmu_hubtlb_ecc_address_index_s(void)
636{ 636{
637 return 32; 637 return 32U;
638} 638}
639static inline u32 fb_mmu_hubtlb_ecc_address_index_f(u32 v) 639static inline u32 fb_mmu_hubtlb_ecc_address_index_f(u32 v)
640{ 640{
641 return (v & 0xffffffff) << 0; 641 return (v & 0xffffffffU) << 0U;
642} 642}
643static inline u32 fb_mmu_hubtlb_ecc_address_index_m(void) 643static inline u32 fb_mmu_hubtlb_ecc_address_index_m(void)
644{ 644{
645 return 0xffffffff << 0; 645 return 0xffffffffU << 0U;
646} 646}
647static inline u32 fb_mmu_hubtlb_ecc_address_index_v(u32 r) 647static inline u32 fb_mmu_hubtlb_ecc_address_index_v(u32 r)
648{ 648{
649 return (r >> 0) & 0xffffffff; 649 return (r >> 0U) & 0xffffffffU;
650} 650}
651static inline u32 fb_mmu_fillunit_ecc_status_r(void) 651static inline u32 fb_mmu_fillunit_ecc_status_r(void)
652{ 652{
653 return 0x00100e98; 653 return 0x00100e98U;
654} 654}
655static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m(void) 655static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m(void)
656{ 656{
657 return 0x1 << 0; 657 return 0x1U << 0U;
658} 658}
659static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m(void) 659static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pte_data_m(void)
660{ 660{
661 return 0x1 << 1; 661 return 0x1U << 1U;
662} 662}
663static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m(void) 663static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_pde0_data_m(void)
664{ 664{
665 return 0x1 << 2; 665 return 0x1U << 2U;
666} 666}
667static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m(void) 667static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_pde0_data_m(void)
668{ 668{
669 return 0x1 << 3; 669 return 0x1U << 3U;
670} 670}
671static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m(void) 671static inline u32 fb_mmu_fillunit_ecc_status_corrected_err_total_counter_overflow_m(void)
672{ 672{
673 return 0x1 << 16; 673 return 0x1U << 16U;
674} 674}
675static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m(void) 675static inline u32 fb_mmu_fillunit_ecc_status_uncorrected_err_total_counter_overflow_m(void)
676{ 676{
677 return 0x1 << 18; 677 return 0x1U << 18U;
678} 678}
679static inline u32 fb_mmu_fillunit_ecc_status_reset_f(u32 v) 679static inline u32 fb_mmu_fillunit_ecc_status_reset_f(u32 v)
680{ 680{
681 return (v & 0x1) << 30; 681 return (v & 0x1U) << 30U;
682} 682}
683static inline u32 fb_mmu_fillunit_ecc_status_reset_clear_f(void) 683static inline u32 fb_mmu_fillunit_ecc_status_reset_clear_f(void)
684{ 684{
685 return 0x40000000; 685 return 0x40000000U;
686} 686}
687static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_r(void) 687static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_r(void)
688{ 688{
689 return 0x00100e9c; 689 return 0x00100e9cU;
690} 690}
691static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_s(void) 691static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_s(void)
692{ 692{
693 return 16; 693 return 16U;
694} 694}
695static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_f(u32 v) 695static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_f(u32 v)
696{ 696{
697 return (v & 0xffff) << 0; 697 return (v & 0xffffU) << 0U;
698} 698}
699static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_m(void) 699static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_m(void)
700{ 700{
701 return 0xffff << 0; 701 return 0xffffU << 0U;
702} 702}
703static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_v(u32 r) 703static inline u32 fb_mmu_fillunit_ecc_corrected_err_count_total_v(u32 r)
704{ 704{
705 return (r >> 0) & 0xffff; 705 return (r >> 0U) & 0xffffU;
706} 706}
707static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_r(void) 707static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_r(void)
708{ 708{
709 return 0x00100ea0; 709 return 0x00100ea0U;
710} 710}
711static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_s(void) 711static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_s(void)
712{ 712{
713 return 16; 713 return 16U;
714} 714}
715static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_f(u32 v) 715static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_f(u32 v)
716{ 716{
717 return (v & 0xffff) << 0; 717 return (v & 0xffffU) << 0U;
718} 718}
719static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_m(void) 719static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_m(void)
720{ 720{
721 return 0xffff << 0; 721 return 0xffffU << 0U;
722} 722}
723static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(u32 r) 723static inline u32 fb_mmu_fillunit_ecc_uncorrected_err_count_total_v(u32 r)
724{ 724{
725 return (r >> 0) & 0xffff; 725 return (r >> 0U) & 0xffffU;
726} 726}
727static inline u32 fb_mmu_fillunit_ecc_address_r(void) 727static inline u32 fb_mmu_fillunit_ecc_address_r(void)
728{ 728{
729 return 0x00100ea4; 729 return 0x00100ea4U;
730} 730}
731static inline u32 fb_mmu_fillunit_ecc_address_index_s(void) 731static inline u32 fb_mmu_fillunit_ecc_address_index_s(void)
732{ 732{
733 return 32; 733 return 32U;
734} 734}
735static inline u32 fb_mmu_fillunit_ecc_address_index_f(u32 v) 735static inline u32 fb_mmu_fillunit_ecc_address_index_f(u32 v)
736{ 736{
737 return (v & 0xffffffff) << 0; 737 return (v & 0xffffffffU) << 0U;
738} 738}
739static inline u32 fb_mmu_fillunit_ecc_address_index_m(void) 739static inline u32 fb_mmu_fillunit_ecc_address_index_m(void)
740{ 740{
741 return 0xffffffff << 0; 741 return 0xffffffffU << 0U;
742} 742}
743static inline u32 fb_mmu_fillunit_ecc_address_index_v(u32 r) 743static inline u32 fb_mmu_fillunit_ecc_address_index_v(u32 r)
744{ 744{
745 return (r >> 0) & 0xffffffff; 745 return (r >> 0U) & 0xffffffffU;
746} 746}
747static inline u32 fb_niso_flush_sysmem_addr_r(void) 747static inline u32 fb_niso_flush_sysmem_addr_r(void)
748{ 748{
749 return 0x00100c10; 749 return 0x00100c10U;
750} 750}
751static inline u32 fb_niso_intr_r(void) 751static inline u32 fb_niso_intr_r(void)
752{ 752{
753 return 0x00100a20; 753 return 0x00100a20U;
754} 754}
755static inline u32 fb_niso_intr_hub_access_counter_notify_m(void) 755static inline u32 fb_niso_intr_hub_access_counter_notify_m(void)
756{ 756{
757 return 0x1 << 0; 757 return 0x1U << 0U;
758} 758}
759static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void) 759static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void)
760{ 760{
761 return 0x1; 761 return 0x1U;
762} 762}
763static inline u32 fb_niso_intr_hub_access_counter_error_m(void) 763static inline u32 fb_niso_intr_hub_access_counter_error_m(void)
764{ 764{
765 return 0x1 << 1; 765 return 0x1U << 1U;
766} 766}
767static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void) 767static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void)
768{ 768{
769 return 0x2; 769 return 0x2U;
770} 770}
771static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void) 771static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void)
772{ 772{
773 return 0x1 << 27; 773 return 0x1U << 27U;
774} 774}
775static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void) 775static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void)
776{ 776{
777 return 0x8000000; 777 return 0x8000000U;
778} 778}
779static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void) 779static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void)
780{ 780{
781 return 0x1 << 28; 781 return 0x1U << 28U;
782} 782}
783static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void) 783static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void)
784{ 784{
785 return 0x10000000; 785 return 0x10000000U;
786} 786}
787static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void) 787static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void)
788{ 788{
789 return 0x1 << 29; 789 return 0x1U << 29U;
790} 790}
791static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void) 791static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void)
792{ 792{
793 return 0x20000000; 793 return 0x20000000U;
794} 794}
795static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void) 795static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void)
796{ 796{
797 return 0x1 << 30; 797 return 0x1U << 30U;
798} 798}
799static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void) 799static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void)
800{ 800{
801 return 0x40000000; 801 return 0x40000000U;
802} 802}
803static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void) 803static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void)
804{ 804{
805 return 0x1 << 31; 805 return 0x1U << 31U;
806} 806}
807static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void) 807static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void)
808{ 808{
809 return 0x80000000; 809 return 0x80000000U;
810} 810}
811static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_m(void) 811static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_m(void)
812{ 812{
813 return 0x1 << 26; 813 return 0x1U << 26U;
814} 814}
815static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f(void) 815static inline u32 fb_niso_intr_mmu_ecc_uncorrected_error_notify_pending_f(void)
816{ 816{
817 return 0x4000000; 817 return 0x4000000U;
818} 818}
819static inline u32 fb_niso_intr_en_r(u32 i) 819static inline u32 fb_niso_intr_en_r(u32 i)
820{ 820{
821 return 0x00100a24 + i*4; 821 return 0x00100a24U + i*4U;
822} 822}
823static inline u32 fb_niso_intr_en__size_1_v(void) 823static inline u32 fb_niso_intr_en__size_1_v(void)
824{ 824{
825 return 0x00000002; 825 return 0x00000002U;
826} 826}
827static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v) 827static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v)
828{ 828{
829 return (v & 0x1) << 0; 829 return (v & 0x1U) << 0U;
830} 830}
831static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void) 831static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void)
832{ 832{
833 return 0x1; 833 return 0x1U;
834} 834}
835static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v) 835static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v)
836{ 836{
837 return (v & 0x1) << 1; 837 return (v & 0x1U) << 1U;
838} 838}
839static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void) 839static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void)
840{ 840{
841 return 0x2; 841 return 0x2U;
842} 842}
843static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v) 843static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v)
844{ 844{
845 return (v & 0x1) << 27; 845 return (v & 0x1U) << 27U;
846} 846}
847static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void) 847static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void)
848{ 848{
849 return 0x8000000; 849 return 0x8000000U;
850} 850}
851static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v) 851static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v)
852{ 852{
853 return (v & 0x1) << 28; 853 return (v & 0x1U) << 28U;
854} 854}
855static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void) 855static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void)
856{ 856{
857 return 0x10000000; 857 return 0x10000000U;
858} 858}
859static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v) 859static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v)
860{ 860{
861 return (v & 0x1) << 29; 861 return (v & 0x1U) << 29U;
862} 862}
863static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void) 863static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void)
864{ 864{
865 return 0x20000000; 865 return 0x20000000U;
866} 866}
867static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v) 867static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v)
868{ 868{
869 return (v & 0x1) << 30; 869 return (v & 0x1U) << 30U;
870} 870}
871static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void) 871static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void)
872{ 872{
873 return 0x40000000; 873 return 0x40000000U;
874} 874}
875static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v) 875static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v)
876{ 876{
877 return (v & 0x1) << 31; 877 return (v & 0x1U) << 31U;
878} 878}
879static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void) 879static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void)
880{ 880{
881 return 0x80000000; 881 return 0x80000000U;
882} 882}
883static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_f(u32 v) 883static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_f(u32 v)
884{ 884{
885 return (v & 0x1) << 26; 885 return (v & 0x1U) << 26U;
886} 886}
887static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_enabled_f(void) 887static inline u32 fb_niso_intr_en_mmu_ecc_uncorrected_error_notify_enabled_f(void)
888{ 888{
889 return 0x4000000; 889 return 0x4000000U;
890} 890}
891static inline u32 fb_niso_intr_en_set_r(u32 i) 891static inline u32 fb_niso_intr_en_set_r(u32 i)
892{ 892{
893 return 0x00100a2c + i*4; 893 return 0x00100a2cU + i*4U;
894} 894}
895static inline u32 fb_niso_intr_en_set__size_1_v(void) 895static inline u32 fb_niso_intr_en_set__size_1_v(void)
896{ 896{
897 return 0x00000002; 897 return 0x00000002U;
898} 898}
899static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void) 899static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void)
900{ 900{
901 return 0x1 << 0; 901 return 0x1U << 0U;
902} 902}
903static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void) 903static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void)
904{ 904{
905 return 0x1; 905 return 0x1U;
906} 906}
907static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void) 907static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void)
908{ 908{
909 return 0x1 << 1; 909 return 0x1U << 1U;
910} 910}
911static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void) 911static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void)
912{ 912{
913 return 0x2; 913 return 0x2U;
914} 914}
915static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void) 915static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void)
916{ 916{
917 return 0x1 << 27; 917 return 0x1U << 27U;
918} 918}
919static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void) 919static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void)
920{ 920{
921 return 0x8000000; 921 return 0x8000000U;
922} 922}
923static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void) 923static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void)
924{ 924{
925 return 0x1 << 28; 925 return 0x1U << 28U;
926} 926}
927static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void) 927static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void)
928{ 928{
929 return 0x10000000; 929 return 0x10000000U;
930} 930}
931static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void) 931static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void)
932{ 932{
933 return 0x1 << 29; 933 return 0x1U << 29U;
934} 934}
935static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void) 935static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void)
936{ 936{
937 return 0x20000000; 937 return 0x20000000U;
938} 938}
939static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void) 939static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void)
940{ 940{
941 return 0x1 << 30; 941 return 0x1U << 30U;
942} 942}
943static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void) 943static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void)
944{ 944{
945 return 0x40000000; 945 return 0x40000000U;
946} 946}
947static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void) 947static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void)
948{ 948{
949 return 0x1 << 31; 949 return 0x1U << 31U;
950} 950}
951static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void) 951static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void)
952{ 952{
953 return 0x80000000; 953 return 0x80000000U;
954} 954}
955static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m(void) 955static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_m(void)
956{ 956{
957 return 0x1 << 26; 957 return 0x1U << 26U;
958} 958}
959static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(void) 959static inline u32 fb_niso_intr_en_set_mmu_ecc_uncorrected_error_notify_set_f(void)
960{ 960{
961 return 0x4000000; 961 return 0x4000000U;
962} 962}
963static inline u32 fb_niso_intr_en_clr_r(u32 i) 963static inline u32 fb_niso_intr_en_clr_r(u32 i)
964{ 964{
965 return 0x00100a34 + i*4; 965 return 0x00100a34U + i*4U;
966} 966}
967static inline u32 fb_niso_intr_en_clr__size_1_v(void) 967static inline u32 fb_niso_intr_en_clr__size_1_v(void)
968{ 968{
969 return 0x00000002; 969 return 0x00000002U;
970} 970}
971static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void) 971static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void)
972{ 972{
973 return 0x1 << 0; 973 return 0x1U << 0U;
974} 974}
975static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void) 975static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void)
976{ 976{
977 return 0x1; 977 return 0x1U;
978} 978}
979static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void) 979static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void)
980{ 980{
981 return 0x1 << 1; 981 return 0x1U << 1U;
982} 982}
983static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void) 983static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void)
984{ 984{
985 return 0x2; 985 return 0x2U;
986} 986}
987static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void) 987static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void)
988{ 988{
989 return 0x1 << 27; 989 return 0x1U << 27U;
990} 990}
991static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void) 991static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void)
992{ 992{
993 return 0x8000000; 993 return 0x8000000U;
994} 994}
995static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void) 995static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void)
996{ 996{
997 return 0x1 << 28; 997 return 0x1U << 28U;
998} 998}
999static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void) 999static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void)
1000{ 1000{
1001 return 0x10000000; 1001 return 0x10000000U;
1002} 1002}
1003static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void) 1003static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void)
1004{ 1004{
1005 return 0x1 << 29; 1005 return 0x1U << 29U;
1006} 1006}
1007static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void) 1007static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void)
1008{ 1008{
1009 return 0x20000000; 1009 return 0x20000000U;
1010} 1010}
1011static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void) 1011static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void)
1012{ 1012{
1013 return 0x1 << 30; 1013 return 0x1U << 30U;
1014} 1014}
1015static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void) 1015static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void)
1016{ 1016{
1017 return 0x40000000; 1017 return 0x40000000U;
1018} 1018}
1019static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void) 1019static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void)
1020{ 1020{
1021 return 0x1 << 31; 1021 return 0x1U << 31U;
1022} 1022}
1023static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void) 1023static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void)
1024{ 1024{
1025 return 0x80000000; 1025 return 0x80000000U;
1026} 1026}
1027static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_m(void) 1027static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_m(void)
1028{ 1028{
1029 return 0x1 << 26; 1029 return 0x1U << 26U;
1030} 1030}
1031static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(void) 1031static inline u32 fb_niso_intr_en_clr_mmu_ecc_uncorrected_error_notify_set_f(void)
1032{ 1032{
1033 return 0x4000000; 1033 return 0x4000000U;
1034} 1034}
1035static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void) 1035static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void)
1036{ 1036{
1037 return 0x00000000; 1037 return 0x00000000U;
1038} 1038}
1039static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void) 1039static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void)
1040{ 1040{
1041 return 0x00000001; 1041 return 0x00000001U;
1042} 1042}
1043static inline u32 fb_mmu_fault_buffer_lo_r(u32 i) 1043static inline u32 fb_mmu_fault_buffer_lo_r(u32 i)
1044{ 1044{
1045 return 0x00100e24 + i*20; 1045 return 0x00100e24U + i*20U;
1046} 1046}
1047static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void) 1047static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void)
1048{ 1048{
1049 return 0x00000002; 1049 return 0x00000002U;
1050} 1050}
1051static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v) 1051static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v)
1052{ 1052{
1053 return (v & 0x1) << 0; 1053 return (v & 0x1U) << 0U;
1054} 1054}
1055static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r) 1055static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r)
1056{ 1056{
1057 return (r >> 0) & 0x1; 1057 return (r >> 0U) & 0x1U;
1058} 1058}
1059static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void) 1059static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void)
1060{ 1060{
1061 return 0x00000000; 1061 return 0x00000000U;
1062} 1062}
1063static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void) 1063static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void)
1064{ 1064{
1065 return 0x0; 1065 return 0x0U;
1066} 1066}
1067static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void) 1067static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void)
1068{ 1068{
1069 return 0x00000001; 1069 return 0x00000001U;
1070} 1070}
1071static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void) 1071static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void)
1072{ 1072{
1073 return 0x1; 1073 return 0x1U;
1074} 1074}
1075static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v) 1075static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v)
1076{ 1076{
1077 return (v & 0x3) << 1; 1077 return (v & 0x3U) << 1U;
1078} 1078}
1079static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r) 1079static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r)
1080{ 1080{
1081 return (r >> 1) & 0x3; 1081 return (r >> 1U) & 0x3U;
1082} 1082}
1083static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void) 1083static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void)
1084{ 1084{
1085 return 0x00000002; 1085 return 0x00000002U;
1086} 1086}
1087static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void) 1087static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void)
1088{ 1088{
1089 return 0x4; 1089 return 0x4U;
1090} 1090}
1091static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void) 1091static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void)
1092{ 1092{
1093 return 0x00000003; 1093 return 0x00000003U;
1094} 1094}
1095static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void) 1095static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void)
1096{ 1096{
1097 return 0x6; 1097 return 0x6U;
1098} 1098}
1099static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v) 1099static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v)
1100{ 1100{
1101 return (v & 0x1) << 3; 1101 return (v & 0x1U) << 3U;
1102} 1102}
1103static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r) 1103static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r)
1104{ 1104{
1105 return (r >> 3) & 0x1; 1105 return (r >> 3U) & 0x1U;
1106} 1106}
1107static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v) 1107static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v)
1108{ 1108{
1109 return (v & 0xfffff) << 12; 1109 return (v & 0xfffffU) << 12U;
1110} 1110}
1111static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r) 1111static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r)
1112{ 1112{
1113 return (r >> 12) & 0xfffff; 1113 return (r >> 12U) & 0xfffffU;
1114} 1114}
1115static inline u32 fb_mmu_fault_buffer_hi_r(u32 i) 1115static inline u32 fb_mmu_fault_buffer_hi_r(u32 i)
1116{ 1116{
1117 return 0x00100e28 + i*20; 1117 return 0x00100e28U + i*20U;
1118} 1118}
1119static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void) 1119static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void)
1120{ 1120{
1121 return 0x00000002; 1121 return 0x00000002U;
1122} 1122}
1123static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v) 1123static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v)
1124{ 1124{
1125 return (v & 0xffffffff) << 0; 1125 return (v & 0xffffffffU) << 0U;
1126} 1126}
1127static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r) 1127static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r)
1128{ 1128{
1129 return (r >> 0) & 0xffffffff; 1129 return (r >> 0U) & 0xffffffffU;
1130} 1130}
1131static inline u32 fb_mmu_fault_buffer_get_r(u32 i) 1131static inline u32 fb_mmu_fault_buffer_get_r(u32 i)
1132{ 1132{
1133 return 0x00100e2c + i*20; 1133 return 0x00100e2cU + i*20U;
1134} 1134}
1135static inline u32 fb_mmu_fault_buffer_get__size_1_v(void) 1135static inline u32 fb_mmu_fault_buffer_get__size_1_v(void)
1136{ 1136{
1137 return 0x00000002; 1137 return 0x00000002U;
1138} 1138}
1139static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v) 1139static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v)
1140{ 1140{
1141 return (v & 0xfffff) << 0; 1141 return (v & 0xfffffU) << 0U;
1142} 1142}
1143static inline u32 fb_mmu_fault_buffer_get_ptr_m(void) 1143static inline u32 fb_mmu_fault_buffer_get_ptr_m(void)
1144{ 1144{
1145 return 0xfffff << 0; 1145 return 0xfffffU << 0U;
1146} 1146}
1147static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r) 1147static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r)
1148{ 1148{
1149 return (r >> 0) & 0xfffff; 1149 return (r >> 0U) & 0xfffffU;
1150} 1150}
1151static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v) 1151static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v)
1152{ 1152{
1153 return (v & 0x1) << 30; 1153 return (v & 0x1U) << 30U;
1154} 1154}
1155static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void) 1155static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void)
1156{ 1156{
1157 return 0x1 << 30; 1157 return 0x1U << 30U;
1158} 1158}
1159static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void) 1159static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void)
1160{ 1160{
1161 return 0x00000001; 1161 return 0x00000001U;
1162} 1162}
1163static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void) 1163static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void)
1164{ 1164{
1165 return 0x40000000; 1165 return 0x40000000U;
1166} 1166}
1167static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v) 1167static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v)
1168{ 1168{
1169 return (v & 0x1) << 31; 1169 return (v & 0x1U) << 31U;
1170} 1170}
1171static inline u32 fb_mmu_fault_buffer_get_overflow_m(void) 1171static inline u32 fb_mmu_fault_buffer_get_overflow_m(void)
1172{ 1172{
1173 return 0x1 << 31; 1173 return 0x1U << 31U;
1174} 1174}
1175static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void) 1175static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void)
1176{ 1176{
1177 return 0x00000001; 1177 return 0x00000001U;
1178} 1178}
1179static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void) 1179static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void)
1180{ 1180{
1181 return 0x80000000; 1181 return 0x80000000U;
1182} 1182}
1183static inline u32 fb_mmu_fault_buffer_put_r(u32 i) 1183static inline u32 fb_mmu_fault_buffer_put_r(u32 i)
1184{ 1184{
1185 return 0x00100e30 + i*20; 1185 return 0x00100e30U + i*20U;
1186} 1186}
1187static inline u32 fb_mmu_fault_buffer_put__size_1_v(void) 1187static inline u32 fb_mmu_fault_buffer_put__size_1_v(void)
1188{ 1188{
1189 return 0x00000002; 1189 return 0x00000002U;
1190} 1190}
1191static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v) 1191static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v)
1192{ 1192{
1193 return (v & 0xfffff) << 0; 1193 return (v & 0xfffffU) << 0U;
1194} 1194}
1195static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r) 1195static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r)
1196{ 1196{
1197 return (r >> 0) & 0xfffff; 1197 return (r >> 0U) & 0xfffffU;
1198} 1198}
1199static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v) 1199static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v)
1200{ 1200{
1201 return (v & 0x1) << 30; 1201 return (v & 0x1U) << 30U;
1202} 1202}
1203static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r) 1203static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r)
1204{ 1204{
1205 return (r >> 30) & 0x1; 1205 return (r >> 30U) & 0x1U;
1206} 1206}
1207static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void) 1207static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void)
1208{ 1208{
1209 return 0x00000001; 1209 return 0x00000001U;
1210} 1210}
1211static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void) 1211static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void)
1212{ 1212{
1213 return 0x40000000; 1213 return 0x40000000U;
1214} 1214}
1215static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void) 1215static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void)
1216{ 1216{
1217 return 0x00000000; 1217 return 0x00000000U;
1218} 1218}
1219static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void) 1219static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void)
1220{ 1220{
1221 return 0x0; 1221 return 0x0U;
1222} 1222}
1223static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v) 1223static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v)
1224{ 1224{
1225 return (v & 0x1) << 31; 1225 return (v & 0x1U) << 31U;
1226} 1226}
1227static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r) 1227static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r)
1228{ 1228{
1229 return (r >> 31) & 0x1; 1229 return (r >> 31U) & 0x1U;
1230} 1230}
1231static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void) 1231static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void)
1232{ 1232{
1233 return 0x00000001; 1233 return 0x00000001U;
1234} 1234}
1235static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void) 1235static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void)
1236{ 1236{
1237 return 0x80000000; 1237 return 0x80000000U;
1238} 1238}
1239static inline u32 fb_mmu_fault_buffer_size_r(u32 i) 1239static inline u32 fb_mmu_fault_buffer_size_r(u32 i)
1240{ 1240{
1241 return 0x00100e34 + i*20; 1241 return 0x00100e34U + i*20U;
1242} 1242}
1243static inline u32 fb_mmu_fault_buffer_size__size_1_v(void) 1243static inline u32 fb_mmu_fault_buffer_size__size_1_v(void)
1244{ 1244{
1245 return 0x00000002; 1245 return 0x00000002U;
1246} 1246}
1247static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v) 1247static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v)
1248{ 1248{
1249 return (v & 0xfffff) << 0; 1249 return (v & 0xfffffU) << 0U;
1250} 1250}
1251static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r) 1251static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r)
1252{ 1252{
1253 return (r >> 0) & 0xfffff; 1253 return (r >> 0U) & 0xfffffU;
1254} 1254}
1255static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v) 1255static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v)
1256{ 1256{
1257 return (v & 0x1) << 29; 1257 return (v & 0x1U) << 29U;
1258} 1258}
1259static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r) 1259static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r)
1260{ 1260{
1261 return (r >> 29) & 0x1; 1261 return (r >> 29U) & 0x1U;
1262} 1262}
1263static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void) 1263static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void)
1264{ 1264{
1265 return 0x00000001; 1265 return 0x00000001U;
1266} 1266}
1267static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void) 1267static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void)
1268{ 1268{
1269 return 0x20000000; 1269 return 0x20000000U;
1270} 1270}
1271static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v) 1271static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v)
1272{ 1272{
1273 return (v & 0x1) << 30; 1273 return (v & 0x1U) << 30U;
1274} 1274}
1275static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r) 1275static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r)
1276{ 1276{
1277 return (r >> 30) & 0x1; 1277 return (r >> 30U) & 0x1U;
1278} 1278}
1279static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void) 1279static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void)
1280{ 1280{
1281 return 0x00000001; 1281 return 0x00000001U;
1282} 1282}
1283static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void) 1283static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void)
1284{ 1284{
1285 return 0x40000000; 1285 return 0x40000000U;
1286} 1286}
1287static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v) 1287static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v)
1288{ 1288{
1289 return (v & 0x1) << 31; 1289 return (v & 0x1U) << 31U;
1290} 1290}
1291static inline u32 fb_mmu_fault_buffer_size_enable_m(void) 1291static inline u32 fb_mmu_fault_buffer_size_enable_m(void)
1292{ 1292{
1293 return 0x1 << 31; 1293 return 0x1U << 31U;
1294} 1294}
1295static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r) 1295static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r)
1296{ 1296{
1297 return (r >> 31) & 0x1; 1297 return (r >> 31U) & 0x1U;
1298} 1298}
1299static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void) 1299static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void)
1300{ 1300{
1301 return 0x00000001; 1301 return 0x00000001U;
1302} 1302}
1303static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void) 1303static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void)
1304{ 1304{
1305 return 0x80000000; 1305 return 0x80000000U;
1306} 1306}
1307static inline u32 fb_mmu_fault_addr_lo_r(void) 1307static inline u32 fb_mmu_fault_addr_lo_r(void)
1308{ 1308{
1309 return 0x00100e4c; 1309 return 0x00100e4cU;
1310} 1310}
1311static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v) 1311static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v)
1312{ 1312{
1313 return (v & 0x3) << 0; 1313 return (v & 0x3U) << 0U;
1314} 1314}
1315static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r) 1315static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r)
1316{ 1316{
1317 return (r >> 0) & 0x3; 1317 return (r >> 0U) & 0x3U;
1318} 1318}
1319static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void) 1319static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void)
1320{ 1320{
1321 return 0x00000002; 1321 return 0x00000002U;
1322} 1322}
1323static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void) 1323static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void)
1324{ 1324{
1325 return 0x2; 1325 return 0x2U;
1326} 1326}
1327static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void) 1327static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void)
1328{ 1328{
1329 return 0x00000003; 1329 return 0x00000003U;
1330} 1330}
1331static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void) 1331static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void)
1332{ 1332{
1333 return 0x3; 1333 return 0x3U;
1334} 1334}
1335static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v) 1335static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v)
1336{ 1336{
1337 return (v & 0xfffff) << 12; 1337 return (v & 0xfffffU) << 12U;
1338} 1338}
1339static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r) 1339static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r)
1340{ 1340{
1341 return (r >> 12) & 0xfffff; 1341 return (r >> 12U) & 0xfffffU;
1342} 1342}
1343static inline u32 fb_mmu_fault_addr_hi_r(void) 1343static inline u32 fb_mmu_fault_addr_hi_r(void)
1344{ 1344{
1345 return 0x00100e50; 1345 return 0x00100e50U;
1346} 1346}
1347static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v) 1347static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v)
1348{ 1348{
1349 return (v & 0xffffffff) << 0; 1349 return (v & 0xffffffffU) << 0U;
1350} 1350}
1351static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r) 1351static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r)
1352{ 1352{
1353 return (r >> 0) & 0xffffffff; 1353 return (r >> 0U) & 0xffffffffU;
1354} 1354}
1355static inline u32 fb_mmu_fault_inst_lo_r(void) 1355static inline u32 fb_mmu_fault_inst_lo_r(void)
1356{ 1356{
1357 return 0x00100e54; 1357 return 0x00100e54U;
1358} 1358}
1359static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r) 1359static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r)
1360{ 1360{
1361 return (r >> 0) & 0x1ff; 1361 return (r >> 0U) & 0x1ffU;
1362} 1362}
1363static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r) 1363static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r)
1364{ 1364{
1365 return (r >> 10) & 0x3; 1365 return (r >> 10U) & 0x3U;
1366} 1366}
1367static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void) 1367static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void)
1368{ 1368{
1369 return 0x00000002; 1369 return 0x00000002U;
1370} 1370}
1371static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void) 1371static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void)
1372{ 1372{
1373 return 0x00000003; 1373 return 0x00000003U;
1374} 1374}
1375static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v) 1375static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v)
1376{ 1376{
1377 return (v & 0xfffff) << 12; 1377 return (v & 0xfffffU) << 12U;
1378} 1378}
1379static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r) 1379static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r)
1380{ 1380{
1381 return (r >> 12) & 0xfffff; 1381 return (r >> 12U) & 0xfffffU;
1382} 1382}
1383static inline u32 fb_mmu_fault_inst_hi_r(void) 1383static inline u32 fb_mmu_fault_inst_hi_r(void)
1384{ 1384{
1385 return 0x00100e58; 1385 return 0x00100e58U;
1386} 1386}
1387static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r) 1387static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r)
1388{ 1388{
1389 return (r >> 0) & 0xffffffff; 1389 return (r >> 0U) & 0xffffffffU;
1390} 1390}
1391static inline u32 fb_mmu_fault_info_r(void) 1391static inline u32 fb_mmu_fault_info_r(void)
1392{ 1392{
1393 return 0x00100e5c; 1393 return 0x00100e5cU;
1394} 1394}
1395static inline u32 fb_mmu_fault_info_fault_type_v(u32 r) 1395static inline u32 fb_mmu_fault_info_fault_type_v(u32 r)
1396{ 1396{
1397 return (r >> 0) & 0x1f; 1397 return (r >> 0U) & 0x1fU;
1398} 1398}
1399static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r) 1399static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r)
1400{ 1400{
1401 return (r >> 7) & 0x1; 1401 return (r >> 7U) & 0x1U;
1402} 1402}
1403static inline u32 fb_mmu_fault_info_client_v(u32 r) 1403static inline u32 fb_mmu_fault_info_client_v(u32 r)
1404{ 1404{
1405 return (r >> 8) & 0x7f; 1405 return (r >> 8U) & 0x7fU;
1406} 1406}
1407static inline u32 fb_mmu_fault_info_access_type_v(u32 r) 1407static inline u32 fb_mmu_fault_info_access_type_v(u32 r)
1408{ 1408{
1409 return (r >> 16) & 0xf; 1409 return (r >> 16U) & 0xfU;
1410} 1410}
1411static inline u32 fb_mmu_fault_info_client_type_v(u32 r) 1411static inline u32 fb_mmu_fault_info_client_type_v(u32 r)
1412{ 1412{
1413 return (r >> 20) & 0x1; 1413 return (r >> 20U) & 0x1U;
1414} 1414}
1415static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r) 1415static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r)
1416{ 1416{
1417 return (r >> 24) & 0x1f; 1417 return (r >> 24U) & 0x1fU;
1418} 1418}
1419static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r) 1419static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r)
1420{ 1420{
1421 return (r >> 29) & 0x1; 1421 return (r >> 29U) & 0x1U;
1422} 1422}
1423static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r) 1423static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r)
1424{ 1424{
1425 return (r >> 30) & 0x1; 1425 return (r >> 30U) & 0x1U;
1426} 1426}
1427static inline u32 fb_mmu_fault_info_valid_v(u32 r) 1427static inline u32 fb_mmu_fault_info_valid_v(u32 r)
1428{ 1428{
1429 return (r >> 31) & 0x1; 1429 return (r >> 31U) & 0x1U;
1430} 1430}
1431static inline u32 fb_mmu_fault_status_r(void) 1431static inline u32 fb_mmu_fault_status_r(void)
1432{ 1432{
1433 return 0x00100e60; 1433 return 0x00100e60U;
1434} 1434}
1435static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void) 1435static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void)
1436{ 1436{
1437 return 0x1 << 0; 1437 return 0x1U << 0U;
1438} 1438}
1439static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void) 1439static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void)
1440{ 1440{
1441 return 0x00000001; 1441 return 0x00000001U;
1442} 1442}
1443static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void) 1443static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void)
1444{ 1444{
1445 return 0x1; 1445 return 0x1U;
1446} 1446}
1447static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void) 1447static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void)
1448{ 1448{
1449 return 0x00000001; 1449 return 0x00000001U;
1450} 1450}
1451static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void) 1451static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void)
1452{ 1452{
1453 return 0x1; 1453 return 0x1U;
1454} 1454}
1455static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void) 1455static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void)
1456{ 1456{
1457 return 0x1 << 1; 1457 return 0x1U << 1U;
1458} 1458}
1459static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void) 1459static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void)
1460{ 1460{
1461 return 0x00000001; 1461 return 0x00000001U;
1462} 1462}
1463static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void) 1463static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void)
1464{ 1464{
1465 return 0x2; 1465 return 0x2U;
1466} 1466}
1467static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void) 1467static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void)
1468{ 1468{
1469 return 0x00000001; 1469 return 0x00000001U;
1470} 1470}
1471static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void) 1471static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void)
1472{ 1472{
1473 return 0x2; 1473 return 0x2U;
1474} 1474}
1475static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void) 1475static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void)
1476{ 1476{
1477 return 0x1 << 2; 1477 return 0x1U << 2U;
1478} 1478}
1479static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void) 1479static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void)
1480{ 1480{
1481 return 0x00000001; 1481 return 0x00000001U;
1482} 1482}
1483static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void) 1483static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void)
1484{ 1484{
1485 return 0x4; 1485 return 0x4U;
1486} 1486}
1487static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void) 1487static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void)
1488{ 1488{
1489 return 0x00000001; 1489 return 0x00000001U;
1490} 1490}
1491static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void) 1491static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void)
1492{ 1492{
1493 return 0x4; 1493 return 0x4U;
1494} 1494}
1495static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void) 1495static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void)
1496{ 1496{
1497 return 0x1 << 3; 1497 return 0x1U << 3U;
1498} 1498}
1499static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void) 1499static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void)
1500{ 1500{
1501 return 0x00000001; 1501 return 0x00000001U;
1502} 1502}
1503static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void) 1503static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void)
1504{ 1504{
1505 return 0x8; 1505 return 0x8U;
1506} 1506}
1507static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void) 1507static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void)
1508{ 1508{
1509 return 0x00000001; 1509 return 0x00000001U;
1510} 1510}
1511static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void) 1511static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void)
1512{ 1512{
1513 return 0x8; 1513 return 0x8U;
1514} 1514}
1515static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void) 1515static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void)
1516{ 1516{
1517 return 0x1 << 4; 1517 return 0x1U << 4U;
1518} 1518}
1519static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void) 1519static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void)
1520{ 1520{
1521 return 0x00000001; 1521 return 0x00000001U;
1522} 1522}
1523static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void) 1523static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void)
1524{ 1524{
1525 return 0x10; 1525 return 0x10U;
1526} 1526}
1527static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void) 1527static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void)
1528{ 1528{
1529 return 0x00000001; 1529 return 0x00000001U;
1530} 1530}
1531static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void) 1531static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void)
1532{ 1532{
1533 return 0x10; 1533 return 0x10U;
1534} 1534}
1535static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void) 1535static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void)
1536{ 1536{
1537 return 0x1 << 5; 1537 return 0x1U << 5U;
1538} 1538}
1539static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void) 1539static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void)
1540{ 1540{
1541 return 0x00000001; 1541 return 0x00000001U;
1542} 1542}
1543static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void) 1543static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void)
1544{ 1544{
1545 return 0x20; 1545 return 0x20U;
1546} 1546}
1547static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void) 1547static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void)
1548{ 1548{
1549 return 0x00000001; 1549 return 0x00000001U;
1550} 1550}
1551static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void) 1551static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void)
1552{ 1552{
1553 return 0x20; 1553 return 0x20U;
1554} 1554}
1555static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void) 1555static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void)
1556{ 1556{
1557 return 0x1 << 6; 1557 return 0x1U << 6U;
1558} 1558}
1559static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void) 1559static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void)
1560{ 1560{
1561 return 0x00000001; 1561 return 0x00000001U;
1562} 1562}
1563static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void) 1563static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void)
1564{ 1564{
1565 return 0x40; 1565 return 0x40U;
1566} 1566}
1567static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void) 1567static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void)
1568{ 1568{
1569 return 0x00000001; 1569 return 0x00000001U;
1570} 1570}
1571static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void) 1571static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void)
1572{ 1572{
1573 return 0x40; 1573 return 0x40U;
1574} 1574}
1575static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void) 1575static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void)
1576{ 1576{
1577 return 0x1 << 7; 1577 return 0x1U << 7U;
1578} 1578}
1579static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void) 1579static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void)
1580{ 1580{
1581 return 0x00000001; 1581 return 0x00000001U;
1582} 1582}
1583static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void) 1583static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void)
1584{ 1584{
1585 return 0x80; 1585 return 0x80U;
1586} 1586}
1587static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void) 1587static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void)
1588{ 1588{
1589 return 0x00000001; 1589 return 0x00000001U;
1590} 1590}
1591static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void) 1591static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void)
1592{ 1592{
1593 return 0x80; 1593 return 0x80U;
1594} 1594}
1595static inline u32 fb_mmu_fault_status_replayable_m(void) 1595static inline u32 fb_mmu_fault_status_replayable_m(void)
1596{ 1596{
1597 return 0x1 << 8; 1597 return 0x1U << 8U;
1598} 1598}
1599static inline u32 fb_mmu_fault_status_replayable_set_v(void) 1599static inline u32 fb_mmu_fault_status_replayable_set_v(void)
1600{ 1600{
1601 return 0x00000001; 1601 return 0x00000001U;
1602} 1602}
1603static inline u32 fb_mmu_fault_status_replayable_set_f(void) 1603static inline u32 fb_mmu_fault_status_replayable_set_f(void)
1604{ 1604{
1605 return 0x100; 1605 return 0x100U;
1606} 1606}
1607static inline u32 fb_mmu_fault_status_replayable_reset_f(void) 1607static inline u32 fb_mmu_fault_status_replayable_reset_f(void)
1608{ 1608{
1609 return 0x0; 1609 return 0x0U;
1610} 1610}
1611static inline u32 fb_mmu_fault_status_non_replayable_m(void) 1611static inline u32 fb_mmu_fault_status_non_replayable_m(void)
1612{ 1612{
1613 return 0x1 << 9; 1613 return 0x1U << 9U;
1614} 1614}
1615static inline u32 fb_mmu_fault_status_non_replayable_set_v(void) 1615static inline u32 fb_mmu_fault_status_non_replayable_set_v(void)
1616{ 1616{
1617 return 0x00000001; 1617 return 0x00000001U;
1618} 1618}
1619static inline u32 fb_mmu_fault_status_non_replayable_set_f(void) 1619static inline u32 fb_mmu_fault_status_non_replayable_set_f(void)
1620{ 1620{
1621 return 0x200; 1621 return 0x200U;
1622} 1622}
1623static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void) 1623static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void)
1624{ 1624{
1625 return 0x0; 1625 return 0x0U;
1626} 1626}
1627static inline u32 fb_mmu_fault_status_replayable_error_m(void) 1627static inline u32 fb_mmu_fault_status_replayable_error_m(void)
1628{ 1628{
1629 return 0x1 << 10; 1629 return 0x1U << 10U;
1630} 1630}
1631static inline u32 fb_mmu_fault_status_replayable_error_set_v(void) 1631static inline u32 fb_mmu_fault_status_replayable_error_set_v(void)
1632{ 1632{
1633 return 0x00000001; 1633 return 0x00000001U;
1634} 1634}
1635static inline u32 fb_mmu_fault_status_replayable_error_set_f(void) 1635static inline u32 fb_mmu_fault_status_replayable_error_set_f(void)
1636{ 1636{
1637 return 0x400; 1637 return 0x400U;
1638} 1638}
1639static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void) 1639static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void)
1640{ 1640{
1641 return 0x0; 1641 return 0x0U;
1642} 1642}
1643static inline u32 fb_mmu_fault_status_non_replayable_error_m(void) 1643static inline u32 fb_mmu_fault_status_non_replayable_error_m(void)
1644{ 1644{
1645 return 0x1 << 11; 1645 return 0x1U << 11U;
1646} 1646}
1647static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void) 1647static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void)
1648{ 1648{
1649 return 0x00000001; 1649 return 0x00000001U;
1650} 1650}
1651static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void) 1651static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void)
1652{ 1652{
1653 return 0x800; 1653 return 0x800U;
1654} 1654}
1655static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void) 1655static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void)
1656{ 1656{
1657 return 0x0; 1657 return 0x0U;
1658} 1658}
1659static inline u32 fb_mmu_fault_status_replayable_overflow_m(void) 1659static inline u32 fb_mmu_fault_status_replayable_overflow_m(void)
1660{ 1660{
1661 return 0x1 << 12; 1661 return 0x1U << 12U;
1662} 1662}
1663static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void) 1663static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void)
1664{ 1664{
1665 return 0x00000001; 1665 return 0x00000001U;
1666} 1666}
1667static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void) 1667static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void)
1668{ 1668{
1669 return 0x1000; 1669 return 0x1000U;
1670} 1670}
1671static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void) 1671static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void)
1672{ 1672{
1673 return 0x0; 1673 return 0x0U;
1674} 1674}
1675static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void) 1675static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void)
1676{ 1676{
1677 return 0x1 << 13; 1677 return 0x1U << 13U;
1678} 1678}
1679static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void) 1679static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void)
1680{ 1680{
1681 return 0x00000001; 1681 return 0x00000001U;
1682} 1682}
1683static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void) 1683static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void)
1684{ 1684{
1685 return 0x2000; 1685 return 0x2000U;
1686} 1686}
1687static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void) 1687static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void)
1688{ 1688{
1689 return 0x0; 1689 return 0x0U;
1690} 1690}
1691static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void) 1691static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void)
1692{ 1692{
1693 return 0x1 << 14; 1693 return 0x1U << 14U;
1694} 1694}
1695static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void) 1695static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void)
1696{ 1696{
1697 return 0x00000001; 1697 return 0x00000001U;
1698} 1698}
1699static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void) 1699static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void)
1700{ 1700{
1701 return 0x4000; 1701 return 0x4000U;
1702} 1702}
1703static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void) 1703static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void)
1704{ 1704{
1705 return 0x1 << 15; 1705 return 0x1U << 15U;
1706} 1706}
1707static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void) 1707static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void)
1708{ 1708{
1709 return 0x00000001; 1709 return 0x00000001U;
1710} 1710}
1711static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void) 1711static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void)
1712{ 1712{
1713 return 0x8000; 1713 return 0x8000U;
1714} 1714}
1715static inline u32 fb_mmu_fault_status_busy_m(void) 1715static inline u32 fb_mmu_fault_status_busy_m(void)
1716{ 1716{
1717 return 0x1 << 30; 1717 return 0x1U << 30U;
1718} 1718}
1719static inline u32 fb_mmu_fault_status_busy_true_v(void) 1719static inline u32 fb_mmu_fault_status_busy_true_v(void)
1720{ 1720{
1721 return 0x00000001; 1721 return 0x00000001U;
1722} 1722}
1723static inline u32 fb_mmu_fault_status_busy_true_f(void) 1723static inline u32 fb_mmu_fault_status_busy_true_f(void)
1724{ 1724{
1725 return 0x40000000; 1725 return 0x40000000U;
1726} 1726}
1727static inline u32 fb_mmu_fault_status_valid_m(void) 1727static inline u32 fb_mmu_fault_status_valid_m(void)
1728{ 1728{
1729 return 0x1 << 31; 1729 return 0x1U << 31U;
1730} 1730}
1731static inline u32 fb_mmu_fault_status_valid_set_v(void) 1731static inline u32 fb_mmu_fault_status_valid_set_v(void)
1732{ 1732{
1733 return 0x00000001; 1733 return 0x00000001U;
1734} 1734}
1735static inline u32 fb_mmu_fault_status_valid_set_f(void) 1735static inline u32 fb_mmu_fault_status_valid_set_f(void)
1736{ 1736{
1737 return 0x80000000; 1737 return 0x80000000U;
1738} 1738}
1739static inline u32 fb_mmu_fault_status_valid_clear_v(void) 1739static inline u32 fb_mmu_fault_status_valid_clear_v(void)
1740{ 1740{
1741 return 0x00000001; 1741 return 0x00000001U;
1742} 1742}
1743static inline u32 fb_mmu_fault_status_valid_clear_f(void) 1743static inline u32 fb_mmu_fault_status_valid_clear_f(void)
1744{ 1744{
1745 return 0x80000000; 1745 return 0x80000000U;
1746} 1746}
1747static inline u32 fb_mmu_num_active_ltcs_r(void) 1747static inline u32 fb_mmu_num_active_ltcs_r(void)
1748{ 1748{
1749 return 0x00100ec0; 1749 return 0x00100ec0U;
1750} 1750}
1751static inline u32 fb_mmu_num_active_ltcs_count_f(u32 v) 1751static inline u32 fb_mmu_num_active_ltcs_count_f(u32 v)
1752{ 1752{
1753 return (v & 0x1f) << 0; 1753 return (v & 0x1fU) << 0U;
1754} 1754}
1755static inline u32 fb_mmu_num_active_ltcs_count_v(u32 r) 1755static inline u32 fb_mmu_num_active_ltcs_count_v(u32 r)
1756{ 1756{
1757 return (r >> 0) & 0x1f; 1757 return (r >> 0U) & 0x1fU;
1758} 1758}
1759static inline u32 fb_mmu_cbc_base_r(void) 1759static inline u32 fb_mmu_cbc_base_r(void)
1760{ 1760{
1761 return 0x00100ec4; 1761 return 0x00100ec4U;
1762} 1762}
1763static inline u32 fb_mmu_cbc_base_address_f(u32 v) 1763static inline u32 fb_mmu_cbc_base_address_f(u32 v)
1764{ 1764{
1765 return (v & 0x3ffffff) << 0; 1765 return (v & 0x3ffffffU) << 0U;
1766} 1766}
1767static inline u32 fb_mmu_cbc_base_address_v(u32 r) 1767static inline u32 fb_mmu_cbc_base_address_v(u32 r)
1768{ 1768{
1769 return (r >> 0) & 0x3ffffff; 1769 return (r >> 0U) & 0x3ffffffU;
1770} 1770}
1771static inline u32 fb_mmu_cbc_base_address_alignment_shift_v(void) 1771static inline u32 fb_mmu_cbc_base_address_alignment_shift_v(void)
1772{ 1772{
1773 return 0x0000000b; 1773 return 0x0000000bU;
1774} 1774}
1775static inline u32 fb_mmu_cbc_top_r(void) 1775static inline u32 fb_mmu_cbc_top_r(void)
1776{ 1776{
1777 return 0x00100ec8; 1777 return 0x00100ec8U;
1778} 1778}
1779static inline u32 fb_mmu_cbc_top_size_f(u32 v) 1779static inline u32 fb_mmu_cbc_top_size_f(u32 v)
1780{ 1780{
1781 return (v & 0x7fff) << 0; 1781 return (v & 0x7fffU) << 0U;
1782} 1782}
1783static inline u32 fb_mmu_cbc_top_size_v(u32 r) 1783static inline u32 fb_mmu_cbc_top_size_v(u32 r)
1784{ 1784{
1785 return (r >> 0) & 0x7fff; 1785 return (r >> 0U) & 0x7fffU;
1786} 1786}
1787static inline u32 fb_mmu_cbc_top_size_alignment_shift_v(void) 1787static inline u32 fb_mmu_cbc_top_size_alignment_shift_v(void)
1788{ 1788{
1789 return 0x0000000b; 1789 return 0x0000000bU;
1790} 1790}
1791static inline u32 fb_mmu_cbc_max_r(void) 1791static inline u32 fb_mmu_cbc_max_r(void)
1792{ 1792{
1793 return 0x00100ecc; 1793 return 0x00100eccU;
1794} 1794}
1795static inline u32 fb_mmu_cbc_max_comptagline_f(u32 v) 1795static inline u32 fb_mmu_cbc_max_comptagline_f(u32 v)
1796{ 1796{
1797 return (v & 0xffffff) << 0; 1797 return (v & 0xffffffU) << 0U;
1798} 1798}
1799static inline u32 fb_mmu_cbc_max_comptagline_v(u32 r) 1799static inline u32 fb_mmu_cbc_max_comptagline_v(u32 r)
1800{ 1800{
1801 return (r >> 0) & 0xffffff; 1801 return (r >> 0U) & 0xffffffU;
1802} 1802}
1803static inline u32 fb_mmu_cbc_max_safe_f(u32 v) 1803static inline u32 fb_mmu_cbc_max_safe_f(u32 v)
1804{ 1804{
1805 return (v & 0x1) << 30; 1805 return (v & 0x1U) << 30U;
1806} 1806}
1807static inline u32 fb_mmu_cbc_max_safe_true_v(void) 1807static inline u32 fb_mmu_cbc_max_safe_true_v(void)
1808{ 1808{
1809 return 0x00000001; 1809 return 0x00000001U;
1810} 1810}
1811static inline u32 fb_mmu_cbc_max_safe_false_v(void) 1811static inline u32 fb_mmu_cbc_max_safe_false_v(void)
1812{ 1812{
1813 return 0x00000000; 1813 return 0x00000000U;
1814} 1814}
1815static inline u32 fb_mmu_cbc_max_unsafe_fault_f(u32 v) 1815static inline u32 fb_mmu_cbc_max_unsafe_fault_f(u32 v)
1816{ 1816{
1817 return (v & 0x1) << 31; 1817 return (v & 0x1U) << 31U;
1818} 1818}
1819static inline u32 fb_mmu_cbc_max_unsafe_fault_enabled_v(void) 1819static inline u32 fb_mmu_cbc_max_unsafe_fault_enabled_v(void)
1820{ 1820{
1821 return 0x00000000; 1821 return 0x00000000U;
1822} 1822}
1823static inline u32 fb_mmu_cbc_max_unsafe_fault_disabled_v(void) 1823static inline u32 fb_mmu_cbc_max_unsafe_fault_disabled_v(void)
1824{ 1824{
1825 return 0x00000001; 1825 return 0x00000001U;
1826} 1826}
1827#endif 1827#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h
index 0d85a486..59cc7a1d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h
@@ -58,630 +58,630 @@
58 58
59static inline u32 fifo_bar1_base_r(void) 59static inline u32 fifo_bar1_base_r(void)
60{ 60{
61 return 0x00002254; 61 return 0x00002254U;
62} 62}
63static inline u32 fifo_bar1_base_ptr_f(u32 v) 63static inline u32 fifo_bar1_base_ptr_f(u32 v)
64{ 64{
65 return (v & 0xfffffff) << 0; 65 return (v & 0xfffffffU) << 0U;
66} 66}
67static inline u32 fifo_bar1_base_ptr_align_shift_v(void) 67static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
68{ 68{
69 return 0x0000000c; 69 return 0x0000000cU;
70} 70}
71static inline u32 fifo_bar1_base_valid_false_f(void) 71static inline u32 fifo_bar1_base_valid_false_f(void)
72{ 72{
73 return 0x0; 73 return 0x0U;
74} 74}
75static inline u32 fifo_bar1_base_valid_true_f(void) 75static inline u32 fifo_bar1_base_valid_true_f(void)
76{ 76{
77 return 0x10000000; 77 return 0x10000000U;
78} 78}
79static inline u32 fifo_userd_writeback_r(void) 79static inline u32 fifo_userd_writeback_r(void)
80{ 80{
81 return 0x0000225c; 81 return 0x0000225cU;
82} 82}
83static inline u32 fifo_userd_writeback_timer_f(u32 v) 83static inline u32 fifo_userd_writeback_timer_f(u32 v)
84{ 84{
85 return (v & 0xff) << 0; 85 return (v & 0xffU) << 0U;
86} 86}
87static inline u32 fifo_userd_writeback_timer_disabled_v(void) 87static inline u32 fifo_userd_writeback_timer_disabled_v(void)
88{ 88{
89 return 0x00000000; 89 return 0x00000000U;
90} 90}
91static inline u32 fifo_userd_writeback_timer_shorter_v(void) 91static inline u32 fifo_userd_writeback_timer_shorter_v(void)
92{ 92{
93 return 0x00000003; 93 return 0x00000003U;
94} 94}
95static inline u32 fifo_userd_writeback_timer_100us_v(void) 95static inline u32 fifo_userd_writeback_timer_100us_v(void)
96{ 96{
97 return 0x00000064; 97 return 0x00000064U;
98} 98}
99static inline u32 fifo_userd_writeback_timescale_f(u32 v) 99static inline u32 fifo_userd_writeback_timescale_f(u32 v)
100{ 100{
101 return (v & 0xf) << 12; 101 return (v & 0xfU) << 12U;
102} 102}
103static inline u32 fifo_userd_writeback_timescale_0_v(void) 103static inline u32 fifo_userd_writeback_timescale_0_v(void)
104{ 104{
105 return 0x00000000; 105 return 0x00000000U;
106} 106}
107static inline u32 fifo_runlist_base_r(void) 107static inline u32 fifo_runlist_base_r(void)
108{ 108{
109 return 0x00002270; 109 return 0x00002270U;
110} 110}
111static inline u32 fifo_runlist_base_ptr_f(u32 v) 111static inline u32 fifo_runlist_base_ptr_f(u32 v)
112{ 112{
113 return (v & 0xfffffff) << 0; 113 return (v & 0xfffffffU) << 0U;
114} 114}
115static inline u32 fifo_runlist_base_target_vid_mem_f(void) 115static inline u32 fifo_runlist_base_target_vid_mem_f(void)
116{ 116{
117 return 0x0; 117 return 0x0U;
118} 118}
119static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) 119static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
120{ 120{
121 return 0x20000000; 121 return 0x20000000U;
122} 122}
123static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) 123static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
124{ 124{
125 return 0x30000000; 125 return 0x30000000U;
126} 126}
127static inline u32 fifo_runlist_r(void) 127static inline u32 fifo_runlist_r(void)
128{ 128{
129 return 0x00002274; 129 return 0x00002274U;
130} 130}
131static inline u32 fifo_runlist_engine_f(u32 v) 131static inline u32 fifo_runlist_engine_f(u32 v)
132{ 132{
133 return (v & 0xf) << 20; 133 return (v & 0xfU) << 20U;
134} 134}
135static inline u32 fifo_eng_runlist_base_r(u32 i) 135static inline u32 fifo_eng_runlist_base_r(u32 i)
136{ 136{
137 return 0x00002280 + i*8; 137 return 0x00002280U + i*8U;
138} 138}
139static inline u32 fifo_eng_runlist_base__size_1_v(void) 139static inline u32 fifo_eng_runlist_base__size_1_v(void)
140{ 140{
141 return 0x00000002; 141 return 0x00000002U;
142} 142}
143static inline u32 fifo_eng_runlist_r(u32 i) 143static inline u32 fifo_eng_runlist_r(u32 i)
144{ 144{
145 return 0x00002284 + i*8; 145 return 0x00002284U + i*8U;
146} 146}
147static inline u32 fifo_eng_runlist__size_1_v(void) 147static inline u32 fifo_eng_runlist__size_1_v(void)
148{ 148{
149 return 0x00000002; 149 return 0x00000002U;
150} 150}
151static inline u32 fifo_eng_runlist_length_f(u32 v) 151static inline u32 fifo_eng_runlist_length_f(u32 v)
152{ 152{
153 return (v & 0xffff) << 0; 153 return (v & 0xffffU) << 0U;
154} 154}
155static inline u32 fifo_eng_runlist_length_max_v(void) 155static inline u32 fifo_eng_runlist_length_max_v(void)
156{ 156{
157 return 0x0000ffff; 157 return 0x0000ffffU;
158} 158}
159static inline u32 fifo_eng_runlist_pending_true_f(void) 159static inline u32 fifo_eng_runlist_pending_true_f(void)
160{ 160{
161 return 0x100000; 161 return 0x100000U;
162} 162}
163static inline u32 fifo_pb_timeslice_r(u32 i) 163static inline u32 fifo_pb_timeslice_r(u32 i)
164{ 164{
165 return 0x00002350 + i*4; 165 return 0x00002350U + i*4U;
166} 166}
167static inline u32 fifo_pb_timeslice_timeout_16_f(void) 167static inline u32 fifo_pb_timeslice_timeout_16_f(void)
168{ 168{
169 return 0x10; 169 return 0x10U;
170} 170}
171static inline u32 fifo_pb_timeslice_timescale_0_f(void) 171static inline u32 fifo_pb_timeslice_timescale_0_f(void)
172{ 172{
173 return 0x0; 173 return 0x0U;
174} 174}
175static inline u32 fifo_pb_timeslice_enable_true_f(void) 175static inline u32 fifo_pb_timeslice_enable_true_f(void)
176{ 176{
177 return 0x10000000; 177 return 0x10000000U;
178} 178}
179static inline u32 fifo_pbdma_map_r(u32 i) 179static inline u32 fifo_pbdma_map_r(u32 i)
180{ 180{
181 return 0x00002390 + i*4; 181 return 0x00002390U + i*4U;
182} 182}
183static inline u32 fifo_intr_0_r(void) 183static inline u32 fifo_intr_0_r(void)
184{ 184{
185 return 0x00002100; 185 return 0x00002100U;
186} 186}
187static inline u32 fifo_intr_0_bind_error_pending_f(void) 187static inline u32 fifo_intr_0_bind_error_pending_f(void)
188{ 188{
189 return 0x1; 189 return 0x1U;
190} 190}
191static inline u32 fifo_intr_0_bind_error_reset_f(void) 191static inline u32 fifo_intr_0_bind_error_reset_f(void)
192{ 192{
193 return 0x1; 193 return 0x1U;
194} 194}
195static inline u32 fifo_intr_0_sched_error_pending_f(void) 195static inline u32 fifo_intr_0_sched_error_pending_f(void)
196{ 196{
197 return 0x100; 197 return 0x100U;
198} 198}
199static inline u32 fifo_intr_0_sched_error_reset_f(void) 199static inline u32 fifo_intr_0_sched_error_reset_f(void)
200{ 200{
201 return 0x100; 201 return 0x100U;
202} 202}
203static inline u32 fifo_intr_0_chsw_error_pending_f(void) 203static inline u32 fifo_intr_0_chsw_error_pending_f(void)
204{ 204{
205 return 0x10000; 205 return 0x10000U;
206} 206}
207static inline u32 fifo_intr_0_chsw_error_reset_f(void) 207static inline u32 fifo_intr_0_chsw_error_reset_f(void)
208{ 208{
209 return 0x10000; 209 return 0x10000U;
210} 210}
211static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) 211static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void)
212{ 212{
213 return 0x800000; 213 return 0x800000U;
214} 214}
215static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) 215static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void)
216{ 216{
217 return 0x800000; 217 return 0x800000U;
218} 218}
219static inline u32 fifo_intr_0_lb_error_pending_f(void) 219static inline u32 fifo_intr_0_lb_error_pending_f(void)
220{ 220{
221 return 0x1000000; 221 return 0x1000000U;
222} 222}
223static inline u32 fifo_intr_0_lb_error_reset_f(void) 223static inline u32 fifo_intr_0_lb_error_reset_f(void)
224{ 224{
225 return 0x1000000; 225 return 0x1000000U;
226} 226}
227static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) 227static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
228{ 228{
229 return 0x20000000; 229 return 0x20000000U;
230} 230}
231static inline u32 fifo_intr_0_runlist_event_pending_f(void) 231static inline u32 fifo_intr_0_runlist_event_pending_f(void)
232{ 232{
233 return 0x40000000; 233 return 0x40000000U;
234} 234}
235static inline u32 fifo_intr_0_channel_intr_pending_f(void) 235static inline u32 fifo_intr_0_channel_intr_pending_f(void)
236{ 236{
237 return 0x80000000; 237 return 0x80000000U;
238} 238}
239static inline u32 fifo_intr_0_ctxsw_timeout_pending_f(void) 239static inline u32 fifo_intr_0_ctxsw_timeout_pending_f(void)
240{ 240{
241 return 0x2; 241 return 0x2U;
242} 242}
243static inline u32 fifo_intr_en_0_r(void) 243static inline u32 fifo_intr_en_0_r(void)
244{ 244{
245 return 0x00002140; 245 return 0x00002140U;
246} 246}
247static inline u32 fifo_intr_en_0_sched_error_f(u32 v) 247static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
248{ 248{
249 return (v & 0x1) << 8; 249 return (v & 0x1U) << 8U;
250} 250}
251static inline u32 fifo_intr_en_0_sched_error_m(void) 251static inline u32 fifo_intr_en_0_sched_error_m(void)
252{ 252{
253 return 0x1 << 8; 253 return 0x1U << 8U;
254} 254}
255static inline u32 fifo_intr_en_0_ctxsw_timeout_pending_f(void) 255static inline u32 fifo_intr_en_0_ctxsw_timeout_pending_f(void)
256{ 256{
257 return 0x2; 257 return 0x2U;
258} 258}
259static inline u32 fifo_intr_en_1_r(void) 259static inline u32 fifo_intr_en_1_r(void)
260{ 260{
261 return 0x00002528; 261 return 0x00002528U;
262} 262}
263static inline u32 fifo_intr_bind_error_r(void) 263static inline u32 fifo_intr_bind_error_r(void)
264{ 264{
265 return 0x0000252c; 265 return 0x0000252cU;
266} 266}
267static inline u32 fifo_intr_sched_error_r(void) 267static inline u32 fifo_intr_sched_error_r(void)
268{ 268{
269 return 0x0000254c; 269 return 0x0000254cU;
270} 270}
271static inline u32 fifo_intr_sched_error_code_f(u32 v) 271static inline u32 fifo_intr_sched_error_code_f(u32 v)
272{ 272{
273 return (v & 0xff) << 0; 273 return (v & 0xffU) << 0U;
274} 274}
275static inline u32 fifo_intr_chsw_error_r(void) 275static inline u32 fifo_intr_chsw_error_r(void)
276{ 276{
277 return 0x0000256c; 277 return 0x0000256cU;
278} 278}
279static inline u32 fifo_intr_ctxsw_timeout_r(void) 279static inline u32 fifo_intr_ctxsw_timeout_r(void)
280{ 280{
281 return 0x00002a30; 281 return 0x00002a30U;
282} 282}
283static inline u32 fifo_intr_ctxsw_timeout_engine_f(u32 v, u32 i) 283static inline u32 fifo_intr_ctxsw_timeout_engine_f(u32 v, u32 i)
284{ 284{
285 return (v & 0x1) << (0 + i*1); 285 return (v & 0x1U) << (0U + i*1U);
286} 286}
287static inline u32 fifo_intr_ctxsw_timeout_engine_v(u32 r, u32 i) 287static inline u32 fifo_intr_ctxsw_timeout_engine_v(u32 r, u32 i)
288{ 288{
289 return (r >> (0 + i*1)) & 0x1; 289 return (r >> (0U + i*1U)) & 0x1U;
290} 290}
291static inline u32 fifo_intr_ctxsw_timeout_engine__size_1_v(void) 291static inline u32 fifo_intr_ctxsw_timeout_engine__size_1_v(void)
292{ 292{
293 return 0x00000020; 293 return 0x00000020U;
294} 294}
295static inline u32 fifo_intr_ctxsw_timeout_engine_pending_v(void) 295static inline u32 fifo_intr_ctxsw_timeout_engine_pending_v(void)
296{ 296{
297 return 0x00000001; 297 return 0x00000001U;
298} 298}
299static inline u32 fifo_intr_ctxsw_timeout_engine_pending_f(u32 i) 299static inline u32 fifo_intr_ctxsw_timeout_engine_pending_f(u32 i)
300{ 300{
301 return 0x1 << (0 + i*1); 301 return 0x1U << (0U + i*1U);
302} 302}
303static inline u32 fifo_intr_ctxsw_timeout_info_r(u32 i) 303static inline u32 fifo_intr_ctxsw_timeout_info_r(u32 i)
304{ 304{
305 return 0x00003200 + i*4; 305 return 0x00003200U + i*4U;
306} 306}
307static inline u32 fifo_intr_ctxsw_timeout_info__size_1_v(void) 307static inline u32 fifo_intr_ctxsw_timeout_info__size_1_v(void)
308{ 308{
309 return 0x00000004; 309 return 0x00000004U;
310} 310}
311static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_v(u32 r) 311static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_v(u32 r)
312{ 312{
313 return (r >> 14) & 0x3; 313 return (r >> 14U) & 0x3U;
314} 314}
315static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_load_v(void) 315static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_load_v(void)
316{ 316{
317 return 0x00000001; 317 return 0x00000001U;
318} 318}
319static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_save_v(void) 319static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_save_v(void)
320{ 320{
321 return 0x00000002; 321 return 0x00000002U;
322} 322}
323static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_switch_v(void) 323static inline u32 fifo_intr_ctxsw_timeout_info_ctxsw_state_switch_v(void)
324{ 324{
325 return 0x00000003; 325 return 0x00000003U;
326} 326}
327static inline u32 fifo_intr_ctxsw_timeout_info_prev_tsgid_v(u32 r) 327static inline u32 fifo_intr_ctxsw_timeout_info_prev_tsgid_v(u32 r)
328{ 328{
329 return (r >> 0) & 0x3fff; 329 return (r >> 0U) & 0x3fffU;
330} 330}
331static inline u32 fifo_intr_ctxsw_timeout_info_next_tsgid_v(u32 r) 331static inline u32 fifo_intr_ctxsw_timeout_info_next_tsgid_v(u32 r)
332{ 332{
333 return (r >> 16) & 0x3fff; 333 return (r >> 16U) & 0x3fffU;
334} 334}
335static inline u32 fifo_intr_ctxsw_timeout_info_status_v(u32 r) 335static inline u32 fifo_intr_ctxsw_timeout_info_status_v(u32 r)
336{ 336{
337 return (r >> 30) & 0x3; 337 return (r >> 30U) & 0x3U;
338} 338}
339static inline u32 fifo_intr_ctxsw_timeout_info_status_awaiting_ack_v(void) 339static inline u32 fifo_intr_ctxsw_timeout_info_status_awaiting_ack_v(void)
340{ 340{
341 return 0x00000000; 341 return 0x00000000U;
342} 342}
343static inline u32 fifo_intr_ctxsw_timeout_info_status_eng_was_reset_v(void) 343static inline u32 fifo_intr_ctxsw_timeout_info_status_eng_was_reset_v(void)
344{ 344{
345 return 0x00000001; 345 return 0x00000001U;
346} 346}
347static inline u32 fifo_intr_ctxsw_timeout_info_status_ack_received_v(void) 347static inline u32 fifo_intr_ctxsw_timeout_info_status_ack_received_v(void)
348{ 348{
349 return 0x00000002; 349 return 0x00000002U;
350} 350}
351static inline u32 fifo_intr_ctxsw_timeout_info_status_dropped_timeout_v(void) 351static inline u32 fifo_intr_ctxsw_timeout_info_status_dropped_timeout_v(void)
352{ 352{
353 return 0x00000003; 353 return 0x00000003U;
354} 354}
355static inline u32 fifo_intr_pbdma_id_r(void) 355static inline u32 fifo_intr_pbdma_id_r(void)
356{ 356{
357 return 0x000025a0; 357 return 0x000025a0U;
358} 358}
359static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) 359static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
360{ 360{
361 return (v & 0x1) << (0 + i*1); 361 return (v & 0x1U) << (0U + i*1U);
362} 362}
363static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) 363static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
364{ 364{
365 return (r >> (0 + i*1)) & 0x1; 365 return (r >> (0U + i*1U)) & 0x1U;
366} 366}
367static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) 367static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
368{ 368{
369 return 0x00000003; 369 return 0x00000003U;
370} 370}
371static inline u32 fifo_intr_runlist_r(void) 371static inline u32 fifo_intr_runlist_r(void)
372{ 372{
373 return 0x00002a00; 373 return 0x00002a00U;
374} 374}
375static inline u32 fifo_fb_timeout_r(void) 375static inline u32 fifo_fb_timeout_r(void)
376{ 376{
377 return 0x00002a04; 377 return 0x00002a04U;
378} 378}
379static inline u32 fifo_fb_timeout_period_m(void) 379static inline u32 fifo_fb_timeout_period_m(void)
380{ 380{
381 return 0x3fffffff << 0; 381 return 0x3fffffffU << 0U;
382} 382}
383static inline u32 fifo_fb_timeout_period_max_f(void) 383static inline u32 fifo_fb_timeout_period_max_f(void)
384{ 384{
385 return 0x3fffffff; 385 return 0x3fffffffU;
386} 386}
387static inline u32 fifo_fb_timeout_period_init_f(void) 387static inline u32 fifo_fb_timeout_period_init_f(void)
388{ 388{
389 return 0x3c00; 389 return 0x3c00U;
390} 390}
391static inline u32 fifo_fb_timeout_detection_m(void) 391static inline u32 fifo_fb_timeout_detection_m(void)
392{ 392{
393 return 0x1 << 31; 393 return 0x1U << 31U;
394} 394}
395static inline u32 fifo_fb_timeout_detection_enabled_f(void) 395static inline u32 fifo_fb_timeout_detection_enabled_f(void)
396{ 396{
397 return 0x80000000; 397 return 0x80000000U;
398} 398}
399static inline u32 fifo_fb_timeout_detection_disabled_f(void) 399static inline u32 fifo_fb_timeout_detection_disabled_f(void)
400{ 400{
401 return 0x0; 401 return 0x0U;
402} 402}
403static inline u32 fifo_sched_disable_r(void) 403static inline u32 fifo_sched_disable_r(void)
404{ 404{
405 return 0x00002630; 405 return 0x00002630U;
406} 406}
407static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) 407static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
408{ 408{
409 return (v & 0x1) << (0 + i*1); 409 return (v & 0x1U) << (0U + i*1U);
410} 410}
411static inline u32 fifo_sched_disable_runlist_m(u32 i) 411static inline u32 fifo_sched_disable_runlist_m(u32 i)
412{ 412{
413 return 0x1 << (0 + i*1); 413 return 0x1U << (0U + i*1U);
414} 414}
415static inline u32 fifo_sched_disable_true_v(void) 415static inline u32 fifo_sched_disable_true_v(void)
416{ 416{
417 return 0x00000001; 417 return 0x00000001U;
418} 418}
419static inline u32 fifo_runlist_preempt_r(void) 419static inline u32 fifo_runlist_preempt_r(void)
420{ 420{
421 return 0x00002638; 421 return 0x00002638U;
422} 422}
423static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i) 423static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i)
424{ 424{
425 return (v & 0x1) << (0 + i*1); 425 return (v & 0x1U) << (0U + i*1U);
426} 426}
427static inline u32 fifo_runlist_preempt_runlist_m(u32 i) 427static inline u32 fifo_runlist_preempt_runlist_m(u32 i)
428{ 428{
429 return 0x1 << (0 + i*1); 429 return 0x1U << (0U + i*1U);
430} 430}
431static inline u32 fifo_runlist_preempt_runlist_pending_v(void) 431static inline u32 fifo_runlist_preempt_runlist_pending_v(void)
432{ 432{
433 return 0x00000001; 433 return 0x00000001U;
434} 434}
435static inline u32 fifo_preempt_r(void) 435static inline u32 fifo_preempt_r(void)
436{ 436{
437 return 0x00002634; 437 return 0x00002634U;
438} 438}
439static inline u32 fifo_preempt_pending_true_f(void) 439static inline u32 fifo_preempt_pending_true_f(void)
440{ 440{
441 return 0x100000; 441 return 0x100000U;
442} 442}
443static inline u32 fifo_preempt_type_channel_f(void) 443static inline u32 fifo_preempt_type_channel_f(void)
444{ 444{
445 return 0x0; 445 return 0x0U;
446} 446}
447static inline u32 fifo_preempt_type_tsg_f(void) 447static inline u32 fifo_preempt_type_tsg_f(void)
448{ 448{
449 return 0x1000000; 449 return 0x1000000U;
450} 450}
451static inline u32 fifo_preempt_chid_f(u32 v) 451static inline u32 fifo_preempt_chid_f(u32 v)
452{ 452{
453 return (v & 0xfff) << 0; 453 return (v & 0xfffU) << 0U;
454} 454}
455static inline u32 fifo_preempt_id_f(u32 v) 455static inline u32 fifo_preempt_id_f(u32 v)
456{ 456{
457 return (v & 0xfff) << 0; 457 return (v & 0xfffU) << 0U;
458} 458}
459static inline u32 fifo_engine_status_r(u32 i) 459static inline u32 fifo_engine_status_r(u32 i)
460{ 460{
461 return 0x00002640 + i*8; 461 return 0x00002640U + i*8U;
462} 462}
463static inline u32 fifo_engine_status__size_1_v(void) 463static inline u32 fifo_engine_status__size_1_v(void)
464{ 464{
465 return 0x00000004; 465 return 0x00000004U;
466} 466}
467static inline u32 fifo_engine_status_id_v(u32 r) 467static inline u32 fifo_engine_status_id_v(u32 r)
468{ 468{
469 return (r >> 0) & 0xfff; 469 return (r >> 0U) & 0xfffU;
470} 470}
471static inline u32 fifo_engine_status_id_type_v(u32 r) 471static inline u32 fifo_engine_status_id_type_v(u32 r)
472{ 472{
473 return (r >> 12) & 0x1; 473 return (r >> 12U) & 0x1U;
474} 474}
475static inline u32 fifo_engine_status_id_type_chid_v(void) 475static inline u32 fifo_engine_status_id_type_chid_v(void)
476{ 476{
477 return 0x00000000; 477 return 0x00000000U;
478} 478}
479static inline u32 fifo_engine_status_id_type_tsgid_v(void) 479static inline u32 fifo_engine_status_id_type_tsgid_v(void)
480{ 480{
481 return 0x00000001; 481 return 0x00000001U;
482} 482}
483static inline u32 fifo_engine_status_ctx_status_v(u32 r) 483static inline u32 fifo_engine_status_ctx_status_v(u32 r)
484{ 484{
485 return (r >> 13) & 0x7; 485 return (r >> 13U) & 0x7U;
486} 486}
487static inline u32 fifo_engine_status_ctx_status_valid_v(void) 487static inline u32 fifo_engine_status_ctx_status_valid_v(void)
488{ 488{
489 return 0x00000001; 489 return 0x00000001U;
490} 490}
491static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) 491static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
492{ 492{
493 return 0x00000005; 493 return 0x00000005U;
494} 494}
495static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) 495static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
496{ 496{
497 return 0x00000006; 497 return 0x00000006U;
498} 498}
499static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) 499static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
500{ 500{
501 return 0x00000007; 501 return 0x00000007U;
502} 502}
503static inline u32 fifo_engine_status_next_id_v(u32 r) 503static inline u32 fifo_engine_status_next_id_v(u32 r)
504{ 504{
505 return (r >> 16) & 0xfff; 505 return (r >> 16U) & 0xfffU;
506} 506}
507static inline u32 fifo_engine_status_next_id_type_v(u32 r) 507static inline u32 fifo_engine_status_next_id_type_v(u32 r)
508{ 508{
509 return (r >> 28) & 0x1; 509 return (r >> 28U) & 0x1U;
510} 510}
511static inline u32 fifo_engine_status_next_id_type_chid_v(void) 511static inline u32 fifo_engine_status_next_id_type_chid_v(void)
512{ 512{
513 return 0x00000000; 513 return 0x00000000U;
514} 514}
515static inline u32 fifo_engine_status_eng_reload_v(u32 r) 515static inline u32 fifo_engine_status_eng_reload_v(u32 r)
516{ 516{
517 return (r >> 29) & 0x1; 517 return (r >> 29U) & 0x1U;
518} 518}
519static inline u32 fifo_engine_status_faulted_v(u32 r) 519static inline u32 fifo_engine_status_faulted_v(u32 r)
520{ 520{
521 return (r >> 30) & 0x1; 521 return (r >> 30U) & 0x1U;
522} 522}
523static inline u32 fifo_engine_status_faulted_true_v(void) 523static inline u32 fifo_engine_status_faulted_true_v(void)
524{ 524{
525 return 0x00000001; 525 return 0x00000001U;
526} 526}
527static inline u32 fifo_engine_status_engine_v(u32 r) 527static inline u32 fifo_engine_status_engine_v(u32 r)
528{ 528{
529 return (r >> 31) & 0x1; 529 return (r >> 31U) & 0x1U;
530} 530}
531static inline u32 fifo_engine_status_engine_idle_v(void) 531static inline u32 fifo_engine_status_engine_idle_v(void)
532{ 532{
533 return 0x00000000; 533 return 0x00000000U;
534} 534}
535static inline u32 fifo_engine_status_engine_busy_v(void) 535static inline u32 fifo_engine_status_engine_busy_v(void)
536{ 536{
537 return 0x00000001; 537 return 0x00000001U;
538} 538}
539static inline u32 fifo_engine_status_ctxsw_v(u32 r) 539static inline u32 fifo_engine_status_ctxsw_v(u32 r)
540{ 540{
541 return (r >> 15) & 0x1; 541 return (r >> 15U) & 0x1U;
542} 542}
543static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) 543static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
544{ 544{
545 return 0x00000001; 545 return 0x00000001U;
546} 546}
547static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) 547static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
548{ 548{
549 return 0x8000; 549 return 0x8000U;
550} 550}
551static inline u32 fifo_eng_ctxsw_timeout_r(void) 551static inline u32 fifo_eng_ctxsw_timeout_r(void)
552{ 552{
553 return 0x00002a0c; 553 return 0x00002a0cU;
554} 554}
555static inline u32 fifo_eng_ctxsw_timeout_period_f(u32 v) 555static inline u32 fifo_eng_ctxsw_timeout_period_f(u32 v)
556{ 556{
557 return (v & 0x7fffffff) << 0; 557 return (v & 0x7fffffffU) << 0U;
558} 558}
559static inline u32 fifo_eng_ctxsw_timeout_period_m(void) 559static inline u32 fifo_eng_ctxsw_timeout_period_m(void)
560{ 560{
561 return 0x7fffffff << 0; 561 return 0x7fffffffU << 0U;
562} 562}
563static inline u32 fifo_eng_ctxsw_timeout_period_v(u32 r) 563static inline u32 fifo_eng_ctxsw_timeout_period_v(u32 r)
564{ 564{
565 return (r >> 0) & 0x7fffffff; 565 return (r >> 0U) & 0x7fffffffU;
566} 566}
567static inline u32 fifo_eng_ctxsw_timeout_period_init_f(void) 567static inline u32 fifo_eng_ctxsw_timeout_period_init_f(void)
568{ 568{
569 return 0x3fffff; 569 return 0x3fffffU;
570} 570}
571static inline u32 fifo_eng_ctxsw_timeout_period_max_f(void) 571static inline u32 fifo_eng_ctxsw_timeout_period_max_f(void)
572{ 572{
573 return 0x7fffffff; 573 return 0x7fffffffU;
574} 574}
575static inline u32 fifo_eng_ctxsw_timeout_detection_f(u32 v) 575static inline u32 fifo_eng_ctxsw_timeout_detection_f(u32 v)
576{ 576{
577 return (v & 0x1) << 31; 577 return (v & 0x1U) << 31U;
578} 578}
579static inline u32 fifo_eng_ctxsw_timeout_detection_m(void) 579static inline u32 fifo_eng_ctxsw_timeout_detection_m(void)
580{ 580{
581 return 0x1 << 31; 581 return 0x1U << 31U;
582} 582}
583static inline u32 fifo_eng_ctxsw_timeout_detection_enabled_f(void) 583static inline u32 fifo_eng_ctxsw_timeout_detection_enabled_f(void)
584{ 584{
585 return 0x80000000; 585 return 0x80000000U;
586} 586}
587static inline u32 fifo_eng_ctxsw_timeout_detection_disabled_f(void) 587static inline u32 fifo_eng_ctxsw_timeout_detection_disabled_f(void)
588{ 588{
589 return 0x0; 589 return 0x0U;
590} 590}
591static inline u32 fifo_pbdma_status_r(u32 i) 591static inline u32 fifo_pbdma_status_r(u32 i)
592{ 592{
593 return 0x00003080 + i*4; 593 return 0x00003080U + i*4U;
594} 594}
595static inline u32 fifo_pbdma_status__size_1_v(void) 595static inline u32 fifo_pbdma_status__size_1_v(void)
596{ 596{
597 return 0x00000003; 597 return 0x00000003U;
598} 598}
599static inline u32 fifo_pbdma_status_id_v(u32 r) 599static inline u32 fifo_pbdma_status_id_v(u32 r)
600{ 600{
601 return (r >> 0) & 0xfff; 601 return (r >> 0U) & 0xfffU;
602} 602}
603static inline u32 fifo_pbdma_status_id_type_v(u32 r) 603static inline u32 fifo_pbdma_status_id_type_v(u32 r)
604{ 604{
605 return (r >> 12) & 0x1; 605 return (r >> 12U) & 0x1U;
606} 606}
607static inline u32 fifo_pbdma_status_id_type_chid_v(void) 607static inline u32 fifo_pbdma_status_id_type_chid_v(void)
608{ 608{
609 return 0x00000000; 609 return 0x00000000U;
610} 610}
611static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) 611static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
612{ 612{
613 return 0x00000001; 613 return 0x00000001U;
614} 614}
615static inline u32 fifo_pbdma_status_chan_status_v(u32 r) 615static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
616{ 616{
617 return (r >> 13) & 0x7; 617 return (r >> 13U) & 0x7U;
618} 618}
619static inline u32 fifo_pbdma_status_chan_status_valid_v(void) 619static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
620{ 620{
621 return 0x00000001; 621 return 0x00000001U;
622} 622}
623static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) 623static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
624{ 624{
625 return 0x00000005; 625 return 0x00000005U;
626} 626}
627static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) 627static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
628{ 628{
629 return 0x00000006; 629 return 0x00000006U;
630} 630}
631static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) 631static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
632{ 632{
633 return 0x00000007; 633 return 0x00000007U;
634} 634}
635static inline u32 fifo_pbdma_status_next_id_v(u32 r) 635static inline u32 fifo_pbdma_status_next_id_v(u32 r)
636{ 636{
637 return (r >> 16) & 0xfff; 637 return (r >> 16U) & 0xfffU;
638} 638}
639static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) 639static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
640{ 640{
641 return (r >> 28) & 0x1; 641 return (r >> 28U) & 0x1U;
642} 642}
643static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) 643static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
644{ 644{
645 return 0x00000000; 645 return 0x00000000U;
646} 646}
647static inline u32 fifo_pbdma_status_chsw_v(u32 r) 647static inline u32 fifo_pbdma_status_chsw_v(u32 r)
648{ 648{
649 return (r >> 15) & 0x1; 649 return (r >> 15U) & 0x1U;
650} 650}
651static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) 651static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
652{ 652{
653 return 0x00000001; 653 return 0x00000001U;
654} 654}
655static inline u32 fifo_cfg0_r(void) 655static inline u32 fifo_cfg0_r(void)
656{ 656{
657 return 0x00002004; 657 return 0x00002004U;
658} 658}
659static inline u32 fifo_cfg0_num_pbdma_v(u32 r) 659static inline u32 fifo_cfg0_num_pbdma_v(u32 r)
660{ 660{
661 return (r >> 0) & 0xff; 661 return (r >> 0U) & 0xffU;
662} 662}
663static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) 663static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r)
664{ 664{
665 return (r >> 16) & 0xff; 665 return (r >> 16U) & 0xffU;
666} 666}
667static inline u32 fifo_fb_iface_r(void) 667static inline u32 fifo_fb_iface_r(void)
668{ 668{
669 return 0x000026f0; 669 return 0x000026f0U;
670} 670}
671static inline u32 fifo_fb_iface_control_v(u32 r) 671static inline u32 fifo_fb_iface_control_v(u32 r)
672{ 672{
673 return (r >> 0) & 0x1; 673 return (r >> 0U) & 0x1U;
674} 674}
675static inline u32 fifo_fb_iface_control_enable_f(void) 675static inline u32 fifo_fb_iface_control_enable_f(void)
676{ 676{
677 return 0x1; 677 return 0x1U;
678} 678}
679static inline u32 fifo_fb_iface_status_v(u32 r) 679static inline u32 fifo_fb_iface_status_v(u32 r)
680{ 680{
681 return (r >> 4) & 0x1; 681 return (r >> 4U) & 0x1U;
682} 682}
683static inline u32 fifo_fb_iface_status_enabled_f(void) 683static inline u32 fifo_fb_iface_status_enabled_f(void)
684{ 684{
685 return 0x10; 685 return 0x10U;
686} 686}
687#endif 687#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h
index b2938b32..45c01de0 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_flush_gv11b.h
@@ -58,130 +58,130 @@
58 58
59static inline u32 flush_l2_system_invalidate_r(void) 59static inline u32 flush_l2_system_invalidate_r(void)
60{ 60{
61 return 0x00070004; 61 return 0x00070004U;
62} 62}
63static inline u32 flush_l2_system_invalidate_pending_v(u32 r) 63static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
64{ 64{
65 return (r >> 0) & 0x1; 65 return (r >> 0U) & 0x1U;
66} 66}
67static inline u32 flush_l2_system_invalidate_pending_busy_v(void) 67static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
68{ 68{
69 return 0x00000001; 69 return 0x00000001U;
70} 70}
71static inline u32 flush_l2_system_invalidate_pending_busy_f(void) 71static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
72{ 72{
73 return 0x1; 73 return 0x1U;
74} 74}
75static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) 75static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
76{ 76{
77 return (r >> 1) & 0x1; 77 return (r >> 1U) & 0x1U;
78} 78}
79static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) 79static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
80{ 80{
81 return 0x00000001; 81 return 0x00000001U;
82} 82}
83static inline u32 flush_l2_flush_dirty_r(void) 83static inline u32 flush_l2_flush_dirty_r(void)
84{ 84{
85 return 0x00070010; 85 return 0x00070010U;
86} 86}
87static inline u32 flush_l2_flush_dirty_pending_v(u32 r) 87static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
88{ 88{
89 return (r >> 0) & 0x1; 89 return (r >> 0U) & 0x1U;
90} 90}
91static inline u32 flush_l2_flush_dirty_pending_empty_v(void) 91static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
92{ 92{
93 return 0x00000000; 93 return 0x00000000U;
94} 94}
95static inline u32 flush_l2_flush_dirty_pending_empty_f(void) 95static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
96{ 96{
97 return 0x0; 97 return 0x0U;
98} 98}
99static inline u32 flush_l2_flush_dirty_pending_busy_v(void) 99static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
100{ 100{
101 return 0x00000001; 101 return 0x00000001U;
102} 102}
103static inline u32 flush_l2_flush_dirty_pending_busy_f(void) 103static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
104{ 104{
105 return 0x1; 105 return 0x1U;
106} 106}
107static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) 107static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
108{ 108{
109 return (r >> 1) & 0x1; 109 return (r >> 1U) & 0x1U;
110} 110}
111static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) 111static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
112{ 112{
113 return 0x00000000; 113 return 0x00000000U;
114} 114}
115static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) 115static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
116{ 116{
117 return 0x0; 117 return 0x0U;
118} 118}
119static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) 119static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
120{ 120{
121 return 0x00000001; 121 return 0x00000001U;
122} 122}
123static inline u32 flush_l2_clean_comptags_r(void) 123static inline u32 flush_l2_clean_comptags_r(void)
124{ 124{
125 return 0x0007000c; 125 return 0x0007000cU;
126} 126}
127static inline u32 flush_l2_clean_comptags_pending_v(u32 r) 127static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
128{ 128{
129 return (r >> 0) & 0x1; 129 return (r >> 0U) & 0x1U;
130} 130}
131static inline u32 flush_l2_clean_comptags_pending_empty_v(void) 131static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
132{ 132{
133 return 0x00000000; 133 return 0x00000000U;
134} 134}
135static inline u32 flush_l2_clean_comptags_pending_empty_f(void) 135static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
136{ 136{
137 return 0x0; 137 return 0x0U;
138} 138}
139static inline u32 flush_l2_clean_comptags_pending_busy_v(void) 139static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
140{ 140{
141 return 0x00000001; 141 return 0x00000001U;
142} 142}
143static inline u32 flush_l2_clean_comptags_pending_busy_f(void) 143static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
144{ 144{
145 return 0x1; 145 return 0x1U;
146} 146}
147static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) 147static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
148{ 148{
149 return (r >> 1) & 0x1; 149 return (r >> 1U) & 0x1U;
150} 150}
151static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) 151static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
152{ 152{
153 return 0x00000000; 153 return 0x00000000U;
154} 154}
155static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) 155static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
156{ 156{
157 return 0x0; 157 return 0x0U;
158} 158}
159static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) 159static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
160{ 160{
161 return 0x00000001; 161 return 0x00000001U;
162} 162}
163static inline u32 flush_fb_flush_r(void) 163static inline u32 flush_fb_flush_r(void)
164{ 164{
165 return 0x00070000; 165 return 0x00070000U;
166} 166}
167static inline u32 flush_fb_flush_pending_v(u32 r) 167static inline u32 flush_fb_flush_pending_v(u32 r)
168{ 168{
169 return (r >> 0) & 0x1; 169 return (r >> 0U) & 0x1U;
170} 170}
171static inline u32 flush_fb_flush_pending_busy_v(void) 171static inline u32 flush_fb_flush_pending_busy_v(void)
172{ 172{
173 return 0x00000001; 173 return 0x00000001U;
174} 174}
175static inline u32 flush_fb_flush_pending_busy_f(void) 175static inline u32 flush_fb_flush_pending_busy_f(void)
176{ 176{
177 return 0x1; 177 return 0x1U;
178} 178}
179static inline u32 flush_fb_flush_outstanding_v(u32 r) 179static inline u32 flush_fb_flush_outstanding_v(u32 r)
180{ 180{
181 return (r >> 1) & 0x1; 181 return (r >> 1U) & 0x1U;
182} 182}
183static inline u32 flush_fb_flush_outstanding_true_v(void) 183static inline u32 flush_fb_flush_outstanding_true_v(void)
184{ 184{
185 return 0x00000001; 185 return 0x00000001U;
186} 186}
187#endif 187#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h
index 6bc0604b..f8d9b196 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h
@@ -58,94 +58,94 @@
58 58
59static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) 59static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
60{ 60{
61 return 0x00021c38 + i*4; 61 return 0x00021c38U + i*4U;
62} 62}
63static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) 63static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i)
64{ 64{
65 return 0x00021838 + i*4; 65 return 0x00021838U + i*4U;
66} 66}
67static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) 67static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void)
68{ 68{
69 return 0x00021944; 69 return 0x00021944U;
70} 70}
71static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) 71static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
72{ 72{
73 return (v & 0xff) << 0; 73 return (v & 0xffU) << 0U;
74} 74}
75static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) 75static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
76{ 76{
77 return 0xff << 0; 77 return 0xffU << 0U;
78} 78}
79static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) 79static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
80{ 80{
81 return (r >> 0) & 0xff; 81 return (r >> 0U) & 0xffU;
82} 82}
83static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) 83static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void)
84{ 84{
85 return 0x00021948; 85 return 0x00021948U;
86} 86}
87static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) 87static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
88{ 88{
89 return (v & 0x1) << 0; 89 return (v & 0x1U) << 0U;
90} 90}
91static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) 91static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
92{ 92{
93 return 0x1 << 0; 93 return 0x1U << 0U;
94} 94}
95static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) 95static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
96{ 96{
97 return (r >> 0) & 0x1; 97 return (r >> 0U) & 0x1U;
98} 98}
99static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) 99static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void)
100{ 100{
101 return 0x1; 101 return 0x1U;
102} 102}
103static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) 103static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void)
104{ 104{
105 return 0x0; 105 return 0x0U;
106} 106}
107static inline u32 fuse_status_opt_fbio_r(void) 107static inline u32 fuse_status_opt_fbio_r(void)
108{ 108{
109 return 0x00021c14; 109 return 0x00021c14U;
110} 110}
111static inline u32 fuse_status_opt_fbio_data_f(u32 v) 111static inline u32 fuse_status_opt_fbio_data_f(u32 v)
112{ 112{
113 return (v & 0xffff) << 0; 113 return (v & 0xffffU) << 0U;
114} 114}
115static inline u32 fuse_status_opt_fbio_data_m(void) 115static inline u32 fuse_status_opt_fbio_data_m(void)
116{ 116{
117 return 0xffff << 0; 117 return 0xffffU << 0U;
118} 118}
119static inline u32 fuse_status_opt_fbio_data_v(u32 r) 119static inline u32 fuse_status_opt_fbio_data_v(u32 r)
120{ 120{
121 return (r >> 0) & 0xffff; 121 return (r >> 0U) & 0xffffU;
122} 122}
123static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) 123static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i)
124{ 124{
125 return 0x00021d70 + i*4; 125 return 0x00021d70U + i*4U;
126} 126}
127static inline u32 fuse_status_opt_fbp_r(void) 127static inline u32 fuse_status_opt_fbp_r(void)
128{ 128{
129 return 0x00021d38; 129 return 0x00021d38U;
130} 130}
131static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) 131static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
132{ 132{
133 return (r >> (0 + i*1)) & 0x1; 133 return (r >> (0U + i*1U)) & 0x1U;
134} 134}
135static inline u32 fuse_opt_ecc_en_r(void) 135static inline u32 fuse_opt_ecc_en_r(void)
136{ 136{
137 return 0x00021228; 137 return 0x00021228U;
138} 138}
139static inline u32 fuse_opt_feature_fuses_override_disable_r(void) 139static inline u32 fuse_opt_feature_fuses_override_disable_r(void)
140{ 140{
141 return 0x000213f0; 141 return 0x000213f0U;
142} 142}
143static inline u32 fuse_opt_sec_debug_en_r(void) 143static inline u32 fuse_opt_sec_debug_en_r(void)
144{ 144{
145 return 0x00021218; 145 return 0x00021218U;
146} 146}
147static inline u32 fuse_opt_priv_sec_en_r(void) 147static inline u32 fuse_opt_priv_sec_en_r(void)
148{ 148{
149 return 0x00021434; 149 return 0x00021434U;
150} 150}
151#endif 151#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h
index d84610f3..c39cc2d8 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gmmu_gv11b.h
@@ -58,1434 +58,1434 @@
58 58
59static inline u32 gmmu_new_pde_is_pte_w(void) 59static inline u32 gmmu_new_pde_is_pte_w(void)
60{ 60{
61 return 0; 61 return 0U;
62} 62}
63static inline u32 gmmu_new_pde_is_pte_false_f(void) 63static inline u32 gmmu_new_pde_is_pte_false_f(void)
64{ 64{
65 return 0x0; 65 return 0x0U;
66} 66}
67static inline u32 gmmu_new_pde_aperture_w(void) 67static inline u32 gmmu_new_pde_aperture_w(void)
68{ 68{
69 return 0; 69 return 0U;
70} 70}
71static inline u32 gmmu_new_pde_aperture_invalid_f(void) 71static inline u32 gmmu_new_pde_aperture_invalid_f(void)
72{ 72{
73 return 0x0; 73 return 0x0U;
74} 74}
75static inline u32 gmmu_new_pde_aperture_video_memory_f(void) 75static inline u32 gmmu_new_pde_aperture_video_memory_f(void)
76{ 76{
77 return 0x2; 77 return 0x2U;
78} 78}
79static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void) 79static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void)
80{ 80{
81 return 0x4; 81 return 0x4U;
82} 82}
83static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void) 83static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void)
84{ 84{
85 return 0x6; 85 return 0x6U;
86} 86}
87static inline u32 gmmu_new_pde_address_sys_f(u32 v) 87static inline u32 gmmu_new_pde_address_sys_f(u32 v)
88{ 88{
89 return (v & 0xffffff) << 8; 89 return (v & 0xffffffU) << 8U;
90} 90}
91static inline u32 gmmu_new_pde_address_sys_w(void) 91static inline u32 gmmu_new_pde_address_sys_w(void)
92{ 92{
93 return 0; 93 return 0U;
94} 94}
95static inline u32 gmmu_new_pde_vol_w(void) 95static inline u32 gmmu_new_pde_vol_w(void)
96{ 96{
97 return 0; 97 return 0U;
98} 98}
99static inline u32 gmmu_new_pde_vol_true_f(void) 99static inline u32 gmmu_new_pde_vol_true_f(void)
100{ 100{
101 return 0x8; 101 return 0x8U;
102} 102}
103static inline u32 gmmu_new_pde_vol_false_f(void) 103static inline u32 gmmu_new_pde_vol_false_f(void)
104{ 104{
105 return 0x0; 105 return 0x0U;
106} 106}
107static inline u32 gmmu_new_pde_address_shift_v(void) 107static inline u32 gmmu_new_pde_address_shift_v(void)
108{ 108{
109 return 0x0000000c; 109 return 0x0000000cU;
110} 110}
111static inline u32 gmmu_new_pde__size_v(void) 111static inline u32 gmmu_new_pde__size_v(void)
112{ 112{
113 return 0x00000008; 113 return 0x00000008U;
114} 114}
115static inline u32 gmmu_new_dual_pde_is_pte_w(void) 115static inline u32 gmmu_new_dual_pde_is_pte_w(void)
116{ 116{
117 return 0; 117 return 0U;
118} 118}
119static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) 119static inline u32 gmmu_new_dual_pde_is_pte_false_f(void)
120{ 120{
121 return 0x0; 121 return 0x0U;
122} 122}
123static inline u32 gmmu_new_dual_pde_aperture_big_w(void) 123static inline u32 gmmu_new_dual_pde_aperture_big_w(void)
124{ 124{
125 return 0; 125 return 0U;
126} 126}
127static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) 127static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void)
128{ 128{
129 return 0x0; 129 return 0x0U;
130} 130}
131static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) 131static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void)
132{ 132{
133 return 0x2; 133 return 0x2U;
134} 134}
135static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void) 135static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void)
136{ 136{
137 return 0x4; 137 return 0x4U;
138} 138}
139static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void) 139static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void)
140{ 140{
141 return 0x6; 141 return 0x6U;
142} 142}
143static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) 143static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v)
144{ 144{
145 return (v & 0xfffffff) << 4; 145 return (v & 0xfffffffU) << 4U;
146} 146}
147static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) 147static inline u32 gmmu_new_dual_pde_address_big_sys_w(void)
148{ 148{
149 return 0; 149 return 0U;
150} 150}
151static inline u32 gmmu_new_dual_pde_aperture_small_w(void) 151static inline u32 gmmu_new_dual_pde_aperture_small_w(void)
152{ 152{
153 return 2; 153 return 2U;
154} 154}
155static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) 155static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void)
156{ 156{
157 return 0x0; 157 return 0x0U;
158} 158}
159static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) 159static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void)
160{ 160{
161 return 0x2; 161 return 0x2U;
162} 162}
163static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void) 163static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void)
164{ 164{
165 return 0x4; 165 return 0x4U;
166} 166}
167static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void) 167static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void)
168{ 168{
169 return 0x6; 169 return 0x6U;
170} 170}
171static inline u32 gmmu_new_dual_pde_vol_small_w(void) 171static inline u32 gmmu_new_dual_pde_vol_small_w(void)
172{ 172{
173 return 2; 173 return 2U;
174} 174}
175static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) 175static inline u32 gmmu_new_dual_pde_vol_small_true_f(void)
176{ 176{
177 return 0x8; 177 return 0x8U;
178} 178}
179static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) 179static inline u32 gmmu_new_dual_pde_vol_small_false_f(void)
180{ 180{
181 return 0x0; 181 return 0x0U;
182} 182}
183static inline u32 gmmu_new_dual_pde_vol_big_w(void) 183static inline u32 gmmu_new_dual_pde_vol_big_w(void)
184{ 184{
185 return 0; 185 return 0U;
186} 186}
187static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) 187static inline u32 gmmu_new_dual_pde_vol_big_true_f(void)
188{ 188{
189 return 0x8; 189 return 0x8U;
190} 190}
191static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) 191static inline u32 gmmu_new_dual_pde_vol_big_false_f(void)
192{ 192{
193 return 0x0; 193 return 0x0U;
194} 194}
195static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) 195static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v)
196{ 196{
197 return (v & 0xffffff) << 8; 197 return (v & 0xffffffU) << 8U;
198} 198}
199static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) 199static inline u32 gmmu_new_dual_pde_address_small_sys_w(void)
200{ 200{
201 return 2; 201 return 2U;
202} 202}
203static inline u32 gmmu_new_dual_pde_address_shift_v(void) 203static inline u32 gmmu_new_dual_pde_address_shift_v(void)
204{ 204{
205 return 0x0000000c; 205 return 0x0000000cU;
206} 206}
207static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) 207static inline u32 gmmu_new_dual_pde_address_big_shift_v(void)
208{ 208{
209 return 0x00000008; 209 return 0x00000008U;
210} 210}
211static inline u32 gmmu_new_dual_pde__size_v(void) 211static inline u32 gmmu_new_dual_pde__size_v(void)
212{ 212{
213 return 0x00000010; 213 return 0x00000010U;
214} 214}
215static inline u32 gmmu_new_pte__size_v(void) 215static inline u32 gmmu_new_pte__size_v(void)
216{ 216{
217 return 0x00000008; 217 return 0x00000008U;
218} 218}
219static inline u32 gmmu_new_pte_valid_w(void) 219static inline u32 gmmu_new_pte_valid_w(void)
220{ 220{
221 return 0; 221 return 0U;
222} 222}
223static inline u32 gmmu_new_pte_valid_true_f(void) 223static inline u32 gmmu_new_pte_valid_true_f(void)
224{ 224{
225 return 0x1; 225 return 0x1U;
226} 226}
227static inline u32 gmmu_new_pte_valid_false_f(void) 227static inline u32 gmmu_new_pte_valid_false_f(void)
228{ 228{
229 return 0x0; 229 return 0x0U;
230} 230}
231static inline u32 gmmu_new_pte_privilege_w(void) 231static inline u32 gmmu_new_pte_privilege_w(void)
232{ 232{
233 return 0; 233 return 0U;
234} 234}
235static inline u32 gmmu_new_pte_privilege_true_f(void) 235static inline u32 gmmu_new_pte_privilege_true_f(void)
236{ 236{
237 return 0x20; 237 return 0x20U;
238} 238}
239static inline u32 gmmu_new_pte_privilege_false_f(void) 239static inline u32 gmmu_new_pte_privilege_false_f(void)
240{ 240{
241 return 0x0; 241 return 0x0U;
242} 242}
243static inline u32 gmmu_new_pte_address_sys_f(u32 v) 243static inline u32 gmmu_new_pte_address_sys_f(u32 v)
244{ 244{
245 return (v & 0xffffff) << 8; 245 return (v & 0xffffffU) << 8U;
246} 246}
247static inline u32 gmmu_new_pte_address_sys_w(void) 247static inline u32 gmmu_new_pte_address_sys_w(void)
248{ 248{
249 return 0; 249 return 0U;
250} 250}
251static inline u32 gmmu_new_pte_address_vid_f(u32 v) 251static inline u32 gmmu_new_pte_address_vid_f(u32 v)
252{ 252{
253 return (v & 0xffffff) << 8; 253 return (v & 0xffffffU) << 8U;
254} 254}
255static inline u32 gmmu_new_pte_address_vid_w(void) 255static inline u32 gmmu_new_pte_address_vid_w(void)
256{ 256{
257 return 0; 257 return 0U;
258} 258}
259static inline u32 gmmu_new_pte_vol_w(void) 259static inline u32 gmmu_new_pte_vol_w(void)
260{ 260{
261 return 0; 261 return 0U;
262} 262}
263static inline u32 gmmu_new_pte_vol_true_f(void) 263static inline u32 gmmu_new_pte_vol_true_f(void)
264{ 264{
265 return 0x8; 265 return 0x8U;
266} 266}
267static inline u32 gmmu_new_pte_vol_false_f(void) 267static inline u32 gmmu_new_pte_vol_false_f(void)
268{ 268{
269 return 0x0; 269 return 0x0U;
270} 270}
271static inline u32 gmmu_new_pte_aperture_w(void) 271static inline u32 gmmu_new_pte_aperture_w(void)
272{ 272{
273 return 0; 273 return 0U;
274} 274}
275static inline u32 gmmu_new_pte_aperture_video_memory_f(void) 275static inline u32 gmmu_new_pte_aperture_video_memory_f(void)
276{ 276{
277 return 0x0; 277 return 0x0U;
278} 278}
279static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void) 279static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void)
280{ 280{
281 return 0x4; 281 return 0x4U;
282} 282}
283static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void) 283static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void)
284{ 284{
285 return 0x6; 285 return 0x6U;
286} 286}
287static inline u32 gmmu_new_pte_read_only_w(void) 287static inline u32 gmmu_new_pte_read_only_w(void)
288{ 288{
289 return 0; 289 return 0U;
290} 290}
291static inline u32 gmmu_new_pte_read_only_true_f(void) 291static inline u32 gmmu_new_pte_read_only_true_f(void)
292{ 292{
293 return 0x40; 293 return 0x40U;
294} 294}
295static inline u32 gmmu_new_pte_comptagline_f(u32 v) 295static inline u32 gmmu_new_pte_comptagline_f(u32 v)
296{ 296{
297 return (v & 0x3ffff) << 4; 297 return (v & 0x3ffffU) << 4U;
298} 298}
299static inline u32 gmmu_new_pte_comptagline_w(void) 299static inline u32 gmmu_new_pte_comptagline_w(void)
300{ 300{
301 return 1; 301 return 1U;
302} 302}
303static inline u32 gmmu_new_pte_kind_f(u32 v) 303static inline u32 gmmu_new_pte_kind_f(u32 v)
304{ 304{
305 return (v & 0xff) << 24; 305 return (v & 0xffU) << 24U;
306} 306}
307static inline u32 gmmu_new_pte_kind_w(void) 307static inline u32 gmmu_new_pte_kind_w(void)
308{ 308{
309 return 1; 309 return 1U;
310} 310}
311static inline u32 gmmu_new_pte_address_shift_v(void) 311static inline u32 gmmu_new_pte_address_shift_v(void)
312{ 312{
313 return 0x0000000c; 313 return 0x0000000cU;
314} 314}
315static inline u32 gmmu_pte_kind_f(u32 v) 315static inline u32 gmmu_pte_kind_f(u32 v)
316{ 316{
317 return (v & 0xff) << 4; 317 return (v & 0xffU) << 4U;
318} 318}
319static inline u32 gmmu_pte_kind_w(void) 319static inline u32 gmmu_pte_kind_w(void)
320{ 320{
321 return 1; 321 return 1U;
322} 322}
323static inline u32 gmmu_pte_kind_invalid_v(void) 323static inline u32 gmmu_pte_kind_invalid_v(void)
324{ 324{
325 return 0x000000ff; 325 return 0x000000ffU;
326} 326}
327static inline u32 gmmu_pte_kind_pitch_v(void) 327static inline u32 gmmu_pte_kind_pitch_v(void)
328{ 328{
329 return 0x00000000; 329 return 0x00000000U;
330} 330}
331static inline u32 gmmu_pte_kind_z16_v(void) 331static inline u32 gmmu_pte_kind_z16_v(void)
332{ 332{
333 return 0x00000001; 333 return 0x00000001U;
334} 334}
335static inline u32 gmmu_pte_kind_z16_2c_v(void) 335static inline u32 gmmu_pte_kind_z16_2c_v(void)
336{ 336{
337 return 0x00000002; 337 return 0x00000002U;
338} 338}
339static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) 339static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void)
340{ 340{
341 return 0x00000003; 341 return 0x00000003U;
342} 342}
343static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) 343static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void)
344{ 344{
345 return 0x00000004; 345 return 0x00000004U;
346} 346}
347static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) 347static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void)
348{ 348{
349 return 0x00000005; 349 return 0x00000005U;
350} 350}
351static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) 351static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void)
352{ 352{
353 return 0x00000006; 353 return 0x00000006U;
354} 354}
355static inline u32 gmmu_pte_kind_z16_2z_v(void) 355static inline u32 gmmu_pte_kind_z16_2z_v(void)
356{ 356{
357 return 0x00000007; 357 return 0x00000007U;
358} 358}
359static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) 359static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void)
360{ 360{
361 return 0x00000008; 361 return 0x00000008U;
362} 362}
363static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) 363static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void)
364{ 364{
365 return 0x00000009; 365 return 0x00000009U;
366} 366}
367static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) 367static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void)
368{ 368{
369 return 0x0000000a; 369 return 0x0000000aU;
370} 370}
371static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) 371static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void)
372{ 372{
373 return 0x0000000b; 373 return 0x0000000bU;
374} 374}
375static inline u32 gmmu_pte_kind_z16_2cz_v(void) 375static inline u32 gmmu_pte_kind_z16_2cz_v(void)
376{ 376{
377 return 0x00000036; 377 return 0x00000036U;
378} 378}
379static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void) 379static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void)
380{ 380{
381 return 0x00000037; 381 return 0x00000037U;
382} 382}
383static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void) 383static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void)
384{ 384{
385 return 0x00000038; 385 return 0x00000038U;
386} 386}
387static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void) 387static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void)
388{ 388{
389 return 0x00000039; 389 return 0x00000039U;
390} 390}
391static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) 391static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void)
392{ 392{
393 return 0x0000005f; 393 return 0x0000005fU;
394} 394}
395static inline u32 gmmu_pte_kind_s8z24_v(void) 395static inline u32 gmmu_pte_kind_s8z24_v(void)
396{ 396{
397 return 0x00000011; 397 return 0x00000011U;
398} 398}
399static inline u32 gmmu_pte_kind_s8z24_1z_v(void) 399static inline u32 gmmu_pte_kind_s8z24_1z_v(void)
400{ 400{
401 return 0x00000012; 401 return 0x00000012U;
402} 402}
403static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) 403static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void)
404{ 404{
405 return 0x00000013; 405 return 0x00000013U;
406} 406}
407static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) 407static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void)
408{ 408{
409 return 0x00000014; 409 return 0x00000014U;
410} 410}
411static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) 411static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void)
412{ 412{
413 return 0x00000015; 413 return 0x00000015U;
414} 414}
415static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) 415static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void)
416{ 416{
417 return 0x00000016; 417 return 0x00000016U;
418} 418}
419static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) 419static inline u32 gmmu_pte_kind_s8z24_2cz_v(void)
420{ 420{
421 return 0x00000017; 421 return 0x00000017U;
422} 422}
423static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) 423static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void)
424{ 424{
425 return 0x00000018; 425 return 0x00000018U;
426} 426}
427static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) 427static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void)
428{ 428{
429 return 0x00000019; 429 return 0x00000019U;
430} 430}
431static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) 431static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void)
432{ 432{
433 return 0x0000001a; 433 return 0x0000001aU;
434} 434}
435static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) 435static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void)
436{ 436{
437 return 0x0000001b; 437 return 0x0000001bU;
438} 438}
439static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) 439static inline u32 gmmu_pte_kind_s8z24_2cs_v(void)
440{ 440{
441 return 0x0000001c; 441 return 0x0000001cU;
442} 442}
443static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) 443static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void)
444{ 444{
445 return 0x0000001d; 445 return 0x0000001dU;
446} 446}
447static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) 447static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void)
448{ 448{
449 return 0x0000001e; 449 return 0x0000001eU;
450} 450}
451static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) 451static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void)
452{ 452{
453 return 0x0000001f; 453 return 0x0000001fU;
454} 454}
455static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) 455static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void)
456{ 456{
457 return 0x00000020; 457 return 0x00000020U;
458} 458}
459static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) 459static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void)
460{ 460{
461 return 0x00000021; 461 return 0x00000021U;
462} 462}
463static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) 463static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void)
464{ 464{
465 return 0x00000022; 465 return 0x00000022U;
466} 466}
467static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) 467static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void)
468{ 468{
469 return 0x00000023; 469 return 0x00000023U;
470} 470}
471static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) 471static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void)
472{ 472{
473 return 0x00000024; 473 return 0x00000024U;
474} 474}
475static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) 475static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void)
476{ 476{
477 return 0x00000025; 477 return 0x00000025U;
478} 478}
479static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) 479static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void)
480{ 480{
481 return 0x00000026; 481 return 0x00000026U;
482} 482}
483static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) 483static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void)
484{ 484{
485 return 0x00000027; 485 return 0x00000027U;
486} 486}
487static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) 487static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void)
488{ 488{
489 return 0x00000028; 489 return 0x00000028U;
490} 490}
491static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) 491static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void)
492{ 492{
493 return 0x00000029; 493 return 0x00000029U;
494} 494}
495static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) 495static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void)
496{ 496{
497 return 0x0000002e; 497 return 0x0000002eU;
498} 498}
499static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) 499static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void)
500{ 500{
501 return 0x0000002f; 501 return 0x0000002fU;
502} 502}
503static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) 503static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void)
504{ 504{
505 return 0x00000030; 505 return 0x00000030U;
506} 506}
507static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) 507static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void)
508{ 508{
509 return 0x00000031; 509 return 0x00000031U;
510} 510}
511static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) 511static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void)
512{ 512{
513 return 0x00000032; 513 return 0x00000032U;
514} 514}
515static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) 515static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void)
516{ 516{
517 return 0x00000033; 517 return 0x00000033U;
518} 518}
519static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) 519static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void)
520{ 520{
521 return 0x00000034; 521 return 0x00000034U;
522} 522}
523static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) 523static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void)
524{ 524{
525 return 0x00000035; 525 return 0x00000035U;
526} 526}
527static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) 527static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void)
528{ 528{
529 return 0x0000003a; 529 return 0x0000003aU;
530} 530}
531static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) 531static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void)
532{ 532{
533 return 0x0000003b; 533 return 0x0000003bU;
534} 534}
535static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) 535static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void)
536{ 536{
537 return 0x0000003c; 537 return 0x0000003cU;
538} 538}
539static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) 539static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void)
540{ 540{
541 return 0x0000003d; 541 return 0x0000003dU;
542} 542}
543static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) 543static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void)
544{ 544{
545 return 0x0000003e; 545 return 0x0000003eU;
546} 546}
547static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) 547static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void)
548{ 548{
549 return 0x0000003f; 549 return 0x0000003fU;
550} 550}
551static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) 551static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void)
552{ 552{
553 return 0x00000040; 553 return 0x00000040U;
554} 554}
555static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) 555static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void)
556{ 556{
557 return 0x00000041; 557 return 0x00000041U;
558} 558}
559static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) 559static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void)
560{ 560{
561 return 0x00000042; 561 return 0x00000042U;
562} 562}
563static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) 563static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void)
564{ 564{
565 return 0x00000043; 565 return 0x00000043U;
566} 566}
567static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) 567static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void)
568{ 568{
569 return 0x00000044; 569 return 0x00000044U;
570} 570}
571static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) 571static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void)
572{ 572{
573 return 0x00000045; 573 return 0x00000045U;
574} 574}
575static inline u32 gmmu_pte_kind_z24s8_v(void) 575static inline u32 gmmu_pte_kind_z24s8_v(void)
576{ 576{
577 return 0x00000046; 577 return 0x00000046U;
578} 578}
579static inline u32 gmmu_pte_kind_z24s8_1z_v(void) 579static inline u32 gmmu_pte_kind_z24s8_1z_v(void)
580{ 580{
581 return 0x00000047; 581 return 0x00000047U;
582} 582}
583static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) 583static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void)
584{ 584{
585 return 0x00000048; 585 return 0x00000048U;
586} 586}
587static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) 587static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void)
588{ 588{
589 return 0x00000049; 589 return 0x00000049U;
590} 590}
591static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) 591static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void)
592{ 592{
593 return 0x0000004a; 593 return 0x0000004aU;
594} 594}
595static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) 595static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void)
596{ 596{
597 return 0x0000004b; 597 return 0x0000004bU;
598} 598}
599static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) 599static inline u32 gmmu_pte_kind_z24s8_2cs_v(void)
600{ 600{
601 return 0x0000004c; 601 return 0x0000004cU;
602} 602}
603static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) 603static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void)
604{ 604{
605 return 0x0000004d; 605 return 0x0000004dU;
606} 606}
607static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) 607static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void)
608{ 608{
609 return 0x0000004e; 609 return 0x0000004eU;
610} 610}
611static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) 611static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void)
612{ 612{
613 return 0x0000004f; 613 return 0x0000004fU;
614} 614}
615static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) 615static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void)
616{ 616{
617 return 0x00000050; 617 return 0x00000050U;
618} 618}
619static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) 619static inline u32 gmmu_pte_kind_z24s8_2cz_v(void)
620{ 620{
621 return 0x00000051; 621 return 0x00000051U;
622} 622}
623static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) 623static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void)
624{ 624{
625 return 0x00000052; 625 return 0x00000052U;
626} 626}
627static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) 627static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void)
628{ 628{
629 return 0x00000053; 629 return 0x00000053U;
630} 630}
631static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) 631static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void)
632{ 632{
633 return 0x00000054; 633 return 0x00000054U;
634} 634}
635static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) 635static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void)
636{ 636{
637 return 0x00000055; 637 return 0x00000055U;
638} 638}
639static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) 639static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void)
640{ 640{
641 return 0x00000056; 641 return 0x00000056U;
642} 642}
643static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) 643static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void)
644{ 644{
645 return 0x00000057; 645 return 0x00000057U;
646} 646}
647static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) 647static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void)
648{ 648{
649 return 0x00000058; 649 return 0x00000058U;
650} 650}
651static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) 651static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void)
652{ 652{
653 return 0x00000059; 653 return 0x00000059U;
654} 654}
655static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) 655static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void)
656{ 656{
657 return 0x0000005a; 657 return 0x0000005aU;
658} 658}
659static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) 659static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void)
660{ 660{
661 return 0x0000005b; 661 return 0x0000005bU;
662} 662}
663static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) 663static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void)
664{ 664{
665 return 0x0000005c; 665 return 0x0000005cU;
666} 666}
667static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) 667static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void)
668{ 668{
669 return 0x0000005d; 669 return 0x0000005dU;
670} 670}
671static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) 671static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void)
672{ 672{
673 return 0x0000005e; 673 return 0x0000005eU;
674} 674}
675static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) 675static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void)
676{ 676{
677 return 0x00000063; 677 return 0x00000063U;
678} 678}
679static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) 679static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void)
680{ 680{
681 return 0x00000064; 681 return 0x00000064U;
682} 682}
683static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) 683static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void)
684{ 684{
685 return 0x00000065; 685 return 0x00000065U;
686} 686}
687static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) 687static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void)
688{ 688{
689 return 0x00000066; 689 return 0x00000066U;
690} 690}
691static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) 691static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void)
692{ 692{
693 return 0x00000067; 693 return 0x00000067U;
694} 694}
695static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) 695static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void)
696{ 696{
697 return 0x00000068; 697 return 0x00000068U;
698} 698}
699static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) 699static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void)
700{ 700{
701 return 0x00000069; 701 return 0x00000069U;
702} 702}
703static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) 703static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void)
704{ 704{
705 return 0x0000006a; 705 return 0x0000006aU;
706} 706}
707static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) 707static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void)
708{ 708{
709 return 0x0000006f; 709 return 0x0000006fU;
710} 710}
711static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) 711static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void)
712{ 712{
713 return 0x00000070; 713 return 0x00000070U;
714} 714}
715static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) 715static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void)
716{ 716{
717 return 0x00000071; 717 return 0x00000071U;
718} 718}
719static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) 719static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void)
720{ 720{
721 return 0x00000072; 721 return 0x00000072U;
722} 722}
723static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) 723static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void)
724{ 724{
725 return 0x00000073; 725 return 0x00000073U;
726} 726}
727static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) 727static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void)
728{ 728{
729 return 0x00000074; 729 return 0x00000074U;
730} 730}
731static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) 731static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void)
732{ 732{
733 return 0x00000075; 733 return 0x00000075U;
734} 734}
735static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) 735static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void)
736{ 736{
737 return 0x00000076; 737 return 0x00000076U;
738} 738}
739static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) 739static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void)
740{ 740{
741 return 0x00000077; 741 return 0x00000077U;
742} 742}
743static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) 743static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void)
744{ 744{
745 return 0x00000078; 745 return 0x00000078U;
746} 746}
747static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) 747static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void)
748{ 748{
749 return 0x00000079; 749 return 0x00000079U;
750} 750}
751static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) 751static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void)
752{ 752{
753 return 0x0000007a; 753 return 0x0000007aU;
754} 754}
755static inline u32 gmmu_pte_kind_zf32_v(void) 755static inline u32 gmmu_pte_kind_zf32_v(void)
756{ 756{
757 return 0x0000007b; 757 return 0x0000007bU;
758} 758}
759static inline u32 gmmu_pte_kind_zf32_1z_v(void) 759static inline u32 gmmu_pte_kind_zf32_1z_v(void)
760{ 760{
761 return 0x0000007c; 761 return 0x0000007cU;
762} 762}
763static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) 763static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void)
764{ 764{
765 return 0x0000007d; 765 return 0x0000007dU;
766} 766}
767static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) 767static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void)
768{ 768{
769 return 0x0000007e; 769 return 0x0000007eU;
770} 770}
771static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) 771static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void)
772{ 772{
773 return 0x0000007f; 773 return 0x0000007fU;
774} 774}
775static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) 775static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void)
776{ 776{
777 return 0x00000080; 777 return 0x00000080U;
778} 778}
779static inline u32 gmmu_pte_kind_zf32_2cs_v(void) 779static inline u32 gmmu_pte_kind_zf32_2cs_v(void)
780{ 780{
781 return 0x00000081; 781 return 0x00000081U;
782} 782}
783static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) 783static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void)
784{ 784{
785 return 0x00000082; 785 return 0x00000082U;
786} 786}
787static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) 787static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void)
788{ 788{
789 return 0x00000083; 789 return 0x00000083U;
790} 790}
791static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) 791static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void)
792{ 792{
793 return 0x00000084; 793 return 0x00000084U;
794} 794}
795static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) 795static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void)
796{ 796{
797 return 0x00000085; 797 return 0x00000085U;
798} 798}
799static inline u32 gmmu_pte_kind_zf32_2cz_v(void) 799static inline u32 gmmu_pte_kind_zf32_2cz_v(void)
800{ 800{
801 return 0x00000086; 801 return 0x00000086U;
802} 802}
803static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) 803static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void)
804{ 804{
805 return 0x00000087; 805 return 0x00000087U;
806} 806}
807static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) 807static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void)
808{ 808{
809 return 0x00000088; 809 return 0x00000088U;
810} 810}
811static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) 811static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void)
812{ 812{
813 return 0x00000089; 813 return 0x00000089U;
814} 814}
815static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) 815static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void)
816{ 816{
817 return 0x0000008a; 817 return 0x0000008aU;
818} 818}
819static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) 819static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void)
820{ 820{
821 return 0x0000008b; 821 return 0x0000008bU;
822} 822}
823static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) 823static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void)
824{ 824{
825 return 0x0000008c; 825 return 0x0000008cU;
826} 826}
827static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) 827static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void)
828{ 828{
829 return 0x0000008d; 829 return 0x0000008dU;
830} 830}
831static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) 831static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void)
832{ 832{
833 return 0x0000008e; 833 return 0x0000008eU;
834} 834}
835static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) 835static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void)
836{ 836{
837 return 0x0000008f; 837 return 0x0000008fU;
838} 838}
839static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) 839static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void)
840{ 840{
841 return 0x00000090; 841 return 0x00000090U;
842} 842}
843static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) 843static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void)
844{ 844{
845 return 0x00000091; 845 return 0x00000091U;
846} 846}
847static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) 847static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void)
848{ 848{
849 return 0x00000092; 849 return 0x00000092U;
850} 850}
851static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) 851static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void)
852{ 852{
853 return 0x00000097; 853 return 0x00000097U;
854} 854}
855static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) 855static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void)
856{ 856{
857 return 0x00000098; 857 return 0x00000098U;
858} 858}
859static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) 859static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void)
860{ 860{
861 return 0x00000099; 861 return 0x00000099U;
862} 862}
863static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) 863static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void)
864{ 864{
865 return 0x0000009a; 865 return 0x0000009aU;
866} 866}
867static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) 867static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void)
868{ 868{
869 return 0x0000009b; 869 return 0x0000009bU;
870} 870}
871static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) 871static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void)
872{ 872{
873 return 0x0000009c; 873 return 0x0000009cU;
874} 874}
875static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) 875static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void)
876{ 876{
877 return 0x0000009d; 877 return 0x0000009dU;
878} 878}
879static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) 879static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void)
880{ 880{
881 return 0x0000009e; 881 return 0x0000009eU;
882} 882}
883static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) 883static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void)
884{ 884{
885 return 0x0000009f; 885 return 0x0000009fU;
886} 886}
887static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) 887static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void)
888{ 888{
889 return 0x000000a0; 889 return 0x000000a0U;
890} 890}
891static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) 891static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void)
892{ 892{
893 return 0x000000a1; 893 return 0x000000a1U;
894} 894}
895static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) 895static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void)
896{ 896{
897 return 0x000000a2; 897 return 0x000000a2U;
898} 898}
899static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) 899static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void)
900{ 900{
901 return 0x000000a3; 901 return 0x000000a3U;
902} 902}
903static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) 903static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void)
904{ 904{
905 return 0x000000a4; 905 return 0x000000a4U;
906} 906}
907static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) 907static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void)
908{ 908{
909 return 0x000000a5; 909 return 0x000000a5U;
910} 910}
911static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) 911static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void)
912{ 912{
913 return 0x000000a6; 913 return 0x000000a6U;
914} 914}
915static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) 915static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void)
916{ 916{
917 return 0x000000a7; 917 return 0x000000a7U;
918} 918}
919static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) 919static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void)
920{ 920{
921 return 0x000000a8; 921 return 0x000000a8U;
922} 922}
923static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) 923static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void)
924{ 924{
925 return 0x000000a9; 925 return 0x000000a9U;
926} 926}
927static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) 927static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void)
928{ 928{
929 return 0x000000aa; 929 return 0x000000aaU;
930} 930}
931static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) 931static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void)
932{ 932{
933 return 0x000000ab; 933 return 0x000000abU;
934} 934}
935static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) 935static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void)
936{ 936{
937 return 0x000000ac; 937 return 0x000000acU;
938} 938}
939static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) 939static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void)
940{ 940{
941 return 0x000000ad; 941 return 0x000000adU;
942} 942}
943static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) 943static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void)
944{ 944{
945 return 0x000000ae; 945 return 0x000000aeU;
946} 946}
947static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) 947static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void)
948{ 948{
949 return 0x000000b3; 949 return 0x000000b3U;
950} 950}
951static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) 951static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void)
952{ 952{
953 return 0x000000b4; 953 return 0x000000b4U;
954} 954}
955static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) 955static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void)
956{ 956{
957 return 0x000000b5; 957 return 0x000000b5U;
958} 958}
959static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) 959static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void)
960{ 960{
961 return 0x000000b6; 961 return 0x000000b6U;
962} 962}
963static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) 963static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void)
964{ 964{
965 return 0x000000b7; 965 return 0x000000b7U;
966} 966}
967static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) 967static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void)
968{ 968{
969 return 0x000000b8; 969 return 0x000000b8U;
970} 970}
971static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) 971static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void)
972{ 972{
973 return 0x000000b9; 973 return 0x000000b9U;
974} 974}
975static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) 975static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void)
976{ 976{
977 return 0x000000ba; 977 return 0x000000baU;
978} 978}
979static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) 979static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void)
980{ 980{
981 return 0x000000bb; 981 return 0x000000bbU;
982} 982}
983static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) 983static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void)
984{ 984{
985 return 0x000000bc; 985 return 0x000000bcU;
986} 986}
987static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) 987static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void)
988{ 988{
989 return 0x000000bd; 989 return 0x000000bdU;
990} 990}
991static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) 991static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void)
992{ 992{
993 return 0x000000be; 993 return 0x000000beU;
994} 994}
995static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) 995static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void)
996{ 996{
997 return 0x000000bf; 997 return 0x000000bfU;
998} 998}
999static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) 999static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void)
1000{ 1000{
1001 return 0x000000c0; 1001 return 0x000000c0U;
1002} 1002}
1003static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) 1003static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void)
1004{ 1004{
1005 return 0x000000c1; 1005 return 0x000000c1U;
1006} 1006}
1007static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) 1007static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void)
1008{ 1008{
1009 return 0x000000c2; 1009 return 0x000000c2U;
1010} 1010}
1011static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) 1011static inline u32 gmmu_pte_kind_zf32_x24s8_v(void)
1012{ 1012{
1013 return 0x000000c3; 1013 return 0x000000c3U;
1014} 1014}
1015static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) 1015static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void)
1016{ 1016{
1017 return 0x000000c4; 1017 return 0x000000c4U;
1018} 1018}
1019static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) 1019static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void)
1020{ 1020{
1021 return 0x000000c5; 1021 return 0x000000c5U;
1022} 1022}
1023static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) 1023static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void)
1024{ 1024{
1025 return 0x000000c6; 1025 return 0x000000c6U;
1026} 1026}
1027static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) 1027static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void)
1028{ 1028{
1029 return 0x000000c7; 1029 return 0x000000c7U;
1030} 1030}
1031static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) 1031static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void)
1032{ 1032{
1033 return 0x000000c8; 1033 return 0x000000c8U;
1034} 1034}
1035static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) 1035static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void)
1036{ 1036{
1037 return 0x000000ce; 1037 return 0x000000ceU;
1038} 1038}
1039static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) 1039static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void)
1040{ 1040{
1041 return 0x000000cf; 1041 return 0x000000cfU;
1042} 1042}
1043static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) 1043static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void)
1044{ 1044{
1045 return 0x000000d0; 1045 return 0x000000d0U;
1046} 1046}
1047static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) 1047static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void)
1048{ 1048{
1049 return 0x000000d1; 1049 return 0x000000d1U;
1050} 1050}
1051static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) 1051static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void)
1052{ 1052{
1053 return 0x000000d2; 1053 return 0x000000d2U;
1054} 1054}
1055static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) 1055static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void)
1056{ 1056{
1057 return 0x000000d3; 1057 return 0x000000d3U;
1058} 1058}
1059static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) 1059static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void)
1060{ 1060{
1061 return 0x000000d4; 1061 return 0x000000d4U;
1062} 1062}
1063static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) 1063static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void)
1064{ 1064{
1065 return 0x000000d5; 1065 return 0x000000d5U;
1066} 1066}
1067static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) 1067static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void)
1068{ 1068{
1069 return 0x000000d6; 1069 return 0x000000d6U;
1070} 1070}
1071static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) 1071static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void)
1072{ 1072{
1073 return 0x000000d7; 1073 return 0x000000d7U;
1074} 1074}
1075static inline u32 gmmu_pte_kind_generic_16bx2_v(void) 1075static inline u32 gmmu_pte_kind_generic_16bx2_v(void)
1076{ 1076{
1077 return 0x000000fe; 1077 return 0x000000feU;
1078} 1078}
1079static inline u32 gmmu_pte_kind_c32_2c_v(void) 1079static inline u32 gmmu_pte_kind_c32_2c_v(void)
1080{ 1080{
1081 return 0x000000d8; 1081 return 0x000000d8U;
1082} 1082}
1083static inline u32 gmmu_pte_kind_c32_2cbr_v(void) 1083static inline u32 gmmu_pte_kind_c32_2cbr_v(void)
1084{ 1084{
1085 return 0x000000d9; 1085 return 0x000000d9U;
1086} 1086}
1087static inline u32 gmmu_pte_kind_c32_2cba_v(void) 1087static inline u32 gmmu_pte_kind_c32_2cba_v(void)
1088{ 1088{
1089 return 0x000000da; 1089 return 0x000000daU;
1090} 1090}
1091static inline u32 gmmu_pte_kind_c32_2cra_v(void) 1091static inline u32 gmmu_pte_kind_c32_2cra_v(void)
1092{ 1092{
1093 return 0x000000db; 1093 return 0x000000dbU;
1094} 1094}
1095static inline u32 gmmu_pte_kind_c32_2bra_v(void) 1095static inline u32 gmmu_pte_kind_c32_2bra_v(void)
1096{ 1096{
1097 return 0x000000dc; 1097 return 0x000000dcU;
1098} 1098}
1099static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) 1099static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void)
1100{ 1100{
1101 return 0x000000dd; 1101 return 0x000000ddU;
1102} 1102}
1103static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) 1103static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void)
1104{ 1104{
1105 return 0x000000de; 1105 return 0x000000deU;
1106} 1106}
1107static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) 1107static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void)
1108{ 1108{
1109 return 0x000000cc; 1109 return 0x000000ccU;
1110} 1110}
1111static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) 1111static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void)
1112{ 1112{
1113 return 0x000000df; 1113 return 0x000000dfU;
1114} 1114}
1115static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) 1115static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void)
1116{ 1116{
1117 return 0x000000e0; 1117 return 0x000000e0U;
1118} 1118}
1119static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) 1119static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void)
1120{ 1120{
1121 return 0x000000e1; 1121 return 0x000000e1U;
1122} 1122}
1123static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) 1123static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void)
1124{ 1124{
1125 return 0x000000e2; 1125 return 0x000000e2U;
1126} 1126}
1127static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) 1127static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void)
1128{ 1128{
1129 return 0x000000e3; 1129 return 0x000000e3U;
1130} 1130}
1131static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void) 1131static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void)
1132{ 1132{
1133 return 0x0000002c; 1133 return 0x0000002cU;
1134} 1134}
1135static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) 1135static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void)
1136{ 1136{
1137 return 0x000000e4; 1137 return 0x000000e4U;
1138} 1138}
1139static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) 1139static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void)
1140{ 1140{
1141 return 0x000000e5; 1141 return 0x000000e5U;
1142} 1142}
1143static inline u32 gmmu_pte_kind_c64_2c_v(void) 1143static inline u32 gmmu_pte_kind_c64_2c_v(void)
1144{ 1144{
1145 return 0x000000e6; 1145 return 0x000000e6U;
1146} 1146}
1147static inline u32 gmmu_pte_kind_c64_2cbr_v(void) 1147static inline u32 gmmu_pte_kind_c64_2cbr_v(void)
1148{ 1148{
1149 return 0x000000e7; 1149 return 0x000000e7U;
1150} 1150}
1151static inline u32 gmmu_pte_kind_c64_2cba_v(void) 1151static inline u32 gmmu_pte_kind_c64_2cba_v(void)
1152{ 1152{
1153 return 0x000000e8; 1153 return 0x000000e8U;
1154} 1154}
1155static inline u32 gmmu_pte_kind_c64_2cra_v(void) 1155static inline u32 gmmu_pte_kind_c64_2cra_v(void)
1156{ 1156{
1157 return 0x000000e9; 1157 return 0x000000e9U;
1158} 1158}
1159static inline u32 gmmu_pte_kind_c64_2bra_v(void) 1159static inline u32 gmmu_pte_kind_c64_2bra_v(void)
1160{ 1160{
1161 return 0x000000ea; 1161 return 0x000000eaU;
1162} 1162}
1163static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) 1163static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void)
1164{ 1164{
1165 return 0x000000eb; 1165 return 0x000000ebU;
1166} 1166}
1167static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) 1167static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void)
1168{ 1168{
1169 return 0x000000ec; 1169 return 0x000000ecU;
1170} 1170}
1171static inline u32 gmmu_pte_kind_c64_ms2_4cbra_v(void) 1171static inline u32 gmmu_pte_kind_c64_ms2_4cbra_v(void)
1172{ 1172{
1173 return 0x000000cd; 1173 return 0x000000cdU;
1174} 1174}
1175static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) 1175static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void)
1176{ 1176{
1177 return 0x000000ed; 1177 return 0x000000edU;
1178} 1178}
1179static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) 1179static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void)
1180{ 1180{
1181 return 0x000000ee; 1181 return 0x000000eeU;
1182} 1182}
1183static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) 1183static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void)
1184{ 1184{
1185 return 0x000000ef; 1185 return 0x000000efU;
1186} 1186}
1187static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) 1187static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void)
1188{ 1188{
1189 return 0x000000f0; 1189 return 0x000000f0U;
1190} 1190}
1191static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) 1191static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void)
1192{ 1192{
1193 return 0x000000f1; 1193 return 0x000000f1U;
1194} 1194}
1195static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void) 1195static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void)
1196{ 1196{
1197 return 0x0000002d; 1197 return 0x0000002dU;
1198} 1198}
1199static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) 1199static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void)
1200{ 1200{
1201 return 0x000000f2; 1201 return 0x000000f2U;
1202} 1202}
1203static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) 1203static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void)
1204{ 1204{
1205 return 0x000000f3; 1205 return 0x000000f3U;
1206} 1206}
1207static inline u32 gmmu_pte_kind_c128_2c_v(void) 1207static inline u32 gmmu_pte_kind_c128_2c_v(void)
1208{ 1208{
1209 return 0x000000f4; 1209 return 0x000000f4U;
1210} 1210}
1211static inline u32 gmmu_pte_kind_c128_2cr_v(void) 1211static inline u32 gmmu_pte_kind_c128_2cr_v(void)
1212{ 1212{
1213 return 0x000000f5; 1213 return 0x000000f5U;
1214} 1214}
1215static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) 1215static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void)
1216{ 1216{
1217 return 0x000000f6; 1217 return 0x000000f6U;
1218} 1218}
1219static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) 1219static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void)
1220{ 1220{
1221 return 0x000000f7; 1221 return 0x000000f7U;
1222} 1222}
1223static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) 1223static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void)
1224{ 1224{
1225 return 0x000000f8; 1225 return 0x000000f8U;
1226} 1226}
1227static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) 1227static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void)
1228{ 1228{
1229 return 0x000000f9; 1229 return 0x000000f9U;
1230} 1230}
1231static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) 1231static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void)
1232{ 1232{
1233 return 0x000000fa; 1233 return 0x000000faU;
1234} 1234}
1235static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) 1235static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void)
1236{ 1236{
1237 return 0x000000fb; 1237 return 0x000000fbU;
1238} 1238}
1239static inline u32 gmmu_pte_kind_x8c24_v(void) 1239static inline u32 gmmu_pte_kind_x8c24_v(void)
1240{ 1240{
1241 return 0x000000fc; 1241 return 0x000000fcU;
1242} 1242}
1243static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) 1243static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void)
1244{ 1244{
1245 return 0x000000fd; 1245 return 0x000000fdU;
1246} 1246}
1247static inline u32 gmmu_pte_kind_smsked_message_v(void) 1247static inline u32 gmmu_pte_kind_smsked_message_v(void)
1248{ 1248{
1249 return 0x000000ca; 1249 return 0x000000caU;
1250} 1250}
1251static inline u32 gmmu_pte_kind_smhost_message_v(void) 1251static inline u32 gmmu_pte_kind_smhost_message_v(void)
1252{ 1252{
1253 return 0x000000cb; 1253 return 0x000000cbU;
1254} 1254}
1255static inline u32 gmmu_pte_kind_s8_v(void) 1255static inline u32 gmmu_pte_kind_s8_v(void)
1256{ 1256{
1257 return 0x0000002a; 1257 return 0x0000002aU;
1258} 1258}
1259static inline u32 gmmu_pte_kind_s8_2s_v(void) 1259static inline u32 gmmu_pte_kind_s8_2s_v(void)
1260{ 1260{
1261 return 0x0000002b; 1261 return 0x0000002bU;
1262} 1262}
1263static inline u32 gmmu_fault_client_type_gpc_v(void) 1263static inline u32 gmmu_fault_client_type_gpc_v(void)
1264{ 1264{
1265 return 0x00000000; 1265 return 0x00000000U;
1266} 1266}
1267static inline u32 gmmu_fault_client_type_hub_v(void) 1267static inline u32 gmmu_fault_client_type_hub_v(void)
1268{ 1268{
1269 return 0x00000001; 1269 return 0x00000001U;
1270} 1270}
1271static inline u32 gmmu_fault_type_unbound_inst_block_v(void) 1271static inline u32 gmmu_fault_type_unbound_inst_block_v(void)
1272{ 1272{
1273 return 0x00000004; 1273 return 0x00000004U;
1274} 1274}
1275static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void) 1275static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void)
1276{ 1276{
1277 return 0x00000005; 1277 return 0x00000005U;
1278} 1278}
1279static inline u32 gmmu_fault_mmu_eng_id_physical_v(void) 1279static inline u32 gmmu_fault_mmu_eng_id_physical_v(void)
1280{ 1280{
1281 return 0x0000001f; 1281 return 0x0000001fU;
1282} 1282}
1283static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void) 1283static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void)
1284{ 1284{
1285 return 0x0000000f; 1285 return 0x0000000fU;
1286} 1286}
1287static inline u32 gmmu_fault_buf_size_v(void) 1287static inline u32 gmmu_fault_buf_size_v(void)
1288{ 1288{
1289 return 0x00000020; 1289 return 0x00000020U;
1290} 1290}
1291static inline u32 gmmu_fault_buf_entry_inst_aperture_v(u32 r) 1291static inline u32 gmmu_fault_buf_entry_inst_aperture_v(u32 r)
1292{ 1292{
1293 return (r >> 8) & 0x3; 1293 return (r >> 8U) & 0x3U;
1294} 1294}
1295static inline u32 gmmu_fault_buf_entry_inst_aperture_w(void) 1295static inline u32 gmmu_fault_buf_entry_inst_aperture_w(void)
1296{ 1296{
1297 return 0; 1297 return 0U;
1298} 1298}
1299static inline u32 gmmu_fault_buf_entry_inst_aperture_vid_mem_v(void) 1299static inline u32 gmmu_fault_buf_entry_inst_aperture_vid_mem_v(void)
1300{ 1300{
1301 return 0x00000000; 1301 return 0x00000000U;
1302} 1302}
1303static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_coh_v(void) 1303static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_coh_v(void)
1304{ 1304{
1305 return 0x00000002; 1305 return 0x00000002U;
1306} 1306}
1307static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_nocoh_v(void) 1307static inline u32 gmmu_fault_buf_entry_inst_aperture_sys_nocoh_v(void)
1308{ 1308{
1309 return 0x00000003; 1309 return 0x00000003U;
1310} 1310}
1311static inline u32 gmmu_fault_buf_entry_inst_lo_f(u32 v) 1311static inline u32 gmmu_fault_buf_entry_inst_lo_f(u32 v)
1312{ 1312{
1313 return (v & 0xfffff) << 12; 1313 return (v & 0xfffffU) << 12U;
1314} 1314}
1315static inline u32 gmmu_fault_buf_entry_inst_lo_v(u32 r) 1315static inline u32 gmmu_fault_buf_entry_inst_lo_v(u32 r)
1316{ 1316{
1317 return (r >> 12) & 0xfffff; 1317 return (r >> 12U) & 0xfffffU;
1318} 1318}
1319static inline u32 gmmu_fault_buf_entry_inst_lo_w(void) 1319static inline u32 gmmu_fault_buf_entry_inst_lo_w(void)
1320{ 1320{
1321 return 0; 1321 return 0U;
1322} 1322}
1323static inline u32 gmmu_fault_buf_entry_inst_hi_v(u32 r) 1323static inline u32 gmmu_fault_buf_entry_inst_hi_v(u32 r)
1324{ 1324{
1325 return (r >> 0) & 0xffffffff; 1325 return (r >> 0U) & 0xffffffffU;
1326} 1326}
1327static inline u32 gmmu_fault_buf_entry_inst_hi_w(void) 1327static inline u32 gmmu_fault_buf_entry_inst_hi_w(void)
1328{ 1328{
1329 return 1; 1329 return 1U;
1330} 1330}
1331static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_v(u32 r) 1331static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_v(u32 r)
1332{ 1332{
1333 return (r >> 0) & 0x3; 1333 return (r >> 0U) & 0x3U;
1334} 1334}
1335static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_w(void) 1335static inline u32 gmmu_fault_buf_entry_addr_phys_aperture_w(void)
1336{ 1336{
1337 return 2; 1337 return 2U;
1338} 1338}
1339static inline u32 gmmu_fault_buf_entry_addr_lo_f(u32 v) 1339static inline u32 gmmu_fault_buf_entry_addr_lo_f(u32 v)
1340{ 1340{
1341 return (v & 0xfffff) << 12; 1341 return (v & 0xfffffU) << 12U;
1342} 1342}
1343static inline u32 gmmu_fault_buf_entry_addr_lo_v(u32 r) 1343static inline u32 gmmu_fault_buf_entry_addr_lo_v(u32 r)
1344{ 1344{
1345 return (r >> 12) & 0xfffff; 1345 return (r >> 12U) & 0xfffffU;
1346} 1346}
1347static inline u32 gmmu_fault_buf_entry_addr_lo_w(void) 1347static inline u32 gmmu_fault_buf_entry_addr_lo_w(void)
1348{ 1348{
1349 return 2; 1349 return 2U;
1350} 1350}
1351static inline u32 gmmu_fault_buf_entry_addr_hi_v(u32 r) 1351static inline u32 gmmu_fault_buf_entry_addr_hi_v(u32 r)
1352{ 1352{
1353 return (r >> 0) & 0xffffffff; 1353 return (r >> 0U) & 0xffffffffU;
1354} 1354}
1355static inline u32 gmmu_fault_buf_entry_addr_hi_w(void) 1355static inline u32 gmmu_fault_buf_entry_addr_hi_w(void)
1356{ 1356{
1357 return 3; 1357 return 3U;
1358} 1358}
1359static inline u32 gmmu_fault_buf_entry_timestamp_lo_v(u32 r) 1359static inline u32 gmmu_fault_buf_entry_timestamp_lo_v(u32 r)
1360{ 1360{
1361 return (r >> 0) & 0xffffffff; 1361 return (r >> 0U) & 0xffffffffU;
1362} 1362}
1363static inline u32 gmmu_fault_buf_entry_timestamp_lo_w(void) 1363static inline u32 gmmu_fault_buf_entry_timestamp_lo_w(void)
1364{ 1364{
1365 return 4; 1365 return 4U;
1366} 1366}
1367static inline u32 gmmu_fault_buf_entry_timestamp_hi_v(u32 r) 1367static inline u32 gmmu_fault_buf_entry_timestamp_hi_v(u32 r)
1368{ 1368{
1369 return (r >> 0) & 0xffffffff; 1369 return (r >> 0U) & 0xffffffffU;
1370} 1370}
1371static inline u32 gmmu_fault_buf_entry_timestamp_hi_w(void) 1371static inline u32 gmmu_fault_buf_entry_timestamp_hi_w(void)
1372{ 1372{
1373 return 5; 1373 return 5U;
1374} 1374}
1375static inline u32 gmmu_fault_buf_entry_engine_id_v(u32 r) 1375static inline u32 gmmu_fault_buf_entry_engine_id_v(u32 r)
1376{ 1376{
1377 return (r >> 0) & 0x1ff; 1377 return (r >> 0U) & 0x1ffU;
1378} 1378}
1379static inline u32 gmmu_fault_buf_entry_engine_id_w(void) 1379static inline u32 gmmu_fault_buf_entry_engine_id_w(void)
1380{ 1380{
1381 return 6; 1381 return 6U;
1382} 1382}
1383static inline u32 gmmu_fault_buf_entry_fault_type_v(u32 r) 1383static inline u32 gmmu_fault_buf_entry_fault_type_v(u32 r)
1384{ 1384{
1385 return (r >> 0) & 0x1f; 1385 return (r >> 0U) & 0x1fU;
1386} 1386}
1387static inline u32 gmmu_fault_buf_entry_fault_type_w(void) 1387static inline u32 gmmu_fault_buf_entry_fault_type_w(void)
1388{ 1388{
1389 return 7; 1389 return 7U;
1390} 1390}
1391static inline u32 gmmu_fault_buf_entry_replayable_fault_v(u32 r) 1391static inline u32 gmmu_fault_buf_entry_replayable_fault_v(u32 r)
1392{ 1392{
1393 return (r >> 7) & 0x1; 1393 return (r >> 7U) & 0x1U;
1394} 1394}
1395static inline u32 gmmu_fault_buf_entry_replayable_fault_w(void) 1395static inline u32 gmmu_fault_buf_entry_replayable_fault_w(void)
1396{ 1396{
1397 return 7; 1397 return 7U;
1398} 1398}
1399static inline u32 gmmu_fault_buf_entry_replayable_fault_true_v(void) 1399static inline u32 gmmu_fault_buf_entry_replayable_fault_true_v(void)
1400{ 1400{
1401 return 0x00000001; 1401 return 0x00000001U;
1402} 1402}
1403static inline u32 gmmu_fault_buf_entry_replayable_fault_true_f(void) 1403static inline u32 gmmu_fault_buf_entry_replayable_fault_true_f(void)
1404{ 1404{
1405 return 0x80; 1405 return 0x80U;
1406} 1406}
1407static inline u32 gmmu_fault_buf_entry_client_v(u32 r) 1407static inline u32 gmmu_fault_buf_entry_client_v(u32 r)
1408{ 1408{
1409 return (r >> 8) & 0x7f; 1409 return (r >> 8U) & 0x7fU;
1410} 1410}
1411static inline u32 gmmu_fault_buf_entry_client_w(void) 1411static inline u32 gmmu_fault_buf_entry_client_w(void)
1412{ 1412{
1413 return 7; 1413 return 7U;
1414} 1414}
1415static inline u32 gmmu_fault_buf_entry_access_type_v(u32 r) 1415static inline u32 gmmu_fault_buf_entry_access_type_v(u32 r)
1416{ 1416{
1417 return (r >> 16) & 0xf; 1417 return (r >> 16U) & 0xfU;
1418} 1418}
1419static inline u32 gmmu_fault_buf_entry_access_type_w(void) 1419static inline u32 gmmu_fault_buf_entry_access_type_w(void)
1420{ 1420{
1421 return 7; 1421 return 7U;
1422} 1422}
1423static inline u32 gmmu_fault_buf_entry_mmu_client_type_v(u32 r) 1423static inline u32 gmmu_fault_buf_entry_mmu_client_type_v(u32 r)
1424{ 1424{
1425 return (r >> 20) & 0x1; 1425 return (r >> 20U) & 0x1U;
1426} 1426}
1427static inline u32 gmmu_fault_buf_entry_mmu_client_type_w(void) 1427static inline u32 gmmu_fault_buf_entry_mmu_client_type_w(void)
1428{ 1428{
1429 return 7; 1429 return 7U;
1430} 1430}
1431static inline u32 gmmu_fault_buf_entry_gpc_id_v(u32 r) 1431static inline u32 gmmu_fault_buf_entry_gpc_id_v(u32 r)
1432{ 1432{
1433 return (r >> 24) & 0x1f; 1433 return (r >> 24U) & 0x1fU;
1434} 1434}
1435static inline u32 gmmu_fault_buf_entry_gpc_id_w(void) 1435static inline u32 gmmu_fault_buf_entry_gpc_id_w(void)
1436{ 1436{
1437 return 7; 1437 return 7U;
1438} 1438}
1439static inline u32 gmmu_fault_buf_entry_protected_mode_v(u32 r) 1439static inline u32 gmmu_fault_buf_entry_protected_mode_v(u32 r)
1440{ 1440{
1441 return (r >> 29) & 0x1; 1441 return (r >> 29U) & 0x1U;
1442} 1442}
1443static inline u32 gmmu_fault_buf_entry_protected_mode_w(void) 1443static inline u32 gmmu_fault_buf_entry_protected_mode_w(void)
1444{ 1444{
1445 return 7; 1445 return 7U;
1446} 1446}
1447static inline u32 gmmu_fault_buf_entry_protected_mode_true_v(void) 1447static inline u32 gmmu_fault_buf_entry_protected_mode_true_v(void)
1448{ 1448{
1449 return 0x00000001; 1449 return 0x00000001U;
1450} 1450}
1451static inline u32 gmmu_fault_buf_entry_protected_mode_true_f(void) 1451static inline u32 gmmu_fault_buf_entry_protected_mode_true_f(void)
1452{ 1452{
1453 return 0x20000000; 1453 return 0x20000000U;
1454} 1454}
1455static inline u32 gmmu_fault_buf_entry_replayable_fault_en_v(u32 r) 1455static inline u32 gmmu_fault_buf_entry_replayable_fault_en_v(u32 r)
1456{ 1456{
1457 return (r >> 30) & 0x1; 1457 return (r >> 30U) & 0x1U;
1458} 1458}
1459static inline u32 gmmu_fault_buf_entry_replayable_fault_en_w(void) 1459static inline u32 gmmu_fault_buf_entry_replayable_fault_en_w(void)
1460{ 1460{
1461 return 7; 1461 return 7U;
1462} 1462}
1463static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_v(void) 1463static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_v(void)
1464{ 1464{
1465 return 0x00000001; 1465 return 0x00000001U;
1466} 1466}
1467static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_f(void) 1467static inline u32 gmmu_fault_buf_entry_replayable_fault_en_true_f(void)
1468{ 1468{
1469 return 0x40000000; 1469 return 0x40000000U;
1470} 1470}
1471static inline u32 gmmu_fault_buf_entry_valid_m(void) 1471static inline u32 gmmu_fault_buf_entry_valid_m(void)
1472{ 1472{
1473 return 0x1 << 31; 1473 return 0x1U << 31U;
1474} 1474}
1475static inline u32 gmmu_fault_buf_entry_valid_v(u32 r) 1475static inline u32 gmmu_fault_buf_entry_valid_v(u32 r)
1476{ 1476{
1477 return (r >> 31) & 0x1; 1477 return (r >> 31U) & 0x1U;
1478} 1478}
1479static inline u32 gmmu_fault_buf_entry_valid_w(void) 1479static inline u32 gmmu_fault_buf_entry_valid_w(void)
1480{ 1480{
1481 return 7; 1481 return 7U;
1482} 1482}
1483static inline u32 gmmu_fault_buf_entry_valid_true_v(void) 1483static inline u32 gmmu_fault_buf_entry_valid_true_v(void)
1484{ 1484{
1485 return 0x00000001; 1485 return 0x00000001U;
1486} 1486}
1487static inline u32 gmmu_fault_buf_entry_valid_true_f(void) 1487static inline u32 gmmu_fault_buf_entry_valid_true_f(void)
1488{ 1488{
1489 return 0x80000000; 1489 return 0x80000000U;
1490} 1490}
1491#endif 1491#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index 1af014f6..3bdf2de2 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -58,4858 +58,4858 @@
58 58
59static inline u32 gr_intr_r(void) 59static inline u32 gr_intr_r(void)
60{ 60{
61 return 0x00400100; 61 return 0x00400100U;
62} 62}
63static inline u32 gr_intr_notify_pending_f(void) 63static inline u32 gr_intr_notify_pending_f(void)
64{ 64{
65 return 0x1; 65 return 0x1U;
66} 66}
67static inline u32 gr_intr_notify_reset_f(void) 67static inline u32 gr_intr_notify_reset_f(void)
68{ 68{
69 return 0x1; 69 return 0x1U;
70} 70}
71static inline u32 gr_intr_semaphore_pending_f(void) 71static inline u32 gr_intr_semaphore_pending_f(void)
72{ 72{
73 return 0x2; 73 return 0x2U;
74} 74}
75static inline u32 gr_intr_semaphore_reset_f(void) 75static inline u32 gr_intr_semaphore_reset_f(void)
76{ 76{
77 return 0x2; 77 return 0x2U;
78} 78}
79static inline u32 gr_intr_illegal_method_pending_f(void) 79static inline u32 gr_intr_illegal_method_pending_f(void)
80{ 80{
81 return 0x10; 81 return 0x10U;
82} 82}
83static inline u32 gr_intr_illegal_method_reset_f(void) 83static inline u32 gr_intr_illegal_method_reset_f(void)
84{ 84{
85 return 0x10; 85 return 0x10U;
86} 86}
87static inline u32 gr_intr_illegal_notify_pending_f(void) 87static inline u32 gr_intr_illegal_notify_pending_f(void)
88{ 88{
89 return 0x40; 89 return 0x40U;
90} 90}
91static inline u32 gr_intr_illegal_notify_reset_f(void) 91static inline u32 gr_intr_illegal_notify_reset_f(void)
92{ 92{
93 return 0x40; 93 return 0x40U;
94} 94}
95static inline u32 gr_intr_firmware_method_f(u32 v) 95static inline u32 gr_intr_firmware_method_f(u32 v)
96{ 96{
97 return (v & 0x1) << 8; 97 return (v & 0x1U) << 8U;
98} 98}
99static inline u32 gr_intr_firmware_method_pending_f(void) 99static inline u32 gr_intr_firmware_method_pending_f(void)
100{ 100{
101 return 0x100; 101 return 0x100U;
102} 102}
103static inline u32 gr_intr_firmware_method_reset_f(void) 103static inline u32 gr_intr_firmware_method_reset_f(void)
104{ 104{
105 return 0x100; 105 return 0x100U;
106} 106}
107static inline u32 gr_intr_illegal_class_pending_f(void) 107static inline u32 gr_intr_illegal_class_pending_f(void)
108{ 108{
109 return 0x20; 109 return 0x20U;
110} 110}
111static inline u32 gr_intr_illegal_class_reset_f(void) 111static inline u32 gr_intr_illegal_class_reset_f(void)
112{ 112{
113 return 0x20; 113 return 0x20U;
114} 114}
115static inline u32 gr_intr_fecs_error_pending_f(void) 115static inline u32 gr_intr_fecs_error_pending_f(void)
116{ 116{
117 return 0x80000; 117 return 0x80000U;
118} 118}
119static inline u32 gr_intr_fecs_error_reset_f(void) 119static inline u32 gr_intr_fecs_error_reset_f(void)
120{ 120{
121 return 0x80000; 121 return 0x80000U;
122} 122}
123static inline u32 gr_intr_class_error_pending_f(void) 123static inline u32 gr_intr_class_error_pending_f(void)
124{ 124{
125 return 0x100000; 125 return 0x100000U;
126} 126}
127static inline u32 gr_intr_class_error_reset_f(void) 127static inline u32 gr_intr_class_error_reset_f(void)
128{ 128{
129 return 0x100000; 129 return 0x100000U;
130} 130}
131static inline u32 gr_intr_exception_pending_f(void) 131static inline u32 gr_intr_exception_pending_f(void)
132{ 132{
133 return 0x200000; 133 return 0x200000U;
134} 134}
135static inline u32 gr_intr_exception_reset_f(void) 135static inline u32 gr_intr_exception_reset_f(void)
136{ 136{
137 return 0x200000; 137 return 0x200000U;
138} 138}
139static inline u32 gr_fecs_intr_r(void) 139static inline u32 gr_fecs_intr_r(void)
140{ 140{
141 return 0x00400144; 141 return 0x00400144U;
142} 142}
143static inline u32 gr_class_error_r(void) 143static inline u32 gr_class_error_r(void)
144{ 144{
145 return 0x00400110; 145 return 0x00400110U;
146} 146}
147static inline u32 gr_class_error_code_v(u32 r) 147static inline u32 gr_class_error_code_v(u32 r)
148{ 148{
149 return (r >> 0) & 0xffff; 149 return (r >> 0U) & 0xffffU;
150} 150}
151static inline u32 gr_intr_nonstall_r(void) 151static inline u32 gr_intr_nonstall_r(void)
152{ 152{
153 return 0x00400120; 153 return 0x00400120U;
154} 154}
155static inline u32 gr_intr_nonstall_trap_pending_f(void) 155static inline u32 gr_intr_nonstall_trap_pending_f(void)
156{ 156{
157 return 0x2; 157 return 0x2U;
158} 158}
159static inline u32 gr_intr_en_r(void) 159static inline u32 gr_intr_en_r(void)
160{ 160{
161 return 0x0040013c; 161 return 0x0040013cU;
162} 162}
163static inline u32 gr_exception_r(void) 163static inline u32 gr_exception_r(void)
164{ 164{
165 return 0x00400108; 165 return 0x00400108U;
166} 166}
167static inline u32 gr_exception_fe_m(void) 167static inline u32 gr_exception_fe_m(void)
168{ 168{
169 return 0x1 << 0; 169 return 0x1U << 0U;
170} 170}
171static inline u32 gr_exception_gpc_m(void) 171static inline u32 gr_exception_gpc_m(void)
172{ 172{
173 return 0x1 << 24; 173 return 0x1U << 24U;
174} 174}
175static inline u32 gr_exception_memfmt_m(void) 175static inline u32 gr_exception_memfmt_m(void)
176{ 176{
177 return 0x1 << 1; 177 return 0x1U << 1U;
178} 178}
179static inline u32 gr_exception_ds_m(void) 179static inline u32 gr_exception_ds_m(void)
180{ 180{
181 return 0x1 << 4; 181 return 0x1U << 4U;
182} 182}
183static inline u32 gr_exception_sked_m(void) 183static inline u32 gr_exception_sked_m(void)
184{ 184{
185 return 0x1 << 8; 185 return 0x1U << 8U;
186} 186}
187static inline u32 gr_exception1_r(void) 187static inline u32 gr_exception1_r(void)
188{ 188{
189 return 0x00400118; 189 return 0x00400118U;
190} 190}
191static inline u32 gr_exception1_gpc_0_pending_f(void) 191static inline u32 gr_exception1_gpc_0_pending_f(void)
192{ 192{
193 return 0x1; 193 return 0x1U;
194} 194}
195static inline u32 gr_exception2_r(void) 195static inline u32 gr_exception2_r(void)
196{ 196{
197 return 0x0040011c; 197 return 0x0040011cU;
198} 198}
199static inline u32 gr_exception_en_r(void) 199static inline u32 gr_exception_en_r(void)
200{ 200{
201 return 0x00400138; 201 return 0x00400138U;
202} 202}
203static inline u32 gr_exception_en_fe_m(void) 203static inline u32 gr_exception_en_fe_m(void)
204{ 204{
205 return 0x1 << 0; 205 return 0x1U << 0U;
206} 206}
207static inline u32 gr_exception_en_fe_enabled_f(void) 207static inline u32 gr_exception_en_fe_enabled_f(void)
208{ 208{
209 return 0x1; 209 return 0x1U;
210} 210}
211static inline u32 gr_exception_en_gpc_m(void) 211static inline u32 gr_exception_en_gpc_m(void)
212{ 212{
213 return 0x1 << 24; 213 return 0x1U << 24U;
214} 214}
215static inline u32 gr_exception_en_gpc_enabled_f(void) 215static inline u32 gr_exception_en_gpc_enabled_f(void)
216{ 216{
217 return 0x1000000; 217 return 0x1000000U;
218} 218}
219static inline u32 gr_exception_en_memfmt_m(void) 219static inline u32 gr_exception_en_memfmt_m(void)
220{ 220{
221 return 0x1 << 1; 221 return 0x1U << 1U;
222} 222}
223static inline u32 gr_exception_en_memfmt_enabled_f(void) 223static inline u32 gr_exception_en_memfmt_enabled_f(void)
224{ 224{
225 return 0x2; 225 return 0x2U;
226} 226}
227static inline u32 gr_exception_en_ds_m(void) 227static inline u32 gr_exception_en_ds_m(void)
228{ 228{
229 return 0x1 << 4; 229 return 0x1U << 4U;
230} 230}
231static inline u32 gr_exception_en_ds_enabled_f(void) 231static inline u32 gr_exception_en_ds_enabled_f(void)
232{ 232{
233 return 0x10; 233 return 0x10U;
234} 234}
235static inline u32 gr_exception1_en_r(void) 235static inline u32 gr_exception1_en_r(void)
236{ 236{
237 return 0x00400130; 237 return 0x00400130U;
238} 238}
239static inline u32 gr_exception2_en_r(void) 239static inline u32 gr_exception2_en_r(void)
240{ 240{
241 return 0x00400134; 241 return 0x00400134U;
242} 242}
243static inline u32 gr_gpfifo_ctl_r(void) 243static inline u32 gr_gpfifo_ctl_r(void)
244{ 244{
245 return 0x00400500; 245 return 0x00400500U;
246} 246}
247static inline u32 gr_gpfifo_ctl_access_f(u32 v) 247static inline u32 gr_gpfifo_ctl_access_f(u32 v)
248{ 248{
249 return (v & 0x1) << 0; 249 return (v & 0x1U) << 0U;
250} 250}
251static inline u32 gr_gpfifo_ctl_access_disabled_f(void) 251static inline u32 gr_gpfifo_ctl_access_disabled_f(void)
252{ 252{
253 return 0x0; 253 return 0x0U;
254} 254}
255static inline u32 gr_gpfifo_ctl_access_enabled_f(void) 255static inline u32 gr_gpfifo_ctl_access_enabled_f(void)
256{ 256{
257 return 0x1; 257 return 0x1U;
258} 258}
259static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) 259static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v)
260{ 260{
261 return (v & 0x1) << 16; 261 return (v & 0x1U) << 16U;
262} 262}
263static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) 263static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void)
264{ 264{
265 return 0x00000001; 265 return 0x00000001U;
266} 266}
267static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) 267static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void)
268{ 268{
269 return 0x10000; 269 return 0x10000U;
270} 270}
271static inline u32 gr_gpfifo_status_r(void) 271static inline u32 gr_gpfifo_status_r(void)
272{ 272{
273 return 0x00400504; 273 return 0x00400504U;
274} 274}
275static inline u32 gr_trapped_addr_r(void) 275static inline u32 gr_trapped_addr_r(void)
276{ 276{
277 return 0x00400704; 277 return 0x00400704U;
278} 278}
279static inline u32 gr_trapped_addr_mthd_v(u32 r) 279static inline u32 gr_trapped_addr_mthd_v(u32 r)
280{ 280{
281 return (r >> 2) & 0xfff; 281 return (r >> 2U) & 0xfffU;
282} 282}
283static inline u32 gr_trapped_addr_subch_v(u32 r) 283static inline u32 gr_trapped_addr_subch_v(u32 r)
284{ 284{
285 return (r >> 16) & 0x7; 285 return (r >> 16U) & 0x7U;
286} 286}
287static inline u32 gr_trapped_data_lo_r(void) 287static inline u32 gr_trapped_data_lo_r(void)
288{ 288{
289 return 0x00400708; 289 return 0x00400708U;
290} 290}
291static inline u32 gr_trapped_data_hi_r(void) 291static inline u32 gr_trapped_data_hi_r(void)
292{ 292{
293 return 0x0040070c; 293 return 0x0040070cU;
294} 294}
295static inline u32 gr_status_r(void) 295static inline u32 gr_status_r(void)
296{ 296{
297 return 0x00400700; 297 return 0x00400700U;
298} 298}
299static inline u32 gr_status_fe_method_upper_v(u32 r) 299static inline u32 gr_status_fe_method_upper_v(u32 r)
300{ 300{
301 return (r >> 1) & 0x1; 301 return (r >> 1U) & 0x1U;
302} 302}
303static inline u32 gr_status_fe_method_lower_v(u32 r) 303static inline u32 gr_status_fe_method_lower_v(u32 r)
304{ 304{
305 return (r >> 2) & 0x1; 305 return (r >> 2U) & 0x1U;
306} 306}
307static inline u32 gr_status_fe_method_lower_idle_v(void) 307static inline u32 gr_status_fe_method_lower_idle_v(void)
308{ 308{
309 return 0x00000000; 309 return 0x00000000U;
310} 310}
311static inline u32 gr_status_fe_gi_v(u32 r) 311static inline u32 gr_status_fe_gi_v(u32 r)
312{ 312{
313 return (r >> 21) & 0x1; 313 return (r >> 21U) & 0x1U;
314} 314}
315static inline u32 gr_status_mask_r(void) 315static inline u32 gr_status_mask_r(void)
316{ 316{
317 return 0x00400610; 317 return 0x00400610U;
318} 318}
319static inline u32 gr_status_1_r(void) 319static inline u32 gr_status_1_r(void)
320{ 320{
321 return 0x00400604; 321 return 0x00400604U;
322} 322}
323static inline u32 gr_status_2_r(void) 323static inline u32 gr_status_2_r(void)
324{ 324{
325 return 0x00400608; 325 return 0x00400608U;
326} 326}
327static inline u32 gr_engine_status_r(void) 327static inline u32 gr_engine_status_r(void)
328{ 328{
329 return 0x0040060c; 329 return 0x0040060cU;
330} 330}
331static inline u32 gr_engine_status_value_busy_f(void) 331static inline u32 gr_engine_status_value_busy_f(void)
332{ 332{
333 return 0x1; 333 return 0x1U;
334} 334}
335static inline u32 gr_pri_be0_becs_be_exception_r(void) 335static inline u32 gr_pri_be0_becs_be_exception_r(void)
336{ 336{
337 return 0x00410204; 337 return 0x00410204U;
338} 338}
339static inline u32 gr_pri_be0_becs_be_exception_en_r(void) 339static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
340{ 340{
341 return 0x00410208; 341 return 0x00410208U;
342} 342}
343static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) 343static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
344{ 344{
345 return 0x00502c90; 345 return 0x00502c90U;
346} 346}
347static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) 347static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
348{ 348{
349 return 0x00502c94; 349 return 0x00502c94U;
350} 350}
351static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) 351static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
352{ 352{
353 return 0x00504508; 353 return 0x00504508U;
354} 354}
355static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) 355static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
356{ 356{
357 return 0x0050450c; 357 return 0x0050450cU;
358} 358}
359static inline u32 gr_activity_0_r(void) 359static inline u32 gr_activity_0_r(void)
360{ 360{
361 return 0x00400380; 361 return 0x00400380U;
362} 362}
363static inline u32 gr_activity_1_r(void) 363static inline u32 gr_activity_1_r(void)
364{ 364{
365 return 0x00400384; 365 return 0x00400384U;
366} 366}
367static inline u32 gr_activity_2_r(void) 367static inline u32 gr_activity_2_r(void)
368{ 368{
369 return 0x00400388; 369 return 0x00400388U;
370} 370}
371static inline u32 gr_activity_4_r(void) 371static inline u32 gr_activity_4_r(void)
372{ 372{
373 return 0x00400390; 373 return 0x00400390U;
374} 374}
375static inline u32 gr_activity_4_gpc0_s(void) 375static inline u32 gr_activity_4_gpc0_s(void)
376{ 376{
377 return 3; 377 return 3U;
378} 378}
379static inline u32 gr_activity_4_gpc0_f(u32 v) 379static inline u32 gr_activity_4_gpc0_f(u32 v)
380{ 380{
381 return (v & 0x7) << 0; 381 return (v & 0x7U) << 0U;
382} 382}
383static inline u32 gr_activity_4_gpc0_m(void) 383static inline u32 gr_activity_4_gpc0_m(void)
384{ 384{
385 return 0x7 << 0; 385 return 0x7U << 0U;
386} 386}
387static inline u32 gr_activity_4_gpc0_v(u32 r) 387static inline u32 gr_activity_4_gpc0_v(u32 r)
388{ 388{
389 return (r >> 0) & 0x7; 389 return (r >> 0U) & 0x7U;
390} 390}
391static inline u32 gr_activity_4_gpc0_empty_v(void) 391static inline u32 gr_activity_4_gpc0_empty_v(void)
392{ 392{
393 return 0x00000000; 393 return 0x00000000U;
394} 394}
395static inline u32 gr_activity_4_gpc0_preempted_v(void) 395static inline u32 gr_activity_4_gpc0_preempted_v(void)
396{ 396{
397 return 0x00000004; 397 return 0x00000004U;
398} 398}
399static inline u32 gr_pri_gpc0_gcc_dbg_r(void) 399static inline u32 gr_pri_gpc0_gcc_dbg_r(void)
400{ 400{
401 return 0x00501000; 401 return 0x00501000U;
402} 402}
403static inline u32 gr_pri_gpcs_gcc_dbg_r(void) 403static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
404{ 404{
405 return 0x00419000; 405 return 0x00419000U;
406} 406}
407static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) 407static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
408{ 408{
409 return 0x1 << 1; 409 return 0x1U << 1U;
410} 410}
411static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) 411static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
412{ 412{
413 return 0x0050433c; 413 return 0x0050433cU;
414} 414}
415static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) 415static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
416{ 416{
417 return 0x00419b3c; 417 return 0x00419b3cU;
418} 418}
419static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) 419static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
420{ 420{
421 return 0x1 << 0; 421 return 0x1U << 0U;
422} 422}
423static inline u32 gr_pri_sked_activity_r(void) 423static inline u32 gr_pri_sked_activity_r(void)
424{ 424{
425 return 0x00407054; 425 return 0x00407054U;
426} 426}
427static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) 427static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void)
428{ 428{
429 return 0x00502c80; 429 return 0x00502c80U;
430} 430}
431static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) 431static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void)
432{ 432{
433 return 0x00502c84; 433 return 0x00502c84U;
434} 434}
435static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) 435static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void)
436{ 436{
437 return 0x00502c88; 437 return 0x00502c88U;
438} 438}
439static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) 439static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void)
440{ 440{
441 return 0x00502c8c; 441 return 0x00502c8cU;
442} 442}
443static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) 443static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void)
444{ 444{
445 return 0x00504500; 445 return 0x00504500U;
446} 446}
447static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) 447static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void)
448{ 448{
449 return 0x00504d00; 449 return 0x00504d00U;
450} 450}
451static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) 451static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void)
452{ 452{
453 return 0x00501d00; 453 return 0x00501d00U;
454} 454}
455static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) 455static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void)
456{ 456{
457 return 0x0041ac80; 457 return 0x0041ac80U;
458} 458}
459static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) 459static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void)
460{ 460{
461 return 0x0041ac84; 461 return 0x0041ac84U;
462} 462}
463static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) 463static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void)
464{ 464{
465 return 0x0041ac88; 465 return 0x0041ac88U;
466} 466}
467static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) 467static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void)
468{ 468{
469 return 0x0041ac8c; 469 return 0x0041ac8cU;
470} 470}
471static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) 471static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void)
472{ 472{
473 return 0x0041c500; 473 return 0x0041c500U;
474} 474}
475static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) 475static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void)
476{ 476{
477 return 0x0041cd00; 477 return 0x0041cd00U;
478} 478}
479static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) 479static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void)
480{ 480{
481 return 0x00419d00; 481 return 0x00419d00U;
482} 482}
483static inline u32 gr_pri_be0_becs_be_activity0_r(void) 483static inline u32 gr_pri_be0_becs_be_activity0_r(void)
484{ 484{
485 return 0x00410200; 485 return 0x00410200U;
486} 486}
487static inline u32 gr_pri_be1_becs_be_activity0_r(void) 487static inline u32 gr_pri_be1_becs_be_activity0_r(void)
488{ 488{
489 return 0x00410600; 489 return 0x00410600U;
490} 490}
491static inline u32 gr_pri_bes_becs_be_activity0_r(void) 491static inline u32 gr_pri_bes_becs_be_activity0_r(void)
492{ 492{
493 return 0x00408a00; 493 return 0x00408a00U;
494} 494}
495static inline u32 gr_pri_ds_mpipe_status_r(void) 495static inline u32 gr_pri_ds_mpipe_status_r(void)
496{ 496{
497 return 0x00405858; 497 return 0x00405858U;
498} 498}
499static inline u32 gr_pri_fe_go_idle_info_r(void) 499static inline u32 gr_pri_fe_go_idle_info_r(void)
500{ 500{
501 return 0x00404194; 501 return 0x00404194U;
502} 502}
503static inline u32 gr_pri_fe_chip_def_info_r(void) 503static inline u32 gr_pri_fe_chip_def_info_r(void)
504{ 504{
505 return 0x00404030; 505 return 0x00404030U;
506} 506}
507static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r) 507static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r)
508{ 508{
509 return (r >> 0) & 0xfff; 509 return (r >> 0U) & 0xfffU;
510} 510}
511static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void) 511static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void)
512{ 512{
513 return 0x00000040; 513 return 0x00000040U;
514} 514}
515static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) 515static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
516{ 516{
517 return 0x00504238; 517 return 0x00504238U;
518} 518}
519static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) 519static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void)
520{ 520{
521 return 0x00504358; 521 return 0x00504358U;
522} 522}
523static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) 523static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void)
524{ 524{
525 return 0x1 << 0; 525 return 0x1U << 0U;
526} 526}
527static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) 527static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void)
528{ 528{
529 return 0x1 << 1; 529 return 0x1U << 1U;
530} 530}
531static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) 531static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void)
532{ 532{
533 return 0x1 << 2; 533 return 0x1U << 2U;
534} 534}
535static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) 535static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void)
536{ 536{
537 return 0x1 << 3; 537 return 0x1U << 3U;
538} 538}
539static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) 539static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void)
540{ 540{
541 return 0x1 << 4; 541 return 0x1U << 4U;
542} 542}
543static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) 543static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void)
544{ 544{
545 return 0x1 << 5; 545 return 0x1U << 5U;
546} 546}
547static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) 547static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void)
548{ 548{
549 return 0x1 << 6; 549 return 0x1U << 6U;
550} 550}
551static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) 551static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void)
552{ 552{
553 return 0x1 << 7; 553 return 0x1U << 7U;
554} 554}
555static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) 555static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void)
556{ 556{
557 return 0x1 << 8; 557 return 0x1U << 8U;
558} 558}
559static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) 559static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void)
560{ 560{
561 return 0x1 << 9; 561 return 0x1U << 9U;
562} 562}
563static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) 563static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void)
564{ 564{
565 return 0x1 << 10; 565 return 0x1U << 10U;
566} 566}
567static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) 567static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void)
568{ 568{
569 return 0x1 << 11; 569 return 0x1U << 11U;
570} 570}
571static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) 571static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void)
572{ 572{
573 return 0x1 << 12; 573 return 0x1U << 12U;
574} 574}
575static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) 575static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void)
576{ 576{
577 return 0x1 << 13; 577 return 0x1U << 13U;
578} 578}
579static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) 579static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void)
580{ 580{
581 return 0x1 << 14; 581 return 0x1U << 14U;
582} 582}
583static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) 583static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void)
584{ 584{
585 return 0x1 << 15; 585 return 0x1U << 15U;
586} 586}
587static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) 587static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r)
588{ 588{
589 return (r >> 24) & 0x1; 589 return (r >> 24U) & 0x1U;
590} 590}
591static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) 591static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r)
592{ 592{
593 return (r >> 26) & 0x1; 593 return (r >> 26U) & 0x1U;
594} 594}
595static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) 595static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void)
596{ 596{
597 return 0x40000000; 597 return 0x40000000U;
598} 598}
599static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) 599static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void)
600{ 600{
601 return 0x0050435c; 601 return 0x0050435cU;
602} 602}
603static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) 603static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void)
604{ 604{
605 return 16; 605 return 16U;
606} 606}
607static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) 607static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r)
608{ 608{
609 return (r >> 0) & 0xffff; 609 return (r >> 0U) & 0xffffU;
610} 610}
611static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) 611static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void)
612{ 612{
613 return 0x00504360; 613 return 0x00504360U;
614} 614}
615static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) 615static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void)
616{ 616{
617 return 16; 617 return 16U;
618} 618}
619static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) 619static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r)
620{ 620{
621 return (r >> 0) & 0xffff; 621 return (r >> 0U) & 0xffffU;
622} 622}
623static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) 623static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void)
624{ 624{
625 return 0x0050436c; 625 return 0x0050436cU;
626} 626}
627static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) 627static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void)
628{ 628{
629 return 0x1 << 0; 629 return 0x1U << 0U;
630} 630}
631static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) 631static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void)
632{ 632{
633 return 0x1 << 1; 633 return 0x1U << 1U;
634} 634}
635static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) 635static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void)
636{ 636{
637 return 0x1 << 2; 637 return 0x1U << 2U;
638} 638}
639static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) 639static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void)
640{ 640{
641 return 0x1 << 3; 641 return 0x1U << 3U;
642} 642}
643static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) 643static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r)
644{ 644{
645 return (r >> 8) & 0x1; 645 return (r >> 8U) & 0x1U;
646} 646}
647static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) 647static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r)
648{ 648{
649 return (r >> 10) & 0x1; 649 return (r >> 10U) & 0x1U;
650} 650}
651static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) 651static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void)
652{ 652{
653 return 0x40000000; 653 return 0x40000000U;
654} 654}
655static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) 655static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void)
656{ 656{
657 return 0x00504370; 657 return 0x00504370U;
658} 658}
659static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) 659static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void)
660{ 660{
661 return 16; 661 return 16U;
662} 662}
663static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) 663static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r)
664{ 664{
665 return (r >> 0) & 0xffff; 665 return (r >> 0U) & 0xffffU;
666} 666}
667static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) 667static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void)
668{ 668{
669 return 0x00504374; 669 return 0x00504374U;
670} 670}
671static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) 671static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void)
672{ 672{
673 return 16; 673 return 16U;
674} 674}
675static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) 675static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r)
676{ 676{
677 return (r >> 0) & 0xffff; 677 return (r >> 0U) & 0xffffU;
678} 678}
679static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_r(void) 679static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_r(void)
680{ 680{
681 return 0x0050464c; 681 return 0x0050464cU;
682} 682}
683static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_data_m(void) 683static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_data_m(void)
684{ 684{
685 return 0x1 << 0; 685 return 0x1U << 0U;
686} 686}
687static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_predecode_m(void) 687static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_predecode_m(void)
688{ 688{
689 return 0x1 << 1; 689 return 0x1U << 1U;
690} 690}
691static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m(void) 691static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m(void)
692{ 692{
693 return 0x1 << 2; 693 return 0x1U << 2U;
694} 694}
695static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_predecode_m(void) 695static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_predecode_m(void)
696{ 696{
697 return 0x1 << 3; 697 return 0x1U << 3U;
698} 698}
699static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_data_m(void) 699static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_data_m(void)
700{ 700{
701 return 0x1 << 4; 701 return 0x1U << 4U;
702} 702}
703static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_predecode_m(void) 703static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_predecode_m(void)
704{ 704{
705 return 0x1 << 5; 705 return 0x1U << 5U;
706} 706}
707static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m(void) 707static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m(void)
708{ 708{
709 return 0x1 << 6; 709 return 0x1U << 6U;
710} 710}
711static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_predecode_m(void) 711static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_predecode_m(void)
712{ 712{
713 return 0x1 << 7; 713 return 0x1U << 7U;
714} 714}
715static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_total_counter_overflow_v(u32 r) 715static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_total_counter_overflow_v(u32 r)
716{ 716{
717 return (r >> 16) & 0x1; 717 return (r >> 16U) & 0x1U;
718} 718}
719static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) 719static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r)
720{ 720{
721 return (r >> 18) & 0x1; 721 return (r >> 18U) & 0x1U;
722} 722}
723static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_reset_task_f(void) 723static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_reset_task_f(void)
724{ 724{
725 return 0x40000000; 725 return 0x40000000U;
726} 726}
727static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r(void) 727static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r(void)
728{ 728{
729 return 0x00504650; 729 return 0x00504650U;
730} 730}
731static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s(void) 731static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s(void)
732{ 732{
733 return 16; 733 return 16U;
734} 734}
735static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_v(u32 r) 735static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_v(u32 r)
736{ 736{
737 return (r >> 0) & 0xffff; 737 return (r >> 0U) & 0xffffU;
738} 738}
739static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r(void) 739static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r(void)
740{ 740{
741 return 0x00504654; 741 return 0x00504654U;
742} 742}
743static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s(void) 743static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s(void)
744{ 744{
745 return 16; 745 return 16U;
746} 746}
747static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_v(u32 r) 747static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_v(u32 r)
748{ 748{
749 return (r >> 0) & 0xffff; 749 return (r >> 0U) & 0xffffU;
750} 750}
751static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void) 751static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void)
752{ 752{
753 return 0x00504624; 753 return 0x00504624U;
754} 754}
755static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_0_m(void) 755static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_0_m(void)
756{ 756{
757 return 0x1 << 0; 757 return 0x1U << 0U;
758} 758}
759static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_1_m(void) 759static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_el1_1_m(void)
760{ 760{
761 return 0x1 << 1; 761 return 0x1U << 1U;
762} 762}
763static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_0_m(void) 763static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_0_m(void)
764{ 764{
765 return 0x1 << 2; 765 return 0x1U << 2U;
766} 766}
767static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_1_m(void) 767static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_el1_1_m(void)
768{ 768{
769 return 0x1 << 3; 769 return 0x1U << 3U;
770} 770}
771static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_pixrpf_m(void) 771static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_pixrpf_m(void)
772{ 772{
773 return 0x1 << 4; 773 return 0x1U << 4U;
774} 774}
775static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_miss_fifo_m(void) 775static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_miss_fifo_m(void)
776{ 776{
777 return 0x1 << 5; 777 return 0x1U << 5U;
778} 778}
779static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m(void) 779static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m(void)
780{ 780{
781 return 0x1 << 6; 781 return 0x1U << 6U;
782} 782}
783static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m(void) 783static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m(void)
784{ 784{
785 return 0x1 << 7; 785 return 0x1U << 7U;
786} 786}
787static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_total_counter_overflow_v(u32 r) 787static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_corrected_err_total_counter_overflow_v(u32 r)
788{ 788{
789 return (r >> 8) & 0x1; 789 return (r >> 8U) & 0x1U;
790} 790}
791static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) 791static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r)
792{ 792{
793 return (r >> 10) & 0x1; 793 return (r >> 10U) & 0x1U;
794} 794}
795static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_reset_task_f(void) 795static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_reset_task_f(void)
796{ 796{
797 return 0x40000000; 797 return 0x40000000U;
798} 798}
799static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r(void) 799static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r(void)
800{ 800{
801 return 0x00504628; 801 return 0x00504628U;
802} 802}
803static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s(void) 803static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s(void)
804{ 804{
805 return 16; 805 return 16U;
806} 806}
807static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_v(u32 r) 807static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_v(u32 r)
808{ 808{
809 return (r >> 0) & 0xffff; 809 return (r >> 0U) & 0xffffU;
810} 810}
811static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r(void) 811static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r(void)
812{ 812{
813 return 0x0050462c; 813 return 0x0050462cU;
814} 814}
815static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s(void) 815static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s(void)
816{ 816{
817 return 16; 817 return 16U;
818} 818}
819static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_v(u32 r) 819static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_v(u32 r)
820{ 820{
821 return (r >> 0) & 0xffff; 821 return (r >> 0U) & 0xffffU;
822} 822}
823static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) 823static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void)
824{ 824{
825 return 0x00504638; 825 return 0x00504638U;
826} 826}
827static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) 827static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void)
828{ 828{
829 return 0x1 << 0; 829 return 0x1U << 0U;
830} 830}
831static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) 831static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void)
832{ 832{
833 return 0x1 << 1; 833 return 0x1U << 1U;
834} 834}
835static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) 835static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void)
836{ 836{
837 return 0x1 << 2; 837 return 0x1U << 2U;
838} 838}
839static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) 839static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void)
840{ 840{
841 return 0x1 << 3; 841 return 0x1U << 3U;
842} 842}
843static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) 843static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void)
844{ 844{
845 return 0x1 << 4; 845 return 0x1U << 4U;
846} 846}
847static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) 847static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void)
848{ 848{
849 return 0x1 << 5; 849 return 0x1U << 5U;
850} 850}
851static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) 851static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void)
852{ 852{
853 return 0x1 << 6; 853 return 0x1U << 6U;
854} 854}
855static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) 855static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void)
856{ 856{
857 return 0x1 << 7; 857 return 0x1U << 7U;
858} 858}
859static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) 859static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r)
860{ 860{
861 return (r >> 16) & 0x1; 861 return (r >> 16U) & 0x1U;
862} 862}
863static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) 863static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r)
864{ 864{
865 return (r >> 18) & 0x1; 865 return (r >> 18U) & 0x1U;
866} 866}
867static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) 867static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void)
868{ 868{
869 return 0x40000000; 869 return 0x40000000U;
870} 870}
871static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) 871static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void)
872{ 872{
873 return 0x0050463c; 873 return 0x0050463cU;
874} 874}
875static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) 875static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void)
876{ 876{
877 return 16; 877 return 16U;
878} 878}
879static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) 879static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r)
880{ 880{
881 return (r >> 0) & 0xffff; 881 return (r >> 0U) & 0xffffU;
882} 882}
883static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) 883static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void)
884{ 884{
885 return 0x00504640; 885 return 0x00504640U;
886} 886}
887static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) 887static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void)
888{ 888{
889 return 16; 889 return 16U;
890} 890}
891static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) 891static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r)
892{ 892{
893 return (r >> 0) & 0xffff; 893 return (r >> 0U) & 0xffffU;
894} 894}
895static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) 895static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void)
896{ 896{
897 return 0x005042c4; 897 return 0x005042c4U;
898} 898}
899static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) 899static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void)
900{ 900{
901 return 0x0; 901 return 0x0U;
902} 902}
903static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) 903static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void)
904{ 904{
905 return 0x1; 905 return 0x1U;
906} 906}
907static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) 907static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void)
908{ 908{
909 return 0x2; 909 return 0x2U;
910} 910}
911static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void) 911static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void)
912{ 912{
913 return 0x00504430; 913 return 0x00504430U;
914} 914}
915static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void) 915static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void)
916{ 916{
917 return 0x40000000; 917 return 0x40000000U;
918} 918}
919static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void) 919static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void)
920{ 920{
921 return 0x00504434; 921 return 0x00504434U;
922} 922}
923static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r) 923static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r)
924{ 924{
925 return (r >> 0) & 0x3f; 925 return (r >> 0U) & 0x3fU;
926} 926}
927static inline u32 gr_pri_be0_crop_status1_r(void) 927static inline u32 gr_pri_be0_crop_status1_r(void)
928{ 928{
929 return 0x00410134; 929 return 0x00410134U;
930} 930}
931static inline u32 gr_pri_bes_crop_status1_r(void) 931static inline u32 gr_pri_bes_crop_status1_r(void)
932{ 932{
933 return 0x00408934; 933 return 0x00408934U;
934} 934}
935static inline u32 gr_pri_be0_zrop_status_r(void) 935static inline u32 gr_pri_be0_zrop_status_r(void)
936{ 936{
937 return 0x00410048; 937 return 0x00410048U;
938} 938}
939static inline u32 gr_pri_be0_zrop_status2_r(void) 939static inline u32 gr_pri_be0_zrop_status2_r(void)
940{ 940{
941 return 0x0041004c; 941 return 0x0041004cU;
942} 942}
943static inline u32 gr_pri_bes_zrop_status_r(void) 943static inline u32 gr_pri_bes_zrop_status_r(void)
944{ 944{
945 return 0x00408848; 945 return 0x00408848U;
946} 946}
947static inline u32 gr_pri_bes_zrop_status2_r(void) 947static inline u32 gr_pri_bes_zrop_status2_r(void)
948{ 948{
949 return 0x0040884c; 949 return 0x0040884cU;
950} 950}
951static inline u32 gr_pipe_bundle_address_r(void) 951static inline u32 gr_pipe_bundle_address_r(void)
952{ 952{
953 return 0x00400200; 953 return 0x00400200U;
954} 954}
955static inline u32 gr_pipe_bundle_address_value_v(u32 r) 955static inline u32 gr_pipe_bundle_address_value_v(u32 r)
956{ 956{
957 return (r >> 0) & 0xffff; 957 return (r >> 0U) & 0xffffU;
958} 958}
959static inline u32 gr_pipe_bundle_address_veid_f(u32 v) 959static inline u32 gr_pipe_bundle_address_veid_f(u32 v)
960{ 960{
961 return (v & 0x3f) << 20; 961 return (v & 0x3fU) << 20U;
962} 962}
963static inline u32 gr_pipe_bundle_address_veid_w(void) 963static inline u32 gr_pipe_bundle_address_veid_w(void)
964{ 964{
965 return 0; 965 return 0U;
966} 966}
967static inline u32 gr_pipe_bundle_data_r(void) 967static inline u32 gr_pipe_bundle_data_r(void)
968{ 968{
969 return 0x00400204; 969 return 0x00400204U;
970} 970}
971static inline u32 gr_pipe_bundle_config_r(void) 971static inline u32 gr_pipe_bundle_config_r(void)
972{ 972{
973 return 0x00400208; 973 return 0x00400208U;
974} 974}
975static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) 975static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void)
976{ 976{
977 return 0x0; 977 return 0x0U;
978} 978}
979static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) 979static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void)
980{ 980{
981 return 0x80000000; 981 return 0x80000000U;
982} 982}
983static inline u32 gr_fe_hww_esr_r(void) 983static inline u32 gr_fe_hww_esr_r(void)
984{ 984{
985 return 0x00404000; 985 return 0x00404000U;
986} 986}
987static inline u32 gr_fe_hww_esr_reset_active_f(void) 987static inline u32 gr_fe_hww_esr_reset_active_f(void)
988{ 988{
989 return 0x40000000; 989 return 0x40000000U;
990} 990}
991static inline u32 gr_fe_hww_esr_en_enable_f(void) 991static inline u32 gr_fe_hww_esr_en_enable_f(void)
992{ 992{
993 return 0x80000000; 993 return 0x80000000U;
994} 994}
995static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void) 995static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void)
996{ 996{
997 return 0x00419eac; 997 return 0x00419eacU;
998} 998}
999static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void) 999static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void)
1000{ 1000{
1001 return 0x0050472c; 1001 return 0x0050472cU;
1002} 1002}
1003static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) 1003static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
1004{ 1004{
1005 return 0x4; 1005 return 0x4U;
1006} 1006}
1007static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) 1007static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void)
1008{ 1008{
1009 return 0x10; 1009 return 0x10U;
1010} 1010}
1011static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) 1011static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void)
1012{ 1012{
1013 return 0x20; 1013 return 0x20U;
1014} 1014}
1015static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) 1015static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void)
1016{ 1016{
1017 return 0x40; 1017 return 0x40U;
1018} 1018}
1019static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void) 1019static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void)
1020{ 1020{
1021 return 0x100; 1021 return 0x100U;
1022} 1022}
1023static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void) 1023static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void)
1024{ 1024{
1025 return 0x00419eb4; 1025 return 0x00419eb4U;
1026} 1026}
1027static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) 1027static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void)
1028{ 1028{
1029 return 0x00504734; 1029 return 0x00504734U;
1030} 1030}
1031static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void) 1031static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void)
1032{ 1032{
1033 return 0x1 << 4; 1033 return 0x1U << 4U;
1034} 1034}
1035static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) 1035static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void)
1036{ 1036{
1037 return 0x10; 1037 return 0x10U;
1038} 1038}
1039static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void) 1039static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void)
1040{ 1040{
1041 return 0x1 << 5; 1041 return 0x1U << 5U;
1042} 1042}
1043static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) 1043static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void)
1044{ 1044{
1045 return 0x20; 1045 return 0x20U;
1046} 1046}
1047static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void) 1047static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void)
1048{ 1048{
1049 return 0x1 << 6; 1049 return 0x1U << 6U;
1050} 1050}
1051static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) 1051static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void)
1052{ 1052{
1053 return 0x40; 1053 return 0x40U;
1054} 1054}
1055static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void) 1055static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void)
1056{ 1056{
1057 return 0x1 << 2; 1057 return 0x1U << 2U;
1058} 1058}
1059static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) 1059static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void)
1060{ 1060{
1061 return 0x4; 1061 return 0x4U;
1062} 1062}
1063static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void) 1063static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void)
1064{ 1064{
1065 return 0x1 << 8; 1065 return 0x1U << 8U;
1066} 1066}
1067static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void) 1067static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void)
1068{ 1068{
1069 return 0x100; 1069 return 0x100U;
1070} 1070}
1071static inline u32 gr_fe_go_idle_timeout_r(void) 1071static inline u32 gr_fe_go_idle_timeout_r(void)
1072{ 1072{
1073 return 0x00404154; 1073 return 0x00404154U;
1074} 1074}
1075static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) 1075static inline u32 gr_fe_go_idle_timeout_count_f(u32 v)
1076{ 1076{
1077 return (v & 0xffffffff) << 0; 1077 return (v & 0xffffffffU) << 0U;
1078} 1078}
1079static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) 1079static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
1080{ 1080{
1081 return 0x0; 1081 return 0x0U;
1082} 1082}
1083static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) 1083static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
1084{ 1084{
1085 return 0x1800; 1085 return 0x1800U;
1086} 1086}
1087static inline u32 gr_fe_object_table_r(u32 i) 1087static inline u32 gr_fe_object_table_r(u32 i)
1088{ 1088{
1089 return 0x00404200 + i*4; 1089 return 0x00404200U + i*4U;
1090} 1090}
1091static inline u32 gr_fe_object_table_nvclass_v(u32 r) 1091static inline u32 gr_fe_object_table_nvclass_v(u32 r)
1092{ 1092{
1093 return (r >> 0) & 0xffff; 1093 return (r >> 0U) & 0xffffU;
1094} 1094}
1095static inline u32 gr_fe_tpc_fs_r(u32 i) 1095static inline u32 gr_fe_tpc_fs_r(u32 i)
1096{ 1096{
1097 return 0x0040a200 + i*4; 1097 return 0x0040a200U + i*4U;
1098} 1098}
1099static inline u32 gr_pri_mme_shadow_raw_index_r(void) 1099static inline u32 gr_pri_mme_shadow_raw_index_r(void)
1100{ 1100{
1101 return 0x00404488; 1101 return 0x00404488U;
1102} 1102}
1103static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) 1103static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void)
1104{ 1104{
1105 return 0x80000000; 1105 return 0x80000000U;
1106} 1106}
1107static inline u32 gr_pri_mme_shadow_raw_data_r(void) 1107static inline u32 gr_pri_mme_shadow_raw_data_r(void)
1108{ 1108{
1109 return 0x0040448c; 1109 return 0x0040448cU;
1110} 1110}
1111static inline u32 gr_mme_hww_esr_r(void) 1111static inline u32 gr_mme_hww_esr_r(void)
1112{ 1112{
1113 return 0x00404490; 1113 return 0x00404490U;
1114} 1114}
1115static inline u32 gr_mme_hww_esr_reset_active_f(void) 1115static inline u32 gr_mme_hww_esr_reset_active_f(void)
1116{ 1116{
1117 return 0x40000000; 1117 return 0x40000000U;
1118} 1118}
1119static inline u32 gr_mme_hww_esr_en_enable_f(void) 1119static inline u32 gr_mme_hww_esr_en_enable_f(void)
1120{ 1120{
1121 return 0x80000000; 1121 return 0x80000000U;
1122} 1122}
1123static inline u32 gr_memfmt_hww_esr_r(void) 1123static inline u32 gr_memfmt_hww_esr_r(void)
1124{ 1124{
1125 return 0x00404600; 1125 return 0x00404600U;
1126} 1126}
1127static inline u32 gr_memfmt_hww_esr_reset_active_f(void) 1127static inline u32 gr_memfmt_hww_esr_reset_active_f(void)
1128{ 1128{
1129 return 0x40000000; 1129 return 0x40000000U;
1130} 1130}
1131static inline u32 gr_memfmt_hww_esr_en_enable_f(void) 1131static inline u32 gr_memfmt_hww_esr_en_enable_f(void)
1132{ 1132{
1133 return 0x80000000; 1133 return 0x80000000U;
1134} 1134}
1135static inline u32 gr_fecs_cpuctl_r(void) 1135static inline u32 gr_fecs_cpuctl_r(void)
1136{ 1136{
1137 return 0x00409100; 1137 return 0x00409100U;
1138} 1138}
1139static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) 1139static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v)
1140{ 1140{
1141 return (v & 0x1) << 1; 1141 return (v & 0x1U) << 1U;
1142} 1142}
1143static inline u32 gr_fecs_cpuctl_alias_r(void) 1143static inline u32 gr_fecs_cpuctl_alias_r(void)
1144{ 1144{
1145 return 0x00409130; 1145 return 0x00409130U;
1146} 1146}
1147static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) 1147static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v)
1148{ 1148{
1149 return (v & 0x1) << 1; 1149 return (v & 0x1U) << 1U;
1150} 1150}
1151static inline u32 gr_fecs_dmactl_r(void) 1151static inline u32 gr_fecs_dmactl_r(void)
1152{ 1152{
1153 return 0x0040910c; 1153 return 0x0040910cU;
1154} 1154}
1155static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) 1155static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
1156{ 1156{
1157 return (v & 0x1) << 0; 1157 return (v & 0x1U) << 0U;
1158} 1158}
1159static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) 1159static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
1160{ 1160{
1161 return 0x1 << 1; 1161 return 0x1U << 1U;
1162} 1162}
1163static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) 1163static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
1164{ 1164{
1165 return 0x1 << 2; 1165 return 0x1U << 2U;
1166} 1166}
1167static inline u32 gr_fecs_os_r(void) 1167static inline u32 gr_fecs_os_r(void)
1168{ 1168{
1169 return 0x00409080; 1169 return 0x00409080U;
1170} 1170}
1171static inline u32 gr_fecs_idlestate_r(void) 1171static inline u32 gr_fecs_idlestate_r(void)
1172{ 1172{
1173 return 0x0040904c; 1173 return 0x0040904cU;
1174} 1174}
1175static inline u32 gr_fecs_mailbox0_r(void) 1175static inline u32 gr_fecs_mailbox0_r(void)
1176{ 1176{
1177 return 0x00409040; 1177 return 0x00409040U;
1178} 1178}
1179static inline u32 gr_fecs_mailbox1_r(void) 1179static inline u32 gr_fecs_mailbox1_r(void)
1180{ 1180{
1181 return 0x00409044; 1181 return 0x00409044U;
1182} 1182}
1183static inline u32 gr_fecs_irqstat_r(void) 1183static inline u32 gr_fecs_irqstat_r(void)
1184{ 1184{
1185 return 0x00409008; 1185 return 0x00409008U;
1186} 1186}
1187static inline u32 gr_fecs_irqmode_r(void) 1187static inline u32 gr_fecs_irqmode_r(void)
1188{ 1188{
1189 return 0x0040900c; 1189 return 0x0040900cU;
1190} 1190}
1191static inline u32 gr_fecs_irqmask_r(void) 1191static inline u32 gr_fecs_irqmask_r(void)
1192{ 1192{
1193 return 0x00409018; 1193 return 0x00409018U;
1194} 1194}
1195static inline u32 gr_fecs_irqdest_r(void) 1195static inline u32 gr_fecs_irqdest_r(void)
1196{ 1196{
1197 return 0x0040901c; 1197 return 0x0040901cU;
1198} 1198}
1199static inline u32 gr_fecs_curctx_r(void) 1199static inline u32 gr_fecs_curctx_r(void)
1200{ 1200{
1201 return 0x00409050; 1201 return 0x00409050U;
1202} 1202}
1203static inline u32 gr_fecs_nxtctx_r(void) 1203static inline u32 gr_fecs_nxtctx_r(void)
1204{ 1204{
1205 return 0x00409054; 1205 return 0x00409054U;
1206} 1206}
1207static inline u32 gr_fecs_engctl_r(void) 1207static inline u32 gr_fecs_engctl_r(void)
1208{ 1208{
1209 return 0x004090a4; 1209 return 0x004090a4U;
1210} 1210}
1211static inline u32 gr_fecs_debug1_r(void) 1211static inline u32 gr_fecs_debug1_r(void)
1212{ 1212{
1213 return 0x00409090; 1213 return 0x00409090U;
1214} 1214}
1215static inline u32 gr_fecs_debuginfo_r(void) 1215static inline u32 gr_fecs_debuginfo_r(void)
1216{ 1216{
1217 return 0x00409094; 1217 return 0x00409094U;
1218} 1218}
1219static inline u32 gr_fecs_icd_cmd_r(void) 1219static inline u32 gr_fecs_icd_cmd_r(void)
1220{ 1220{
1221 return 0x00409200; 1221 return 0x00409200U;
1222} 1222}
1223static inline u32 gr_fecs_icd_cmd_opc_s(void) 1223static inline u32 gr_fecs_icd_cmd_opc_s(void)
1224{ 1224{
1225 return 4; 1225 return 4U;
1226} 1226}
1227static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) 1227static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
1228{ 1228{
1229 return (v & 0xf) << 0; 1229 return (v & 0xfU) << 0U;
1230} 1230}
1231static inline u32 gr_fecs_icd_cmd_opc_m(void) 1231static inline u32 gr_fecs_icd_cmd_opc_m(void)
1232{ 1232{
1233 return 0xf << 0; 1233 return 0xfU << 0U;
1234} 1234}
1235static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) 1235static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
1236{ 1236{
1237 return (r >> 0) & 0xf; 1237 return (r >> 0U) & 0xfU;
1238} 1238}
1239static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) 1239static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void)
1240{ 1240{
1241 return 0x8; 1241 return 0x8U;
1242} 1242}
1243static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) 1243static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void)
1244{ 1244{
1245 return 0xe; 1245 return 0xeU;
1246} 1246}
1247static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) 1247static inline u32 gr_fecs_icd_cmd_idx_f(u32 v)
1248{ 1248{
1249 return (v & 0x1f) << 8; 1249 return (v & 0x1fU) << 8U;
1250} 1250}
1251static inline u32 gr_fecs_icd_rdata_r(void) 1251static inline u32 gr_fecs_icd_rdata_r(void)
1252{ 1252{
1253 return 0x0040920c; 1253 return 0x0040920cU;
1254} 1254}
1255static inline u32 gr_fecs_imemc_r(u32 i) 1255static inline u32 gr_fecs_imemc_r(u32 i)
1256{ 1256{
1257 return 0x00409180 + i*16; 1257 return 0x00409180U + i*16U;
1258} 1258}
1259static inline u32 gr_fecs_imemc_offs_f(u32 v) 1259static inline u32 gr_fecs_imemc_offs_f(u32 v)
1260{ 1260{
1261 return (v & 0x3f) << 2; 1261 return (v & 0x3fU) << 2U;
1262} 1262}
1263static inline u32 gr_fecs_imemc_blk_f(u32 v) 1263static inline u32 gr_fecs_imemc_blk_f(u32 v)
1264{ 1264{
1265 return (v & 0xff) << 8; 1265 return (v & 0xffU) << 8U;
1266} 1266}
1267static inline u32 gr_fecs_imemc_aincw_f(u32 v) 1267static inline u32 gr_fecs_imemc_aincw_f(u32 v)
1268{ 1268{
1269 return (v & 0x1) << 24; 1269 return (v & 0x1U) << 24U;
1270} 1270}
1271static inline u32 gr_fecs_imemd_r(u32 i) 1271static inline u32 gr_fecs_imemd_r(u32 i)
1272{ 1272{
1273 return 0x00409184 + i*16; 1273 return 0x00409184U + i*16U;
1274} 1274}
1275static inline u32 gr_fecs_imemt_r(u32 i) 1275static inline u32 gr_fecs_imemt_r(u32 i)
1276{ 1276{
1277 return 0x00409188 + i*16; 1277 return 0x00409188U + i*16U;
1278} 1278}
1279static inline u32 gr_fecs_imemt_tag_f(u32 v) 1279static inline u32 gr_fecs_imemt_tag_f(u32 v)
1280{ 1280{
1281 return (v & 0xffff) << 0; 1281 return (v & 0xffffU) << 0U;
1282} 1282}
1283static inline u32 gr_fecs_dmemc_r(u32 i) 1283static inline u32 gr_fecs_dmemc_r(u32 i)
1284{ 1284{
1285 return 0x004091c0 + i*8; 1285 return 0x004091c0U + i*8U;
1286} 1286}
1287static inline u32 gr_fecs_dmemc_offs_s(void) 1287static inline u32 gr_fecs_dmemc_offs_s(void)
1288{ 1288{
1289 return 6; 1289 return 6U;
1290} 1290}
1291static inline u32 gr_fecs_dmemc_offs_f(u32 v) 1291static inline u32 gr_fecs_dmemc_offs_f(u32 v)
1292{ 1292{
1293 return (v & 0x3f) << 2; 1293 return (v & 0x3fU) << 2U;
1294} 1294}
1295static inline u32 gr_fecs_dmemc_offs_m(void) 1295static inline u32 gr_fecs_dmemc_offs_m(void)
1296{ 1296{
1297 return 0x3f << 2; 1297 return 0x3fU << 2U;
1298} 1298}
1299static inline u32 gr_fecs_dmemc_offs_v(u32 r) 1299static inline u32 gr_fecs_dmemc_offs_v(u32 r)
1300{ 1300{
1301 return (r >> 2) & 0x3f; 1301 return (r >> 2U) & 0x3fU;
1302} 1302}
1303static inline u32 gr_fecs_dmemc_blk_f(u32 v) 1303static inline u32 gr_fecs_dmemc_blk_f(u32 v)
1304{ 1304{
1305 return (v & 0xff) << 8; 1305 return (v & 0xffU) << 8U;
1306} 1306}
1307static inline u32 gr_fecs_dmemc_aincw_f(u32 v) 1307static inline u32 gr_fecs_dmemc_aincw_f(u32 v)
1308{ 1308{
1309 return (v & 0x1) << 24; 1309 return (v & 0x1U) << 24U;
1310} 1310}
1311static inline u32 gr_fecs_dmemd_r(u32 i) 1311static inline u32 gr_fecs_dmemd_r(u32 i)
1312{ 1312{
1313 return 0x004091c4 + i*8; 1313 return 0x004091c4U + i*8U;
1314} 1314}
1315static inline u32 gr_fecs_dmatrfbase_r(void) 1315static inline u32 gr_fecs_dmatrfbase_r(void)
1316{ 1316{
1317 return 0x00409110; 1317 return 0x00409110U;
1318} 1318}
1319static inline u32 gr_fecs_dmatrfmoffs_r(void) 1319static inline u32 gr_fecs_dmatrfmoffs_r(void)
1320{ 1320{
1321 return 0x00409114; 1321 return 0x00409114U;
1322} 1322}
1323static inline u32 gr_fecs_dmatrffboffs_r(void) 1323static inline u32 gr_fecs_dmatrffboffs_r(void)
1324{ 1324{
1325 return 0x0040911c; 1325 return 0x0040911cU;
1326} 1326}
1327static inline u32 gr_fecs_dmatrfcmd_r(void) 1327static inline u32 gr_fecs_dmatrfcmd_r(void)
1328{ 1328{
1329 return 0x00409118; 1329 return 0x00409118U;
1330} 1330}
1331static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) 1331static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v)
1332{ 1332{
1333 return (v & 0x1) << 4; 1333 return (v & 0x1U) << 4U;
1334} 1334}
1335static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) 1335static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v)
1336{ 1336{
1337 return (v & 0x1) << 5; 1337 return (v & 0x1U) << 5U;
1338} 1338}
1339static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) 1339static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v)
1340{ 1340{
1341 return (v & 0x7) << 8; 1341 return (v & 0x7U) << 8U;
1342} 1342}
1343static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) 1343static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v)
1344{ 1344{
1345 return (v & 0x7) << 12; 1345 return (v & 0x7U) << 12U;
1346} 1346}
1347static inline u32 gr_fecs_bootvec_r(void) 1347static inline u32 gr_fecs_bootvec_r(void)
1348{ 1348{
1349 return 0x00409104; 1349 return 0x00409104U;
1350} 1350}
1351static inline u32 gr_fecs_bootvec_vec_f(u32 v) 1351static inline u32 gr_fecs_bootvec_vec_f(u32 v)
1352{ 1352{
1353 return (v & 0xffffffff) << 0; 1353 return (v & 0xffffffffU) << 0U;
1354} 1354}
1355static inline u32 gr_fecs_falcon_hwcfg_r(void) 1355static inline u32 gr_fecs_falcon_hwcfg_r(void)
1356{ 1356{
1357 return 0x00409108; 1357 return 0x00409108U;
1358} 1358}
1359static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) 1359static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
1360{ 1360{
1361 return 0x0041a108; 1361 return 0x0041a108U;
1362} 1362}
1363static inline u32 gr_fecs_falcon_rm_r(void) 1363static inline u32 gr_fecs_falcon_rm_r(void)
1364{ 1364{
1365 return 0x00409084; 1365 return 0x00409084U;
1366} 1366}
1367static inline u32 gr_fecs_current_ctx_r(void) 1367static inline u32 gr_fecs_current_ctx_r(void)
1368{ 1368{
1369 return 0x00409b00; 1369 return 0x00409b00U;
1370} 1370}
1371static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) 1371static inline u32 gr_fecs_current_ctx_ptr_f(u32 v)
1372{ 1372{
1373 return (v & 0xfffffff) << 0; 1373 return (v & 0xfffffffU) << 0U;
1374} 1374}
1375static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) 1375static inline u32 gr_fecs_current_ctx_ptr_v(u32 r)
1376{ 1376{
1377 return (r >> 0) & 0xfffffff; 1377 return (r >> 0U) & 0xfffffffU;
1378} 1378}
1379static inline u32 gr_fecs_current_ctx_target_s(void) 1379static inline u32 gr_fecs_current_ctx_target_s(void)
1380{ 1380{
1381 return 2; 1381 return 2U;
1382} 1382}
1383static inline u32 gr_fecs_current_ctx_target_f(u32 v) 1383static inline u32 gr_fecs_current_ctx_target_f(u32 v)
1384{ 1384{
1385 return (v & 0x3) << 28; 1385 return (v & 0x3U) << 28U;
1386} 1386}
1387static inline u32 gr_fecs_current_ctx_target_m(void) 1387static inline u32 gr_fecs_current_ctx_target_m(void)
1388{ 1388{
1389 return 0x3 << 28; 1389 return 0x3U << 28U;
1390} 1390}
1391static inline u32 gr_fecs_current_ctx_target_v(u32 r) 1391static inline u32 gr_fecs_current_ctx_target_v(u32 r)
1392{ 1392{
1393 return (r >> 28) & 0x3; 1393 return (r >> 28U) & 0x3U;
1394} 1394}
1395static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) 1395static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void)
1396{ 1396{
1397 return 0x0; 1397 return 0x0U;
1398} 1398}
1399static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void) 1399static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void)
1400{ 1400{
1401 return 0x20000000; 1401 return 0x20000000U;
1402} 1402}
1403static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void) 1403static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void)
1404{ 1404{
1405 return 0x30000000; 1405 return 0x30000000U;
1406} 1406}
1407static inline u32 gr_fecs_current_ctx_valid_s(void) 1407static inline u32 gr_fecs_current_ctx_valid_s(void)
1408{ 1408{
1409 return 1; 1409 return 1U;
1410} 1410}
1411static inline u32 gr_fecs_current_ctx_valid_f(u32 v) 1411static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
1412{ 1412{
1413 return (v & 0x1) << 31; 1413 return (v & 0x1U) << 31U;
1414} 1414}
1415static inline u32 gr_fecs_current_ctx_valid_m(void) 1415static inline u32 gr_fecs_current_ctx_valid_m(void)
1416{ 1416{
1417 return 0x1 << 31; 1417 return 0x1U << 31U;
1418} 1418}
1419static inline u32 gr_fecs_current_ctx_valid_v(u32 r) 1419static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
1420{ 1420{
1421 return (r >> 31) & 0x1; 1421 return (r >> 31U) & 0x1U;
1422} 1422}
1423static inline u32 gr_fecs_current_ctx_valid_false_f(void) 1423static inline u32 gr_fecs_current_ctx_valid_false_f(void)
1424{ 1424{
1425 return 0x0; 1425 return 0x0U;
1426} 1426}
1427static inline u32 gr_fecs_method_data_r(void) 1427static inline u32 gr_fecs_method_data_r(void)
1428{ 1428{
1429 return 0x00409500; 1429 return 0x00409500U;
1430} 1430}
1431static inline u32 gr_fecs_method_push_r(void) 1431static inline u32 gr_fecs_method_push_r(void)
1432{ 1432{
1433 return 0x00409504; 1433 return 0x00409504U;
1434} 1434}
1435static inline u32 gr_fecs_method_push_adr_f(u32 v) 1435static inline u32 gr_fecs_method_push_adr_f(u32 v)
1436{ 1436{
1437 return (v & 0xfff) << 0; 1437 return (v & 0xfffU) << 0U;
1438} 1438}
1439static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) 1439static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void)
1440{ 1440{
1441 return 0x00000003; 1441 return 0x00000003U;
1442} 1442}
1443static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) 1443static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void)
1444{ 1444{
1445 return 0x3; 1445 return 0x3U;
1446} 1446}
1447static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) 1447static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void)
1448{ 1448{
1449 return 0x00000010; 1449 return 0x00000010U;
1450} 1450}
1451static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) 1451static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void)
1452{ 1452{
1453 return 0x00000009; 1453 return 0x00000009U;
1454} 1454}
1455static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) 1455static inline u32 gr_fecs_method_push_adr_restore_golden_v(void)
1456{ 1456{
1457 return 0x00000015; 1457 return 0x00000015U;
1458} 1458}
1459static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) 1459static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void)
1460{ 1460{
1461 return 0x00000016; 1461 return 0x00000016U;
1462} 1462}
1463static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) 1463static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void)
1464{ 1464{
1465 return 0x00000025; 1465 return 0x00000025U;
1466} 1466}
1467static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) 1467static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void)
1468{ 1468{
1469 return 0x00000030; 1469 return 0x00000030U;
1470} 1470}
1471static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) 1471static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void)
1472{ 1472{
1473 return 0x00000031; 1473 return 0x00000031U;
1474} 1474}
1475static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) 1475static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void)
1476{ 1476{
1477 return 0x00000032; 1477 return 0x00000032U;
1478} 1478}
1479static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) 1479static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void)
1480{ 1480{
1481 return 0x00000038; 1481 return 0x00000038U;
1482} 1482}
1483static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) 1483static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void)
1484{ 1484{
1485 return 0x00000039; 1485 return 0x00000039U;
1486} 1486}
1487static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) 1487static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
1488{ 1488{
1489 return 0x21; 1489 return 0x21U;
1490} 1490}
1491static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) 1491static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void)
1492{ 1492{
1493 return 0x0000001a; 1493 return 0x0000001aU;
1494} 1494}
1495static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) 1495static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
1496{ 1496{
1497 return 0x00000004; 1497 return 0x00000004U;
1498} 1498}
1499static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) 1499static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void)
1500{ 1500{
1501 return 0x0000003a; 1501 return 0x0000003aU;
1502} 1502}
1503static inline u32 gr_fecs_host_int_status_r(void) 1503static inline u32 gr_fecs_host_int_status_r(void)
1504{ 1504{
1505 return 0x00409c18; 1505 return 0x00409c18U;
1506} 1506}
1507static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) 1507static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v)
1508{ 1508{
1509 return (v & 0x1) << 16; 1509 return (v & 0x1U) << 16U;
1510} 1510}
1511static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) 1511static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
1512{ 1512{
1513 return (v & 0x1) << 17; 1513 return (v & 0x1U) << 17U;
1514} 1514}
1515static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) 1515static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
1516{ 1516{
1517 return (v & 0x1) << 18; 1517 return (v & 0x1U) << 18U;
1518} 1518}
1519static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) 1519static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
1520{ 1520{
1521 return (v & 0xffff) << 0; 1521 return (v & 0xffffU) << 0U;
1522} 1522}
1523static inline u32 gr_fecs_host_int_status_ecc_corrected_f(u32 v) 1523static inline u32 gr_fecs_host_int_status_ecc_corrected_f(u32 v)
1524{ 1524{
1525 return (v & 0x1) << 21; 1525 return (v & 0x1U) << 21U;
1526} 1526}
1527static inline u32 gr_fecs_host_int_status_ecc_corrected_m(void) 1527static inline u32 gr_fecs_host_int_status_ecc_corrected_m(void)
1528{ 1528{
1529 return 0x1 << 21; 1529 return 0x1U << 21U;
1530} 1530}
1531static inline u32 gr_fecs_host_int_status_ecc_uncorrected_f(u32 v) 1531static inline u32 gr_fecs_host_int_status_ecc_uncorrected_f(u32 v)
1532{ 1532{
1533 return (v & 0x1) << 22; 1533 return (v & 0x1U) << 22U;
1534} 1534}
1535static inline u32 gr_fecs_host_int_status_ecc_uncorrected_m(void) 1535static inline u32 gr_fecs_host_int_status_ecc_uncorrected_m(void)
1536{ 1536{
1537 return 0x1 << 22; 1537 return 0x1U << 22U;
1538} 1538}
1539static inline u32 gr_fecs_host_int_clear_r(void) 1539static inline u32 gr_fecs_host_int_clear_r(void)
1540{ 1540{
1541 return 0x00409c20; 1541 return 0x00409c20U;
1542} 1542}
1543static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) 1543static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v)
1544{ 1544{
1545 return (v & 0x1) << 1; 1545 return (v & 0x1U) << 1U;
1546} 1546}
1547static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) 1547static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void)
1548{ 1548{
1549 return 0x2; 1549 return 0x2U;
1550} 1550}
1551static inline u32 gr_fecs_host_int_enable_r(void) 1551static inline u32 gr_fecs_host_int_enable_r(void)
1552{ 1552{
1553 return 0x00409c24; 1553 return 0x00409c24U;
1554} 1554}
1555static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) 1555static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void)
1556{ 1556{
1557 return 0x2; 1557 return 0x2U;
1558} 1558}
1559static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) 1559static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void)
1560{ 1560{
1561 return 0x10000; 1561 return 0x10000U;
1562} 1562}
1563static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) 1563static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void)
1564{ 1564{
1565 return 0x20000; 1565 return 0x20000U;
1566} 1566}
1567static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) 1567static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void)
1568{ 1568{
1569 return 0x40000; 1569 return 0x40000U;
1570} 1570}
1571static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) 1571static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void)
1572{ 1572{
1573 return 0x80000; 1573 return 0x80000U;
1574} 1574}
1575static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) 1575static inline u32 gr_fecs_ctxsw_reset_ctl_r(void)
1576{ 1576{
1577 return 0x00409614; 1577 return 0x00409614U;
1578} 1578}
1579static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) 1579static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void)
1580{ 1580{
1581 return 0x0; 1581 return 0x0U;
1582} 1582}
1583static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) 1583static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void)
1584{ 1584{
1585 return 0x0; 1585 return 0x0U;
1586} 1586}
1587static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) 1587static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void)
1588{ 1588{
1589 return 0x0; 1589 return 0x0U;
1590} 1590}
1591static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) 1591static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void)
1592{ 1592{
1593 return 0x10; 1593 return 0x10U;
1594} 1594}
1595static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) 1595static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void)
1596{ 1596{
1597 return 0x20; 1597 return 0x20U;
1598} 1598}
1599static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) 1599static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void)
1600{ 1600{
1601 return 0x40; 1601 return 0x40U;
1602} 1602}
1603static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) 1603static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void)
1604{ 1604{
1605 return 0x0; 1605 return 0x0U;
1606} 1606}
1607static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) 1607static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void)
1608{ 1608{
1609 return 0x100; 1609 return 0x100U;
1610} 1610}
1611static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) 1611static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void)
1612{ 1612{
1613 return 0x0; 1613 return 0x0U;
1614} 1614}
1615static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) 1615static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void)
1616{ 1616{
1617 return 0x200; 1617 return 0x200U;
1618} 1618}
1619static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) 1619static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void)
1620{ 1620{
1621 return 1; 1621 return 1U;
1622} 1622}
1623static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) 1623static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
1624{ 1624{
1625 return (v & 0x1) << 10; 1625 return (v & 0x1U) << 10U;
1626} 1626}
1627static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) 1627static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
1628{ 1628{
1629 return 0x1 << 10; 1629 return 0x1U << 10U;
1630} 1630}
1631static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) 1631static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
1632{ 1632{
1633 return (r >> 10) & 0x1; 1633 return (r >> 10U) & 0x1U;
1634} 1634}
1635static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) 1635static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void)
1636{ 1636{
1637 return 0x0; 1637 return 0x0U;
1638} 1638}
1639static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) 1639static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void)
1640{ 1640{
1641 return 0x400; 1641 return 0x400U;
1642} 1642}
1643static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) 1643static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void)
1644{ 1644{
1645 return 0x0040960c; 1645 return 0x0040960cU;
1646} 1646}
1647static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) 1647static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i)
1648{ 1648{
1649 return 0x00409800 + i*4; 1649 return 0x00409800U + i*4U;
1650} 1650}
1651static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) 1651static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void)
1652{ 1652{
1653 return 0x00000010; 1653 return 0x00000010U;
1654} 1654}
1655static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) 1655static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v)
1656{ 1656{
1657 return (v & 0xffffffff) << 0; 1657 return (v & 0xffffffffU) << 0U;
1658} 1658}
1659static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) 1659static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void)
1660{ 1660{
1661 return 0x00000001; 1661 return 0x00000001U;
1662} 1662}
1663static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) 1663static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void)
1664{ 1664{
1665 return 0x00000002; 1665 return 0x00000002U;
1666} 1666}
1667static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) 1667static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i)
1668{ 1668{
1669 return 0x004098c0 + i*4; 1669 return 0x004098c0U + i*4U;
1670} 1670}
1671static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) 1671static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v)
1672{ 1672{
1673 return (v & 0xffffffff) << 0; 1673 return (v & 0xffffffffU) << 0U;
1674} 1674}
1675static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) 1675static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i)
1676{ 1676{
1677 return 0x00409840 + i*4; 1677 return 0x00409840U + i*4U;
1678} 1678}
1679static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) 1679static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v)
1680{ 1680{
1681 return (v & 0xffffffff) << 0; 1681 return (v & 0xffffffffU) << 0U;
1682} 1682}
1683static inline u32 gr_fecs_fs_r(void) 1683static inline u32 gr_fecs_fs_r(void)
1684{ 1684{
1685 return 0x00409604; 1685 return 0x00409604U;
1686} 1686}
1687static inline u32 gr_fecs_fs_num_available_gpcs_s(void) 1687static inline u32 gr_fecs_fs_num_available_gpcs_s(void)
1688{ 1688{
1689 return 5; 1689 return 5U;
1690} 1690}
1691static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) 1691static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
1692{ 1692{
1693 return (v & 0x1f) << 0; 1693 return (v & 0x1fU) << 0U;
1694} 1694}
1695static inline u32 gr_fecs_fs_num_available_gpcs_m(void) 1695static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
1696{ 1696{
1697 return 0x1f << 0; 1697 return 0x1fU << 0U;
1698} 1698}
1699static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) 1699static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
1700{ 1700{
1701 return (r >> 0) & 0x1f; 1701 return (r >> 0U) & 0x1fU;
1702} 1702}
1703static inline u32 gr_fecs_fs_num_available_fbps_s(void) 1703static inline u32 gr_fecs_fs_num_available_fbps_s(void)
1704{ 1704{
1705 return 5; 1705 return 5U;
1706} 1706}
1707static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) 1707static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
1708{ 1708{
1709 return (v & 0x1f) << 16; 1709 return (v & 0x1fU) << 16U;
1710} 1710}
1711static inline u32 gr_fecs_fs_num_available_fbps_m(void) 1711static inline u32 gr_fecs_fs_num_available_fbps_m(void)
1712{ 1712{
1713 return 0x1f << 16; 1713 return 0x1fU << 16U;
1714} 1714}
1715static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) 1715static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
1716{ 1716{
1717 return (r >> 16) & 0x1f; 1717 return (r >> 16U) & 0x1fU;
1718} 1718}
1719static inline u32 gr_fecs_cfg_r(void) 1719static inline u32 gr_fecs_cfg_r(void)
1720{ 1720{
1721 return 0x00409620; 1721 return 0x00409620U;
1722} 1722}
1723static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) 1723static inline u32 gr_fecs_cfg_imem_sz_v(u32 r)
1724{ 1724{
1725 return (r >> 0) & 0xff; 1725 return (r >> 0U) & 0xffU;
1726} 1726}
1727static inline u32 gr_fecs_rc_lanes_r(void) 1727static inline u32 gr_fecs_rc_lanes_r(void)
1728{ 1728{
1729 return 0x00409880; 1729 return 0x00409880U;
1730} 1730}
1731static inline u32 gr_fecs_rc_lanes_num_chains_s(void) 1731static inline u32 gr_fecs_rc_lanes_num_chains_s(void)
1732{ 1732{
1733 return 6; 1733 return 6U;
1734} 1734}
1735static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) 1735static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
1736{ 1736{
1737 return (v & 0x3f) << 0; 1737 return (v & 0x3fU) << 0U;
1738} 1738}
1739static inline u32 gr_fecs_rc_lanes_num_chains_m(void) 1739static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
1740{ 1740{
1741 return 0x3f << 0; 1741 return 0x3fU << 0U;
1742} 1742}
1743static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) 1743static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
1744{ 1744{
1745 return (r >> 0) & 0x3f; 1745 return (r >> 0U) & 0x3fU;
1746} 1746}
1747static inline u32 gr_fecs_ctxsw_status_1_r(void) 1747static inline u32 gr_fecs_ctxsw_status_1_r(void)
1748{ 1748{
1749 return 0x00409400; 1749 return 0x00409400U;
1750} 1750}
1751static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) 1751static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void)
1752{ 1752{
1753 return 1; 1753 return 1U;
1754} 1754}
1755static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) 1755static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
1756{ 1756{
1757 return (v & 0x1) << 12; 1757 return (v & 0x1U) << 12U;
1758} 1758}
1759static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) 1759static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
1760{ 1760{
1761 return 0x1 << 12; 1761 return 0x1U << 12U;
1762} 1762}
1763static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) 1763static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
1764{ 1764{
1765 return (r >> 12) & 0x1; 1765 return (r >> 12U) & 0x1U;
1766} 1766}
1767static inline u32 gr_fecs_arb_ctx_adr_r(void) 1767static inline u32 gr_fecs_arb_ctx_adr_r(void)
1768{ 1768{
1769 return 0x00409a24; 1769 return 0x00409a24U;
1770} 1770}
1771static inline u32 gr_fecs_new_ctx_r(void) 1771static inline u32 gr_fecs_new_ctx_r(void)
1772{ 1772{
1773 return 0x00409b04; 1773 return 0x00409b04U;
1774} 1774}
1775static inline u32 gr_fecs_new_ctx_ptr_s(void) 1775static inline u32 gr_fecs_new_ctx_ptr_s(void)
1776{ 1776{
1777 return 28; 1777 return 28U;
1778} 1778}
1779static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) 1779static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
1780{ 1780{
1781 return (v & 0xfffffff) << 0; 1781 return (v & 0xfffffffU) << 0U;
1782} 1782}
1783static inline u32 gr_fecs_new_ctx_ptr_m(void) 1783static inline u32 gr_fecs_new_ctx_ptr_m(void)
1784{ 1784{
1785 return 0xfffffff << 0; 1785 return 0xfffffffU << 0U;
1786} 1786}
1787static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) 1787static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
1788{ 1788{
1789 return (r >> 0) & 0xfffffff; 1789 return (r >> 0U) & 0xfffffffU;
1790} 1790}
1791static inline u32 gr_fecs_new_ctx_target_s(void) 1791static inline u32 gr_fecs_new_ctx_target_s(void)
1792{ 1792{
1793 return 2; 1793 return 2U;
1794} 1794}
1795static inline u32 gr_fecs_new_ctx_target_f(u32 v) 1795static inline u32 gr_fecs_new_ctx_target_f(u32 v)
1796{ 1796{
1797 return (v & 0x3) << 28; 1797 return (v & 0x3U) << 28U;
1798} 1798}
1799static inline u32 gr_fecs_new_ctx_target_m(void) 1799static inline u32 gr_fecs_new_ctx_target_m(void)
1800{ 1800{
1801 return 0x3 << 28; 1801 return 0x3U << 28U;
1802} 1802}
1803static inline u32 gr_fecs_new_ctx_target_v(u32 r) 1803static inline u32 gr_fecs_new_ctx_target_v(u32 r)
1804{ 1804{
1805 return (r >> 28) & 0x3; 1805 return (r >> 28U) & 0x3U;
1806} 1806}
1807static inline u32 gr_fecs_new_ctx_valid_s(void) 1807static inline u32 gr_fecs_new_ctx_valid_s(void)
1808{ 1808{
1809 return 1; 1809 return 1U;
1810} 1810}
1811static inline u32 gr_fecs_new_ctx_valid_f(u32 v) 1811static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
1812{ 1812{
1813 return (v & 0x1) << 31; 1813 return (v & 0x1U) << 31U;
1814} 1814}
1815static inline u32 gr_fecs_new_ctx_valid_m(void) 1815static inline u32 gr_fecs_new_ctx_valid_m(void)
1816{ 1816{
1817 return 0x1 << 31; 1817 return 0x1U << 31U;
1818} 1818}
1819static inline u32 gr_fecs_new_ctx_valid_v(u32 r) 1819static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
1820{ 1820{
1821 return (r >> 31) & 0x1; 1821 return (r >> 31U) & 0x1U;
1822} 1822}
1823static inline u32 gr_fecs_arb_ctx_ptr_r(void) 1823static inline u32 gr_fecs_arb_ctx_ptr_r(void)
1824{ 1824{
1825 return 0x00409a0c; 1825 return 0x00409a0cU;
1826} 1826}
1827static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) 1827static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void)
1828{ 1828{
1829 return 28; 1829 return 28U;
1830} 1830}
1831static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) 1831static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
1832{ 1832{
1833 return (v & 0xfffffff) << 0; 1833 return (v & 0xfffffffU) << 0U;
1834} 1834}
1835static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) 1835static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
1836{ 1836{
1837 return 0xfffffff << 0; 1837 return 0xfffffffU << 0U;
1838} 1838}
1839static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) 1839static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
1840{ 1840{
1841 return (r >> 0) & 0xfffffff; 1841 return (r >> 0U) & 0xfffffffU;
1842} 1842}
1843static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) 1843static inline u32 gr_fecs_arb_ctx_ptr_target_s(void)
1844{ 1844{
1845 return 2; 1845 return 2U;
1846} 1846}
1847static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) 1847static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
1848{ 1848{
1849 return (v & 0x3) << 28; 1849 return (v & 0x3U) << 28U;
1850} 1850}
1851static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) 1851static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
1852{ 1852{
1853 return 0x3 << 28; 1853 return 0x3U << 28U;
1854} 1854}
1855static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) 1855static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
1856{ 1856{
1857 return (r >> 28) & 0x3; 1857 return (r >> 28U) & 0x3U;
1858} 1858}
1859static inline u32 gr_fecs_arb_ctx_cmd_r(void) 1859static inline u32 gr_fecs_arb_ctx_cmd_r(void)
1860{ 1860{
1861 return 0x00409a10; 1861 return 0x00409a10U;
1862} 1862}
1863static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) 1863static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void)
1864{ 1864{
1865 return 5; 1865 return 5U;
1866} 1866}
1867static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) 1867static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
1868{ 1868{
1869 return (v & 0x1f) << 0; 1869 return (v & 0x1fU) << 0U;
1870} 1870}
1871static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) 1871static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
1872{ 1872{
1873 return 0x1f << 0; 1873 return 0x1fU << 0U;
1874} 1874}
1875static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) 1875static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
1876{ 1876{
1877 return (r >> 0) & 0x1f; 1877 return (r >> 0U) & 0x1fU;
1878} 1878}
1879static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) 1879static inline u32 gr_fecs_ctxsw_status_fe_0_r(void)
1880{ 1880{
1881 return 0x00409c00; 1881 return 0x00409c00U;
1882} 1882}
1883static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) 1883static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void)
1884{ 1884{
1885 return 0x00502c04; 1885 return 0x00502c04U;
1886} 1886}
1887static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) 1887static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
1888{ 1888{
1889 return 0x00502400; 1889 return 0x00502400U;
1890} 1890}
1891static inline u32 gr_fecs_ctxsw_idlestate_r(void) 1891static inline u32 gr_fecs_ctxsw_idlestate_r(void)
1892{ 1892{
1893 return 0x00409420; 1893 return 0x00409420U;
1894} 1894}
1895static inline u32 gr_fecs_feature_override_ecc_r(void) 1895static inline u32 gr_fecs_feature_override_ecc_r(void)
1896{ 1896{
1897 return 0x00409658; 1897 return 0x00409658U;
1898} 1898}
1899static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) 1899static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r)
1900{ 1900{
1901 return (r >> 3) & 0x1; 1901 return (r >> 3U) & 0x1U;
1902} 1902}
1903static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) 1903static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r)
1904{ 1904{
1905 return (r >> 15) & 0x1; 1905 return (r >> 15U) & 0x1U;
1906} 1906}
1907static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) 1907static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r)
1908{ 1908{
1909 return (r >> 0) & 0x1; 1909 return (r >> 0U) & 0x1U;
1910} 1910}
1911static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) 1911static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r)
1912{ 1912{
1913 return (r >> 12) & 0x1; 1913 return (r >> 12U) & 0x1U;
1914} 1914}
1915static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) 1915static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
1916{ 1916{
1917 return 0x00502420; 1917 return 0x00502420U;
1918} 1918}
1919static inline u32 gr_rstr2d_gpc_map_r(u32 i) 1919static inline u32 gr_rstr2d_gpc_map_r(u32 i)
1920{ 1920{
1921 return 0x0040780c + i*4; 1921 return 0x0040780cU + i*4U;
1922} 1922}
1923static inline u32 gr_rstr2d_map_table_cfg_r(void) 1923static inline u32 gr_rstr2d_map_table_cfg_r(void)
1924{ 1924{
1925 return 0x004078bc; 1925 return 0x004078bcU;
1926} 1926}
1927static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) 1927static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v)
1928{ 1928{
1929 return (v & 0xff) << 0; 1929 return (v & 0xffU) << 0U;
1930} 1930}
1931static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) 1931static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v)
1932{ 1932{
1933 return (v & 0xff) << 8; 1933 return (v & 0xffU) << 8U;
1934} 1934}
1935static inline u32 gr_pd_hww_esr_r(void) 1935static inline u32 gr_pd_hww_esr_r(void)
1936{ 1936{
1937 return 0x00406018; 1937 return 0x00406018U;
1938} 1938}
1939static inline u32 gr_pd_hww_esr_reset_active_f(void) 1939static inline u32 gr_pd_hww_esr_reset_active_f(void)
1940{ 1940{
1941 return 0x40000000; 1941 return 0x40000000U;
1942} 1942}
1943static inline u32 gr_pd_hww_esr_en_enable_f(void) 1943static inline u32 gr_pd_hww_esr_en_enable_f(void)
1944{ 1944{
1945 return 0x80000000; 1945 return 0x80000000U;
1946} 1946}
1947static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) 1947static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i)
1948{ 1948{
1949 return 0x00406028 + i*4; 1949 return 0x00406028U + i*4U;
1950} 1950}
1951static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) 1951static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void)
1952{ 1952{
1953 return 0x00000004; 1953 return 0x00000004U;
1954} 1954}
1955static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) 1955static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v)
1956{ 1956{
1957 return (v & 0xf) << 0; 1957 return (v & 0xfU) << 0U;
1958} 1958}
1959static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) 1959static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v)
1960{ 1960{
1961 return (v & 0xf) << 4; 1961 return (v & 0xfU) << 4U;
1962} 1962}
1963static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) 1963static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v)
1964{ 1964{
1965 return (v & 0xf) << 8; 1965 return (v & 0xfU) << 8U;
1966} 1966}
1967static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) 1967static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v)
1968{ 1968{
1969 return (v & 0xf) << 12; 1969 return (v & 0xfU) << 12U;
1970} 1970}
1971static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) 1971static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v)
1972{ 1972{
1973 return (v & 0xf) << 16; 1973 return (v & 0xfU) << 16U;
1974} 1974}
1975static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) 1975static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v)
1976{ 1976{
1977 return (v & 0xf) << 20; 1977 return (v & 0xfU) << 20U;
1978} 1978}
1979static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) 1979static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v)
1980{ 1980{
1981 return (v & 0xf) << 24; 1981 return (v & 0xfU) << 24U;
1982} 1982}
1983static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) 1983static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v)
1984{ 1984{
1985 return (v & 0xf) << 28; 1985 return (v & 0xfU) << 28U;
1986} 1986}
1987static inline u32 gr_pd_ab_dist_cfg0_r(void) 1987static inline u32 gr_pd_ab_dist_cfg0_r(void)
1988{ 1988{
1989 return 0x004064c0; 1989 return 0x004064c0U;
1990} 1990}
1991static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) 1991static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void)
1992{ 1992{
1993 return 0x80000000; 1993 return 0x80000000U;
1994} 1994}
1995static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) 1995static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void)
1996{ 1996{
1997 return 0x0; 1997 return 0x0U;
1998} 1998}
1999static inline u32 gr_pd_ab_dist_cfg1_r(void) 1999static inline u32 gr_pd_ab_dist_cfg1_r(void)
2000{ 2000{
2001 return 0x004064c4; 2001 return 0x004064c4U;
2002} 2002}
2003static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) 2003static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
2004{ 2004{
2005 return 0xffff; 2005 return 0xffffU;
2006} 2006}
2007static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) 2007static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v)
2008{ 2008{
2009 return (v & 0xffff) << 16; 2009 return (v & 0xffffU) << 16U;
2010} 2010}
2011static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) 2011static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void)
2012{ 2012{
2013 return 0x00000080; 2013 return 0x00000080U;
2014} 2014}
2015static inline u32 gr_pd_ab_dist_cfg2_r(void) 2015static inline u32 gr_pd_ab_dist_cfg2_r(void)
2016{ 2016{
2017 return 0x004064c8; 2017 return 0x004064c8U;
2018} 2018}
2019static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) 2019static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
2020{ 2020{
2021 return (v & 0x1fff) << 0; 2021 return (v & 0x1fffU) << 0U;
2022} 2022}
2023static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) 2023static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
2024{ 2024{
2025 return 0x00000380; 2025 return 0x00000380U;
2026} 2026}
2027static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) 2027static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
2028{ 2028{
2029 return (v & 0x1fff) << 16; 2029 return (v & 0x1fffU) << 16U;
2030} 2030}
2031static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) 2031static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
2032{ 2032{
2033 return 0x00000020; 2033 return 0x00000020U;
2034} 2034}
2035static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) 2035static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
2036{ 2036{
2037 return 0x00000302; 2037 return 0x00000302U;
2038} 2038}
2039static inline u32 gr_pd_dist_skip_table_r(u32 i) 2039static inline u32 gr_pd_dist_skip_table_r(u32 i)
2040{ 2040{
2041 return 0x004064d0 + i*4; 2041 return 0x004064d0U + i*4U;
2042} 2042}
2043static inline u32 gr_pd_dist_skip_table__size_1_v(void) 2043static inline u32 gr_pd_dist_skip_table__size_1_v(void)
2044{ 2044{
2045 return 0x00000008; 2045 return 0x00000008U;
2046} 2046}
2047static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) 2047static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v)
2048{ 2048{
2049 return (v & 0xff) << 0; 2049 return (v & 0xffU) << 0U;
2050} 2050}
2051static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) 2051static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v)
2052{ 2052{
2053 return (v & 0xff) << 8; 2053 return (v & 0xffU) << 8U;
2054} 2054}
2055static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) 2055static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v)
2056{ 2056{
2057 return (v & 0xff) << 16; 2057 return (v & 0xffU) << 16U;
2058} 2058}
2059static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) 2059static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v)
2060{ 2060{
2061 return (v & 0xff) << 24; 2061 return (v & 0xffU) << 24U;
2062} 2062}
2063static inline u32 gr_ds_debug_r(void) 2063static inline u32 gr_ds_debug_r(void)
2064{ 2064{
2065 return 0x00405800; 2065 return 0x00405800U;
2066} 2066}
2067static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) 2067static inline u32 gr_ds_debug_timeslice_mode_disable_f(void)
2068{ 2068{
2069 return 0x0; 2069 return 0x0U;
2070} 2070}
2071static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) 2071static inline u32 gr_ds_debug_timeslice_mode_enable_f(void)
2072{ 2072{
2073 return 0x8000000; 2073 return 0x8000000U;
2074} 2074}
2075static inline u32 gr_ds_zbc_color_r_r(void) 2075static inline u32 gr_ds_zbc_color_r_r(void)
2076{ 2076{
2077 return 0x00405804; 2077 return 0x00405804U;
2078} 2078}
2079static inline u32 gr_ds_zbc_color_r_val_f(u32 v) 2079static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
2080{ 2080{
2081 return (v & 0xffffffff) << 0; 2081 return (v & 0xffffffffU) << 0U;
2082} 2082}
2083static inline u32 gr_ds_zbc_color_g_r(void) 2083static inline u32 gr_ds_zbc_color_g_r(void)
2084{ 2084{
2085 return 0x00405808; 2085 return 0x00405808U;
2086} 2086}
2087static inline u32 gr_ds_zbc_color_g_val_f(u32 v) 2087static inline u32 gr_ds_zbc_color_g_val_f(u32 v)
2088{ 2088{
2089 return (v & 0xffffffff) << 0; 2089 return (v & 0xffffffffU) << 0U;
2090} 2090}
2091static inline u32 gr_ds_zbc_color_b_r(void) 2091static inline u32 gr_ds_zbc_color_b_r(void)
2092{ 2092{
2093 return 0x0040580c; 2093 return 0x0040580cU;
2094} 2094}
2095static inline u32 gr_ds_zbc_color_b_val_f(u32 v) 2095static inline u32 gr_ds_zbc_color_b_val_f(u32 v)
2096{ 2096{
2097 return (v & 0xffffffff) << 0; 2097 return (v & 0xffffffffU) << 0U;
2098} 2098}
2099static inline u32 gr_ds_zbc_color_a_r(void) 2099static inline u32 gr_ds_zbc_color_a_r(void)
2100{ 2100{
2101 return 0x00405810; 2101 return 0x00405810U;
2102} 2102}
2103static inline u32 gr_ds_zbc_color_a_val_f(u32 v) 2103static inline u32 gr_ds_zbc_color_a_val_f(u32 v)
2104{ 2104{
2105 return (v & 0xffffffff) << 0; 2105 return (v & 0xffffffffU) << 0U;
2106} 2106}
2107static inline u32 gr_ds_zbc_color_fmt_r(void) 2107static inline u32 gr_ds_zbc_color_fmt_r(void)
2108{ 2108{
2109 return 0x00405814; 2109 return 0x00405814U;
2110} 2110}
2111static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) 2111static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v)
2112{ 2112{
2113 return (v & 0x7f) << 0; 2113 return (v & 0x7fU) << 0U;
2114} 2114}
2115static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) 2115static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void)
2116{ 2116{
2117 return 0x0; 2117 return 0x0U;
2118} 2118}
2119static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) 2119static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void)
2120{ 2120{
2121 return 0x00000001; 2121 return 0x00000001U;
2122} 2122}
2123static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) 2123static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void)
2124{ 2124{
2125 return 0x00000002; 2125 return 0x00000002U;
2126} 2126}
2127static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) 2127static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
2128{ 2128{
2129 return 0x00000004; 2129 return 0x00000004U;
2130} 2130}
2131static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) 2131static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
2132{ 2132{
2133 return 0x00000028; 2133 return 0x00000028U;
2134} 2134}
2135static inline u32 gr_ds_zbc_z_r(void) 2135static inline u32 gr_ds_zbc_z_r(void)
2136{ 2136{
2137 return 0x00405818; 2137 return 0x00405818U;
2138} 2138}
2139static inline u32 gr_ds_zbc_z_val_s(void) 2139static inline u32 gr_ds_zbc_z_val_s(void)
2140{ 2140{
2141 return 32; 2141 return 32U;
2142} 2142}
2143static inline u32 gr_ds_zbc_z_val_f(u32 v) 2143static inline u32 gr_ds_zbc_z_val_f(u32 v)
2144{ 2144{
2145 return (v & 0xffffffff) << 0; 2145 return (v & 0xffffffffU) << 0U;
2146} 2146}
2147static inline u32 gr_ds_zbc_z_val_m(void) 2147static inline u32 gr_ds_zbc_z_val_m(void)
2148{ 2148{
2149 return 0xffffffff << 0; 2149 return 0xffffffffU << 0U;
2150} 2150}
2151static inline u32 gr_ds_zbc_z_val_v(u32 r) 2151static inline u32 gr_ds_zbc_z_val_v(u32 r)
2152{ 2152{
2153 return (r >> 0) & 0xffffffff; 2153 return (r >> 0U) & 0xffffffffU;
2154} 2154}
2155static inline u32 gr_ds_zbc_z_val__init_v(void) 2155static inline u32 gr_ds_zbc_z_val__init_v(void)
2156{ 2156{
2157 return 0x00000000; 2157 return 0x00000000U;
2158} 2158}
2159static inline u32 gr_ds_zbc_z_val__init_f(void) 2159static inline u32 gr_ds_zbc_z_val__init_f(void)
2160{ 2160{
2161 return 0x0; 2161 return 0x0U;
2162} 2162}
2163static inline u32 gr_ds_zbc_z_fmt_r(void) 2163static inline u32 gr_ds_zbc_z_fmt_r(void)
2164{ 2164{
2165 return 0x0040581c; 2165 return 0x0040581cU;
2166} 2166}
2167static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) 2167static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v)
2168{ 2168{
2169 return (v & 0x1) << 0; 2169 return (v & 0x1U) << 0U;
2170} 2170}
2171static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) 2171static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void)
2172{ 2172{
2173 return 0x0; 2173 return 0x0U;
2174} 2174}
2175static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) 2175static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void)
2176{ 2176{
2177 return 0x00000001; 2177 return 0x00000001U;
2178} 2178}
2179static inline u32 gr_ds_zbc_tbl_index_r(void) 2179static inline u32 gr_ds_zbc_tbl_index_r(void)
2180{ 2180{
2181 return 0x00405820; 2181 return 0x00405820U;
2182} 2182}
2183static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) 2183static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v)
2184{ 2184{
2185 return (v & 0xf) << 0; 2185 return (v & 0xfU) << 0U;
2186} 2186}
2187static inline u32 gr_ds_zbc_tbl_ld_r(void) 2187static inline u32 gr_ds_zbc_tbl_ld_r(void)
2188{ 2188{
2189 return 0x00405824; 2189 return 0x00405824U;
2190} 2190}
2191static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) 2191static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void)
2192{ 2192{
2193 return 0x0; 2193 return 0x0U;
2194} 2194}
2195static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) 2195static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void)
2196{ 2196{
2197 return 0x1; 2197 return 0x1U;
2198} 2198}
2199static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) 2199static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void)
2200{ 2200{
2201 return 0x0; 2201 return 0x0U;
2202} 2202}
2203static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) 2203static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
2204{ 2204{
2205 return 0x4; 2205 return 0x4U;
2206} 2206}
2207static inline u32 gr_ds_tga_constraintlogic_beta_r(void) 2207static inline u32 gr_ds_tga_constraintlogic_beta_r(void)
2208{ 2208{
2209 return 0x00405830; 2209 return 0x00405830U;
2210} 2210}
2211static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) 2211static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
2212{ 2212{
2213 return (v & 0x3fffff) << 0; 2213 return (v & 0x3fffffU) << 0U;
2214} 2214}
2215static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) 2215static inline u32 gr_ds_tga_constraintlogic_alpha_r(void)
2216{ 2216{
2217 return 0x0040585c; 2217 return 0x0040585cU;
2218} 2218}
2219static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) 2219static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v)
2220{ 2220{
2221 return (v & 0xffff) << 0; 2221 return (v & 0xffffU) << 0U;
2222} 2222}
2223static inline u32 gr_ds_hww_esr_r(void) 2223static inline u32 gr_ds_hww_esr_r(void)
2224{ 2224{
2225 return 0x00405840; 2225 return 0x00405840U;
2226} 2226}
2227static inline u32 gr_ds_hww_esr_reset_s(void) 2227static inline u32 gr_ds_hww_esr_reset_s(void)
2228{ 2228{
2229 return 1; 2229 return 1U;
2230} 2230}
2231static inline u32 gr_ds_hww_esr_reset_f(u32 v) 2231static inline u32 gr_ds_hww_esr_reset_f(u32 v)
2232{ 2232{
2233 return (v & 0x1) << 30; 2233 return (v & 0x1U) << 30U;
2234} 2234}
2235static inline u32 gr_ds_hww_esr_reset_m(void) 2235static inline u32 gr_ds_hww_esr_reset_m(void)
2236{ 2236{
2237 return 0x1 << 30; 2237 return 0x1U << 30U;
2238} 2238}
2239static inline u32 gr_ds_hww_esr_reset_v(u32 r) 2239static inline u32 gr_ds_hww_esr_reset_v(u32 r)
2240{ 2240{
2241 return (r >> 30) & 0x1; 2241 return (r >> 30U) & 0x1U;
2242} 2242}
2243static inline u32 gr_ds_hww_esr_reset_task_v(void) 2243static inline u32 gr_ds_hww_esr_reset_task_v(void)
2244{ 2244{
2245 return 0x00000001; 2245 return 0x00000001U;
2246} 2246}
2247static inline u32 gr_ds_hww_esr_reset_task_f(void) 2247static inline u32 gr_ds_hww_esr_reset_task_f(void)
2248{ 2248{
2249 return 0x40000000; 2249 return 0x40000000U;
2250} 2250}
2251static inline u32 gr_ds_hww_esr_en_enabled_f(void) 2251static inline u32 gr_ds_hww_esr_en_enabled_f(void)
2252{ 2252{
2253 return 0x80000000; 2253 return 0x80000000U;
2254} 2254}
2255static inline u32 gr_ds_hww_esr_2_r(void) 2255static inline u32 gr_ds_hww_esr_2_r(void)
2256{ 2256{
2257 return 0x00405848; 2257 return 0x00405848U;
2258} 2258}
2259static inline u32 gr_ds_hww_esr_2_reset_s(void) 2259static inline u32 gr_ds_hww_esr_2_reset_s(void)
2260{ 2260{
2261 return 1; 2261 return 1U;
2262} 2262}
2263static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) 2263static inline u32 gr_ds_hww_esr_2_reset_f(u32 v)
2264{ 2264{
2265 return (v & 0x1) << 30; 2265 return (v & 0x1U) << 30U;
2266} 2266}
2267static inline u32 gr_ds_hww_esr_2_reset_m(void) 2267static inline u32 gr_ds_hww_esr_2_reset_m(void)
2268{ 2268{
2269 return 0x1 << 30; 2269 return 0x1U << 30U;
2270} 2270}
2271static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) 2271static inline u32 gr_ds_hww_esr_2_reset_v(u32 r)
2272{ 2272{
2273 return (r >> 30) & 0x1; 2273 return (r >> 30U) & 0x1U;
2274} 2274}
2275static inline u32 gr_ds_hww_esr_2_reset_task_v(void) 2275static inline u32 gr_ds_hww_esr_2_reset_task_v(void)
2276{ 2276{
2277 return 0x00000001; 2277 return 0x00000001U;
2278} 2278}
2279static inline u32 gr_ds_hww_esr_2_reset_task_f(void) 2279static inline u32 gr_ds_hww_esr_2_reset_task_f(void)
2280{ 2280{
2281 return 0x40000000; 2281 return 0x40000000U;
2282} 2282}
2283static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) 2283static inline u32 gr_ds_hww_esr_2_en_enabled_f(void)
2284{ 2284{
2285 return 0x80000000; 2285 return 0x80000000U;
2286} 2286}
2287static inline u32 gr_ds_hww_report_mask_r(void) 2287static inline u32 gr_ds_hww_report_mask_r(void)
2288{ 2288{
2289 return 0x00405844; 2289 return 0x00405844U;
2290} 2290}
2291static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) 2291static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void)
2292{ 2292{
2293 return 0x1; 2293 return 0x1U;
2294} 2294}
2295static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) 2295static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void)
2296{ 2296{
2297 return 0x2; 2297 return 0x2U;
2298} 2298}
2299static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) 2299static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void)
2300{ 2300{
2301 return 0x4; 2301 return 0x4U;
2302} 2302}
2303static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) 2303static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void)
2304{ 2304{
2305 return 0x8; 2305 return 0x8U;
2306} 2306}
2307static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) 2307static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void)
2308{ 2308{
2309 return 0x10; 2309 return 0x10U;
2310} 2310}
2311static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) 2311static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void)
2312{ 2312{
2313 return 0x20; 2313 return 0x20U;
2314} 2314}
2315static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) 2315static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void)
2316{ 2316{
2317 return 0x40; 2317 return 0x40U;
2318} 2318}
2319static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) 2319static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void)
2320{ 2320{
2321 return 0x80; 2321 return 0x80U;
2322} 2322}
2323static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) 2323static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void)
2324{ 2324{
2325 return 0x100; 2325 return 0x100U;
2326} 2326}
2327static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) 2327static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void)
2328{ 2328{
2329 return 0x200; 2329 return 0x200U;
2330} 2330}
2331static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) 2331static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void)
2332{ 2332{
2333 return 0x400; 2333 return 0x400U;
2334} 2334}
2335static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) 2335static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void)
2336{ 2336{
2337 return 0x800; 2337 return 0x800U;
2338} 2338}
2339static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) 2339static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void)
2340{ 2340{
2341 return 0x1000; 2341 return 0x1000U;
2342} 2342}
2343static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) 2343static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void)
2344{ 2344{
2345 return 0x2000; 2345 return 0x2000U;
2346} 2346}
2347static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) 2347static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void)
2348{ 2348{
2349 return 0x4000; 2349 return 0x4000U;
2350} 2350}
2351static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) 2351static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void)
2352{ 2352{
2353 return 0x8000; 2353 return 0x8000U;
2354} 2354}
2355static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) 2355static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void)
2356{ 2356{
2357 return 0x10000; 2357 return 0x10000U;
2358} 2358}
2359static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) 2359static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void)
2360{ 2360{
2361 return 0x20000; 2361 return 0x20000U;
2362} 2362}
2363static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) 2363static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void)
2364{ 2364{
2365 return 0x40000; 2365 return 0x40000U;
2366} 2366}
2367static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) 2367static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void)
2368{ 2368{
2369 return 0x80000; 2369 return 0x80000U;
2370} 2370}
2371static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) 2371static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void)
2372{ 2372{
2373 return 0x100000; 2373 return 0x100000U;
2374} 2374}
2375static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) 2375static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void)
2376{ 2376{
2377 return 0x200000; 2377 return 0x200000U;
2378} 2378}
2379static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) 2379static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void)
2380{ 2380{
2381 return 0x400000; 2381 return 0x400000U;
2382} 2382}
2383static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) 2383static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void)
2384{ 2384{
2385 return 0x800000; 2385 return 0x800000U;
2386} 2386}
2387static inline u32 gr_ds_hww_report_mask_2_r(void) 2387static inline u32 gr_ds_hww_report_mask_2_r(void)
2388{ 2388{
2389 return 0x0040584c; 2389 return 0x0040584cU;
2390} 2390}
2391static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) 2391static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void)
2392{ 2392{
2393 return 0x1; 2393 return 0x1U;
2394} 2394}
2395static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) 2395static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i)
2396{ 2396{
2397 return 0x00405870 + i*4; 2397 return 0x00405870U + i*4U;
2398} 2398}
2399static inline u32 gr_scc_bundle_cb_base_r(void) 2399static inline u32 gr_scc_bundle_cb_base_r(void)
2400{ 2400{
2401 return 0x00408004; 2401 return 0x00408004U;
2402} 2402}
2403static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) 2403static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v)
2404{ 2404{
2405 return (v & 0xffffffff) << 0; 2405 return (v & 0xffffffffU) << 0U;
2406} 2406}
2407static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) 2407static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void)
2408{ 2408{
2409 return 0x00000008; 2409 return 0x00000008U;
2410} 2410}
2411static inline u32 gr_scc_bundle_cb_size_r(void) 2411static inline u32 gr_scc_bundle_cb_size_r(void)
2412{ 2412{
2413 return 0x00408008; 2413 return 0x00408008U;
2414} 2414}
2415static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) 2415static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
2416{ 2416{
2417 return (v & 0x7ff) << 0; 2417 return (v & 0x7ffU) << 0U;
2418} 2418}
2419static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) 2419static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
2420{ 2420{
2421 return 0x00000030; 2421 return 0x00000030U;
2422} 2422}
2423static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) 2423static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
2424{ 2424{
2425 return 0x00000100; 2425 return 0x00000100U;
2426} 2426}
2427static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) 2427static inline u32 gr_scc_bundle_cb_size_valid_false_v(void)
2428{ 2428{
2429 return 0x00000000; 2429 return 0x00000000U;
2430} 2430}
2431static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) 2431static inline u32 gr_scc_bundle_cb_size_valid_false_f(void)
2432{ 2432{
2433 return 0x0; 2433 return 0x0U;
2434} 2434}
2435static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) 2435static inline u32 gr_scc_bundle_cb_size_valid_true_f(void)
2436{ 2436{
2437 return 0x80000000; 2437 return 0x80000000U;
2438} 2438}
2439static inline u32 gr_scc_pagepool_base_r(void) 2439static inline u32 gr_scc_pagepool_base_r(void)
2440{ 2440{
2441 return 0x0040800c; 2441 return 0x0040800cU;
2442} 2442}
2443static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) 2443static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v)
2444{ 2444{
2445 return (v & 0xffffffff) << 0; 2445 return (v & 0xffffffffU) << 0U;
2446} 2446}
2447static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) 2447static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void)
2448{ 2448{
2449 return 0x00000008; 2449 return 0x00000008U;
2450} 2450}
2451static inline u32 gr_scc_pagepool_r(void) 2451static inline u32 gr_scc_pagepool_r(void)
2452{ 2452{
2453 return 0x00408010; 2453 return 0x00408010U;
2454} 2454}
2455static inline u32 gr_scc_pagepool_total_pages_f(u32 v) 2455static inline u32 gr_scc_pagepool_total_pages_f(u32 v)
2456{ 2456{
2457 return (v & 0x3ff) << 0; 2457 return (v & 0x3ffU) << 0U;
2458} 2458}
2459static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) 2459static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
2460{ 2460{
2461 return 0x00000000; 2461 return 0x00000000U;
2462} 2462}
2463static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) 2463static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void)
2464{ 2464{
2465 return 0x00000200; 2465 return 0x00000200U;
2466} 2466}
2467static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) 2467static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
2468{ 2468{
2469 return 0x00000100; 2469 return 0x00000100U;
2470} 2470}
2471static inline u32 gr_scc_pagepool_max_valid_pages_s(void) 2471static inline u32 gr_scc_pagepool_max_valid_pages_s(void)
2472{ 2472{
2473 return 10; 2473 return 10U;
2474} 2474}
2475static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) 2475static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
2476{ 2476{
2477 return (v & 0x3ff) << 10; 2477 return (v & 0x3ffU) << 10U;
2478} 2478}
2479static inline u32 gr_scc_pagepool_max_valid_pages_m(void) 2479static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
2480{ 2480{
2481 return 0x3ff << 10; 2481 return 0x3ffU << 10U;
2482} 2482}
2483static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) 2483static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
2484{ 2484{
2485 return (r >> 10) & 0x3ff; 2485 return (r >> 10U) & 0x3ffU;
2486} 2486}
2487static inline u32 gr_scc_pagepool_valid_true_f(void) 2487static inline u32 gr_scc_pagepool_valid_true_f(void)
2488{ 2488{
2489 return 0x80000000; 2489 return 0x80000000U;
2490} 2490}
2491static inline u32 gr_scc_init_r(void) 2491static inline u32 gr_scc_init_r(void)
2492{ 2492{
2493 return 0x0040802c; 2493 return 0x0040802cU;
2494} 2494}
2495static inline u32 gr_scc_init_ram_trigger_f(void) 2495static inline u32 gr_scc_init_ram_trigger_f(void)
2496{ 2496{
2497 return 0x1; 2497 return 0x1U;
2498} 2498}
2499static inline u32 gr_scc_hww_esr_r(void) 2499static inline u32 gr_scc_hww_esr_r(void)
2500{ 2500{
2501 return 0x00408030; 2501 return 0x00408030U;
2502} 2502}
2503static inline u32 gr_scc_hww_esr_reset_active_f(void) 2503static inline u32 gr_scc_hww_esr_reset_active_f(void)
2504{ 2504{
2505 return 0x40000000; 2505 return 0x40000000U;
2506} 2506}
2507static inline u32 gr_scc_hww_esr_en_enable_f(void) 2507static inline u32 gr_scc_hww_esr_en_enable_f(void)
2508{ 2508{
2509 return 0x80000000; 2509 return 0x80000000U;
2510} 2510}
2511static inline u32 gr_sked_hww_esr_r(void) 2511static inline u32 gr_sked_hww_esr_r(void)
2512{ 2512{
2513 return 0x00407020; 2513 return 0x00407020U;
2514} 2514}
2515static inline u32 gr_sked_hww_esr_reset_active_f(void) 2515static inline u32 gr_sked_hww_esr_reset_active_f(void)
2516{ 2516{
2517 return 0x40000000; 2517 return 0x40000000U;
2518} 2518}
2519static inline u32 gr_sked_hww_esr_en_r(void) 2519static inline u32 gr_sked_hww_esr_en_r(void)
2520{ 2520{
2521 return 0x00407024; 2521 return 0x00407024U;
2522} 2522}
2523static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void) 2523static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void)
2524{ 2524{
2525 return 0x1 << 25; 2525 return 0x1U << 25U;
2526} 2526}
2527static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void) 2527static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void)
2528{ 2528{
2529 return 0x0; 2529 return 0x0U;
2530} 2530}
2531static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void) 2531static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void)
2532{ 2532{
2533 return 0x2000000; 2533 return 0x2000000U;
2534} 2534}
2535static inline u32 gr_cwd_fs_r(void) 2535static inline u32 gr_cwd_fs_r(void)
2536{ 2536{
2537 return 0x00405b00; 2537 return 0x00405b00U;
2538} 2538}
2539static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) 2539static inline u32 gr_cwd_fs_num_gpcs_f(u32 v)
2540{ 2540{
2541 return (v & 0xff) << 0; 2541 return (v & 0xffU) << 0U;
2542} 2542}
2543static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) 2543static inline u32 gr_cwd_fs_num_tpcs_f(u32 v)
2544{ 2544{
2545 return (v & 0xff) << 8; 2545 return (v & 0xffU) << 8U;
2546} 2546}
2547static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) 2547static inline u32 gr_cwd_gpc_tpc_id_r(u32 i)
2548{ 2548{
2549 return 0x00405b60 + i*4; 2549 return 0x00405b60U + i*4U;
2550} 2550}
2551static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void) 2551static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void)
2552{ 2552{
2553 return 4; 2553 return 4U;
2554} 2554}
2555static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) 2555static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v)
2556{ 2556{
2557 return (v & 0xf) << 0; 2557 return (v & 0xfU) << 0U;
2558} 2558}
2559static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void) 2559static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void)
2560{ 2560{
2561 return 4; 2561 return 4U;
2562} 2562}
2563static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v) 2563static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v)
2564{ 2564{
2565 return (v & 0xf) << 4; 2565 return (v & 0xfU) << 4U;
2566} 2566}
2567static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) 2567static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v)
2568{ 2568{
2569 return (v & 0xf) << 8; 2569 return (v & 0xfU) << 8U;
2570} 2570}
2571static inline u32 gr_cwd_sm_id_r(u32 i) 2571static inline u32 gr_cwd_sm_id_r(u32 i)
2572{ 2572{
2573 return 0x00405ba0 + i*4; 2573 return 0x00405ba0U + i*4U;
2574} 2574}
2575static inline u32 gr_cwd_sm_id__size_1_v(void) 2575static inline u32 gr_cwd_sm_id__size_1_v(void)
2576{ 2576{
2577 return 0x00000010; 2577 return 0x00000010U;
2578} 2578}
2579static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) 2579static inline u32 gr_cwd_sm_id_tpc0_f(u32 v)
2580{ 2580{
2581 return (v & 0xff) << 0; 2581 return (v & 0xffU) << 0U;
2582} 2582}
2583static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) 2583static inline u32 gr_cwd_sm_id_tpc1_f(u32 v)
2584{ 2584{
2585 return (v & 0xff) << 8; 2585 return (v & 0xffU) << 8U;
2586} 2586}
2587static inline u32 gr_gpc0_fs_gpc_r(void) 2587static inline u32 gr_gpc0_fs_gpc_r(void)
2588{ 2588{
2589 return 0x00502608; 2589 return 0x00502608U;
2590} 2590}
2591static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) 2591static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r)
2592{ 2592{
2593 return (r >> 0) & 0x1f; 2593 return (r >> 0U) & 0x1fU;
2594} 2594}
2595static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) 2595static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r)
2596{ 2596{
2597 return (r >> 16) & 0x1f; 2597 return (r >> 16U) & 0x1fU;
2598} 2598}
2599static inline u32 gr_gpc0_cfg_r(void) 2599static inline u32 gr_gpc0_cfg_r(void)
2600{ 2600{
2601 return 0x00502620; 2601 return 0x00502620U;
2602} 2602}
2603static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) 2603static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r)
2604{ 2604{
2605 return (r >> 0) & 0xff; 2605 return (r >> 0U) & 0xffU;
2606} 2606}
2607static inline u32 gr_gpccs_rc_lanes_r(void) 2607static inline u32 gr_gpccs_rc_lanes_r(void)
2608{ 2608{
2609 return 0x00502880; 2609 return 0x00502880U;
2610} 2610}
2611static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) 2611static inline u32 gr_gpccs_rc_lanes_num_chains_s(void)
2612{ 2612{
2613 return 6; 2613 return 6U;
2614} 2614}
2615static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) 2615static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
2616{ 2616{
2617 return (v & 0x3f) << 0; 2617 return (v & 0x3fU) << 0U;
2618} 2618}
2619static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) 2619static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
2620{ 2620{
2621 return 0x3f << 0; 2621 return 0x3fU << 0U;
2622} 2622}
2623static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) 2623static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
2624{ 2624{
2625 return (r >> 0) & 0x3f; 2625 return (r >> 0U) & 0x3fU;
2626} 2626}
2627static inline u32 gr_gpccs_rc_lane_size_r(void) 2627static inline u32 gr_gpccs_rc_lane_size_r(void)
2628{ 2628{
2629 return 0x00502910; 2629 return 0x00502910U;
2630} 2630}
2631static inline u32 gr_gpccs_rc_lane_size_v_s(void) 2631static inline u32 gr_gpccs_rc_lane_size_v_s(void)
2632{ 2632{
2633 return 24; 2633 return 24U;
2634} 2634}
2635static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) 2635static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
2636{ 2636{
2637 return (v & 0xffffff) << 0; 2637 return (v & 0xffffffU) << 0U;
2638} 2638}
2639static inline u32 gr_gpccs_rc_lane_size_v_m(void) 2639static inline u32 gr_gpccs_rc_lane_size_v_m(void)
2640{ 2640{
2641 return 0xffffff << 0; 2641 return 0xffffffU << 0U;
2642} 2642}
2643static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) 2643static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
2644{ 2644{
2645 return (r >> 0) & 0xffffff; 2645 return (r >> 0U) & 0xffffffU;
2646} 2646}
2647static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) 2647static inline u32 gr_gpccs_rc_lane_size_v_0_v(void)
2648{ 2648{
2649 return 0x00000000; 2649 return 0x00000000U;
2650} 2650}
2651static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) 2651static inline u32 gr_gpccs_rc_lane_size_v_0_f(void)
2652{ 2652{
2653 return 0x0; 2653 return 0x0U;
2654} 2654}
2655static inline u32 gr_gpc0_zcull_fs_r(void) 2655static inline u32 gr_gpc0_zcull_fs_r(void)
2656{ 2656{
2657 return 0x00500910; 2657 return 0x00500910U;
2658} 2658}
2659static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) 2659static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v)
2660{ 2660{
2661 return (v & 0x1ff) << 0; 2661 return (v & 0x1ffU) << 0U;
2662} 2662}
2663static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) 2663static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v)
2664{ 2664{
2665 return (v & 0xf) << 16; 2665 return (v & 0xfU) << 16U;
2666} 2666}
2667static inline u32 gr_gpc0_zcull_ram_addr_r(void) 2667static inline u32 gr_gpc0_zcull_ram_addr_r(void)
2668{ 2668{
2669 return 0x00500914; 2669 return 0x00500914U;
2670} 2670}
2671static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) 2671static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v)
2672{ 2672{
2673 return (v & 0xf) << 0; 2673 return (v & 0xfU) << 0U;
2674} 2674}
2675static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) 2675static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v)
2676{ 2676{
2677 return (v & 0xf) << 8; 2677 return (v & 0xfU) << 8U;
2678} 2678}
2679static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) 2679static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void)
2680{ 2680{
2681 return 0x00500918; 2681 return 0x00500918U;
2682} 2682}
2683static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) 2683static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v)
2684{ 2684{
2685 return (v & 0xffffff) << 0; 2685 return (v & 0xffffffU) << 0U;
2686} 2686}
2687static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) 2687static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void)
2688{ 2688{
2689 return 0x00800000; 2689 return 0x00800000U;
2690} 2690}
2691static inline u32 gr_gpc0_zcull_total_ram_size_r(void) 2691static inline u32 gr_gpc0_zcull_total_ram_size_r(void)
2692{ 2692{
2693 return 0x00500920; 2693 return 0x00500920U;
2694} 2694}
2695static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) 2695static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v)
2696{ 2696{
2697 return (v & 0xffff) << 0; 2697 return (v & 0xffffU) << 0U;
2698} 2698}
2699static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) 2699static inline u32 gr_gpc0_zcull_zcsize_r(u32 i)
2700{ 2700{
2701 return 0x00500a04 + i*32; 2701 return 0x00500a04U + i*32U;
2702} 2702}
2703static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) 2703static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void)
2704{ 2704{
2705 return 0x00000040; 2705 return 0x00000040U;
2706} 2706}
2707static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) 2707static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void)
2708{ 2708{
2709 return 0x00000010; 2709 return 0x00000010U;
2710} 2710}
2711static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) 2711static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i)
2712{ 2712{
2713 return 0x00500c10 + i*4; 2713 return 0x00500c10U + i*4U;
2714} 2714}
2715static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) 2715static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v)
2716{ 2716{
2717 return (v & 0xff) << 0; 2717 return (v & 0xffU) << 0U;
2718} 2718}
2719static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) 2719static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i)
2720{ 2720{
2721 return 0x00500c30 + i*4; 2721 return 0x00500c30U + i*4U;
2722} 2722}
2723static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) 2723static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r)
2724{ 2724{
2725 return (r >> 0) & 0xff; 2725 return (r >> 0U) & 0xffU;
2726} 2726}
2727static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) 2727static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void)
2728{ 2728{
2729 return 0x00504088; 2729 return 0x00504088U;
2730} 2730}
2731static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) 2731static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
2732{ 2732{
2733 return (v & 0xffff) << 0; 2733 return (v & 0xffffU) << 0U;
2734} 2734}
2735static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) 2735static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
2736{ 2736{
2737 return 0x00504608; 2737 return 0x00504608U;
2738} 2738}
2739static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) 2739static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v)
2740{ 2740{
2741 return (v & 0xffff) << 0; 2741 return (v & 0xffffU) << 0U;
2742} 2742}
2743static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) 2743static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r)
2744{ 2744{
2745 return (r >> 0) & 0xffff; 2745 return (r >> 0U) & 0xffffU;
2746} 2746}
2747static inline u32 gr_gpc0_tpc0_sm_arch_r(void) 2747static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
2748{ 2748{
2749 return 0x00504330; 2749 return 0x00504330U;
2750} 2750}
2751static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) 2751static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
2752{ 2752{
2753 return (r >> 0) & 0xff; 2753 return (r >> 0U) & 0xffU;
2754} 2754}
2755static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) 2755static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r)
2756{ 2756{
2757 return (r >> 8) & 0xfff; 2757 return (r >> 8U) & 0xfffU;
2758} 2758}
2759static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) 2759static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r)
2760{ 2760{
2761 return (r >> 20) & 0xfff; 2761 return (r >> 20U) & 0xfffU;
2762} 2762}
2763static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) 2763static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
2764{ 2764{
2765 return 0x00503018; 2765 return 0x00503018U;
2766} 2766}
2767static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) 2767static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
2768{ 2768{
2769 return 0x1 << 0; 2769 return 0x1U << 0U;
2770} 2770}
2771static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) 2771static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
2772{ 2772{
2773 return 0x1; 2773 return 0x1U;
2774} 2774}
2775static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) 2775static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void)
2776{ 2776{
2777 return 0x005030c0; 2777 return 0x005030c0U;
2778} 2778}
2779static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) 2779static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v)
2780{ 2780{
2781 return (v & 0x3fffff) << 0; 2781 return (v & 0x3fffffU) << 0U;
2782} 2782}
2783static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) 2783static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
2784{ 2784{
2785 return 0x3fffff << 0; 2785 return 0x3fffffU << 0U;
2786} 2786}
2787static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) 2787static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
2788{ 2788{
2789 return 0x00000800; 2789 return 0x00000800U;
2790} 2790}
2791static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) 2791static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void)
2792{ 2792{
2793 return 0x00001100; 2793 return 0x00001100U;
2794} 2794}
2795static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) 2795static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
2796{ 2796{
2797 return 0x00000020; 2797 return 0x00000020U;
2798} 2798}
2799static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) 2799static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void)
2800{ 2800{
2801 return 0x005030f4; 2801 return 0x005030f4U;
2802} 2802}
2803static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) 2803static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void)
2804{ 2804{
2805 return 0x005030e4; 2805 return 0x005030e4U;
2806} 2806}
2807static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) 2807static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v)
2808{ 2808{
2809 return (v & 0xffff) << 0; 2809 return (v & 0xffffU) << 0U;
2810} 2810}
2811static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) 2811static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void)
2812{ 2812{
2813 return 0xffff << 0; 2813 return 0xffffU << 0U;
2814} 2814}
2815static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) 2815static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void)
2816{ 2816{
2817 return 0x00000800; 2817 return 0x00000800U;
2818} 2818}
2819static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) 2819static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void)
2820{ 2820{
2821 return 0x00000020; 2821 return 0x00000020U;
2822} 2822}
2823static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) 2823static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void)
2824{ 2824{
2825 return 0x005030f8; 2825 return 0x005030f8U;
2826} 2826}
2827static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) 2827static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void)
2828{ 2828{
2829 return 0x005030f0; 2829 return 0x005030f0U;
2830} 2830}
2831static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) 2831static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v)
2832{ 2832{
2833 return (v & 0x3fffff) << 0; 2833 return (v & 0x3fffffU) << 0U;
2834} 2834}
2835static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) 2835static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void)
2836{ 2836{
2837 return 0x00000800; 2837 return 0x00000800U;
2838} 2838}
2839static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) 2839static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void)
2840{ 2840{
2841 return 0x00419e00; 2841 return 0x00419e00U;
2842} 2842}
2843static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) 2843static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v)
2844{ 2844{
2845 return (v & 0xffffffff) << 0; 2845 return (v & 0xffffffffU) << 0U;
2846} 2846}
2847static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) 2847static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void)
2848{ 2848{
2849 return 0x00419e04; 2849 return 0x00419e04U;
2850} 2850}
2851static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) 2851static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void)
2852{ 2852{
2853 return 21; 2853 return 21U;
2854} 2854}
2855static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) 2855static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v)
2856{ 2856{
2857 return (v & 0x1fffff) << 0; 2857 return (v & 0x1fffffU) << 0U;
2858} 2858}
2859static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) 2859static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void)
2860{ 2860{
2861 return 0x1fffff << 0; 2861 return 0x1fffffU << 0U;
2862} 2862}
2863static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) 2863static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r)
2864{ 2864{
2865 return (r >> 0) & 0x1fffff; 2865 return (r >> 0U) & 0x1fffffU;
2866} 2866}
2867static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) 2867static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void)
2868{ 2868{
2869 return 0x80; 2869 return 0x80U;
2870} 2870}
2871static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) 2871static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void)
2872{ 2872{
2873 return 1; 2873 return 1U;
2874} 2874}
2875static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) 2875static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v)
2876{ 2876{
2877 return (v & 0x1) << 31; 2877 return (v & 0x1U) << 31U;
2878} 2878}
2879static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) 2879static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void)
2880{ 2880{
2881 return 0x1 << 31; 2881 return 0x1U << 31U;
2882} 2882}
2883static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) 2883static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r)
2884{ 2884{
2885 return (r >> 31) & 0x1; 2885 return (r >> 31U) & 0x1U;
2886} 2886}
2887static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) 2887static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void)
2888{ 2888{
2889 return 0x80000000; 2889 return 0x80000000U;
2890} 2890}
2891static inline u32 gr_gpccs_falcon_addr_r(void) 2891static inline u32 gr_gpccs_falcon_addr_r(void)
2892{ 2892{
2893 return 0x0041a0ac; 2893 return 0x0041a0acU;
2894} 2894}
2895static inline u32 gr_gpccs_falcon_addr_lsb_s(void) 2895static inline u32 gr_gpccs_falcon_addr_lsb_s(void)
2896{ 2896{
2897 return 6; 2897 return 6U;
2898} 2898}
2899static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) 2899static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
2900{ 2900{
2901 return (v & 0x3f) << 0; 2901 return (v & 0x3fU) << 0U;
2902} 2902}
2903static inline u32 gr_gpccs_falcon_addr_lsb_m(void) 2903static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
2904{ 2904{
2905 return 0x3f << 0; 2905 return 0x3fU << 0U;
2906} 2906}
2907static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) 2907static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
2908{ 2908{
2909 return (r >> 0) & 0x3f; 2909 return (r >> 0U) & 0x3fU;
2910} 2910}
2911static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) 2911static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void)
2912{ 2912{
2913 return 0x00000000; 2913 return 0x00000000U;
2914} 2914}
2915static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) 2915static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void)
2916{ 2916{
2917 return 0x0; 2917 return 0x0U;
2918} 2918}
2919static inline u32 gr_gpccs_falcon_addr_msb_s(void) 2919static inline u32 gr_gpccs_falcon_addr_msb_s(void)
2920{ 2920{
2921 return 6; 2921 return 6U;
2922} 2922}
2923static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) 2923static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
2924{ 2924{
2925 return (v & 0x3f) << 6; 2925 return (v & 0x3fU) << 6U;
2926} 2926}
2927static inline u32 gr_gpccs_falcon_addr_msb_m(void) 2927static inline u32 gr_gpccs_falcon_addr_msb_m(void)
2928{ 2928{
2929 return 0x3f << 6; 2929 return 0x3fU << 6U;
2930} 2930}
2931static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) 2931static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
2932{ 2932{
2933 return (r >> 6) & 0x3f; 2933 return (r >> 6U) & 0x3fU;
2934} 2934}
2935static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) 2935static inline u32 gr_gpccs_falcon_addr_msb_init_v(void)
2936{ 2936{
2937 return 0x00000000; 2937 return 0x00000000U;
2938} 2938}
2939static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) 2939static inline u32 gr_gpccs_falcon_addr_msb_init_f(void)
2940{ 2940{
2941 return 0x0; 2941 return 0x0U;
2942} 2942}
2943static inline u32 gr_gpccs_falcon_addr_ext_s(void) 2943static inline u32 gr_gpccs_falcon_addr_ext_s(void)
2944{ 2944{
2945 return 12; 2945 return 12U;
2946} 2946}
2947static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) 2947static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
2948{ 2948{
2949 return (v & 0xfff) << 0; 2949 return (v & 0xfffU) << 0U;
2950} 2950}
2951static inline u32 gr_gpccs_falcon_addr_ext_m(void) 2951static inline u32 gr_gpccs_falcon_addr_ext_m(void)
2952{ 2952{
2953 return 0xfff << 0; 2953 return 0xfffU << 0U;
2954} 2954}
2955static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) 2955static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
2956{ 2956{
2957 return (r >> 0) & 0xfff; 2957 return (r >> 0U) & 0xfffU;
2958} 2958}
2959static inline u32 gr_gpccs_cpuctl_r(void) 2959static inline u32 gr_gpccs_cpuctl_r(void)
2960{ 2960{
2961 return 0x0041a100; 2961 return 0x0041a100U;
2962} 2962}
2963static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) 2963static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v)
2964{ 2964{
2965 return (v & 0x1) << 1; 2965 return (v & 0x1U) << 1U;
2966} 2966}
2967static inline u32 gr_gpccs_dmactl_r(void) 2967static inline u32 gr_gpccs_dmactl_r(void)
2968{ 2968{
2969 return 0x0041a10c; 2969 return 0x0041a10cU;
2970} 2970}
2971static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) 2971static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
2972{ 2972{
2973 return (v & 0x1) << 0; 2973 return (v & 0x1U) << 0U;
2974} 2974}
2975static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) 2975static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
2976{ 2976{
2977 return 0x1 << 1; 2977 return 0x1U << 1U;
2978} 2978}
2979static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) 2979static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
2980{ 2980{
2981 return 0x1 << 2; 2981 return 0x1U << 2U;
2982} 2982}
2983static inline u32 gr_gpccs_imemc_r(u32 i) 2983static inline u32 gr_gpccs_imemc_r(u32 i)
2984{ 2984{
2985 return 0x0041a180 + i*16; 2985 return 0x0041a180U + i*16U;
2986} 2986}
2987static inline u32 gr_gpccs_imemc_offs_f(u32 v) 2987static inline u32 gr_gpccs_imemc_offs_f(u32 v)
2988{ 2988{
2989 return (v & 0x3f) << 2; 2989 return (v & 0x3fU) << 2U;
2990} 2990}
2991static inline u32 gr_gpccs_imemc_blk_f(u32 v) 2991static inline u32 gr_gpccs_imemc_blk_f(u32 v)
2992{ 2992{
2993 return (v & 0xff) << 8; 2993 return (v & 0xffU) << 8U;
2994} 2994}
2995static inline u32 gr_gpccs_imemc_aincw_f(u32 v) 2995static inline u32 gr_gpccs_imemc_aincw_f(u32 v)
2996{ 2996{
2997 return (v & 0x1) << 24; 2997 return (v & 0x1U) << 24U;
2998} 2998}
2999static inline u32 gr_gpccs_imemd_r(u32 i) 2999static inline u32 gr_gpccs_imemd_r(u32 i)
3000{ 3000{
3001 return 0x0041a184 + i*16; 3001 return 0x0041a184U + i*16U;
3002} 3002}
3003static inline u32 gr_gpccs_imemt_r(u32 i) 3003static inline u32 gr_gpccs_imemt_r(u32 i)
3004{ 3004{
3005 return 0x0041a188 + i*16; 3005 return 0x0041a188U + i*16U;
3006} 3006}
3007static inline u32 gr_gpccs_imemt__size_1_v(void) 3007static inline u32 gr_gpccs_imemt__size_1_v(void)
3008{ 3008{
3009 return 0x00000004; 3009 return 0x00000004U;
3010} 3010}
3011static inline u32 gr_gpccs_imemt_tag_f(u32 v) 3011static inline u32 gr_gpccs_imemt_tag_f(u32 v)
3012{ 3012{
3013 return (v & 0xffff) << 0; 3013 return (v & 0xffffU) << 0U;
3014} 3014}
3015static inline u32 gr_gpccs_dmemc_r(u32 i) 3015static inline u32 gr_gpccs_dmemc_r(u32 i)
3016{ 3016{
3017 return 0x0041a1c0 + i*8; 3017 return 0x0041a1c0U + i*8U;
3018} 3018}
3019static inline u32 gr_gpccs_dmemc_offs_f(u32 v) 3019static inline u32 gr_gpccs_dmemc_offs_f(u32 v)
3020{ 3020{
3021 return (v & 0x3f) << 2; 3021 return (v & 0x3fU) << 2U;
3022} 3022}
3023static inline u32 gr_gpccs_dmemc_blk_f(u32 v) 3023static inline u32 gr_gpccs_dmemc_blk_f(u32 v)
3024{ 3024{
3025 return (v & 0xff) << 8; 3025 return (v & 0xffU) << 8U;
3026} 3026}
3027static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) 3027static inline u32 gr_gpccs_dmemc_aincw_f(u32 v)
3028{ 3028{
3029 return (v & 0x1) << 24; 3029 return (v & 0x1U) << 24U;
3030} 3030}
3031static inline u32 gr_gpccs_dmemd_r(u32 i) 3031static inline u32 gr_gpccs_dmemd_r(u32 i)
3032{ 3032{
3033 return 0x0041a1c4 + i*8; 3033 return 0x0041a1c4U + i*8U;
3034} 3034}
3035static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) 3035static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i)
3036{ 3036{
3037 return 0x0041a800 + i*4; 3037 return 0x0041a800U + i*4U;
3038} 3038}
3039static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) 3039static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v)
3040{ 3040{
3041 return (v & 0xffffffff) << 0; 3041 return (v & 0xffffffffU) << 0U;
3042} 3042}
3043static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) 3043static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void)
3044{ 3044{
3045 return 0x00418e24; 3045 return 0x00418e24U;
3046} 3046}
3047static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) 3047static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void)
3048{ 3048{
3049 return 32; 3049 return 32U;
3050} 3050}
3051static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) 3051static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v)
3052{ 3052{
3053 return (v & 0xffffffff) << 0; 3053 return (v & 0xffffffffU) << 0U;
3054} 3054}
3055static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) 3055static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void)
3056{ 3056{
3057 return 0xffffffff << 0; 3057 return 0xffffffffU << 0U;
3058} 3058}
3059static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) 3059static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r)
3060{ 3060{
3061 return (r >> 0) & 0xffffffff; 3061 return (r >> 0U) & 0xffffffffU;
3062} 3062}
3063static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) 3063static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void)
3064{ 3064{
3065 return 0x00000000; 3065 return 0x00000000U;
3066} 3066}
3067static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) 3067static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void)
3068{ 3068{
3069 return 0x0; 3069 return 0x0U;
3070} 3070}
3071static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) 3071static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void)
3072{ 3072{
3073 return 0x00418e28; 3073 return 0x00418e28U;
3074} 3074}
3075static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) 3075static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void)
3076{ 3076{
3077 return 11; 3077 return 11U;
3078} 3078}
3079static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) 3079static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v)
3080{ 3080{
3081 return (v & 0x7ff) << 0; 3081 return (v & 0x7ffU) << 0U;
3082} 3082}
3083static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) 3083static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void)
3084{ 3084{
3085 return 0x7ff << 0; 3085 return 0x7ffU << 0U;
3086} 3086}
3087static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) 3087static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
3088{ 3088{
3089 return (r >> 0) & 0x7ff; 3089 return (r >> 0U) & 0x7ffU;
3090} 3090}
3091static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) 3091static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void)
3092{ 3092{
3093 return 0x00000030; 3093 return 0x00000030U;
3094} 3094}
3095static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) 3095static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void)
3096{ 3096{
3097 return 0x30; 3097 return 0x30U;
3098} 3098}
3099static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) 3099static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void)
3100{ 3100{
3101 return 1; 3101 return 1U;
3102} 3102}
3103static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) 3103static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v)
3104{ 3104{
3105 return (v & 0x1) << 31; 3105 return (v & 0x1U) << 31U;
3106} 3106}
3107static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) 3107static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void)
3108{ 3108{
3109 return 0x1 << 31; 3109 return 0x1U << 31U;
3110} 3110}
3111static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) 3111static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r)
3112{ 3112{
3113 return (r >> 31) & 0x1; 3113 return (r >> 31U) & 0x1U;
3114} 3114}
3115static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) 3115static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void)
3116{ 3116{
3117 return 0x00000000; 3117 return 0x00000000U;
3118} 3118}
3119static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) 3119static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void)
3120{ 3120{
3121 return 0x0; 3121 return 0x0U;
3122} 3122}
3123static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) 3123static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void)
3124{ 3124{
3125 return 0x00000001; 3125 return 0x00000001U;
3126} 3126}
3127static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) 3127static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void)
3128{ 3128{
3129 return 0x80000000; 3129 return 0x80000000U;
3130} 3130}
3131static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) 3131static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void)
3132{ 3132{
3133 return 0x005001dc; 3133 return 0x005001dcU;
3134} 3134}
3135static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) 3135static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v)
3136{ 3136{
3137 return (v & 0xffff) << 0; 3137 return (v & 0xffffU) << 0U;
3138} 3138}
3139static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) 3139static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void)
3140{ 3140{
3141 return 0x00000170; 3141 return 0x00000170U;
3142} 3142}
3143static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) 3143static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void)
3144{ 3144{
3145 return 0x00000100; 3145 return 0x00000100U;
3146} 3146}
3147static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) 3147static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void)
3148{ 3148{
3149 return 0x005001d8; 3149 return 0x005001d8U;
3150} 3150}
3151static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) 3151static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v)
3152{ 3152{
3153 return (v & 0xffffffff) << 0; 3153 return (v & 0xffffffffU) << 0U;
3154} 3154}
3155static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) 3155static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void)
3156{ 3156{
3157 return 0x00000008; 3157 return 0x00000008U;
3158} 3158}
3159static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) 3159static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void)
3160{ 3160{
3161 return 0x004181e4; 3161 return 0x004181e4U;
3162} 3162}
3163static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) 3163static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v)
3164{ 3164{
3165 return (v & 0xfff) << 0; 3165 return (v & 0xfffU) << 0U;
3166} 3166}
3167static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) 3167static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void)
3168{ 3168{
3169 return 0x00000100; 3169 return 0x00000100U;
3170} 3170}
3171static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) 3171static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void)
3172{ 3172{
3173 return 0x0041befc; 3173 return 0x0041befcU;
3174} 3174}
3175static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) 3175static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v)
3176{ 3176{
3177 return (v & 0xfff) << 0; 3177 return (v & 0xfffU) << 0U;
3178} 3178}
3179static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) 3179static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i)
3180{ 3180{
3181 return 0x00418ea0 + i*4; 3181 return 0x00418ea0U + i*4U;
3182} 3182}
3183static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) 3183static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
3184{ 3184{
3185 return (v & 0x3fffff) << 0; 3185 return (v & 0x3fffffU) << 0U;
3186} 3186}
3187static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) 3187static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
3188{ 3188{
3189 return 0x3fffff << 0; 3189 return 0x3fffffU << 0U;
3190} 3190}
3191static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) 3191static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i)
3192{ 3192{
3193 return 0x00418010 + i*4; 3193 return 0x00418010U + i*4U;
3194} 3194}
3195static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) 3195static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v)
3196{ 3196{
3197 return (v & 0xffffffff) << 0; 3197 return (v & 0xffffffffU) << 0U;
3198} 3198}
3199static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) 3199static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i)
3200{ 3200{
3201 return 0x0041804c + i*4; 3201 return 0x0041804cU + i*4U;
3202} 3202}
3203static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) 3203static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v)
3204{ 3204{
3205 return (v & 0xffffffff) << 0; 3205 return (v & 0xffffffffU) << 0U;
3206} 3206}
3207static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) 3207static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i)
3208{ 3208{
3209 return 0x00418088 + i*4; 3209 return 0x00418088U + i*4U;
3210} 3210}
3211static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) 3211static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v)
3212{ 3212{
3213 return (v & 0xffffffff) << 0; 3213 return (v & 0xffffffffU) << 0U;
3214} 3214}
3215static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) 3215static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i)
3216{ 3216{
3217 return 0x004180c4 + i*4; 3217 return 0x004180c4U + i*4U;
3218} 3218}
3219static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) 3219static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v)
3220{ 3220{
3221 return (v & 0xffffffff) << 0; 3221 return (v & 0xffffffffU) << 0U;
3222} 3222}
3223static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) 3223static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void)
3224{ 3224{
3225 return 0x00418100; 3225 return 0x00418100U;
3226} 3226}
3227static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) 3227static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i)
3228{ 3228{
3229 return 0x00418110 + i*4; 3229 return 0x00418110U + i*4U;
3230} 3230}
3231static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) 3231static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v)
3232{ 3232{
3233 return (v & 0xffffffff) << 0; 3233 return (v & 0xffffffffU) << 0U;
3234} 3234}
3235static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) 3235static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void)
3236{ 3236{
3237 return 0x0041814c; 3237 return 0x0041814cU;
3238} 3238}
3239static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i) 3239static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i)
3240{ 3240{
3241 return 0x0041815c + i*4; 3241 return 0x0041815cU + i*4U;
3242} 3242}
3243static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v) 3243static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v)
3244{ 3244{
3245 return (v & 0xff) << 0; 3245 return (v & 0xffU) << 0U;
3246} 3246}
3247static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void) 3247static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void)
3248{ 3248{
3249 return 0x00418198; 3249 return 0x00418198U;
3250} 3250}
3251static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) 3251static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
3252{ 3252{
3253 return 0x00418810; 3253 return 0x00418810U;
3254} 3254}
3255static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) 3255static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v)
3256{ 3256{
3257 return (v & 0xfffffff) << 0; 3257 return (v & 0xfffffffU) << 0U;
3258} 3258}
3259static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) 3259static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void)
3260{ 3260{
3261 return 0x0000000c; 3261 return 0x0000000cU;
3262} 3262}
3263static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) 3263static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
3264{ 3264{
3265 return 0x80000000; 3265 return 0x80000000U;
3266} 3266}
3267static inline u32 gr_crstr_gpc_map_r(u32 i) 3267static inline u32 gr_crstr_gpc_map_r(u32 i)
3268{ 3268{
3269 return 0x00418b08 + i*4; 3269 return 0x00418b08U + i*4U;
3270} 3270}
3271static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) 3271static inline u32 gr_crstr_gpc_map_tile0_f(u32 v)
3272{ 3272{
3273 return (v & 0x1f) << 0; 3273 return (v & 0x1fU) << 0U;
3274} 3274}
3275static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) 3275static inline u32 gr_crstr_gpc_map_tile1_f(u32 v)
3276{ 3276{
3277 return (v & 0x1f) << 5; 3277 return (v & 0x1fU) << 5U;
3278} 3278}
3279static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) 3279static inline u32 gr_crstr_gpc_map_tile2_f(u32 v)
3280{ 3280{
3281 return (v & 0x1f) << 10; 3281 return (v & 0x1fU) << 10U;
3282} 3282}
3283static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) 3283static inline u32 gr_crstr_gpc_map_tile3_f(u32 v)
3284{ 3284{
3285 return (v & 0x1f) << 15; 3285 return (v & 0x1fU) << 15U;
3286} 3286}
3287static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) 3287static inline u32 gr_crstr_gpc_map_tile4_f(u32 v)
3288{ 3288{
3289 return (v & 0x1f) << 20; 3289 return (v & 0x1fU) << 20U;
3290} 3290}
3291static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) 3291static inline u32 gr_crstr_gpc_map_tile5_f(u32 v)
3292{ 3292{
3293 return (v & 0x1f) << 25; 3293 return (v & 0x1fU) << 25U;
3294} 3294}
3295static inline u32 gr_crstr_map_table_cfg_r(void) 3295static inline u32 gr_crstr_map_table_cfg_r(void)
3296{ 3296{
3297 return 0x00418bb8; 3297 return 0x00418bb8U;
3298} 3298}
3299static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) 3299static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v)
3300{ 3300{
3301 return (v & 0xff) << 0; 3301 return (v & 0xffU) << 0U;
3302} 3302}
3303static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) 3303static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
3304{ 3304{
3305 return (v & 0xff) << 8; 3305 return (v & 0xffU) << 8U;
3306} 3306}
3307static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) 3307static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i)
3308{ 3308{
3309 return 0x00418980 + i*4; 3309 return 0x00418980U + i*4U;
3310} 3310}
3311static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) 3311static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v)
3312{ 3312{
3313 return (v & 0x7) << 0; 3313 return (v & 0x7U) << 0U;
3314} 3314}
3315static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) 3315static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v)
3316{ 3316{
3317 return (v & 0x7) << 4; 3317 return (v & 0x7U) << 4U;
3318} 3318}
3319static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) 3319static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v)
3320{ 3320{
3321 return (v & 0x7) << 8; 3321 return (v & 0x7U) << 8U;
3322} 3322}
3323static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) 3323static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v)
3324{ 3324{
3325 return (v & 0x7) << 12; 3325 return (v & 0x7U) << 12U;
3326} 3326}
3327static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) 3327static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v)
3328{ 3328{
3329 return (v & 0x7) << 16; 3329 return (v & 0x7U) << 16U;
3330} 3330}
3331static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) 3331static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v)
3332{ 3332{
3333 return (v & 0x7) << 20; 3333 return (v & 0x7U) << 20U;
3334} 3334}
3335static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) 3335static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v)
3336{ 3336{
3337 return (v & 0x7) << 24; 3337 return (v & 0x7U) << 24U;
3338} 3338}
3339static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) 3339static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v)
3340{ 3340{
3341 return (v & 0x7) << 28; 3341 return (v & 0x7U) << 28U;
3342} 3342}
3343static inline u32 gr_gpcs_gpm_pd_cfg_r(void) 3343static inline u32 gr_gpcs_gpm_pd_cfg_r(void)
3344{ 3344{
3345 return 0x00418c6c; 3345 return 0x00418c6cU;
3346} 3346}
3347static inline u32 gr_gpcs_gcc_pagepool_base_r(void) 3347static inline u32 gr_gpcs_gcc_pagepool_base_r(void)
3348{ 3348{
3349 return 0x00419004; 3349 return 0x00419004U;
3350} 3350}
3351static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) 3351static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v)
3352{ 3352{
3353 return (v & 0xffffffff) << 0; 3353 return (v & 0xffffffffU) << 0U;
3354} 3354}
3355static inline u32 gr_gpcs_gcc_pagepool_r(void) 3355static inline u32 gr_gpcs_gcc_pagepool_r(void)
3356{ 3356{
3357 return 0x00419008; 3357 return 0x00419008U;
3358} 3358}
3359static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) 3359static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v)
3360{ 3360{
3361 return (v & 0x3ff) << 0; 3361 return (v & 0x3ffU) << 0U;
3362} 3362}
3363static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) 3363static inline u32 gr_gpcs_tpcs_pe_vaf_r(void)
3364{ 3364{
3365 return 0x0041980c; 3365 return 0x0041980cU;
3366} 3366}
3367static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) 3367static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void)
3368{ 3368{
3369 return 0x10; 3369 return 0x10U;
3370} 3370}
3371static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) 3371static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void)
3372{ 3372{
3373 return 0x00419848; 3373 return 0x00419848U;
3374} 3374}
3375static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) 3375static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v)
3376{ 3376{
3377 return (v & 0xfffffff) << 0; 3377 return (v & 0xfffffffU) << 0U;
3378} 3378}
3379static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) 3379static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v)
3380{ 3380{
3381 return (v & 0x1) << 28; 3381 return (v & 0x1U) << 28U;
3382} 3382}
3383static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) 3383static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
3384{ 3384{
3385 return 0x10000000; 3385 return 0x10000000U;
3386} 3386}
3387static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) 3387static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
3388{ 3388{
3389 return 0x00419c00; 3389 return 0x00419c00U;
3390} 3390}
3391static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) 3391static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void)
3392{ 3392{
3393 return 0x0; 3393 return 0x0U;
3394} 3394}
3395static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) 3395static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
3396{ 3396{
3397 return 0x8; 3397 return 0x8U;
3398} 3398}
3399static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) 3399static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void)
3400{ 3400{
3401 return 0x00419c2c; 3401 return 0x00419c2cU;
3402} 3402}
3403static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) 3403static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v)
3404{ 3404{
3405 return (v & 0xfffffff) << 0; 3405 return (v & 0xfffffffU) << 0U;
3406} 3406}
3407static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) 3407static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v)
3408{ 3408{
3409 return (v & 0x1) << 28; 3409 return (v & 0x1U) << 28U;
3410} 3410}
3411static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) 3411static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void)
3412{ 3412{
3413 return 0x10000000; 3413 return 0x10000000U;
3414} 3414}
3415static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void) 3415static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void)
3416{ 3416{
3417 return 0x00419ea8; 3417 return 0x00419ea8U;
3418} 3418}
3419static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void) 3419static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void)
3420{ 3420{
3421 return 0x00504728; 3421 return 0x00504728U;
3422} 3422}
3423static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) 3423static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void)
3424{ 3424{
3425 return 0x2; 3425 return 0x2U;
3426} 3426}
3427static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) 3427static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void)
3428{ 3428{
3429 return 0x4; 3429 return 0x4U;
3430} 3430}
3431static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) 3431static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void)
3432{ 3432{
3433 return 0x10; 3433 return 0x10U;
3434} 3434}
3435static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) 3435static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
3436{ 3436{
3437 return 0x20; 3437 return 0x20U;
3438} 3438}
3439static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) 3439static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void)
3440{ 3440{
3441 return 0x40; 3441 return 0x40U;
3442} 3442}
3443static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) 3443static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
3444{ 3444{
3445 return 0x100; 3445 return 0x100U;
3446} 3446}
3447static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) 3447static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
3448{ 3448{
3449 return 0x200; 3449 return 0x200U;
3450} 3450}
3451static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) 3451static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
3452{ 3452{
3453 return 0x800; 3453 return 0x800U;
3454} 3454}
3455static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) 3455static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void)
3456{ 3456{
3457 return 0x2000; 3457 return 0x2000U;
3458} 3458}
3459static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) 3459static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void)
3460{ 3460{
3461 return 0x4000; 3461 return 0x4000U;
3462} 3462}
3463static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) 3463static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
3464{ 3464{
3465 return 0x8000; 3465 return 0x8000U;
3466} 3466}
3467static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) 3467static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
3468{ 3468{
3469 return 0x10000; 3469 return 0x10000U;
3470} 3470}
3471static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) 3471static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
3472{ 3472{
3473 return 0x40000; 3473 return 0x40000U;
3474} 3474}
3475static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) 3475static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void)
3476{ 3476{
3477 return 0x800000; 3477 return 0x800000U;
3478} 3478}
3479static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) 3479static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void)
3480{ 3480{
3481 return 0x400000; 3481 return 0x400000U;
3482} 3482}
3483static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) 3483static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
3484{ 3484{
3485 return 0x00419d0c; 3485 return 0x00419d0cU;
3486} 3486}
3487static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) 3487static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void)
3488{ 3488{
3489 return 0x2; 3489 return 0x2U;
3490} 3490}
3491static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) 3491static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void)
3492{ 3492{
3493 return 0x1; 3493 return 0x1U;
3494} 3494}
3495static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void) 3495static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void)
3496{ 3496{
3497 return 0x10; 3497 return 0x10U;
3498} 3498}
3499static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) 3499static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
3500{ 3500{
3501 return 0x0050450c; 3501 return 0x0050450cU;
3502} 3502}
3503static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) 3503static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r)
3504{ 3504{
3505 return (r >> 1) & 0x1; 3505 return (r >> 1U) & 0x1U;
3506} 3506}
3507static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) 3507static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
3508{ 3508{
3509 return 0x2; 3509 return 0x2U;
3510} 3510}
3511static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void) 3511static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void)
3512{ 3512{
3513 return 0x10; 3513 return 0x10U;
3514} 3514}
3515static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) 3515static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void)
3516{ 3516{
3517 return 0x0041ac94; 3517 return 0x0041ac94U;
3518} 3518}
3519static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v) 3519static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v)
3520{ 3520{
3521 return (v & 0x1) << 2; 3521 return (v & 0x1U) << 2U;
3522} 3522}
3523static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) 3523static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v)
3524{ 3524{
3525 return (v & 0xff) << 16; 3525 return (v & 0xffU) << 16U;
3526} 3526}
3527static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpccs_f(u32 v) 3527static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpccs_f(u32 v)
3528{ 3528{
3529 return (v & 0x1) << 14; 3529 return (v & 0x1U) << 14U;
3530} 3530}
3531static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(u32 v) 3531static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpcmmu_f(u32 v)
3532{ 3532{
3533 return (v & 0x1) << 15; 3533 return (v & 0x1U) << 15U;
3534} 3534}
3535static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) 3535static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
3536{ 3536{
3537 return 0x00502c90; 3537 return 0x00502c90U;
3538} 3538}
3539static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r) 3539static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r)
3540{ 3540{
3541 return (r >> 2) & 0x1; 3541 return (r >> 2U) & 0x1U;
3542} 3542}
3543static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) 3543static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
3544{ 3544{
3545 return (r >> 16) & 0xff; 3545 return (r >> 16U) & 0xffU;
3546} 3546}
3547static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) 3547static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void)
3548{ 3548{
3549 return 0x00000001; 3549 return 0x00000001U;
3550} 3550}
3551static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_f(u32 v) 3551static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_f(u32 v)
3552{ 3552{
3553 return (v & 0x1) << 14; 3553 return (v & 0x1U) << 14U;
3554} 3554}
3555static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_m(void) 3555static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_m(void)
3556{ 3556{
3557 return 0x1 << 14; 3557 return 0x1U << 14U;
3558} 3558}
3559static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_pending_f(void) 3559static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_pending_f(void)
3560{ 3560{
3561 return 0x4000; 3561 return 0x4000U;
3562} 3562}
3563static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_f(u32 v) 3563static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_f(u32 v)
3564{ 3564{
3565 return (v & 0x1) << 15; 3565 return (v & 0x1U) << 15U;
3566} 3566}
3567static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_m(void) 3567static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_m(void)
3568{ 3568{
3569 return 0x1 << 15; 3569 return 0x1U << 15U;
3570} 3570}
3571static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_pending_f(void) 3571static inline u32 gr_gpc0_gpccs_gpc_exception_gpcmmu_pending_f(void)
3572{ 3572{
3573 return 0x8000; 3573 return 0x8000U;
3574} 3574}
3575static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_r(void) 3575static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_r(void)
3576{ 3576{
3577 return 0x00501048; 3577 return 0x00501048U;
3578} 3578}
3579static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank0_m(void) 3579static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank0_m(void)
3580{ 3580{
3581 return 0x1 << 0; 3581 return 0x1U << 0U;
3582} 3582}
3583static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank1_m(void) 3583static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_bank1_m(void)
3584{ 3584{
3585 return 0x1 << 1; 3585 return 0x1U << 1U;
3586} 3586}
3587static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank0_m(void) 3587static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank0_m(void)
3588{ 3588{
3589 return 0x1 << 4; 3589 return 0x1U << 4U;
3590} 3590}
3591static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank1_m(void) 3591static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank1_m(void)
3592{ 3592{
3593 return 0x1 << 5; 3593 return 0x1U << 5U;
3594} 3594}
3595static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_total_counter_overflow_v(u32 r) 3595static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_corrected_err_total_counter_overflow_v(u32 r)
3596{ 3596{
3597 return (r >> 8) & 0x1; 3597 return (r >> 8U) & 0x1U;
3598} 3598}
3599static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) 3599static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r)
3600{ 3600{
3601 return (r >> 10) & 0x1; 3601 return (r >> 10U) & 0x1U;
3602} 3602}
3603static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_reset_task_f(void) 3603static inline u32 gr_pri_gpc0_gcc_l15_ecc_status_reset_task_f(void)
3604{ 3604{
3605 return 0x40000000; 3605 return 0x40000000U;
3606} 3606}
3607static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r(void) 3607static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r(void)
3608{ 3608{
3609 return 0x0050104c; 3609 return 0x0050104cU;
3610} 3610}
3611static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s(void) 3611static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s(void)
3612{ 3612{
3613 return 16; 3613 return 16U;
3614} 3614}
3615static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_v(u32 r) 3615static inline u32 gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_v(u32 r)
3616{ 3616{
3617 return (r >> 0) & 0xffff; 3617 return (r >> 0U) & 0xffffU;
3618} 3618}
3619static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r(void) 3619static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r(void)
3620{ 3620{
3621 return 0x00501054; 3621 return 0x00501054U;
3622} 3622}
3623static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s(void) 3623static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s(void)
3624{ 3624{
3625 return 16; 3625 return 16U;
3626} 3626}
3627static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v(u32 r) 3627static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v(u32 r)
3628{ 3628{
3629 return (r >> 0) & 0xffff; 3629 return (r >> 0U) & 0xffffU;
3630} 3630}
3631static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) 3631static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void)
3632{ 3632{
3633 return 0x00504508; 3633 return 0x00504508U;
3634} 3634}
3635static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) 3635static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r)
3636{ 3636{
3637 return (r >> 0) & 0x1; 3637 return (r >> 0U) & 0x1U;
3638} 3638}
3639static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) 3639static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void)
3640{ 3640{
3641 return 0x00000001; 3641 return 0x00000001U;
3642} 3642}
3643static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) 3643static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r)
3644{ 3644{
3645 return (r >> 1) & 0x1; 3645 return (r >> 1U) & 0x1U;
3646} 3646}
3647static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) 3647static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
3648{ 3648{
3649 return 0x00000001; 3649 return 0x00000001U;
3650} 3650}
3651static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void) 3651static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void)
3652{ 3652{
3653 return 0x1 << 4; 3653 return 0x1U << 4U;
3654} 3654}
3655static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void) 3655static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void)
3656{ 3656{
3657 return 0x10; 3657 return 0x10U;
3658} 3658}
3659static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) 3659static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void)
3660{ 3660{
3661 return 0x00504704; 3661 return 0x00504704U;
3662} 3662}
3663static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) 3663static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void)
3664{ 3664{
3665 return 0x1 << 0; 3665 return 0x1U << 0U;
3666} 3666}
3667static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) 3667static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r)
3668{ 3668{
3669 return (r >> 0) & 0x1; 3669 return (r >> 0U) & 0x1U;
3670} 3670}
3671static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) 3671static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void)
3672{ 3672{
3673 return 0x00000001; 3673 return 0x00000001U;
3674} 3674}
3675static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void) 3675static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void)
3676{ 3676{
3677 return 0x1; 3677 return 0x1U;
3678} 3678}
3679static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) 3679static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void)
3680{ 3680{
3681 return 0x00000000; 3681 return 0x00000000U;
3682} 3682}
3683static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void) 3683static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void)
3684{ 3684{
3685 return 0x0; 3685 return 0x0U;
3686} 3686}
3687static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void) 3687static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void)
3688{ 3688{
3689 return 0x1 << 31; 3689 return 0x1U << 31U;
3690} 3690}
3691static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) 3691static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void)
3692{ 3692{
3693 return 0x80000000; 3693 return 0x80000000U;
3694} 3694}
3695static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) 3695static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void)
3696{ 3696{
3697 return 0x0; 3697 return 0x0U;
3698} 3698}
3699static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void) 3699static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void)
3700{ 3700{
3701 return 0x1 << 3; 3701 return 0x1U << 3U;
3702} 3702}
3703static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) 3703static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void)
3704{ 3704{
3705 return 0x8; 3705 return 0x8U;
3706} 3706}
3707static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) 3707static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void)
3708{ 3708{
3709 return 0x0; 3709 return 0x0U;
3710} 3710}
3711static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) 3711static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void)
3712{ 3712{
3713 return 0x40000000; 3713 return 0x40000000U;
3714} 3714}
3715static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void) 3715static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void)
3716{ 3716{
3717 return 0x00504708; 3717 return 0x00504708U;
3718} 3718}
3719static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void) 3719static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void)
3720{ 3720{
3721 return 0x0050470c; 3721 return 0x0050470cU;
3722} 3722}
3723static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void) 3723static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void)
3724{ 3724{
3725 return 0x00504710; 3725 return 0x00504710U;
3726} 3726}
3727static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void) 3727static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void)
3728{ 3728{
3729 return 0x00504714; 3729 return 0x00504714U;
3730} 3730}
3731static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void) 3731static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void)
3732{ 3732{
3733 return 0x00504718; 3733 return 0x00504718U;
3734} 3734}
3735static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void) 3735static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void)
3736{ 3736{
3737 return 0x0050471c; 3737 return 0x0050471cU;
3738} 3738}
3739static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void) 3739static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void)
3740{ 3740{
3741 return 0x00419e90; 3741 return 0x00419e90U;
3742} 3742}
3743static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void) 3743static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void)
3744{ 3744{
3745 return 0x00419e94; 3745 return 0x00419e94U;
3746} 3746}
3747static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void) 3747static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void)
3748{ 3748{
3749 return 0x00419e80; 3749 return 0x00419e80U;
3750} 3750}
3751static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) 3751static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void)
3752{ 3752{
3753 return 0x00504700; 3753 return 0x00504700U;
3754} 3754}
3755static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) 3755static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r)
3756{ 3756{
3757 return (r >> 0) & 0x1; 3757 return (r >> 0U) & 0x1U;
3758} 3758}
3759static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) 3759static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r)
3760{ 3760{
3761 return (r >> 4) & 0x1; 3761 return (r >> 4U) & 0x1U;
3762} 3762}
3763static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) 3763static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void)
3764{ 3764{
3765 return 0x00000001; 3765 return 0x00000001U;
3766} 3766}
3767static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) 3767static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void)
3768{ 3768{
3769 return 0x00504730; 3769 return 0x00504730U;
3770} 3770}
3771static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) 3771static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r)
3772{ 3772{
3773 return (r >> 0) & 0xffff; 3773 return (r >> 0U) & 0xffffU;
3774} 3774}
3775static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) 3775static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void)
3776{ 3776{
3777 return 0x00000000; 3777 return 0x00000000U;
3778} 3778}
3779static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) 3779static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void)
3780{ 3780{
3781 return 0x0; 3781 return 0x0U;
3782} 3782}
3783static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) 3783static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void)
3784{ 3784{
3785 return 0xff << 16; 3785 return 0xffU << 16U;
3786} 3786}
3787static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) 3787static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void)
3788{ 3788{
3789 return 0xf << 24; 3789 return 0xfU << 24U;
3790} 3790}
3791static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) 3791static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void)
3792{ 3792{
3793 return 0x0; 3793 return 0x0U;
3794} 3794}
3795static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void) 3795static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void)
3796{ 3796{
3797 return 0x0050460c; 3797 return 0x0050460cU;
3798} 3798}
3799static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r) 3799static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r)
3800{ 3800{
3801 return (r >> 0) & 0x1; 3801 return (r >> 0U) & 0x1U;
3802} 3802}
3803static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r) 3803static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r)
3804{ 3804{
3805 return (r >> 1) & 0x1; 3805 return (r >> 1U) & 0x1U;
3806} 3806}
3807static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) 3807static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void)
3808{ 3808{
3809 return 0x00504738; 3809 return 0x00504738U;
3810} 3810}
3811static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) 3811static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
3812{ 3812{
3813 return 0x005043a0; 3813 return 0x005043a0U;
3814} 3814}
3815static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) 3815static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
3816{ 3816{
3817 return 0x00419ba0; 3817 return 0x00419ba0U;
3818} 3818}
3819static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) 3819static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
3820{ 3820{
3821 return 0x1 << 4; 3821 return 0x1U << 4U;
3822} 3822}
3823static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) 3823static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
3824{ 3824{
3825 return (v & 0x1) << 4; 3825 return (v & 0x1U) << 4U;
3826} 3826}
3827static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) 3827static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
3828{ 3828{
3829 return 0x005043b0; 3829 return 0x005043b0U;
3830} 3830}
3831static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) 3831static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
3832{ 3832{
3833 return 0x00419bb0; 3833 return 0x00419bb0U;
3834} 3834}
3835static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) 3835static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
3836{ 3836{
3837 return 0x1 << 0; 3837 return 0x1U << 0U;
3838} 3838}
3839static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) 3839static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
3840{ 3840{
3841 return (v & 0x1) << 0; 3841 return (v & 0x1U) << 0U;
3842} 3842}
3843static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) 3843static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
3844{ 3844{
3845 return 0x0041be08; 3845 return 0x0041be08U;
3846} 3846}
3847static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) 3847static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
3848{ 3848{
3849 return 0x4; 3849 return 0x4U;
3850} 3850}
3851static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) 3851static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i)
3852{ 3852{
3853 return 0x0041bf00 + i*4; 3853 return 0x0041bf00U + i*4U;
3854} 3854}
3855static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) 3855static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
3856{ 3856{
3857 return 0x0041bfd0; 3857 return 0x0041bfd0U;
3858} 3858}
3859static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) 3859static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v)
3860{ 3860{
3861 return (v & 0xff) << 0; 3861 return (v & 0xffU) << 0U;
3862} 3862}
3863static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) 3863static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v)
3864{ 3864{
3865 return (v & 0xff) << 8; 3865 return (v & 0xffU) << 8U;
3866} 3866}
3867static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) 3867static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v)
3868{ 3868{
3869 return (v & 0x1f) << 16; 3869 return (v & 0x1fU) << 16U;
3870} 3870}
3871static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) 3871static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
3872{ 3872{
3873 return (v & 0x7) << 21; 3873 return (v & 0x7U) << 21U;
3874} 3874}
3875static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) 3875static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
3876{ 3876{
3877 return 0x0041bfd4; 3877 return 0x0041bfd4U;
3878} 3878}
3879static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) 3879static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
3880{ 3880{
3881 return (v & 0xffffff) << 0; 3881 return (v & 0xffffffU) << 0U;
3882} 3882}
3883static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) 3883static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i)
3884{ 3884{
3885 return 0x0041bfb0 + i*4; 3885 return 0x0041bfb0U + i*4U;
3886} 3886}
3887static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void) 3887static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void)
3888{ 3888{
3889 return 0x00000005; 3889 return 0x00000005U;
3890} 3890}
3891static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) 3891static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v)
3892{ 3892{
3893 return (v & 0xff) << 0; 3893 return (v & 0xffU) << 0U;
3894} 3894}
3895static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) 3895static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v)
3896{ 3896{
3897 return (v & 0xff) << 8; 3897 return (v & 0xffU) << 8U;
3898} 3898}
3899static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) 3899static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v)
3900{ 3900{
3901 return (v & 0xff) << 16; 3901 return (v & 0xffU) << 16U;
3902} 3902}
3903static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) 3903static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v)
3904{ 3904{
3905 return (v & 0xff) << 24; 3905 return (v & 0xffU) << 24U;
3906} 3906}
3907static inline u32 gr_bes_zrop_settings_r(void) 3907static inline u32 gr_bes_zrop_settings_r(void)
3908{ 3908{
3909 return 0x00408850; 3909 return 0x00408850U;
3910} 3910}
3911static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) 3911static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v)
3912{ 3912{
3913 return (v & 0xf) << 0; 3913 return (v & 0xfU) << 0U;
3914} 3914}
3915static inline u32 gr_be0_crop_debug3_r(void) 3915static inline u32 gr_be0_crop_debug3_r(void)
3916{ 3916{
3917 return 0x00410108; 3917 return 0x00410108U;
3918} 3918}
3919static inline u32 gr_bes_crop_debug3_r(void) 3919static inline u32 gr_bes_crop_debug3_r(void)
3920{ 3920{
3921 return 0x00408908; 3921 return 0x00408908U;
3922} 3922}
3923static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) 3923static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void)
3924{ 3924{
3925 return 0x1 << 31; 3925 return 0x1U << 31U;
3926} 3926}
3927static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void) 3927static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void)
3928{ 3928{
3929 return 0x1 << 1; 3929 return 0x1U << 1U;
3930} 3930}
3931static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void) 3931static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void)
3932{ 3932{
3933 return 0x0; 3933 return 0x0U;
3934} 3934}
3935static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void) 3935static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void)
3936{ 3936{
3937 return 0x2; 3937 return 0x2U;
3938} 3938}
3939static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void) 3939static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void)
3940{ 3940{
3941 return 0x1 << 2; 3941 return 0x1U << 2U;
3942} 3942}
3943static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void) 3943static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void)
3944{ 3944{
3945 return 0x0; 3945 return 0x0U;
3946} 3946}
3947static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void) 3947static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void)
3948{ 3948{
3949 return 0x4; 3949 return 0x4U;
3950} 3950}
3951static inline u32 gr_bes_crop_settings_r(void) 3951static inline u32 gr_bes_crop_settings_r(void)
3952{ 3952{
3953 return 0x00408958; 3953 return 0x00408958U;
3954} 3954}
3955static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) 3955static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v)
3956{ 3956{
3957 return (v & 0xf) << 0; 3957 return (v & 0xfU) << 0U;
3958} 3958}
3959static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) 3959static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void)
3960{ 3960{
3961 return 0x00000020; 3961 return 0x00000020U;
3962} 3962}
3963static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) 3963static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void)
3964{ 3964{
3965 return 0x00000020; 3965 return 0x00000020U;
3966} 3966}
3967static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) 3967static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void)
3968{ 3968{
3969 return 0x000000c0; 3969 return 0x000000c0U;
3970} 3970}
3971static inline u32 gr_zcull_subregion_qty_v(void) 3971static inline u32 gr_zcull_subregion_qty_v(void)
3972{ 3972{
3973 return 0x00000010; 3973 return 0x00000010U;
3974} 3974}
3975static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void) 3975static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void)
3976{ 3976{
3977 return 0x00419a00; 3977 return 0x00419a00U;
3978} 3978}
3979static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v) 3979static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v)
3980{ 3980{
3981 return (v & 0x1) << 19; 3981 return (v & 0x1U) << 19U;
3982} 3982}
3983static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void) 3983static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void)
3984{ 3984{
3985 return 0x1 << 19; 3985 return 0x1U << 19U;
3986} 3986}
3987static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void) 3987static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void)
3988{ 3988{
3989 return 0x00419bf0; 3989 return 0x00419bf0U;
3990} 3990}
3991static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v) 3991static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v)
3992{ 3992{
3993 return (v & 0x1) << 5; 3993 return (v & 0x1U) << 5U;
3994} 3994}
3995static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void) 3995static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void)
3996{ 3996{
3997 return 0x1 << 5; 3997 return 0x1U << 5U;
3998} 3998}
3999static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v) 3999static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v)
4000{ 4000{
4001 return (v & 0x1) << 10; 4001 return (v & 0x1U) << 10U;
4002} 4002}
4003static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) 4003static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void)
4004{ 4004{
4005 return 0x1 << 10; 4005 return 0x1U << 10U;
4006} 4006}
4007static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r(void) 4007static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r(void)
4008{ 4008{
4009 return 0x00584200; 4009 return 0x00584200U;
4010} 4010}
4011static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r(void) 4011static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r(void)
4012{ 4012{
4013 return 0x00584204; 4013 return 0x00584204U;
4014} 4014}
4015static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r(void) 4015static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r(void)
4016{ 4016{
4017 return 0x00584208; 4017 return 0x00584208U;
4018} 4018}
4019static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control1_r(void) 4019static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control1_r(void)
4020{ 4020{
4021 return 0x00584210; 4021 return 0x00584210U;
4022} 4022}
4023static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control2_r(void) 4023static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control2_r(void)
4024{ 4024{
4025 return 0x00584214; 4025 return 0x00584214U;
4026} 4026}
4027static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control3_r(void) 4027static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control3_r(void)
4028{ 4028{
4029 return 0x00584218; 4029 return 0x00584218U;
4030} 4030}
4031static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control4_r(void) 4031static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control4_r(void)
4032{ 4032{
4033 return 0x0058421c; 4033 return 0x0058421cU;
4034} 4034}
4035static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r(void) 4035static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r(void)
4036{ 4036{
4037 return 0x0058420c; 4037 return 0x0058420cU;
4038} 4038}
4039static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter0_control_r(void) 4039static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter0_control_r(void)
4040{ 4040{
4041 return 0x00584220; 4041 return 0x00584220U;
4042} 4042}
4043static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter1_control_r(void) 4043static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter1_control_r(void)
4044{ 4044{
4045 return 0x00584224; 4045 return 0x00584224U;
4046} 4046}
4047static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter2_control_r(void) 4047static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter2_control_r(void)
4048{ 4048{
4049 return 0x00584228; 4049 return 0x00584228U;
4050} 4050}
4051static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter3_control_r(void) 4051static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter3_control_r(void)
4052{ 4052{
4053 return 0x0058422c; 4053 return 0x0058422cU;
4054} 4054}
4055static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter4_control_r(void) 4055static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter4_control_r(void)
4056{ 4056{
4057 return 0x00584230; 4057 return 0x00584230U;
4058} 4058}
4059static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter5_control_r(void) 4059static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter5_control_r(void)
4060{ 4060{
4061 return 0x00584234; 4061 return 0x00584234U;
4062} 4062}
4063static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter6_control_r(void) 4063static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter6_control_r(void)
4064{ 4064{
4065 return 0x00584238; 4065 return 0x00584238U;
4066} 4066}
4067static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter7_control_r(void) 4067static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter7_control_r(void)
4068{ 4068{
4069 return 0x0058423c; 4069 return 0x0058423cU;
4070} 4070}
4071static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s0_r(void) 4071static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s0_r(void)
4072{ 4072{
4073 return 0x00584600; 4073 return 0x00584600U;
4074} 4074}
4075static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s1_r(void) 4075static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s1_r(void)
4076{ 4076{
4077 return 0x00584604; 4077 return 0x00584604U;
4078} 4078}
4079static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s0_r(void) 4079static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s0_r(void)
4080{ 4080{
4081 return 0x00584624; 4081 return 0x00584624U;
4082} 4082}
4083static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s0_r(void) 4083static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s0_r(void)
4084{ 4084{
4085 return 0x00584628; 4085 return 0x00584628U;
4086} 4086}
4087static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s0_r(void) 4087static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s0_r(void)
4088{ 4088{
4089 return 0x0058462c; 4089 return 0x0058462cU;
4090} 4090}
4091static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s0_r(void) 4091static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s0_r(void)
4092{ 4092{
4093 return 0x00584630; 4093 return 0x00584630U;
4094} 4094}
4095static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s1_r(void) 4095static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s1_r(void)
4096{ 4096{
4097 return 0x00584634; 4097 return 0x00584634U;
4098} 4098}
4099static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s1_r(void) 4099static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s1_r(void)
4100{ 4100{
4101 return 0x00584638; 4101 return 0x00584638U;
4102} 4102}
4103static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s1_r(void) 4103static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s1_r(void)
4104{ 4104{
4105 return 0x0058463c; 4105 return 0x0058463cU;
4106} 4106}
4107static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s1_r(void) 4107static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s1_r(void)
4108{ 4108{
4109 return 0x00584640; 4109 return 0x00584640U;
4110} 4110}
4111static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s2_r(void) 4111static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s2_r(void)
4112{ 4112{
4113 return 0x00584644; 4113 return 0x00584644U;
4114} 4114}
4115static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s2_r(void) 4115static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s2_r(void)
4116{ 4116{
4117 return 0x00584648; 4117 return 0x00584648U;
4118} 4118}
4119static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s2_r(void) 4119static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s2_r(void)
4120{ 4120{
4121 return 0x0058464c; 4121 return 0x0058464cU;
4122} 4122}
4123static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s2_r(void) 4123static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s2_r(void)
4124{ 4124{
4125 return 0x00584650; 4125 return 0x00584650U;
4126} 4126}
4127static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s3_r(void) 4127static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s3_r(void)
4128{ 4128{
4129 return 0x00584654; 4129 return 0x00584654U;
4130} 4130}
4131static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s3_r(void) 4131static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s3_r(void)
4132{ 4132{
4133 return 0x00584658; 4133 return 0x00584658U;
4134} 4134}
4135static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s3_r(void) 4135static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s3_r(void)
4136{ 4136{
4137 return 0x0058465c; 4137 return 0x0058465cU;
4138} 4138}
4139static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s3_r(void) 4139static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s3_r(void)
4140{ 4140{
4141 return 0x00584660; 4141 return 0x00584660U;
4142} 4142}
4143static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter4_r(void) 4143static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter4_r(void)
4144{ 4144{
4145 return 0x00584614; 4145 return 0x00584614U;
4146} 4146}
4147static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter5_r(void) 4147static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter5_r(void)
4148{ 4148{
4149 return 0x00584618; 4149 return 0x00584618U;
4150} 4150}
4151static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter6_r(void) 4151static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter6_r(void)
4152{ 4152{
4153 return 0x0058461c; 4153 return 0x0058461cU;
4154} 4154}
4155static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter7_r(void) 4155static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter7_r(void)
4156{ 4156{
4157 return 0x00584620; 4157 return 0x00584620U;
4158} 4158}
4159static inline u32 gr_fe_pwr_mode_r(void) 4159static inline u32 gr_fe_pwr_mode_r(void)
4160{ 4160{
4161 return 0x00404170; 4161 return 0x00404170U;
4162} 4162}
4163static inline u32 gr_fe_pwr_mode_mode_auto_f(void) 4163static inline u32 gr_fe_pwr_mode_mode_auto_f(void)
4164{ 4164{
4165 return 0x0; 4165 return 0x0U;
4166} 4166}
4167static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) 4167static inline u32 gr_fe_pwr_mode_mode_force_on_f(void)
4168{ 4168{
4169 return 0x2; 4169 return 0x2U;
4170} 4170}
4171static inline u32 gr_fe_pwr_mode_req_v(u32 r) 4171static inline u32 gr_fe_pwr_mode_req_v(u32 r)
4172{ 4172{
4173 return (r >> 4) & 0x1; 4173 return (r >> 4U) & 0x1U;
4174} 4174}
4175static inline u32 gr_fe_pwr_mode_req_send_f(void) 4175static inline u32 gr_fe_pwr_mode_req_send_f(void)
4176{ 4176{
4177 return 0x10; 4177 return 0x10U;
4178} 4178}
4179static inline u32 gr_fe_pwr_mode_req_done_v(void) 4179static inline u32 gr_fe_pwr_mode_req_done_v(void)
4180{ 4180{
4181 return 0x00000000; 4181 return 0x00000000U;
4182} 4182}
4183static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) 4183static inline u32 gr_gpcs_pri_mmu_ctrl_r(void)
4184{ 4184{
4185 return 0x00418880; 4185 return 0x00418880U;
4186} 4186}
4187static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) 4187static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void)
4188{ 4188{
4189 return 0x1 << 0; 4189 return 0x1U << 0U;
4190} 4190}
4191static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) 4191static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void)
4192{ 4192{
4193 return 0x1 << 11; 4193 return 0x1U << 11U;
4194} 4194}
4195static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) 4195static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void)
4196{ 4196{
4197 return 0x1 << 1; 4197 return 0x1U << 1U;
4198} 4198}
4199static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) 4199static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void)
4200{ 4200{
4201 return 0x1 << 2; 4201 return 0x1U << 2U;
4202} 4202}
4203static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) 4203static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void)
4204{ 4204{
4205 return 0x3 << 3; 4205 return 0x3U << 3U;
4206} 4206}
4207static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) 4207static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void)
4208{ 4208{
4209 return 0x3 << 5; 4209 return 0x3U << 5U;
4210} 4210}
4211static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) 4211static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void)
4212{ 4212{
4213 return 0x3 << 28; 4213 return 0x3U << 28U;
4214} 4214}
4215static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) 4215static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void)
4216{ 4216{
4217 return 0x1 << 30; 4217 return 0x1U << 30U;
4218} 4218}
4219static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) 4219static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
4220{ 4220{
4221 return 0x1 << 31; 4221 return 0x1U << 31U;
4222} 4222}
4223static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) 4223static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
4224{ 4224{
4225 return 0x00418890; 4225 return 0x00418890U;
4226} 4226}
4227static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) 4227static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void)
4228{ 4228{
4229 return 0x00418894; 4229 return 0x00418894U;
4230} 4230}
4231static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) 4231static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
4232{ 4232{
4233 return 0x004188b0; 4233 return 0x004188b0U;
4234} 4234}
4235static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) 4235static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r)
4236{ 4236{
4237 return (r >> 16) & 0x1; 4237 return (r >> 16U) & 0x1U;
4238} 4238}
4239static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) 4239static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void)
4240{ 4240{
4241 return 0x00000001; 4241 return 0x00000001U;
4242} 4242}
4243static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) 4243static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void)
4244{ 4244{
4245 return 0x004188b4; 4245 return 0x004188b4U;
4246} 4246}
4247static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) 4247static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void)
4248{ 4248{
4249 return 0x004188b8; 4249 return 0x004188b8U;
4250} 4250}
4251static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) 4251static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
4252{ 4252{
4253 return 0x004188ac; 4253 return 0x004188acU;
4254} 4254}
4255static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void) 4255static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void)
4256{ 4256{
4257 return 0x00419e84; 4257 return 0x00419e84U;
4258} 4258}
4259static inline u32 gr_fe_gfxp_wfi_timeout_r(void) 4259static inline u32 gr_fe_gfxp_wfi_timeout_r(void)
4260{ 4260{
4261 return 0x004041c0; 4261 return 0x004041c0U;
4262} 4262}
4263static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) 4263static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v)
4264{ 4264{
4265 return (v & 0xffffffff) << 0; 4265 return (v & 0xffffffffU) << 0U;
4266} 4266}
4267static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) 4267static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void)
4268{ 4268{
4269 return 0x0; 4269 return 0x0U;
4270} 4270}
4271static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) 4271static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void)
4272{ 4272{
4273 return 0x00419bd8; 4273 return 0x00419bd8U;
4274} 4274}
4275static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) 4275static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
4276{ 4276{
4277 return (v & 0x7) << 8; 4277 return (v & 0x7U) << 8U;
4278} 4278}
4279static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) 4279static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void)
4280{ 4280{
4281 return 0x7 << 8; 4281 return 0x7U << 8U;
4282} 4282}
4283static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) 4283static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void)
4284{ 4284{
4285 return 0x100; 4285 return 0x100U;
4286} 4286}
4287static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) 4287static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void)
4288{ 4288{
4289 return 0x00419ba4; 4289 return 0x00419ba4U;
4290} 4290}
4291static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) 4291static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void)
4292{ 4292{
4293 return 0x3 << 11; 4293 return 0x3U << 11U;
4294} 4294}
4295static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) 4295static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void)
4296{ 4296{
4297 return 0x1000; 4297 return 0x1000U;
4298} 4298}
4299static inline u32 gr_gpcs_tc_debug0_r(void) 4299static inline u32 gr_gpcs_tc_debug0_r(void)
4300{ 4300{
4301 return 0x00418708; 4301 return 0x00418708U;
4302} 4302}
4303static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) 4303static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v)
4304{ 4304{
4305 return (v & 0x1ff) << 0; 4305 return (v & 0x1ffU) << 0U;
4306} 4306}
4307static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) 4307static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void)
4308{ 4308{
4309 return 0x1ff << 0; 4309 return 0x1ffU << 0U;
4310} 4310}
4311static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_r(void) 4311static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_r(void)
4312{ 4312{
4313 return 0x00500324; 4313 return 0x00500324U;
4314} 4314}
4315static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_f(u32 v) 4315static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_f(u32 v)
4316{ 4316{
4317 return (v & 0x1) << 0; 4317 return (v & 0x1U) << 0U;
4318} 4318}
4319static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_m(void) 4319static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_m(void)
4320{ 4320{
4321 return 0x1 << 0; 4321 return 0x1U << 0U;
4322} 4322}
4323static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_f(u32 v) 4323static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_f(u32 v)
4324{ 4324{
4325 return (v & 0x1) << 1; 4325 return (v & 0x1U) << 1U;
4326} 4326}
4327static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_m(void) 4327static inline u32 gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_m(void)
4328{ 4328{
4329 return 0x1 << 1; 4329 return 0x1U << 1U;
4330} 4330}
4331static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_r(void) 4331static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_r(void)
4332{ 4332{
4333 return 0x00500314; 4333 return 0x00500314U;
4334} 4334}
4335static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_f(u32 v) 4335static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_f(u32 v)
4336{ 4336{
4337 return (v & 0x1) << 0; 4337 return (v & 0x1U) << 0U;
4338} 4338}
4339static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_m(void) 4339static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_m(void)
4340{ 4340{
4341 return 0x1 << 0; 4341 return 0x1U << 0U;
4342} 4342}
4343static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_f(u32 v) 4343static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_f(u32 v)
4344{ 4344{
4345 return (v & 0x1) << 2; 4345 return (v & 0x1U) << 2U;
4346} 4346}
4347static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_m(void) 4347static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_m(void)
4348{ 4348{
4349 return 0x1 << 2; 4349 return 0x1U << 2U;
4350} 4350}
4351static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_f(u32 v) 4351static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_f(u32 v)
4352{ 4352{
4353 return (v & 0x1) << 1; 4353 return (v & 0x1U) << 1U;
4354} 4354}
4355static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_m(void) 4355static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_m(void)
4356{ 4356{
4357 return 0x1 << 1; 4357 return 0x1U << 1U;
4358} 4358}
4359static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_f(u32 v) 4359static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_f(u32 v)
4360{ 4360{
4361 return (v & 0x1) << 3; 4361 return (v & 0x1U) << 3U;
4362} 4362}
4363static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_m(void) 4363static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_m(void)
4364{ 4364{
4365 return 0x1 << 3; 4365 return 0x1U << 3U;
4366} 4366}
4367static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) 4367static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v)
4368{ 4368{
4369 return (v & 0x1) << 18; 4369 return (v & 0x1U) << 18U;
4370} 4370}
4371static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void) 4371static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_total_counter_overflow_m(void)
4372{ 4372{
4373 return 0x1 << 18; 4373 return 0x1U << 18U;
4374} 4374}
4375static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_f(u32 v) 4375static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_f(u32 v)
4376{ 4376{
4377 return (v & 0x1) << 16; 4377 return (v & 0x1U) << 16U;
4378} 4378}
4379static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_m(void) 4379static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_total_counter_overflow_m(void)
4380{ 4380{
4381 return 0x1 << 16; 4381 return 0x1U << 16U;
4382} 4382}
4383static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) 4383static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v)
4384{ 4384{
4385 return (v & 0x1) << 19; 4385 return (v & 0x1U) << 19U;
4386} 4386}
4387static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_m(void) 4387static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_unique_counter_overflow_m(void)
4388{ 4388{
4389 return 0x1 << 19; 4389 return 0x1U << 19U;
4390} 4390}
4391static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) 4391static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_f(u32 v)
4392{ 4392{
4393 return (v & 0x1) << 17; 4393 return (v & 0x1U) << 17U;
4394} 4394}
4395static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_m(void) 4395static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_unique_counter_overflow_m(void)
4396{ 4396{
4397 return 0x1 << 17; 4397 return 0x1U << 17U;
4398} 4398}
4399static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_f(u32 v) 4399static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_f(u32 v)
4400{ 4400{
4401 return (v & 0x1) << 30; 4401 return (v & 0x1U) << 30U;
4402} 4402}
4403static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_task_f(void) 4403static inline u32 gr_gpc0_mmu_l1tlb_ecc_status_reset_task_f(void)
4404{ 4404{
4405 return 0x40000000; 4405 return 0x40000000U;
4406} 4406}
4407static inline u32 gr_gpc0_mmu_l1tlb_ecc_address_r(void) 4407static inline u32 gr_gpc0_mmu_l1tlb_ecc_address_r(void)
4408{ 4408{
4409 return 0x00500320; 4409 return 0x00500320U;
4410} 4410}
4411static inline u32 gr_gpc0_mmu_l1tlb_ecc_address_index_f(u32 v) 4411static inline u32 gr_gpc0_mmu_l1tlb_ecc_address_index_f(u32 v)
4412{ 4412{
4413 return (v & 0xffffffff) << 0; 4413 return (v & 0xffffffffU) << 0U;
4414} 4414}
4415static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_r(void) 4415static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_r(void)
4416{ 4416{
4417 return 0x00500318; 4417 return 0x00500318U;
4418} 4418}
4419static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_s(void) 4419static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_s(void)
4420{ 4420{
4421 return 16; 4421 return 16U;
4422} 4422}
4423static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_f(u32 v) 4423static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_f(u32 v)
4424{ 4424{
4425 return (v & 0xffff) << 0; 4425 return (v & 0xffffU) << 0U;
4426} 4426}
4427static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_m(void) 4427static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_m(void)
4428{ 4428{
4429 return 0xffff << 0; 4429 return 0xffffU << 0U;
4430} 4430}
4431static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_v(u32 r) 4431static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_v(u32 r)
4432{ 4432{
4433 return (r >> 0) & 0xffff; 4433 return (r >> 0U) & 0xffffU;
4434} 4434}
4435static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_s(void) 4435static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_s(void)
4436{ 4436{
4437 return 16; 4437 return 16U;
4438} 4438}
4439static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_f(u32 v) 4439static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_f(u32 v)
4440{ 4440{
4441 return (v & 0xffff) << 16; 4441 return (v & 0xffffU) << 16U;
4442} 4442}
4443static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_m(void) 4443static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_m(void)
4444{ 4444{
4445 return 0xffff << 16; 4445 return 0xffffU << 16U;
4446} 4446}
4447static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_v(u32 r) 4447static inline u32 gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_unique_total_v(u32 r)
4448{ 4448{
4449 return (r >> 16) & 0xffff; 4449 return (r >> 16U) & 0xffffU;
4450} 4450}
4451static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_r(void) 4451static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_r(void)
4452{ 4452{
4453 return 0x0050031c; 4453 return 0x0050031cU;
4454} 4454}
4455static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_s(void) 4455static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_s(void)
4456{ 4456{
4457 return 16; 4457 return 16U;
4458} 4458}
4459static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_f(u32 v) 4459static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_f(u32 v)
4460{ 4460{
4461 return (v & 0xffff) << 0; 4461 return (v & 0xffffU) << 0U;
4462} 4462}
4463static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_m(void) 4463static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_m(void)
4464{ 4464{
4465 return 0xffff << 0; 4465 return 0xffffU << 0U;
4466} 4466}
4467static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_v(u32 r) 4467static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_v(u32 r)
4468{ 4468{
4469 return (r >> 0) & 0xffff; 4469 return (r >> 0U) & 0xffffU;
4470} 4470}
4471static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_s(void) 4471static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_s(void)
4472{ 4472{
4473 return 16; 4473 return 16U;
4474} 4474}
4475static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_f(u32 v) 4475static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_f(u32 v)
4476{ 4476{
4477 return (v & 0xffff) << 16; 4477 return (v & 0xffffU) << 16U;
4478} 4478}
4479static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_m(void) 4479static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_m(void)
4480{ 4480{
4481 return 0xffff << 16; 4481 return 0xffffU << 16U;
4482} 4482}
4483static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_v(u32 r) 4483static inline u32 gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_unique_total_v(u32 r)
4484{ 4484{
4485 return (r >> 16) & 0xffff; 4485 return (r >> 16U) & 0xffffU;
4486} 4486}
4487static inline u32 gr_gpc0_gpccs_hww_esr_r(void) 4487static inline u32 gr_gpc0_gpccs_hww_esr_r(void)
4488{ 4488{
4489 return 0x00502c98; 4489 return 0x00502c98U;
4490} 4490}
4491static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_f(u32 v) 4491static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_f(u32 v)
4492{ 4492{
4493 return (v & 0x1) << 0; 4493 return (v & 0x1U) << 0U;
4494} 4494}
4495static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_m(void) 4495static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_m(void)
4496{ 4496{
4497 return 0x1 << 0; 4497 return 0x1U << 0U;
4498} 4498}
4499static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_pending_f(void) 4499static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_pending_f(void)
4500{ 4500{
4501 return 0x1; 4501 return 0x1U;
4502} 4502}
4503static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_f(u32 v) 4503static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_f(u32 v)
4504{ 4504{
4505 return (v & 0x1) << 1; 4505 return (v & 0x1U) << 1U;
4506} 4506}
4507static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m(void) 4507static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m(void)
4508{ 4508{
4509 return 0x1 << 1; 4509 return 0x1U << 1U;
4510} 4510}
4511static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_pending_f(void) 4511static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_pending_f(void)
4512{ 4512{
4513 return 0x2; 4513 return 0x2U;
4514} 4514}
4515static inline u32 gr_gpc0_gpccs_falcon_ecc_status_r(void) 4515static inline u32 gr_gpc0_gpccs_falcon_ecc_status_r(void)
4516{ 4516{
4517 return 0x00502678; 4517 return 0x00502678U;
4518} 4518}
4519static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_f(u32 v) 4519static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_f(u32 v)
4520{ 4520{
4521 return (v & 0x1) << 0; 4521 return (v & 0x1U) << 0U;
4522} 4522}
4523static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m(void) 4523static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m(void)
4524{ 4524{
4525 return 0x1 << 0; 4525 return 0x1U << 0U;
4526} 4526}
4527static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_pending_f(void) 4527static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_pending_f(void)
4528{ 4528{
4529 return 0x1; 4529 return 0x1U;
4530} 4530}
4531static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_f(u32 v) 4531static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_f(u32 v)
4532{ 4532{
4533 return (v & 0x1) << 1; 4533 return (v & 0x1U) << 1U;
4534} 4534}
4535static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m(void) 4535static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m(void)
4536{ 4536{
4537 return 0x1 << 1; 4537 return 0x1U << 1U;
4538} 4538}
4539static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_pending_f(void) 4539static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_pending_f(void)
4540{ 4540{
4541 return 0x2; 4541 return 0x2U;
4542} 4542}
4543static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) 4543static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_f(u32 v)
4544{ 4544{
4545 return (v & 0x1) << 4; 4545 return (v & 0x1U) << 4U;
4546} 4546}
4547static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m(void) 4547static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m(void)
4548{ 4548{
4549 return 0x1 << 4; 4549 return 0x1U << 4U;
4550} 4550}
4551static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) 4551static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_pending_f(void)
4552{ 4552{
4553 return 0x10; 4553 return 0x10U;
4554} 4554}
4555static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) 4555static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v)
4556{ 4556{
4557 return (v & 0x1) << 5; 4557 return (v & 0x1U) << 5U;
4558} 4558}
4559static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m(void) 4559static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m(void)
4560{ 4560{
4561 return 0x1 << 5; 4561 return 0x1U << 5U;
4562} 4562}
4563static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) 4563static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void)
4564{ 4564{
4565 return 0x20; 4565 return 0x20U;
4566} 4566}
4567static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) 4567static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v)
4568{ 4568{
4569 return (v & 0x1) << 10; 4569 return (v & 0x1U) << 10U;
4570} 4570}
4571static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) 4571static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void)
4572{ 4572{
4573 return 0x1 << 10; 4573 return 0x1U << 10U;
4574} 4574}
4575static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) 4575static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void)
4576{ 4576{
4577 return 0x400; 4577 return 0x400U;
4578} 4578}
4579static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) 4579static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v)
4580{ 4580{
4581 return (v & 0x1) << 8; 4581 return (v & 0x1U) << 8U;
4582} 4582}
4583static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) 4583static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void)
4584{ 4584{
4585 return 0x1 << 8; 4585 return 0x1U << 8U;
4586} 4586}
4587static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) 4587static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void)
4588{ 4588{
4589 return 0x100; 4589 return 0x100U;
4590} 4590}
4591static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) 4591static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v)
4592{ 4592{
4593 return (v & 0x1) << 11; 4593 return (v & 0x1U) << 11U;
4594} 4594}
4595static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) 4595static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void)
4596{ 4596{
4597 return 0x1 << 11; 4597 return 0x1U << 11U;
4598} 4598}
4599static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) 4599static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void)
4600{ 4600{
4601 return 0x800; 4601 return 0x800U;
4602} 4602}
4603static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) 4603static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v)
4604{ 4604{
4605 return (v & 0x1) << 9; 4605 return (v & 0x1U) << 9U;
4606} 4606}
4607static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) 4607static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void)
4608{ 4608{
4609 return 0x1 << 9; 4609 return 0x1U << 9U;
4610} 4610}
4611static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) 4611static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void)
4612{ 4612{
4613 return 0x200; 4613 return 0x200U;
4614} 4614}
4615static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_f(u32 v) 4615static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_f(u32 v)
4616{ 4616{
4617 return (v & 0x1) << 31; 4617 return (v & 0x1U) << 31U;
4618} 4618}
4619static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_task_f(void) 4619static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_task_f(void)
4620{ 4620{
4621 return 0x80000000; 4621 return 0x80000000U;
4622} 4622}
4623static inline u32 gr_gpc0_gpccs_falcon_ecc_address_r(void) 4623static inline u32 gr_gpc0_gpccs_falcon_ecc_address_r(void)
4624{ 4624{
4625 return 0x00502684; 4625 return 0x00502684U;
4626} 4626}
4627static inline u32 gr_gpc0_gpccs_falcon_ecc_address_index_f(u32 v) 4627static inline u32 gr_gpc0_gpccs_falcon_ecc_address_index_f(u32 v)
4628{ 4628{
4629 return (v & 0x7fffff) << 0; 4629 return (v & 0x7fffffU) << 0U;
4630} 4630}
4631static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_s(void) 4631static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_s(void)
4632{ 4632{
4633 return 20; 4633 return 20U;
4634} 4634}
4635static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_f(u32 v) 4635static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_f(u32 v)
4636{ 4636{
4637 return (v & 0xfffff) << 0; 4637 return (v & 0xfffffU) << 0U;
4638} 4638}
4639static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_m(void) 4639static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_m(void)
4640{ 4640{
4641 return 0xfffff << 0; 4641 return 0xfffffU << 0U;
4642} 4642}
4643static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_v(u32 r) 4643static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_v(u32 r)
4644{ 4644{
4645 return (r >> 0) & 0xfffff; 4645 return (r >> 0U) & 0xfffffU;
4646} 4646}
4647static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r(void) 4647static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r(void)
4648{ 4648{
4649 return 0x0050267c; 4649 return 0x0050267cU;
4650} 4650}
4651static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_s(void) 4651static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_s(void)
4652{ 4652{
4653 return 16; 4653 return 16U;
4654} 4654}
4655static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_f(u32 v) 4655static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_f(u32 v)
4656{ 4656{
4657 return (v & 0xffff) << 0; 4657 return (v & 0xffffU) << 0U;
4658} 4658}
4659static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_m(void) 4659static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_m(void)
4660{ 4660{
4661 return 0xffff << 0; 4661 return 0xffffU << 0U;
4662} 4662}
4663static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(u32 r) 4663static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(u32 r)
4664{ 4664{
4665 return (r >> 0) & 0xffff; 4665 return (r >> 0U) & 0xffffU;
4666} 4666}
4667static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_s(void) 4667static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_s(void)
4668{ 4668{
4669 return 16; 4669 return 16U;
4670} 4670}
4671static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) 4671static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_f(u32 v)
4672{ 4672{
4673 return (v & 0xffff) << 16; 4673 return (v & 0xffffU) << 16U;
4674} 4674}
4675static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_m(void) 4675static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_m(void)
4676{ 4676{
4677 return 0xffff << 16; 4677 return 0xffffU << 16U;
4678} 4678}
4679static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) 4679static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_v(u32 r)
4680{ 4680{
4681 return (r >> 16) & 0xffff; 4681 return (r >> 16U) & 0xffffU;
4682} 4682}
4683static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r(void) 4683static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r(void)
4684{ 4684{
4685 return 0x00502680; 4685 return 0x00502680U;
4686} 4686}
4687static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_f(u32 v) 4687static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_f(u32 v)
4688{ 4688{
4689 return (v & 0xffff) << 0; 4689 return (v & 0xffffU) << 0U;
4690} 4690}
4691static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_m(void) 4691static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_m(void)
4692{ 4692{
4693 return 0xffff << 0; 4693 return 0xffffU << 0U;
4694} 4694}
4695static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(u32 r) 4695static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(u32 r)
4696{ 4696{
4697 return (r >> 0) & 0xffff; 4697 return (r >> 0U) & 0xffffU;
4698} 4698}
4699static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_s(void) 4699static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_s(void)
4700{ 4700{
4701 return 16; 4701 return 16U;
4702} 4702}
4703static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) 4703static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v)
4704{ 4704{
4705 return (v & 0xffff) << 16; 4705 return (v & 0xffffU) << 16U;
4706} 4706}
4707static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_m(void) 4707static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_m(void)
4708{ 4708{
4709 return 0xffff << 16; 4709 return 0xffffU << 16U;
4710} 4710}
4711static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) 4711static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r)
4712{ 4712{
4713 return (r >> 16) & 0xffff; 4713 return (r >> 16U) & 0xffffU;
4714} 4714}
4715static inline u32 gr_fecs_falcon_ecc_status_r(void) 4715static inline u32 gr_fecs_falcon_ecc_status_r(void)
4716{ 4716{
4717 return 0x00409678; 4717 return 0x00409678U;
4718} 4718}
4719static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_f(u32 v) 4719static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_f(u32 v)
4720{ 4720{
4721 return (v & 0x1) << 0; 4721 return (v & 0x1U) << 0U;
4722} 4722}
4723static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_m(void) 4723static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_m(void)
4724{ 4724{
4725 return 0x1 << 0; 4725 return 0x1U << 0U;
4726} 4726}
4727static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_pending_f(void) 4727static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_pending_f(void)
4728{ 4728{
4729 return 0x1; 4729 return 0x1U;
4730} 4730}
4731static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_f(u32 v) 4731static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_f(u32 v)
4732{ 4732{
4733 return (v & 0x1) << 1; 4733 return (v & 0x1U) << 1U;
4734} 4734}
4735static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_m(void) 4735static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_m(void)
4736{ 4736{
4737 return 0x1 << 1; 4737 return 0x1U << 1U;
4738} 4738}
4739static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_pending_f(void) 4739static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_pending_f(void)
4740{ 4740{
4741 return 0x2; 4741 return 0x2U;
4742} 4742}
4743static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) 4743static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_f(u32 v)
4744{ 4744{
4745 return (v & 0x1) << 4; 4745 return (v & 0x1U) << 4U;
4746} 4746}
4747static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_m(void) 4747static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_m(void)
4748{ 4748{
4749 return 0x1 << 4; 4749 return 0x1U << 4U;
4750} 4750}
4751static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) 4751static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_pending_f(void)
4752{ 4752{
4753 return 0x10; 4753 return 0x10U;
4754} 4754}
4755static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) 4755static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v)
4756{ 4756{
4757 return (v & 0x1) << 5; 4757 return (v & 0x1U) << 5U;
4758} 4758}
4759static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m(void) 4759static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m(void)
4760{ 4760{
4761 return 0x1 << 5; 4761 return 0x1U << 5U;
4762} 4762}
4763static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) 4763static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void)
4764{ 4764{
4765 return 0x20; 4765 return 0x20U;
4766} 4766}
4767static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) 4767static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v)
4768{ 4768{
4769 return (v & 0x1) << 10; 4769 return (v & 0x1U) << 10U;
4770} 4770}
4771static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) 4771static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void)
4772{ 4772{
4773 return 0x1 << 10; 4773 return 0x1U << 10U;
4774} 4774}
4775static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) 4775static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void)
4776{ 4776{
4777 return 0x400; 4777 return 0x400U;
4778} 4778}
4779static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) 4779static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v)
4780{ 4780{
4781 return (v & 0x1) << 8; 4781 return (v & 0x1U) << 8U;
4782} 4782}
4783static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) 4783static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void)
4784{ 4784{
4785 return 0x1 << 8; 4785 return 0x1U << 8U;
4786} 4786}
4787static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) 4787static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void)
4788{ 4788{
4789 return 0x100; 4789 return 0x100U;
4790} 4790}
4791static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) 4791static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v)
4792{ 4792{
4793 return (v & 0x1) << 11; 4793 return (v & 0x1U) << 11U;
4794} 4794}
4795static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) 4795static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void)
4796{ 4796{
4797 return 0x1 << 11; 4797 return 0x1U << 11U;
4798} 4798}
4799static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) 4799static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void)
4800{ 4800{
4801 return 0x800; 4801 return 0x800U;
4802} 4802}
4803static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) 4803static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v)
4804{ 4804{
4805 return (v & 0x1) << 9; 4805 return (v & 0x1U) << 9U;
4806} 4806}
4807static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) 4807static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void)
4808{ 4808{
4809 return 0x1 << 9; 4809 return 0x1U << 9U;
4810} 4810}
4811static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) 4811static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void)
4812{ 4812{
4813 return 0x200; 4813 return 0x200U;
4814} 4814}
4815static inline u32 gr_fecs_falcon_ecc_status_reset_f(u32 v) 4815static inline u32 gr_fecs_falcon_ecc_status_reset_f(u32 v)
4816{ 4816{
4817 return (v & 0x1) << 31; 4817 return (v & 0x1U) << 31U;
4818} 4818}
4819static inline u32 gr_fecs_falcon_ecc_status_reset_task_f(void) 4819static inline u32 gr_fecs_falcon_ecc_status_reset_task_f(void)
4820{ 4820{
4821 return 0x80000000; 4821 return 0x80000000U;
4822} 4822}
4823static inline u32 gr_fecs_falcon_ecc_address_r(void) 4823static inline u32 gr_fecs_falcon_ecc_address_r(void)
4824{ 4824{
4825 return 0x00409684; 4825 return 0x00409684U;
4826} 4826}
4827static inline u32 gr_fecs_falcon_ecc_address_index_f(u32 v) 4827static inline u32 gr_fecs_falcon_ecc_address_index_f(u32 v)
4828{ 4828{
4829 return (v & 0x7fffff) << 0; 4829 return (v & 0x7fffffU) << 0U;
4830} 4830}
4831static inline u32 gr_fecs_falcon_ecc_address_row_address_s(void) 4831static inline u32 gr_fecs_falcon_ecc_address_row_address_s(void)
4832{ 4832{
4833 return 20; 4833 return 20U;
4834} 4834}
4835static inline u32 gr_fecs_falcon_ecc_address_row_address_f(u32 v) 4835static inline u32 gr_fecs_falcon_ecc_address_row_address_f(u32 v)
4836{ 4836{
4837 return (v & 0xfffff) << 0; 4837 return (v & 0xfffffU) << 0U;
4838} 4838}
4839static inline u32 gr_fecs_falcon_ecc_address_row_address_m(void) 4839static inline u32 gr_fecs_falcon_ecc_address_row_address_m(void)
4840{ 4840{
4841 return 0xfffff << 0; 4841 return 0xfffffU << 0U;
4842} 4842}
4843static inline u32 gr_fecs_falcon_ecc_address_row_address_v(u32 r) 4843static inline u32 gr_fecs_falcon_ecc_address_row_address_v(u32 r)
4844{ 4844{
4845 return (r >> 0) & 0xfffff; 4845 return (r >> 0U) & 0xfffffU;
4846} 4846}
4847static inline u32 gr_fecs_falcon_ecc_corrected_err_count_r(void) 4847static inline u32 gr_fecs_falcon_ecc_corrected_err_count_r(void)
4848{ 4848{
4849 return 0x0040967c; 4849 return 0x0040967cU;
4850} 4850}
4851static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_s(void) 4851static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_s(void)
4852{ 4852{
4853 return 16; 4853 return 16U;
4854} 4854}
4855static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_f(u32 v) 4855static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_f(u32 v)
4856{ 4856{
4857 return (v & 0xffff) << 0; 4857 return (v & 0xffffU) << 0U;
4858} 4858}
4859static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_m(void) 4859static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_m(void)
4860{ 4860{
4861 return 0xffff << 0; 4861 return 0xffffU << 0U;
4862} 4862}
4863static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_v(u32 r) 4863static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_v(u32 r)
4864{ 4864{
4865 return (r >> 0) & 0xffff; 4865 return (r >> 0U) & 0xffffU;
4866} 4866}
4867static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_s(void) 4867static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_s(void)
4868{ 4868{
4869 return 16; 4869 return 16U;
4870} 4870}
4871static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) 4871static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_f(u32 v)
4872{ 4872{
4873 return (v & 0xffff) << 16; 4873 return (v & 0xffffU) << 16U;
4874} 4874}
4875static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_m(void) 4875static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_m(void)
4876{ 4876{
4877 return 0xffff << 16; 4877 return 0xffffU << 16U;
4878} 4878}
4879static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) 4879static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_v(u32 r)
4880{ 4880{
4881 return (r >> 16) & 0xffff; 4881 return (r >> 16U) & 0xffffU;
4882} 4882}
4883static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_r(void) 4883static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_r(void)
4884{ 4884{
4885 return 0x00409680; 4885 return 0x00409680U;
4886} 4886}
4887static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_f(u32 v) 4887static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_f(u32 v)
4888{ 4888{
4889 return (v & 0xffff) << 0; 4889 return (v & 0xffffU) << 0U;
4890} 4890}
4891static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_m(void) 4891static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_m(void)
4892{ 4892{
4893 return 0xffff << 0; 4893 return 0xffffU << 0U;
4894} 4894}
4895static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_v(u32 r) 4895static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_v(u32 r)
4896{ 4896{
4897 return (r >> 0) & 0xffff; 4897 return (r >> 0U) & 0xffffU;
4898} 4898}
4899static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_s(void) 4899static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_s(void)
4900{ 4900{
4901 return 16; 4901 return 16U;
4902} 4902}
4903static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) 4903static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v)
4904{ 4904{
4905 return (v & 0xffff) << 16; 4905 return (v & 0xffffU) << 16U;
4906} 4906}
4907static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_m(void) 4907static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_m(void)
4908{ 4908{
4909 return 0xffff << 16; 4909 return 0xffffU << 16U;
4910} 4910}
4911static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) 4911static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r)
4912{ 4912{
4913 return (r >> 16) & 0xffff; 4913 return (r >> 16U) & 0xffffU;
4914} 4914}
4915#endif 4915#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h
index e1b0f47a..769bcf0c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ltc_gv11b.h
@@ -58,746 +58,746 @@
58 58
59static inline u32 ltc_pltcg_base_v(void) 59static inline u32 ltc_pltcg_base_v(void)
60{ 60{
61 return 0x00140000; 61 return 0x00140000U;
62} 62}
63static inline u32 ltc_pltcg_extent_v(void) 63static inline u32 ltc_pltcg_extent_v(void)
64{ 64{
65 return 0x0017ffff; 65 return 0x0017ffffU;
66} 66}
67static inline u32 ltc_ltc0_ltss_v(void) 67static inline u32 ltc_ltc0_ltss_v(void)
68{ 68{
69 return 0x00140200; 69 return 0x00140200U;
70} 70}
71static inline u32 ltc_ltc0_lts0_v(void) 71static inline u32 ltc_ltc0_lts0_v(void)
72{ 72{
73 return 0x00140400; 73 return 0x00140400U;
74} 74}
75static inline u32 ltc_ltcs_ltss_v(void) 75static inline u32 ltc_ltcs_ltss_v(void)
76{ 76{
77 return 0x0017e200; 77 return 0x0017e200U;
78} 78}
79static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) 79static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
80{ 80{
81 return 0x0014046c; 81 return 0x0014046cU;
82} 82}
83static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) 83static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
84{ 84{
85 return 0x00140518; 85 return 0x00140518U;
86} 86}
87static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) 87static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
88{ 88{
89 return 0x0017e318; 89 return 0x0017e318U;
90} 90}
91static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) 91static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
92{ 92{
93 return 0x1 << 15; 93 return 0x1U << 15U;
94} 94}
95static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) 95static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
96{ 96{
97 return 0x00140494; 97 return 0x00140494U;
98} 98}
99static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) 99static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
100{ 100{
101 return (r >> 0) & 0xffff; 101 return (r >> 0U) & 0xffffU;
102} 102}
103static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) 103static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
104{ 104{
105 return (r >> 16) & 0x3; 105 return (r >> 16U) & 0x3U;
106} 106}
107static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) 107static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
108{ 108{
109 return 0x00000000; 109 return 0x00000000U;
110} 110}
111static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) 111static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
112{ 112{
113 return 0x00000001; 113 return 0x00000001U;
114} 114}
115static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) 115static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
116{ 116{
117 return 0x00000002; 117 return 0x00000002U;
118} 118}
119static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) 119static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
120{ 120{
121 return 0x0017e26c; 121 return 0x0017e26cU;
122} 122}
123static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) 123static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
124{ 124{
125 return 0x1; 125 return 0x1U;
126} 126}
127static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) 127static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
128{ 128{
129 return 0x2; 129 return 0x2U;
130} 130}
131static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) 131static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
132{ 132{
133 return (r >> 2) & 0x1; 133 return (r >> 2U) & 0x1U;
134} 134}
135static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) 135static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
136{ 136{
137 return 0x00000001; 137 return 0x00000001U;
138} 138}
139static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) 139static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
140{ 140{
141 return 0x4; 141 return 0x4U;
142} 142}
143static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) 143static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
144{ 144{
145 return 0x0014046c; 145 return 0x0014046cU;
146} 146}
147static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) 147static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
148{ 148{
149 return 0x0017e270; 149 return 0x0017e270U;
150} 150}
151static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) 151static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
152{ 152{
153 return (v & 0x3ffff) << 0; 153 return (v & 0x3ffffU) << 0U;
154} 154}
155static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) 155static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
156{ 156{
157 return 0x0017e274; 157 return 0x0017e274U;
158} 158}
159static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) 159static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
160{ 160{
161 return (v & 0x3ffff) << 0; 161 return (v & 0x3ffffU) << 0U;
162} 162}
163static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) 163static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
164{ 164{
165 return 0x0003ffff; 165 return 0x0003ffffU;
166} 166}
167static inline u32 ltc_ltcs_ltss_cbc_base_r(void) 167static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
168{ 168{
169 return 0x0017e278; 169 return 0x0017e278U;
170} 170}
171static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) 171static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
172{ 172{
173 return 0x0000000b; 173 return 0x0000000bU;
174} 174}
175static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) 175static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
176{ 176{
177 return (r >> 0) & 0x3ffffff; 177 return (r >> 0U) & 0x3ffffffU;
178} 178}
179static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) 179static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
180{ 180{
181 return 0x0017e27c; 181 return 0x0017e27cU;
182} 182}
183static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r) 183static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r)
184{ 184{
185 return (r >> 0) & 0x1f; 185 return (r >> 0U) & 0x1fU;
186} 186}
187static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v) 187static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v)
188{ 188{
189 return (v & 0x1) << 24; 189 return (v & 0x1U) << 24U;
190} 190}
191static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r) 191static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r)
192{ 192{
193 return (r >> 24) & 0x1; 193 return (r >> 24U) & 0x1U;
194} 194}
195static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v) 195static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v)
196{ 196{
197 return (v & 0x1) << 25; 197 return (v & 0x1U) << 25U;
198} 198}
199static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r) 199static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r)
200{ 200{
201 return (r >> 25) & 0x1; 201 return (r >> 25U) & 0x1U;
202} 202}
203static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) 203static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
204{ 204{
205 return 0x0017e000; 205 return 0x0017e000U;
206} 206}
207static inline u32 ltc_ltcs_ltss_cbc_param_r(void) 207static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
208{ 208{
209 return 0x0017e280; 209 return 0x0017e280U;
210} 210}
211static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) 211static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
212{ 212{
213 return (r >> 0) & 0xffff; 213 return (r >> 0U) & 0xffffU;
214} 214}
215static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) 215static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
216{ 216{
217 return (r >> 24) & 0xf; 217 return (r >> 24U) & 0xfU;
218} 218}
219static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) 219static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
220{ 220{
221 return (r >> 28) & 0xf; 221 return (r >> 28U) & 0xfU;
222} 222}
223static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) 223static inline u32 ltc_ltcs_ltss_cbc_param2_r(void)
224{ 224{
225 return 0x0017e3f4; 225 return 0x0017e3f4U;
226} 226}
227static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) 227static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r)
228{ 228{
229 return (r >> 0) & 0xffff; 229 return (r >> 0U) & 0xffffU;
230} 230}
231static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) 231static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
232{ 232{
233 return 0x0017e2ac; 233 return 0x0017e2acU;
234} 234}
235static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) 235static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
236{ 236{
237 return (v & 0x1f) << 16; 237 return (v & 0x1fU) << 16U;
238} 238}
239static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) 239static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
240{ 240{
241 return 0x0017e338; 241 return 0x0017e338U;
242} 242}
243static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) 243static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
244{ 244{
245 return (v & 0xf) << 0; 245 return (v & 0xfU) << 0U;
246} 246}
247static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) 247static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
248{ 248{
249 return 0x0017e33c + i*4; 249 return 0x0017e33cU + i*4U;
250} 250}
251static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) 251static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
252{ 252{
253 return 0x00000004; 253 return 0x00000004U;
254} 254}
255static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) 255static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
256{ 256{
257 return 0x0017e34c; 257 return 0x0017e34cU;
258} 258}
259static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) 259static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
260{ 260{
261 return 32; 261 return 32U;
262} 262}
263static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) 263static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
264{ 264{
265 return (v & 0xffffffff) << 0; 265 return (v & 0xffffffffU) << 0U;
266} 266}
267static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) 267static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
268{ 268{
269 return 0xffffffff << 0; 269 return 0xffffffffU << 0U;
270} 270}
271static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) 271static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
272{ 272{
273 return (r >> 0) & 0xffffffff; 273 return (r >> 0U) & 0xffffffffU;
274} 274}
275static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void) 275static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void)
276{ 276{
277 return 0x0017e204; 277 return 0x0017e204U;
278} 278}
279static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void) 279static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void)
280{ 280{
281 return 8; 281 return 8U;
282} 282}
283static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v) 283static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v)
284{ 284{
285 return (v & 0xff) << 0; 285 return (v & 0xffU) << 0U;
286} 286}
287static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void) 287static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void)
288{ 288{
289 return 0xff << 0; 289 return 0xffU << 0U;
290} 290}
291static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r) 291static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r)
292{ 292{
293 return (r >> 0) & 0xff; 293 return (r >> 0U) & 0xffU;
294} 294}
295static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) 295static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
296{ 296{
297 return 0x0017e2b0; 297 return 0x0017e2b0U;
298} 298}
299static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) 299static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
300{ 300{
301 return 0x10000000; 301 return 0x10000000U;
302} 302}
303static inline u32 ltc_ltcs_ltss_g_elpg_r(void) 303static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
304{ 304{
305 return 0x0017e214; 305 return 0x0017e214U;
306} 306}
307static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) 307static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
308{ 308{
309 return (r >> 0) & 0x1; 309 return (r >> 0U) & 0x1U;
310} 310}
311static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) 311static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
312{ 312{
313 return 0x00000001; 313 return 0x00000001U;
314} 314}
315static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) 315static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
316{ 316{
317 return 0x1; 317 return 0x1U;
318} 318}
319static inline u32 ltc_ltc0_ltss_g_elpg_r(void) 319static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
320{ 320{
321 return 0x00140214; 321 return 0x00140214U;
322} 322}
323static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) 323static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
324{ 324{
325 return (r >> 0) & 0x1; 325 return (r >> 0U) & 0x1U;
326} 326}
327static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) 327static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
328{ 328{
329 return 0x00000001; 329 return 0x00000001U;
330} 330}
331static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) 331static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
332{ 332{
333 return 0x1; 333 return 0x1U;
334} 334}
335static inline u32 ltc_ltc1_ltss_g_elpg_r(void) 335static inline u32 ltc_ltc1_ltss_g_elpg_r(void)
336{ 336{
337 return 0x00142214; 337 return 0x00142214U;
338} 338}
339static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) 339static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r)
340{ 340{
341 return (r >> 0) & 0x1; 341 return (r >> 0U) & 0x1U;
342} 342}
343static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) 343static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void)
344{ 344{
345 return 0x00000001; 345 return 0x00000001U;
346} 346}
347static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) 347static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void)
348{ 348{
349 return 0x1; 349 return 0x1U;
350} 350}
351static inline u32 ltc_ltcs_ltss_intr_r(void) 351static inline u32 ltc_ltcs_ltss_intr_r(void)
352{ 352{
353 return 0x0017e20c; 353 return 0x0017e20cU;
354} 354}
355static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) 355static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void)
356{ 356{
357 return 0x100; 357 return 0x100U;
358} 358}
359static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) 359static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void)
360{ 360{
361 return 0x200; 361 return 0x200U;
362} 362}
363static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) 363static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
364{ 364{
365 return 0x1 << 20; 365 return 0x1U << 20U;
366} 366}
367static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) 367static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
368{ 368{
369 return 0x1 << 30; 369 return 0x1U << 30U;
370} 370}
371static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) 371static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void)
372{ 372{
373 return 0x1000000; 373 return 0x1000000U;
374} 374}
375static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) 375static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void)
376{ 376{
377 return 0x2000000; 377 return 0x2000000U;
378} 378}
379static inline u32 ltc_ltc0_lts0_intr_r(void) 379static inline u32 ltc_ltc0_lts0_intr_r(void)
380{ 380{
381 return 0x0014040c; 381 return 0x0014040cU;
382} 382}
383static inline u32 ltc_ltcs_ltss_intr3_r(void) 383static inline u32 ltc_ltcs_ltss_intr3_r(void)
384{ 384{
385 return 0x0017e388; 385 return 0x0017e388U;
386} 386}
387static inline u32 ltc_ltcs_ltss_intr3_ecc_corrected_m(void) 387static inline u32 ltc_ltcs_ltss_intr3_ecc_corrected_m(void)
388{ 388{
389 return 0x1 << 7; 389 return 0x1U << 7U;
390} 390}
391static inline u32 ltc_ltcs_ltss_intr3_ecc_uncorrected_m(void) 391static inline u32 ltc_ltcs_ltss_intr3_ecc_uncorrected_m(void)
392{ 392{
393 return 0x1 << 8; 393 return 0x1U << 8U;
394} 394}
395static inline u32 ltc_ltc0_lts0_intr3_r(void) 395static inline u32 ltc_ltc0_lts0_intr3_r(void)
396{ 396{
397 return 0x00140588; 397 return 0x00140588U;
398} 398}
399static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_r(void) 399static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_r(void)
400{ 400{
401 return 0x001404f0; 401 return 0x001404f0U;
402} 402}
403static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_f(u32 v) 403static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_f(u32 v)
404{ 404{
405 return (v & 0x1) << 1; 405 return (v & 0x1U) << 1U;
406} 406}
407static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m(void) 407static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_rstg_m(void)
408{ 408{
409 return 0x1 << 1; 409 return 0x1U << 1U;
410} 410}
411static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_f(u32 v) 411static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_f(u32 v)
412{ 412{
413 return (v & 0x1) << 3; 413 return (v & 0x1U) << 3U;
414} 414}
415static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m(void) 415static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_tstg_m(void)
416{ 416{
417 return 0x1 << 3; 417 return 0x1U << 3U;
418} 418}
419static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_f(u32 v) 419static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_f(u32 v)
420{ 420{
421 return (v & 0x1) << 5; 421 return (v & 0x1U) << 5U;
422} 422}
423static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m(void) 423static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_dstg_m(void)
424{ 424{
425 return 0x1 << 5; 425 return 0x1U << 5U;
426} 426}
427static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_f(u32 v) 427static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_f(u32 v)
428{ 428{
429 return (v & 0x1) << 0; 429 return (v & 0x1U) << 0U;
430} 430}
431static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m(void) 431static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_rstg_m(void)
432{ 432{
433 return 0x1 << 0; 433 return 0x1U << 0U;
434} 434}
435static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_f(u32 v) 435static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_f(u32 v)
436{ 436{
437 return (v & 0x1) << 2; 437 return (v & 0x1U) << 2U;
438} 438}
439static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m(void) 439static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_tstg_m(void)
440{ 440{
441 return 0x1 << 2; 441 return 0x1U << 2U;
442} 442}
443static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_f(u32 v) 443static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_f(u32 v)
444{ 444{
445 return (v & 0x1) << 4; 445 return (v & 0x1U) << 4U;
446} 446}
447static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m(void) 447static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_dstg_m(void)
448{ 448{
449 return 0x1 << 4; 449 return 0x1U << 4U;
450} 450}
451static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) 451static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v)
452{ 452{
453 return (v & 0x1) << 18; 453 return (v & 0x1U) << 18U;
454} 454}
455static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m(void) 455static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_total_counter_overflow_m(void)
456{ 456{
457 return 0x1 << 18; 457 return 0x1U << 18U;
458} 458}
459static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_f(u32 v) 459static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_f(u32 v)
460{ 460{
461 return (v & 0x1) << 16; 461 return (v & 0x1U) << 16U;
462} 462}
463static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m(void) 463static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_total_counter_overflow_m(void)
464{ 464{
465 return 0x1 << 16; 465 return 0x1U << 16U;
466} 466}
467static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) 467static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v)
468{ 468{
469 return (v & 0x1) << 19; 469 return (v & 0x1U) << 19U;
470} 470}
471static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_m(void) 471static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_uncorrected_err_unique_counter_overflow_m(void)
472{ 472{
473 return 0x1 << 19; 473 return 0x1U << 19U;
474} 474}
475static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) 475static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_f(u32 v)
476{ 476{
477 return (v & 0x1) << 17; 477 return (v & 0x1U) << 17U;
478} 478}
479static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_m(void) 479static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_corrected_err_unique_counter_overflow_m(void)
480{ 480{
481 return 0x1 << 17; 481 return 0x1U << 17U;
482} 482}
483static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_f(u32 v) 483static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_f(u32 v)
484{ 484{
485 return (v & 0x1) << 30; 485 return (v & 0x1U) << 30U;
486} 486}
487static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f(void) 487static inline u32 ltc_ltc0_lts0_l2_cache_ecc_status_reset_task_f(void)
488{ 488{
489 return 0x40000000; 489 return 0x40000000U;
490} 490}
491static inline u32 ltc_ltc0_lts0_l2_cache_ecc_address_r(void) 491static inline u32 ltc_ltc0_lts0_l2_cache_ecc_address_r(void)
492{ 492{
493 return 0x001404fc; 493 return 0x001404fcU;
494} 494}
495static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r(void) 495static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_r(void)
496{ 496{
497 return 0x001404f4; 497 return 0x001404f4U;
498} 498}
499static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s(void) 499static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_s(void)
500{ 500{
501 return 16; 501 return 16U;
502} 502}
503static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_f(u32 v) 503static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_f(u32 v)
504{ 504{
505 return (v & 0xffff) << 0; 505 return (v & 0xffffU) << 0U;
506} 506}
507static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_m(void) 507static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_m(void)
508{ 508{
509 return 0xffff << 0; 509 return 0xffffU << 0U;
510} 510}
511static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(u32 r) 511static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_total_v(u32 r)
512{ 512{
513 return (r >> 0) & 0xffff; 513 return (r >> 0U) & 0xffffU;
514} 514}
515static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_s(void) 515static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_s(void)
516{ 516{
517 return 16; 517 return 16U;
518} 518}
519static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_f(u32 v) 519static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_f(u32 v)
520{ 520{
521 return (v & 0xffff) << 16; 521 return (v & 0xffffU) << 16U;
522} 522}
523static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_m(void) 523static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_m(void)
524{ 524{
525 return 0xffff << 16; 525 return 0xffffU << 16U;
526} 526}
527static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_v(u32 r) 527static inline u32 ltc_ltc0_lts0_l2_cache_ecc_corrected_err_count_unique_total_v(u32 r)
528{ 528{
529 return (r >> 16) & 0xffff; 529 return (r >> 16U) & 0xffffU;
530} 530}
531static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r(void) 531static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_r(void)
532{ 532{
533 return 0x001404f8; 533 return 0x001404f8U;
534} 534}
535static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s(void) 535static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_s(void)
536{ 536{
537 return 16; 537 return 16U;
538} 538}
539static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_f(u32 v) 539static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_f(u32 v)
540{ 540{
541 return (v & 0xffff) << 0; 541 return (v & 0xffffU) << 0U;
542} 542}
543static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_m(void) 543static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_m(void)
544{ 544{
545 return 0xffff << 0; 545 return 0xffffU << 0U;
546} 546}
547static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(u32 r) 547static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_total_v(u32 r)
548{ 548{
549 return (r >> 0) & 0xffff; 549 return (r >> 0U) & 0xffffU;
550} 550}
551static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_s(void) 551static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_s(void)
552{ 552{
553 return 16; 553 return 16U;
554} 554}
555static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_f(u32 v) 555static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_f(u32 v)
556{ 556{
557 return (v & 0xffff) << 16; 557 return (v & 0xffffU) << 16U;
558} 558}
559static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_m(void) 559static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_m(void)
560{ 560{
561 return 0xffff << 16; 561 return 0xffffU << 16U;
562} 562}
563static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_v(u32 r) 563static inline u32 ltc_ltc0_lts0_l2_cache_ecc_uncorrected_err_count_unique_total_v(u32 r)
564{ 564{
565 return (r >> 16) & 0xffff; 565 return (r >> 16U) & 0xffffU;
566} 566}
567static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) 567static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void)
568{ 568{
569 return 0x0014051c; 569 return 0x0014051cU;
570} 570}
571static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) 571static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void)
572{ 572{
573 return 0xff << 0; 573 return 0xffU << 0U;
574} 574}
575static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) 575static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r)
576{ 576{
577 return (r >> 0) & 0xff; 577 return (r >> 0U) & 0xffU;
578} 578}
579static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) 579static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void)
580{ 580{
581 return 0xff << 16; 581 return 0xffU << 16U;
582} 582}
583static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) 583static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r)
584{ 584{
585 return (r >> 16) & 0xff; 585 return (r >> 16U) & 0xffU;
586} 586}
587static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) 587static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
588{ 588{
589 return 0x0017e2a0; 589 return 0x0017e2a0U;
590} 590}
591static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) 591static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
592{ 592{
593 return (r >> 0) & 0x1; 593 return (r >> 0U) & 0x1U;
594} 594}
595static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) 595static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
596{ 596{
597 return 0x00000001; 597 return 0x00000001U;
598} 598}
599static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) 599static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
600{ 600{
601 return 0x1; 601 return 0x1U;
602} 602}
603static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) 603static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
604{ 604{
605 return (r >> 8) & 0xf; 605 return (r >> 8U) & 0xfU;
606} 606}
607static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) 607static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
608{ 608{
609 return 0x00000003; 609 return 0x00000003U;
610} 610}
611static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) 611static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
612{ 612{
613 return 0x300; 613 return 0x300U;
614} 614}
615static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) 615static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
616{ 616{
617 return (r >> 28) & 0x1; 617 return (r >> 28U) & 0x1U;
618} 618}
619static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) 619static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
620{ 620{
621 return 0x00000001; 621 return 0x00000001U;
622} 622}
623static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) 623static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
624{ 624{
625 return 0x10000000; 625 return 0x10000000U;
626} 626}
627static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) 627static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
628{ 628{
629 return (r >> 29) & 0x1; 629 return (r >> 29U) & 0x1U;
630} 630}
631static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) 631static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
632{ 632{
633 return 0x00000001; 633 return 0x00000001U;
634} 634}
635static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) 635static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
636{ 636{
637 return 0x20000000; 637 return 0x20000000U;
638} 638}
639static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) 639static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
640{ 640{
641 return (r >> 30) & 0x1; 641 return (r >> 30U) & 0x1U;
642} 642}
643static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) 643static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
644{ 644{
645 return 0x00000001; 645 return 0x00000001U;
646} 646}
647static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) 647static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
648{ 648{
649 return 0x40000000; 649 return 0x40000000U;
650} 650}
651static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) 651static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
652{ 652{
653 return 0x0017e2a4; 653 return 0x0017e2a4U;
654} 654}
655static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) 655static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
656{ 656{
657 return (r >> 0) & 0x1; 657 return (r >> 0U) & 0x1U;
658} 658}
659static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) 659static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
660{ 660{
661 return 0x00000001; 661 return 0x00000001U;
662} 662}
663static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) 663static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
664{ 664{
665 return 0x1; 665 return 0x1U;
666} 666}
667static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) 667static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
668{ 668{
669 return (r >> 8) & 0xf; 669 return (r >> 8U) & 0xfU;
670} 670}
671static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) 671static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
672{ 672{
673 return 0x00000003; 673 return 0x00000003U;
674} 674}
675static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) 675static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
676{ 676{
677 return 0x300; 677 return 0x300U;
678} 678}
679static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) 679static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
680{ 680{
681 return (r >> 16) & 0x1; 681 return (r >> 16U) & 0x1U;
682} 682}
683static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) 683static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
684{ 684{
685 return 0x00000001; 685 return 0x00000001U;
686} 686}
687static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) 687static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
688{ 688{
689 return 0x10000; 689 return 0x10000U;
690} 690}
691static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) 691static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
692{ 692{
693 return (r >> 28) & 0x1; 693 return (r >> 28U) & 0x1U;
694} 694}
695static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) 695static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
696{ 696{
697 return 0x00000001; 697 return 0x00000001U;
698} 698}
699static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) 699static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
700{ 700{
701 return 0x10000000; 701 return 0x10000000U;
702} 702}
703static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) 703static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
704{ 704{
705 return (r >> 29) & 0x1; 705 return (r >> 29U) & 0x1U;
706} 706}
707static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) 707static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
708{ 708{
709 return 0x00000001; 709 return 0x00000001U;
710} 710}
711static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) 711static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
712{ 712{
713 return 0x20000000; 713 return 0x20000000U;
714} 714}
715static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) 715static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
716{ 716{
717 return (r >> 30) & 0x1; 717 return (r >> 30U) & 0x1U;
718} 718}
719static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) 719static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
720{ 720{
721 return 0x00000001; 721 return 0x00000001U;
722} 722}
723static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) 723static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
724{ 724{
725 return 0x40000000; 725 return 0x40000000U;
726} 726}
727static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) 727static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
728{ 728{
729 return 0x001402a0; 729 return 0x001402a0U;
730} 730}
731static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) 731static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
732{ 732{
733 return (r >> 0) & 0x1; 733 return (r >> 0U) & 0x1U;
734} 734}
735static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) 735static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
736{ 736{
737 return 0x00000001; 737 return 0x00000001U;
738} 738}
739static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) 739static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
740{ 740{
741 return 0x1; 741 return 0x1U;
742} 742}
743static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) 743static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
744{ 744{
745 return 0x001402a4; 745 return 0x001402a4U;
746} 746}
747static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) 747static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
748{ 748{
749 return (r >> 0) & 0x1; 749 return (r >> 0U) & 0x1U;
750} 750}
751static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) 751static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
752{ 752{
753 return 0x00000001; 753 return 0x00000001U;
754} 754}
755static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) 755static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
756{ 756{
757 return 0x1; 757 return 0x1U;
758} 758}
759static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) 759static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void)
760{ 760{
761 return 0x001422a0; 761 return 0x001422a0U;
762} 762}
763static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) 763static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r)
764{ 764{
765 return (r >> 0) & 0x1; 765 return (r >> 0U) & 0x1U;
766} 766}
767static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) 767static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void)
768{ 768{
769 return 0x00000001; 769 return 0x00000001U;
770} 770}
771static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) 771static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void)
772{ 772{
773 return 0x1; 773 return 0x1U;
774} 774}
775static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) 775static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void)
776{ 776{
777 return 0x001422a4; 777 return 0x001422a4U;
778} 778}
779static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) 779static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r)
780{ 780{
781 return (r >> 0) & 0x1; 781 return (r >> 0U) & 0x1U;
782} 782}
783static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) 783static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void)
784{ 784{
785 return 0x00000001; 785 return 0x00000001U;
786} 786}
787static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) 787static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void)
788{ 788{
789 return 0x1; 789 return 0x1U;
790} 790}
791static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) 791static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void)
792{ 792{
793 return 0x0014058c; 793 return 0x0014058cU;
794} 794}
795static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) 795static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r)
796{ 796{
797 return (r >> 0) & 0xffff; 797 return (r >> 0U) & 0xffffU;
798} 798}
799static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) 799static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r)
800{ 800{
801 return (r >> 16) & 0x1f; 801 return (r >> 16U) & 0x1fU;
802} 802}
803#endif 803#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h
index 7228cd8b..bff73076 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h
@@ -58,194 +58,194 @@
58 58
59static inline u32 mc_boot_0_r(void) 59static inline u32 mc_boot_0_r(void)
60{ 60{
61 return 0x00000000; 61 return 0x00000000U;
62} 62}
63static inline u32 mc_boot_0_architecture_v(u32 r) 63static inline u32 mc_boot_0_architecture_v(u32 r)
64{ 64{
65 return (r >> 24) & 0x1f; 65 return (r >> 24U) & 0x1fU;
66} 66}
67static inline u32 mc_boot_0_implementation_v(u32 r) 67static inline u32 mc_boot_0_implementation_v(u32 r)
68{ 68{
69 return (r >> 20) & 0xf; 69 return (r >> 20U) & 0xfU;
70} 70}
71static inline u32 mc_boot_0_major_revision_v(u32 r) 71static inline u32 mc_boot_0_major_revision_v(u32 r)
72{ 72{
73 return (r >> 4) & 0xf; 73 return (r >> 4U) & 0xfU;
74} 74}
75static inline u32 mc_boot_0_minor_revision_v(u32 r) 75static inline u32 mc_boot_0_minor_revision_v(u32 r)
76{ 76{
77 return (r >> 0) & 0xf; 77 return (r >> 0U) & 0xfU;
78} 78}
79static inline u32 mc_intr_r(u32 i) 79static inline u32 mc_intr_r(u32 i)
80{ 80{
81 return 0x00000100 + i*4; 81 return 0x00000100U + i*4U;
82} 82}
83static inline u32 mc_intr_pfifo_pending_f(void) 83static inline u32 mc_intr_pfifo_pending_f(void)
84{ 84{
85 return 0x100; 85 return 0x100U;
86} 86}
87static inline u32 mc_intr_hub_pending_f(void) 87static inline u32 mc_intr_hub_pending_f(void)
88{ 88{
89 return 0x200; 89 return 0x200U;
90} 90}
91static inline u32 mc_intr_pgraph_pending_f(void) 91static inline u32 mc_intr_pgraph_pending_f(void)
92{ 92{
93 return 0x1000; 93 return 0x1000U;
94} 94}
95static inline u32 mc_intr_pmu_pending_f(void) 95static inline u32 mc_intr_pmu_pending_f(void)
96{ 96{
97 return 0x1000000; 97 return 0x1000000U;
98} 98}
99static inline u32 mc_intr_ltc_pending_f(void) 99static inline u32 mc_intr_ltc_pending_f(void)
100{ 100{
101 return 0x2000000; 101 return 0x2000000U;
102} 102}
103static inline u32 mc_intr_priv_ring_pending_f(void) 103static inline u32 mc_intr_priv_ring_pending_f(void)
104{ 104{
105 return 0x40000000; 105 return 0x40000000U;
106} 106}
107static inline u32 mc_intr_pbus_pending_f(void) 107static inline u32 mc_intr_pbus_pending_f(void)
108{ 108{
109 return 0x10000000; 109 return 0x10000000U;
110} 110}
111static inline u32 mc_intr_en_r(u32 i) 111static inline u32 mc_intr_en_r(u32 i)
112{ 112{
113 return 0x00000140 + i*4; 113 return 0x00000140U + i*4U;
114} 114}
115static inline u32 mc_intr_en_set_r(u32 i) 115static inline u32 mc_intr_en_set_r(u32 i)
116{ 116{
117 return 0x00000160 + i*4; 117 return 0x00000160U + i*4U;
118} 118}
119static inline u32 mc_intr_en_clear_r(u32 i) 119static inline u32 mc_intr_en_clear_r(u32 i)
120{ 120{
121 return 0x00000180 + i*4; 121 return 0x00000180U + i*4U;
122} 122}
123static inline u32 mc_enable_r(void) 123static inline u32 mc_enable_r(void)
124{ 124{
125 return 0x00000200; 125 return 0x00000200U;
126} 126}
127static inline u32 mc_enable_xbar_enabled_f(void) 127static inline u32 mc_enable_xbar_enabled_f(void)
128{ 128{
129 return 0x4; 129 return 0x4U;
130} 130}
131static inline u32 mc_enable_l2_enabled_f(void) 131static inline u32 mc_enable_l2_enabled_f(void)
132{ 132{
133 return 0x8; 133 return 0x8U;
134} 134}
135static inline u32 mc_enable_pmedia_s(void) 135static inline u32 mc_enable_pmedia_s(void)
136{ 136{
137 return 1; 137 return 1U;
138} 138}
139static inline u32 mc_enable_pmedia_f(u32 v) 139static inline u32 mc_enable_pmedia_f(u32 v)
140{ 140{
141 return (v & 0x1) << 4; 141 return (v & 0x1U) << 4U;
142} 142}
143static inline u32 mc_enable_pmedia_m(void) 143static inline u32 mc_enable_pmedia_m(void)
144{ 144{
145 return 0x1 << 4; 145 return 0x1U << 4U;
146} 146}
147static inline u32 mc_enable_pmedia_v(u32 r) 147static inline u32 mc_enable_pmedia_v(u32 r)
148{ 148{
149 return (r >> 4) & 0x1; 149 return (r >> 4U) & 0x1U;
150} 150}
151static inline u32 mc_enable_ce0_m(void) 151static inline u32 mc_enable_ce0_m(void)
152{ 152{
153 return 0x1 << 6; 153 return 0x1U << 6U;
154} 154}
155static inline u32 mc_enable_pfifo_enabled_f(void) 155static inline u32 mc_enable_pfifo_enabled_f(void)
156{ 156{
157 return 0x100; 157 return 0x100U;
158} 158}
159static inline u32 mc_enable_pgraph_enabled_f(void) 159static inline u32 mc_enable_pgraph_enabled_f(void)
160{ 160{
161 return 0x1000; 161 return 0x1000U;
162} 162}
163static inline u32 mc_enable_pwr_v(u32 r) 163static inline u32 mc_enable_pwr_v(u32 r)
164{ 164{
165 return (r >> 13) & 0x1; 165 return (r >> 13U) & 0x1U;
166} 166}
167static inline u32 mc_enable_pwr_disabled_v(void) 167static inline u32 mc_enable_pwr_disabled_v(void)
168{ 168{
169 return 0x00000000; 169 return 0x00000000U;
170} 170}
171static inline u32 mc_enable_pwr_enabled_f(void) 171static inline u32 mc_enable_pwr_enabled_f(void)
172{ 172{
173 return 0x2000; 173 return 0x2000U;
174} 174}
175static inline u32 mc_enable_pfb_enabled_f(void) 175static inline u32 mc_enable_pfb_enabled_f(void)
176{ 176{
177 return 0x100000; 177 return 0x100000U;
178} 178}
179static inline u32 mc_enable_ce2_m(void) 179static inline u32 mc_enable_ce2_m(void)
180{ 180{
181 return 0x1 << 21; 181 return 0x1U << 21U;
182} 182}
183static inline u32 mc_enable_ce2_enabled_f(void) 183static inline u32 mc_enable_ce2_enabled_f(void)
184{ 184{
185 return 0x200000; 185 return 0x200000U;
186} 186}
187static inline u32 mc_enable_blg_enabled_f(void) 187static inline u32 mc_enable_blg_enabled_f(void)
188{ 188{
189 return 0x8000000; 189 return 0x8000000U;
190} 190}
191static inline u32 mc_enable_perfmon_enabled_f(void) 191static inline u32 mc_enable_perfmon_enabled_f(void)
192{ 192{
193 return 0x10000000; 193 return 0x10000000U;
194} 194}
195static inline u32 mc_enable_hub_enabled_f(void) 195static inline u32 mc_enable_hub_enabled_f(void)
196{ 196{
197 return 0x20000000; 197 return 0x20000000U;
198} 198}
199static inline u32 mc_intr_ltc_r(void) 199static inline u32 mc_intr_ltc_r(void)
200{ 200{
201 return 0x000001c0; 201 return 0x000001c0U;
202} 202}
203static inline u32 mc_enable_pb_r(void) 203static inline u32 mc_enable_pb_r(void)
204{ 204{
205 return 0x00000204; 205 return 0x00000204U;
206} 206}
207static inline u32 mc_enable_pb_0_s(void) 207static inline u32 mc_enable_pb_0_s(void)
208{ 208{
209 return 1; 209 return 1U;
210} 210}
211static inline u32 mc_enable_pb_0_f(u32 v) 211static inline u32 mc_enable_pb_0_f(u32 v)
212{ 212{
213 return (v & 0x1) << 0; 213 return (v & 0x1U) << 0U;
214} 214}
215static inline u32 mc_enable_pb_0_m(void) 215static inline u32 mc_enable_pb_0_m(void)
216{ 216{
217 return 0x1 << 0; 217 return 0x1U << 0U;
218} 218}
219static inline u32 mc_enable_pb_0_v(u32 r) 219static inline u32 mc_enable_pb_0_v(u32 r)
220{ 220{
221 return (r >> 0) & 0x1; 221 return (r >> 0U) & 0x1U;
222} 222}
223static inline u32 mc_enable_pb_0_enabled_v(void) 223static inline u32 mc_enable_pb_0_enabled_v(void)
224{ 224{
225 return 0x00000001; 225 return 0x00000001U;
226} 226}
227static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) 227static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
228{ 228{
229 return (v & 0x1) << (0 + i*1); 229 return (v & 0x1U) << (0U + i*1U);
230} 230}
231static inline u32 mc_elpg_enable_r(void) 231static inline u32 mc_elpg_enable_r(void)
232{ 232{
233 return 0x0000020c; 233 return 0x0000020cU;
234} 234}
235static inline u32 mc_elpg_enable_xbar_enabled_f(void) 235static inline u32 mc_elpg_enable_xbar_enabled_f(void)
236{ 236{
237 return 0x4; 237 return 0x4U;
238} 238}
239static inline u32 mc_elpg_enable_pfb_enabled_f(void) 239static inline u32 mc_elpg_enable_pfb_enabled_f(void)
240{ 240{
241 return 0x100000; 241 return 0x100000U;
242} 242}
243static inline u32 mc_elpg_enable_hub_enabled_f(void) 243static inline u32 mc_elpg_enable_hub_enabled_f(void)
244{ 244{
245 return 0x20000000; 245 return 0x20000000U;
246} 246}
247static inline u32 mc_elpg_enable_l2_enabled_f(void) 247static inline u32 mc_elpg_enable_l2_enabled_f(void)
248{ 248{
249 return 0x8; 249 return 0x8U;
250} 250}
251#endif 251#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h
index 025a7af3..74ff4002 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h
@@ -58,594 +58,594 @@
58 58
59static inline u32 pbdma_gp_entry1_r(void) 59static inline u32 pbdma_gp_entry1_r(void)
60{ 60{
61 return 0x10000004; 61 return 0x10000004U;
62} 62}
63static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) 63static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
64{ 64{
65 return (r >> 0) & 0xff; 65 return (r >> 0U) & 0xffU;
66} 66}
67static inline u32 pbdma_gp_entry1_length_f(u32 v) 67static inline u32 pbdma_gp_entry1_length_f(u32 v)
68{ 68{
69 return (v & 0x1fffff) << 10; 69 return (v & 0x1fffffU) << 10U;
70} 70}
71static inline u32 pbdma_gp_entry1_length_v(u32 r) 71static inline u32 pbdma_gp_entry1_length_v(u32 r)
72{ 72{
73 return (r >> 10) & 0x1fffff; 73 return (r >> 10U) & 0x1fffffU;
74} 74}
75static inline u32 pbdma_gp_base_r(u32 i) 75static inline u32 pbdma_gp_base_r(u32 i)
76{ 76{
77 return 0x00040048 + i*8192; 77 return 0x00040048U + i*8192U;
78} 78}
79static inline u32 pbdma_gp_base__size_1_v(void) 79static inline u32 pbdma_gp_base__size_1_v(void)
80{ 80{
81 return 0x00000003; 81 return 0x00000003U;
82} 82}
83static inline u32 pbdma_gp_base_offset_f(u32 v) 83static inline u32 pbdma_gp_base_offset_f(u32 v)
84{ 84{
85 return (v & 0x1fffffff) << 3; 85 return (v & 0x1fffffffU) << 3U;
86} 86}
87static inline u32 pbdma_gp_base_rsvd_s(void) 87static inline u32 pbdma_gp_base_rsvd_s(void)
88{ 88{
89 return 3; 89 return 3U;
90} 90}
91static inline u32 pbdma_gp_base_hi_r(u32 i) 91static inline u32 pbdma_gp_base_hi_r(u32 i)
92{ 92{
93 return 0x0004004c + i*8192; 93 return 0x0004004cU + i*8192U;
94} 94}
95static inline u32 pbdma_gp_base_hi_offset_f(u32 v) 95static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
96{ 96{
97 return (v & 0xff) << 0; 97 return (v & 0xffU) << 0U;
98} 98}
99static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) 99static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
100{ 100{
101 return (v & 0x1f) << 16; 101 return (v & 0x1fU) << 16U;
102} 102}
103static inline u32 pbdma_gp_fetch_r(u32 i) 103static inline u32 pbdma_gp_fetch_r(u32 i)
104{ 104{
105 return 0x00040050 + i*8192; 105 return 0x00040050U + i*8192U;
106} 106}
107static inline u32 pbdma_gp_get_r(u32 i) 107static inline u32 pbdma_gp_get_r(u32 i)
108{ 108{
109 return 0x00040014 + i*8192; 109 return 0x00040014U + i*8192U;
110} 110}
111static inline u32 pbdma_gp_put_r(u32 i) 111static inline u32 pbdma_gp_put_r(u32 i)
112{ 112{
113 return 0x00040000 + i*8192; 113 return 0x00040000U + i*8192U;
114} 114}
115static inline u32 pbdma_pb_fetch_r(u32 i) 115static inline u32 pbdma_pb_fetch_r(u32 i)
116{ 116{
117 return 0x00040054 + i*8192; 117 return 0x00040054U + i*8192U;
118} 118}
119static inline u32 pbdma_pb_fetch_hi_r(u32 i) 119static inline u32 pbdma_pb_fetch_hi_r(u32 i)
120{ 120{
121 return 0x00040058 + i*8192; 121 return 0x00040058U + i*8192U;
122} 122}
123static inline u32 pbdma_get_r(u32 i) 123static inline u32 pbdma_get_r(u32 i)
124{ 124{
125 return 0x00040018 + i*8192; 125 return 0x00040018U + i*8192U;
126} 126}
127static inline u32 pbdma_get_hi_r(u32 i) 127static inline u32 pbdma_get_hi_r(u32 i)
128{ 128{
129 return 0x0004001c + i*8192; 129 return 0x0004001cU + i*8192U;
130} 130}
131static inline u32 pbdma_put_r(u32 i) 131static inline u32 pbdma_put_r(u32 i)
132{ 132{
133 return 0x0004005c + i*8192; 133 return 0x0004005cU + i*8192U;
134} 134}
135static inline u32 pbdma_put_hi_r(u32 i) 135static inline u32 pbdma_put_hi_r(u32 i)
136{ 136{
137 return 0x00040060 + i*8192; 137 return 0x00040060U + i*8192U;
138} 138}
139static inline u32 pbdma_pb_header_r(u32 i) 139static inline u32 pbdma_pb_header_r(u32 i)
140{ 140{
141 return 0x00040084 + i*8192; 141 return 0x00040084U + i*8192U;
142} 142}
143static inline u32 pbdma_pb_header_priv_user_f(void) 143static inline u32 pbdma_pb_header_priv_user_f(void)
144{ 144{
145 return 0x0; 145 return 0x0U;
146} 146}
147static inline u32 pbdma_pb_header_method_zero_f(void) 147static inline u32 pbdma_pb_header_method_zero_f(void)
148{ 148{
149 return 0x0; 149 return 0x0U;
150} 150}
151static inline u32 pbdma_pb_header_subchannel_zero_f(void) 151static inline u32 pbdma_pb_header_subchannel_zero_f(void)
152{ 152{
153 return 0x0; 153 return 0x0U;
154} 154}
155static inline u32 pbdma_pb_header_level_main_f(void) 155static inline u32 pbdma_pb_header_level_main_f(void)
156{ 156{
157 return 0x0; 157 return 0x0U;
158} 158}
159static inline u32 pbdma_pb_header_first_true_f(void) 159static inline u32 pbdma_pb_header_first_true_f(void)
160{ 160{
161 return 0x400000; 161 return 0x400000U;
162} 162}
163static inline u32 pbdma_pb_header_type_inc_f(void) 163static inline u32 pbdma_pb_header_type_inc_f(void)
164{ 164{
165 return 0x20000000; 165 return 0x20000000U;
166} 166}
167static inline u32 pbdma_pb_header_type_non_inc_f(void) 167static inline u32 pbdma_pb_header_type_non_inc_f(void)
168{ 168{
169 return 0x60000000; 169 return 0x60000000U;
170} 170}
171static inline u32 pbdma_hdr_shadow_r(u32 i) 171static inline u32 pbdma_hdr_shadow_r(u32 i)
172{ 172{
173 return 0x00040118 + i*8192; 173 return 0x00040118U + i*8192U;
174} 174}
175static inline u32 pbdma_subdevice_r(u32 i) 175static inline u32 pbdma_subdevice_r(u32 i)
176{ 176{
177 return 0x00040094 + i*8192; 177 return 0x00040094U + i*8192U;
178} 178}
179static inline u32 pbdma_subdevice_id_f(u32 v) 179static inline u32 pbdma_subdevice_id_f(u32 v)
180{ 180{
181 return (v & 0xfff) << 0; 181 return (v & 0xfffU) << 0U;
182} 182}
183static inline u32 pbdma_subdevice_status_active_f(void) 183static inline u32 pbdma_subdevice_status_active_f(void)
184{ 184{
185 return 0x10000000; 185 return 0x10000000U;
186} 186}
187static inline u32 pbdma_subdevice_channel_dma_enable_f(void) 187static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
188{ 188{
189 return 0x20000000; 189 return 0x20000000U;
190} 190}
191static inline u32 pbdma_method0_r(u32 i) 191static inline u32 pbdma_method0_r(u32 i)
192{ 192{
193 return 0x000400c0 + i*8192; 193 return 0x000400c0U + i*8192U;
194} 194}
195static inline u32 pbdma_method0_fifo_size_v(void) 195static inline u32 pbdma_method0_fifo_size_v(void)
196{ 196{
197 return 0x00000004; 197 return 0x00000004U;
198} 198}
199static inline u32 pbdma_method0_addr_f(u32 v) 199static inline u32 pbdma_method0_addr_f(u32 v)
200{ 200{
201 return (v & 0xfff) << 2; 201 return (v & 0xfffU) << 2U;
202} 202}
203static inline u32 pbdma_method0_addr_v(u32 r) 203static inline u32 pbdma_method0_addr_v(u32 r)
204{ 204{
205 return (r >> 2) & 0xfff; 205 return (r >> 2U) & 0xfffU;
206} 206}
207static inline u32 pbdma_method0_subch_v(u32 r) 207static inline u32 pbdma_method0_subch_v(u32 r)
208{ 208{
209 return (r >> 16) & 0x7; 209 return (r >> 16U) & 0x7U;
210} 210}
211static inline u32 pbdma_method0_first_true_f(void) 211static inline u32 pbdma_method0_first_true_f(void)
212{ 212{
213 return 0x400000; 213 return 0x400000U;
214} 214}
215static inline u32 pbdma_method0_valid_true_f(void) 215static inline u32 pbdma_method0_valid_true_f(void)
216{ 216{
217 return 0x80000000; 217 return 0x80000000U;
218} 218}
219static inline u32 pbdma_method1_r(u32 i) 219static inline u32 pbdma_method1_r(u32 i)
220{ 220{
221 return 0x000400c8 + i*8192; 221 return 0x000400c8U + i*8192U;
222} 222}
223static inline u32 pbdma_method2_r(u32 i) 223static inline u32 pbdma_method2_r(u32 i)
224{ 224{
225 return 0x000400d0 + i*8192; 225 return 0x000400d0U + i*8192U;
226} 226}
227static inline u32 pbdma_method3_r(u32 i) 227static inline u32 pbdma_method3_r(u32 i)
228{ 228{
229 return 0x000400d8 + i*8192; 229 return 0x000400d8U + i*8192U;
230} 230}
231static inline u32 pbdma_data0_r(u32 i) 231static inline u32 pbdma_data0_r(u32 i)
232{ 232{
233 return 0x000400c4 + i*8192; 233 return 0x000400c4U + i*8192U;
234} 234}
235static inline u32 pbdma_acquire_r(u32 i) 235static inline u32 pbdma_acquire_r(u32 i)
236{ 236{
237 return 0x00040030 + i*8192; 237 return 0x00040030U + i*8192U;
238} 238}
239static inline u32 pbdma_acquire_retry_man_2_f(void) 239static inline u32 pbdma_acquire_retry_man_2_f(void)
240{ 240{
241 return 0x2; 241 return 0x2U;
242} 242}
243static inline u32 pbdma_acquire_retry_exp_2_f(void) 243static inline u32 pbdma_acquire_retry_exp_2_f(void)
244{ 244{
245 return 0x100; 245 return 0x100U;
246} 246}
247static inline u32 pbdma_acquire_timeout_exp_f(u32 v) 247static inline u32 pbdma_acquire_timeout_exp_f(u32 v)
248{ 248{
249 return (v & 0xf) << 11; 249 return (v & 0xfU) << 11U;
250} 250}
251static inline u32 pbdma_acquire_timeout_exp_max_v(void) 251static inline u32 pbdma_acquire_timeout_exp_max_v(void)
252{ 252{
253 return 0x0000000f; 253 return 0x0000000fU;
254} 254}
255static inline u32 pbdma_acquire_timeout_exp_max_f(void) 255static inline u32 pbdma_acquire_timeout_exp_max_f(void)
256{ 256{
257 return 0x7800; 257 return 0x7800U;
258} 258}
259static inline u32 pbdma_acquire_timeout_man_f(u32 v) 259static inline u32 pbdma_acquire_timeout_man_f(u32 v)
260{ 260{
261 return (v & 0xffff) << 15; 261 return (v & 0xffffU) << 15U;
262} 262}
263static inline u32 pbdma_acquire_timeout_man_max_v(void) 263static inline u32 pbdma_acquire_timeout_man_max_v(void)
264{ 264{
265 return 0x0000ffff; 265 return 0x0000ffffU;
266} 266}
267static inline u32 pbdma_acquire_timeout_man_max_f(void) 267static inline u32 pbdma_acquire_timeout_man_max_f(void)
268{ 268{
269 return 0x7fff8000; 269 return 0x7fff8000U;
270} 270}
271static inline u32 pbdma_acquire_timeout_en_enable_f(void) 271static inline u32 pbdma_acquire_timeout_en_enable_f(void)
272{ 272{
273 return 0x80000000; 273 return 0x80000000U;
274} 274}
275static inline u32 pbdma_acquire_timeout_en_disable_f(void) 275static inline u32 pbdma_acquire_timeout_en_disable_f(void)
276{ 276{
277 return 0x0; 277 return 0x0U;
278} 278}
279static inline u32 pbdma_status_r(u32 i) 279static inline u32 pbdma_status_r(u32 i)
280{ 280{
281 return 0x00040100 + i*8192; 281 return 0x00040100U + i*8192U;
282} 282}
283static inline u32 pbdma_channel_r(u32 i) 283static inline u32 pbdma_channel_r(u32 i)
284{ 284{
285 return 0x00040120 + i*8192; 285 return 0x00040120U + i*8192U;
286} 286}
287static inline u32 pbdma_signature_r(u32 i) 287static inline u32 pbdma_signature_r(u32 i)
288{ 288{
289 return 0x00040010 + i*8192; 289 return 0x00040010U + i*8192U;
290} 290}
291static inline u32 pbdma_signature_hw_valid_f(void) 291static inline u32 pbdma_signature_hw_valid_f(void)
292{ 292{
293 return 0xface; 293 return 0xfaceU;
294} 294}
295static inline u32 pbdma_signature_sw_zero_f(void) 295static inline u32 pbdma_signature_sw_zero_f(void)
296{ 296{
297 return 0x0; 297 return 0x0U;
298} 298}
299static inline u32 pbdma_userd_r(u32 i) 299static inline u32 pbdma_userd_r(u32 i)
300{ 300{
301 return 0x00040008 + i*8192; 301 return 0x00040008U + i*8192U;
302} 302}
303static inline u32 pbdma_userd_target_vid_mem_f(void) 303static inline u32 pbdma_userd_target_vid_mem_f(void)
304{ 304{
305 return 0x0; 305 return 0x0U;
306} 306}
307static inline u32 pbdma_userd_target_sys_mem_coh_f(void) 307static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
308{ 308{
309 return 0x2; 309 return 0x2U;
310} 310}
311static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void) 311static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
312{ 312{
313 return 0x3; 313 return 0x3U;
314} 314}
315static inline u32 pbdma_userd_addr_f(u32 v) 315static inline u32 pbdma_userd_addr_f(u32 v)
316{ 316{
317 return (v & 0x7fffff) << 9; 317 return (v & 0x7fffffU) << 9U;
318} 318}
319static inline u32 pbdma_config_r(u32 i) 319static inline u32 pbdma_config_r(u32 i)
320{ 320{
321 return 0x000400f4 + i*8192; 321 return 0x000400f4U + i*8192U;
322} 322}
323static inline u32 pbdma_config_l2_evict_first_f(void) 323static inline u32 pbdma_config_l2_evict_first_f(void)
324{ 324{
325 return 0x0; 325 return 0x0U;
326} 326}
327static inline u32 pbdma_config_l2_evict_normal_f(void) 327static inline u32 pbdma_config_l2_evict_normal_f(void)
328{ 328{
329 return 0x1; 329 return 0x1U;
330} 330}
331static inline u32 pbdma_config_l2_evict_last_f(void) 331static inline u32 pbdma_config_l2_evict_last_f(void)
332{ 332{
333 return 0x2; 333 return 0x2U;
334} 334}
335static inline u32 pbdma_config_ce_split_enable_f(void) 335static inline u32 pbdma_config_ce_split_enable_f(void)
336{ 336{
337 return 0x0; 337 return 0x0U;
338} 338}
339static inline u32 pbdma_config_ce_split_disable_f(void) 339static inline u32 pbdma_config_ce_split_disable_f(void)
340{ 340{
341 return 0x10; 341 return 0x10U;
342} 342}
343static inline u32 pbdma_config_auth_level_non_privileged_f(void) 343static inline u32 pbdma_config_auth_level_non_privileged_f(void)
344{ 344{
345 return 0x0; 345 return 0x0U;
346} 346}
347static inline u32 pbdma_config_auth_level_privileged_f(void) 347static inline u32 pbdma_config_auth_level_privileged_f(void)
348{ 348{
349 return 0x100; 349 return 0x100U;
350} 350}
351static inline u32 pbdma_config_userd_writeback_disable_f(void) 351static inline u32 pbdma_config_userd_writeback_disable_f(void)
352{ 352{
353 return 0x0; 353 return 0x0U;
354} 354}
355static inline u32 pbdma_config_userd_writeback_enable_f(void) 355static inline u32 pbdma_config_userd_writeback_enable_f(void)
356{ 356{
357 return 0x1000; 357 return 0x1000U;
358} 358}
359static inline u32 pbdma_userd_hi_r(u32 i) 359static inline u32 pbdma_userd_hi_r(u32 i)
360{ 360{
361 return 0x0004000c + i*8192; 361 return 0x0004000cU + i*8192U;
362} 362}
363static inline u32 pbdma_userd_hi_addr_f(u32 v) 363static inline u32 pbdma_userd_hi_addr_f(u32 v)
364{ 364{
365 return (v & 0xff) << 0; 365 return (v & 0xffU) << 0U;
366} 366}
367static inline u32 pbdma_hce_ctrl_r(u32 i) 367static inline u32 pbdma_hce_ctrl_r(u32 i)
368{ 368{
369 return 0x000400e4 + i*8192; 369 return 0x000400e4U + i*8192U;
370} 370}
371static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) 371static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
372{ 372{
373 return 0x20; 373 return 0x20U;
374} 374}
375static inline u32 pbdma_intr_0_r(u32 i) 375static inline u32 pbdma_intr_0_r(u32 i)
376{ 376{
377 return 0x00040108 + i*8192; 377 return 0x00040108U + i*8192U;
378} 378}
379static inline u32 pbdma_intr_0_memreq_v(u32 r) 379static inline u32 pbdma_intr_0_memreq_v(u32 r)
380{ 380{
381 return (r >> 0) & 0x1; 381 return (r >> 0U) & 0x1U;
382} 382}
383static inline u32 pbdma_intr_0_memreq_pending_f(void) 383static inline u32 pbdma_intr_0_memreq_pending_f(void)
384{ 384{
385 return 0x1; 385 return 0x1U;
386} 386}
387static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) 387static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
388{ 388{
389 return 0x2; 389 return 0x2U;
390} 390}
391static inline u32 pbdma_intr_0_memack_extra_pending_f(void) 391static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
392{ 392{
393 return 0x4; 393 return 0x4U;
394} 394}
395static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) 395static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
396{ 396{
397 return 0x8; 397 return 0x8U;
398} 398}
399static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) 399static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
400{ 400{
401 return 0x10; 401 return 0x10U;
402} 402}
403static inline u32 pbdma_intr_0_memflush_pending_f(void) 403static inline u32 pbdma_intr_0_memflush_pending_f(void)
404{ 404{
405 return 0x20; 405 return 0x20U;
406} 406}
407static inline u32 pbdma_intr_0_memop_pending_f(void) 407static inline u32 pbdma_intr_0_memop_pending_f(void)
408{ 408{
409 return 0x40; 409 return 0x40U;
410} 410}
411static inline u32 pbdma_intr_0_lbconnect_pending_f(void) 411static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
412{ 412{
413 return 0x80; 413 return 0x80U;
414} 414}
415static inline u32 pbdma_intr_0_lbreq_pending_f(void) 415static inline u32 pbdma_intr_0_lbreq_pending_f(void)
416{ 416{
417 return 0x100; 417 return 0x100U;
418} 418}
419static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) 419static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
420{ 420{
421 return 0x200; 421 return 0x200U;
422} 422}
423static inline u32 pbdma_intr_0_lback_extra_pending_f(void) 423static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
424{ 424{
425 return 0x400; 425 return 0x400U;
426} 426}
427static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) 427static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
428{ 428{
429 return 0x800; 429 return 0x800U;
430} 430}
431static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) 431static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
432{ 432{
433 return 0x1000; 433 return 0x1000U;
434} 434}
435static inline u32 pbdma_intr_0_gpfifo_pending_f(void) 435static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
436{ 436{
437 return 0x2000; 437 return 0x2000U;
438} 438}
439static inline u32 pbdma_intr_0_gpptr_pending_f(void) 439static inline u32 pbdma_intr_0_gpptr_pending_f(void)
440{ 440{
441 return 0x4000; 441 return 0x4000U;
442} 442}
443static inline u32 pbdma_intr_0_gpentry_pending_f(void) 443static inline u32 pbdma_intr_0_gpentry_pending_f(void)
444{ 444{
445 return 0x8000; 445 return 0x8000U;
446} 446}
447static inline u32 pbdma_intr_0_gpcrc_pending_f(void) 447static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
448{ 448{
449 return 0x10000; 449 return 0x10000U;
450} 450}
451static inline u32 pbdma_intr_0_pbptr_pending_f(void) 451static inline u32 pbdma_intr_0_pbptr_pending_f(void)
452{ 452{
453 return 0x20000; 453 return 0x20000U;
454} 454}
455static inline u32 pbdma_intr_0_pbentry_pending_f(void) 455static inline u32 pbdma_intr_0_pbentry_pending_f(void)
456{ 456{
457 return 0x40000; 457 return 0x40000U;
458} 458}
459static inline u32 pbdma_intr_0_pbcrc_pending_f(void) 459static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
460{ 460{
461 return 0x80000; 461 return 0x80000U;
462} 462}
463static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void) 463static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void)
464{ 464{
465 return 0x100000; 465 return 0x100000U;
466} 466}
467static inline u32 pbdma_intr_0_method_pending_f(void) 467static inline u32 pbdma_intr_0_method_pending_f(void)
468{ 468{
469 return 0x200000; 469 return 0x200000U;
470} 470}
471static inline u32 pbdma_intr_0_methodcrc_pending_f(void) 471static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
472{ 472{
473 return 0x400000; 473 return 0x400000U;
474} 474}
475static inline u32 pbdma_intr_0_device_pending_f(void) 475static inline u32 pbdma_intr_0_device_pending_f(void)
476{ 476{
477 return 0x800000; 477 return 0x800000U;
478} 478}
479static inline u32 pbdma_intr_0_eng_reset_pending_f(void) 479static inline u32 pbdma_intr_0_eng_reset_pending_f(void)
480{ 480{
481 return 0x1000000; 481 return 0x1000000U;
482} 482}
483static inline u32 pbdma_intr_0_semaphore_pending_f(void) 483static inline u32 pbdma_intr_0_semaphore_pending_f(void)
484{ 484{
485 return 0x2000000; 485 return 0x2000000U;
486} 486}
487static inline u32 pbdma_intr_0_acquire_pending_f(void) 487static inline u32 pbdma_intr_0_acquire_pending_f(void)
488{ 488{
489 return 0x4000000; 489 return 0x4000000U;
490} 490}
491static inline u32 pbdma_intr_0_pri_pending_f(void) 491static inline u32 pbdma_intr_0_pri_pending_f(void)
492{ 492{
493 return 0x8000000; 493 return 0x8000000U;
494} 494}
495static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) 495static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
496{ 496{
497 return 0x20000000; 497 return 0x20000000U;
498} 498}
499static inline u32 pbdma_intr_0_pbseg_pending_f(void) 499static inline u32 pbdma_intr_0_pbseg_pending_f(void)
500{ 500{
501 return 0x40000000; 501 return 0x40000000U;
502} 502}
503static inline u32 pbdma_intr_0_signature_pending_f(void) 503static inline u32 pbdma_intr_0_signature_pending_f(void)
504{ 504{
505 return 0x80000000; 505 return 0x80000000U;
506} 506}
507static inline u32 pbdma_intr_1_r(u32 i) 507static inline u32 pbdma_intr_1_r(u32 i)
508{ 508{
509 return 0x00040148 + i*8192; 509 return 0x00040148U + i*8192U;
510} 510}
511static inline u32 pbdma_intr_1_ctxnotvalid_m(void) 511static inline u32 pbdma_intr_1_ctxnotvalid_m(void)
512{ 512{
513 return 0x1 << 31; 513 return 0x1U << 31U;
514} 514}
515static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) 515static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void)
516{ 516{
517 return 0x80000000; 517 return 0x80000000U;
518} 518}
519static inline u32 pbdma_intr_en_0_r(u32 i) 519static inline u32 pbdma_intr_en_0_r(u32 i)
520{ 520{
521 return 0x0004010c + i*8192; 521 return 0x0004010cU + i*8192U;
522} 522}
523static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) 523static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
524{ 524{
525 return 0x100; 525 return 0x100U;
526} 526}
527static inline u32 pbdma_intr_en_1_r(u32 i) 527static inline u32 pbdma_intr_en_1_r(u32 i)
528{ 528{
529 return 0x0004014c + i*8192; 529 return 0x0004014cU + i*8192U;
530} 530}
531static inline u32 pbdma_intr_stall_r(u32 i) 531static inline u32 pbdma_intr_stall_r(u32 i)
532{ 532{
533 return 0x0004013c + i*8192; 533 return 0x0004013cU + i*8192U;
534} 534}
535static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) 535static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
536{ 536{
537 return 0x100; 537 return 0x100U;
538} 538}
539static inline u32 pbdma_intr_stall_1_r(u32 i) 539static inline u32 pbdma_intr_stall_1_r(u32 i)
540{ 540{
541 return 0x00040140 + i*8192; 541 return 0x00040140U + i*8192U;
542} 542}
543static inline u32 pbdma_udma_nop_r(void) 543static inline u32 pbdma_udma_nop_r(void)
544{ 544{
545 return 0x00000008; 545 return 0x00000008U;
546} 546}
547static inline u32 pbdma_runlist_timeslice_r(u32 i) 547static inline u32 pbdma_runlist_timeslice_r(u32 i)
548{ 548{
549 return 0x000400f8 + i*8192; 549 return 0x000400f8U + i*8192U;
550} 550}
551static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) 551static inline u32 pbdma_runlist_timeslice_timeout_128_f(void)
552{ 552{
553 return 0x80; 553 return 0x80U;
554} 554}
555static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) 555static inline u32 pbdma_runlist_timeslice_timescale_3_f(void)
556{ 556{
557 return 0x3000; 557 return 0x3000U;
558} 558}
559static inline u32 pbdma_runlist_timeslice_enable_true_f(void) 559static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
560{ 560{
561 return 0x10000000; 561 return 0x10000000U;
562} 562}
563static inline u32 pbdma_target_r(u32 i) 563static inline u32 pbdma_target_r(u32 i)
564{ 564{
565 return 0x000400ac + i*8192; 565 return 0x000400acU + i*8192U;
566} 566}
567static inline u32 pbdma_target_engine_sw_f(void) 567static inline u32 pbdma_target_engine_sw_f(void)
568{ 568{
569 return 0x1f; 569 return 0x1fU;
570} 570}
571static inline u32 pbdma_target_eng_ctx_valid_true_f(void) 571static inline u32 pbdma_target_eng_ctx_valid_true_f(void)
572{ 572{
573 return 0x10000; 573 return 0x10000U;
574} 574}
575static inline u32 pbdma_target_eng_ctx_valid_false_f(void) 575static inline u32 pbdma_target_eng_ctx_valid_false_f(void)
576{ 576{
577 return 0x0; 577 return 0x0U;
578} 578}
579static inline u32 pbdma_target_ce_ctx_valid_true_f(void) 579static inline u32 pbdma_target_ce_ctx_valid_true_f(void)
580{ 580{
581 return 0x20000; 581 return 0x20000U;
582} 582}
583static inline u32 pbdma_target_ce_ctx_valid_false_f(void) 583static inline u32 pbdma_target_ce_ctx_valid_false_f(void)
584{ 584{
585 return 0x0; 585 return 0x0U;
586} 586}
587static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void) 587static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void)
588{ 588{
589 return 0x0; 589 return 0x0U;
590} 590}
591static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void) 591static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void)
592{ 592{
593 return 0x1000000; 593 return 0x1000000U;
594} 594}
595static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void) 595static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void)
596{ 596{
597 return 0x2000000; 597 return 0x2000000U;
598} 598}
599static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void) 599static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void)
600{ 600{
601 return 0x3000000; 601 return 0x3000000U;
602} 602}
603static inline u32 pbdma_target_should_send_tsg_event_true_f(void) 603static inline u32 pbdma_target_should_send_tsg_event_true_f(void)
604{ 604{
605 return 0x20000000; 605 return 0x20000000U;
606} 606}
607static inline u32 pbdma_target_should_send_tsg_event_false_f(void) 607static inline u32 pbdma_target_should_send_tsg_event_false_f(void)
608{ 608{
609 return 0x0; 609 return 0x0U;
610} 610}
611static inline u32 pbdma_target_needs_host_tsg_event_true_f(void) 611static inline u32 pbdma_target_needs_host_tsg_event_true_f(void)
612{ 612{
613 return 0x80000000; 613 return 0x80000000U;
614} 614}
615static inline u32 pbdma_target_needs_host_tsg_event_false_f(void) 615static inline u32 pbdma_target_needs_host_tsg_event_false_f(void)
616{ 616{
617 return 0x0; 617 return 0x0U;
618} 618}
619static inline u32 pbdma_set_channel_info_r(u32 i) 619static inline u32 pbdma_set_channel_info_r(u32 i)
620{ 620{
621 return 0x000400fc + i*8192; 621 return 0x000400fcU + i*8192U;
622} 622}
623static inline u32 pbdma_set_channel_info_scg_type_graphics_compute0_f(void) 623static inline u32 pbdma_set_channel_info_scg_type_graphics_compute0_f(void)
624{ 624{
625 return 0x0; 625 return 0x0U;
626} 626}
627static inline u32 pbdma_set_channel_info_scg_type_compute1_f(void) 627static inline u32 pbdma_set_channel_info_scg_type_compute1_f(void)
628{ 628{
629 return 0x1; 629 return 0x1U;
630} 630}
631static inline u32 pbdma_set_channel_info_veid_f(u32 v) 631static inline u32 pbdma_set_channel_info_veid_f(u32 v)
632{ 632{
633 return (v & 0x3f) << 8; 633 return (v & 0x3fU) << 8U;
634} 634}
635static inline u32 pbdma_timeout_r(u32 i) 635static inline u32 pbdma_timeout_r(u32 i)
636{ 636{
637 return 0x0004012c + i*8192; 637 return 0x0004012cU + i*8192U;
638} 638}
639static inline u32 pbdma_timeout_period_m(void) 639static inline u32 pbdma_timeout_period_m(void)
640{ 640{
641 return 0xffffffff << 0; 641 return 0xffffffffU << 0U;
642} 642}
643static inline u32 pbdma_timeout_period_max_f(void) 643static inline u32 pbdma_timeout_period_max_f(void)
644{ 644{
645 return 0xffffffff; 645 return 0xffffffffU;
646} 646}
647static inline u32 pbdma_timeout_period_init_f(void) 647static inline u32 pbdma_timeout_period_init_f(void)
648{ 648{
649 return 0x10000; 649 return 0x10000U;
650} 650}
651#endif 651#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h
index 5adee5f3..788a6ab6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_perf_gv11b.h
@@ -58,154 +58,154 @@
58 58
59static inline u32 perf_pmasys_control_r(void) 59static inline u32 perf_pmasys_control_r(void)
60{ 60{
61 return 0x0024a000; 61 return 0x0024a000U;
62} 62}
63static inline u32 perf_pmasys_control_membuf_status_v(u32 r) 63static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
64{ 64{
65 return (r >> 4) & 0x1; 65 return (r >> 4U) & 0x1U;
66} 66}
67static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) 67static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
68{ 68{
69 return 0x00000001; 69 return 0x00000001U;
70} 70}
71static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) 71static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
72{ 72{
73 return 0x10; 73 return 0x10U;
74} 74}
75static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) 75static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
76{ 76{
77 return (v & 0x1) << 5; 77 return (v & 0x1U) << 5U;
78} 78}
79static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) 79static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
80{ 80{
81 return (r >> 5) & 0x1; 81 return (r >> 5U) & 0x1U;
82} 82}
83static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) 83static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
84{ 84{
85 return 0x00000001; 85 return 0x00000001U;
86} 86}
87static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) 87static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
88{ 88{
89 return 0x20; 89 return 0x20U;
90} 90}
91static inline u32 perf_pmasys_mem_block_r(void) 91static inline u32 perf_pmasys_mem_block_r(void)
92{ 92{
93 return 0x0024a070; 93 return 0x0024a070U;
94} 94}
95static inline u32 perf_pmasys_mem_block_base_f(u32 v) 95static inline u32 perf_pmasys_mem_block_base_f(u32 v)
96{ 96{
97 return (v & 0xfffffff) << 0; 97 return (v & 0xfffffffU) << 0U;
98} 98}
99static inline u32 perf_pmasys_mem_block_target_f(u32 v) 99static inline u32 perf_pmasys_mem_block_target_f(u32 v)
100{ 100{
101 return (v & 0x3) << 28; 101 return (v & 0x3U) << 28U;
102} 102}
103static inline u32 perf_pmasys_mem_block_target_v(u32 r) 103static inline u32 perf_pmasys_mem_block_target_v(u32 r)
104{ 104{
105 return (r >> 28) & 0x3; 105 return (r >> 28U) & 0x3U;
106} 106}
107static inline u32 perf_pmasys_mem_block_target_lfb_v(void) 107static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
108{ 108{
109 return 0x00000000; 109 return 0x00000000U;
110} 110}
111static inline u32 perf_pmasys_mem_block_target_lfb_f(void) 111static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
112{ 112{
113 return 0x0; 113 return 0x0U;
114} 114}
115static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) 115static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
116{ 116{
117 return 0x00000002; 117 return 0x00000002U;
118} 118}
119static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) 119static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
120{ 120{
121 return 0x20000000; 121 return 0x20000000U;
122} 122}
123static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) 123static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
124{ 124{
125 return 0x00000003; 125 return 0x00000003U;
126} 126}
127static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) 127static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
128{ 128{
129 return 0x30000000; 129 return 0x30000000U;
130} 130}
131static inline u32 perf_pmasys_mem_block_valid_f(u32 v) 131static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
132{ 132{
133 return (v & 0x1) << 31; 133 return (v & 0x1U) << 31U;
134} 134}
135static inline u32 perf_pmasys_mem_block_valid_v(u32 r) 135static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
136{ 136{
137 return (r >> 31) & 0x1; 137 return (r >> 31U) & 0x1U;
138} 138}
139static inline u32 perf_pmasys_mem_block_valid_true_v(void) 139static inline u32 perf_pmasys_mem_block_valid_true_v(void)
140{ 140{
141 return 0x00000001; 141 return 0x00000001U;
142} 142}
143static inline u32 perf_pmasys_mem_block_valid_true_f(void) 143static inline u32 perf_pmasys_mem_block_valid_true_f(void)
144{ 144{
145 return 0x80000000; 145 return 0x80000000U;
146} 146}
147static inline u32 perf_pmasys_mem_block_valid_false_v(void) 147static inline u32 perf_pmasys_mem_block_valid_false_v(void)
148{ 148{
149 return 0x00000000; 149 return 0x00000000U;
150} 150}
151static inline u32 perf_pmasys_mem_block_valid_false_f(void) 151static inline u32 perf_pmasys_mem_block_valid_false_f(void)
152{ 152{
153 return 0x0; 153 return 0x0U;
154} 154}
155static inline u32 perf_pmasys_outbase_r(void) 155static inline u32 perf_pmasys_outbase_r(void)
156{ 156{
157 return 0x0024a074; 157 return 0x0024a074U;
158} 158}
159static inline u32 perf_pmasys_outbase_ptr_f(u32 v) 159static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
160{ 160{
161 return (v & 0x7ffffff) << 5; 161 return (v & 0x7ffffffU) << 5U;
162} 162}
163static inline u32 perf_pmasys_outbaseupper_r(void) 163static inline u32 perf_pmasys_outbaseupper_r(void)
164{ 164{
165 return 0x0024a078; 165 return 0x0024a078U;
166} 166}
167static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) 167static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
168{ 168{
169 return (v & 0xff) << 0; 169 return (v & 0xffU) << 0U;
170} 170}
171static inline u32 perf_pmasys_outsize_r(void) 171static inline u32 perf_pmasys_outsize_r(void)
172{ 172{
173 return 0x0024a07c; 173 return 0x0024a07cU;
174} 174}
175static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) 175static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
176{ 176{
177 return (v & 0x7ffffff) << 5; 177 return (v & 0x7ffffffU) << 5U;
178} 178}
179static inline u32 perf_pmasys_mem_bytes_r(void) 179static inline u32 perf_pmasys_mem_bytes_r(void)
180{ 180{
181 return 0x0024a084; 181 return 0x0024a084U;
182} 182}
183static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) 183static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
184{ 184{
185 return (v & 0xfffffff) << 4; 185 return (v & 0xfffffffU) << 4U;
186} 186}
187static inline u32 perf_pmasys_mem_bump_r(void) 187static inline u32 perf_pmasys_mem_bump_r(void)
188{ 188{
189 return 0x0024a088; 189 return 0x0024a088U;
190} 190}
191static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) 191static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
192{ 192{
193 return (v & 0xfffffff) << 4; 193 return (v & 0xfffffffU) << 4U;
194} 194}
195static inline u32 perf_pmasys_enginestatus_r(void) 195static inline u32 perf_pmasys_enginestatus_r(void)
196{ 196{
197 return 0x0024a0a4; 197 return 0x0024a0a4U;
198} 198}
199static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) 199static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
200{ 200{
201 return (v & 0x1) << 4; 201 return (v & 0x1U) << 4U;
202} 202}
203static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) 203static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
204{ 204{
205 return 0x00000001; 205 return 0x00000001U;
206} 206}
207static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) 207static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
208{ 208{
209 return 0x10; 209 return 0x10U;
210} 210}
211#endif 211#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h
index 1568f310..456d6316 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pram_gv11b.h
@@ -58,6 +58,6 @@
58 58
59static inline u32 pram_data032_r(u32 i) 59static inline u32 pram_data032_r(u32 i)
60{ 60{
61 return 0x00700000 + i*4; 61 return 0x00700000U + i*4U;
62} 62}
63#endif 63#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h
index 24509b08..a653681d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringmaster_gv11b.h
@@ -58,110 +58,110 @@
58 58
59static inline u32 pri_ringmaster_command_r(void) 59static inline u32 pri_ringmaster_command_r(void)
60{ 60{
61 return 0x0012004c; 61 return 0x0012004cU;
62} 62}
63static inline u32 pri_ringmaster_command_cmd_m(void) 63static inline u32 pri_ringmaster_command_cmd_m(void)
64{ 64{
65 return 0x3f << 0; 65 return 0x3fU << 0U;
66} 66}
67static inline u32 pri_ringmaster_command_cmd_v(u32 r) 67static inline u32 pri_ringmaster_command_cmd_v(u32 r)
68{ 68{
69 return (r >> 0) & 0x3f; 69 return (r >> 0U) & 0x3fU;
70} 70}
71static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) 71static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
72{ 72{
73 return 0x00000000; 73 return 0x00000000U;
74} 74}
75static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) 75static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
76{ 76{
77 return 0x1; 77 return 0x1U;
78} 78}
79static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) 79static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
80{ 80{
81 return 0x2; 81 return 0x2U;
82} 82}
83static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) 83static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
84{ 84{
85 return 0x3; 85 return 0x3U;
86} 86}
87static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) 87static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
88{ 88{
89 return 0x0; 89 return 0x0U;
90} 90}
91static inline u32 pri_ringmaster_command_data_r(void) 91static inline u32 pri_ringmaster_command_data_r(void)
92{ 92{
93 return 0x00120048; 93 return 0x00120048U;
94} 94}
95static inline u32 pri_ringmaster_start_results_r(void) 95static inline u32 pri_ringmaster_start_results_r(void)
96{ 96{
97 return 0x00120050; 97 return 0x00120050U;
98} 98}
99static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) 99static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
100{ 100{
101 return (r >> 0) & 0x1; 101 return (r >> 0U) & 0x1U;
102} 102}
103static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) 103static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
104{ 104{
105 return 0x00000001; 105 return 0x00000001U;
106} 106}
107static inline u32 pri_ringmaster_intr_status0_r(void) 107static inline u32 pri_ringmaster_intr_status0_r(void)
108{ 108{
109 return 0x00120058; 109 return 0x00120058U;
110} 110}
111static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r) 111static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
112{ 112{
113 return (r >> 0) & 0x1; 113 return (r >> 0U) & 0x1U;
114} 114}
115static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r) 115static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
116{ 116{
117 return (r >> 1) & 0x1; 117 return (r >> 1U) & 0x1U;
118} 118}
119static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r) 119static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
120{ 120{
121 return (r >> 2) & 0x1; 121 return (r >> 2U) & 0x1U;
122} 122}
123static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r) 123static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
124{ 124{
125 return (r >> 8) & 0x1; 125 return (r >> 8U) & 0x1U;
126} 126}
127static inline u32 pri_ringmaster_intr_status1_r(void) 127static inline u32 pri_ringmaster_intr_status1_r(void)
128{ 128{
129 return 0x0012005c; 129 return 0x0012005cU;
130} 130}
131static inline u32 pri_ringmaster_global_ctl_r(void) 131static inline u32 pri_ringmaster_global_ctl_r(void)
132{ 132{
133 return 0x00120060; 133 return 0x00120060U;
134} 134}
135static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) 135static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
136{ 136{
137 return 0x1; 137 return 0x1U;
138} 138}
139static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) 139static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
140{ 140{
141 return 0x0; 141 return 0x0U;
142} 142}
143static inline u32 pri_ringmaster_enum_fbp_r(void) 143static inline u32 pri_ringmaster_enum_fbp_r(void)
144{ 144{
145 return 0x00120074; 145 return 0x00120074U;
146} 146}
147static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) 147static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
148{ 148{
149 return (r >> 0) & 0x1f; 149 return (r >> 0U) & 0x1fU;
150} 150}
151static inline u32 pri_ringmaster_enum_gpc_r(void) 151static inline u32 pri_ringmaster_enum_gpc_r(void)
152{ 152{
153 return 0x00120078; 153 return 0x00120078U;
154} 154}
155static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) 155static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
156{ 156{
157 return (r >> 0) & 0x1f; 157 return (r >> 0U) & 0x1fU;
158} 158}
159static inline u32 pri_ringmaster_enum_ltc_r(void) 159static inline u32 pri_ringmaster_enum_ltc_r(void)
160{ 160{
161 return 0x0012006c; 161 return 0x0012006cU;
162} 162}
163static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) 163static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
164{ 164{
165 return (r >> 0) & 0x1f; 165 return (r >> 0U) & 0x1fU;
166} 166}
167#endif 167#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h
index 119e2075..47da22c0 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_gpc_gv11b.h
@@ -58,22 +58,22 @@
58 58
59static inline u32 pri_ringstation_gpc_master_config_r(u32 i) 59static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
60{ 60{
61 return 0x00128300 + i*4; 61 return 0x00128300U + i*4U;
62} 62}
63static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void) 63static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
64{ 64{
65 return 0x00128120; 65 return 0x00128120U;
66} 66}
67static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void) 67static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
68{ 68{
69 return 0x00128124; 69 return 0x00128124U;
70} 70}
71static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void) 71static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
72{ 72{
73 return 0x00128128; 73 return 0x00128128U;
74} 74}
75static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void) 75static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
76{ 76{
77 return 0x0012812c; 77 return 0x0012812cU;
78} 78}
79#endif 79#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h
index 85b86c98..622b6d7b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pri_ringstation_sys_gv11b.h
@@ -58,34 +58,34 @@
58 58
59static inline u32 pri_ringstation_sys_master_config_r(u32 i) 59static inline u32 pri_ringstation_sys_master_config_r(u32 i)
60{ 60{
61 return 0x00122300 + i*4; 61 return 0x00122300U + i*4U;
62} 62}
63static inline u32 pri_ringstation_sys_decode_config_r(void) 63static inline u32 pri_ringstation_sys_decode_config_r(void)
64{ 64{
65 return 0x00122204; 65 return 0x00122204U;
66} 66}
67static inline u32 pri_ringstation_sys_decode_config_ring_m(void) 67static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
68{ 68{
69 return 0x7 << 0; 69 return 0x7U << 0U;
70} 70}
71static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) 71static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
72{ 72{
73 return 0x1; 73 return 0x1U;
74} 74}
75static inline u32 pri_ringstation_sys_priv_error_adr_r(void) 75static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
76{ 76{
77 return 0x00122120; 77 return 0x00122120U;
78} 78}
79static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void) 79static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
80{ 80{
81 return 0x00122124; 81 return 0x00122124U;
82} 82}
83static inline u32 pri_ringstation_sys_priv_error_info_r(void) 83static inline u32 pri_ringstation_sys_priv_error_info_r(void)
84{ 84{
85 return 0x00122128; 85 return 0x00122128U;
86} 86}
87static inline u32 pri_ringstation_sys_priv_error_code_r(void) 87static inline u32 pri_ringstation_sys_priv_error_code_r(void)
88{ 88{
89 return 0x0012212c; 89 return 0x0012212cU;
90} 90}
91#endif 91#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h
index 8406ea21..808fe316 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_proj_gv11b.h
@@ -58,130 +58,130 @@
58 58
59static inline u32 proj_gpc_base_v(void) 59static inline u32 proj_gpc_base_v(void)
60{ 60{
61 return 0x00500000; 61 return 0x00500000U;
62} 62}
63static inline u32 proj_gpc_shared_base_v(void) 63static inline u32 proj_gpc_shared_base_v(void)
64{ 64{
65 return 0x00418000; 65 return 0x00418000U;
66} 66}
67static inline u32 proj_gpc_stride_v(void) 67static inline u32 proj_gpc_stride_v(void)
68{ 68{
69 return 0x00008000; 69 return 0x00008000U;
70} 70}
71static inline u32 proj_ltc_stride_v(void) 71static inline u32 proj_ltc_stride_v(void)
72{ 72{
73 return 0x00002000; 73 return 0x00002000U;
74} 74}
75static inline u32 proj_lts_stride_v(void) 75static inline u32 proj_lts_stride_v(void)
76{ 76{
77 return 0x00000200; 77 return 0x00000200U;
78} 78}
79static inline u32 proj_fbpa_stride_v(void) 79static inline u32 proj_fbpa_stride_v(void)
80{ 80{
81 return 0x00004000; 81 return 0x00004000U;
82} 82}
83static inline u32 proj_ppc_in_gpc_base_v(void) 83static inline u32 proj_ppc_in_gpc_base_v(void)
84{ 84{
85 return 0x00003000; 85 return 0x00003000U;
86} 86}
87static inline u32 proj_ppc_in_gpc_shared_base_v(void) 87static inline u32 proj_ppc_in_gpc_shared_base_v(void)
88{ 88{
89 return 0x00003e00; 89 return 0x00003e00U;
90} 90}
91static inline u32 proj_ppc_in_gpc_stride_v(void) 91static inline u32 proj_ppc_in_gpc_stride_v(void)
92{ 92{
93 return 0x00000200; 93 return 0x00000200U;
94} 94}
95static inline u32 proj_rop_base_v(void) 95static inline u32 proj_rop_base_v(void)
96{ 96{
97 return 0x00410000; 97 return 0x00410000U;
98} 98}
99static inline u32 proj_rop_shared_base_v(void) 99static inline u32 proj_rop_shared_base_v(void)
100{ 100{
101 return 0x00408800; 101 return 0x00408800U;
102} 102}
103static inline u32 proj_rop_stride_v(void) 103static inline u32 proj_rop_stride_v(void)
104{ 104{
105 return 0x00000400; 105 return 0x00000400U;
106} 106}
107static inline u32 proj_tpc_in_gpc_base_v(void) 107static inline u32 proj_tpc_in_gpc_base_v(void)
108{ 108{
109 return 0x00004000; 109 return 0x00004000U;
110} 110}
111static inline u32 proj_tpc_in_gpc_stride_v(void) 111static inline u32 proj_tpc_in_gpc_stride_v(void)
112{ 112{
113 return 0x00000800; 113 return 0x00000800U;
114} 114}
115static inline u32 proj_tpc_in_gpc_shared_base_v(void) 115static inline u32 proj_tpc_in_gpc_shared_base_v(void)
116{ 116{
117 return 0x00001800; 117 return 0x00001800U;
118} 118}
119static inline u32 proj_smpc_base_v(void) 119static inline u32 proj_smpc_base_v(void)
120{ 120{
121 return 0x00000200; 121 return 0x00000200U;
122} 122}
123static inline u32 proj_smpc_shared_base_v(void) 123static inline u32 proj_smpc_shared_base_v(void)
124{ 124{
125 return 0x00000300; 125 return 0x00000300U;
126} 126}
127static inline u32 proj_smpc_unique_base_v(void) 127static inline u32 proj_smpc_unique_base_v(void)
128{ 128{
129 return 0x00000600; 129 return 0x00000600U;
130} 130}
131static inline u32 proj_smpc_stride_v(void) 131static inline u32 proj_smpc_stride_v(void)
132{ 132{
133 return 0x00000100; 133 return 0x00000100U;
134} 134}
135static inline u32 proj_host_num_engines_v(void) 135static inline u32 proj_host_num_engines_v(void)
136{ 136{
137 return 0x00000004; 137 return 0x00000004U;
138} 138}
139static inline u32 proj_host_num_pbdma_v(void) 139static inline u32 proj_host_num_pbdma_v(void)
140{ 140{
141 return 0x00000003; 141 return 0x00000003U;
142} 142}
143static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) 143static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
144{ 144{
145 return 0x00000004; 145 return 0x00000004U;
146} 146}
147static inline u32 proj_scal_litter_num_fbps_v(void) 147static inline u32 proj_scal_litter_num_fbps_v(void)
148{ 148{
149 return 0x00000001; 149 return 0x00000001U;
150} 150}
151static inline u32 proj_scal_litter_num_fbpas_v(void) 151static inline u32 proj_scal_litter_num_fbpas_v(void)
152{ 152{
153 return 0x00000001; 153 return 0x00000001U;
154} 154}
155static inline u32 proj_scal_litter_num_gpcs_v(void) 155static inline u32 proj_scal_litter_num_gpcs_v(void)
156{ 156{
157 return 0x00000001; 157 return 0x00000001U;
158} 158}
159static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) 159static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
160{ 160{
161 return 0x00000002; 161 return 0x00000002U;
162} 162}
163static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) 163static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
164{ 164{
165 return 0x00000002; 165 return 0x00000002U;
166} 166}
167static inline u32 proj_scal_litter_num_zcull_banks_v(void) 167static inline u32 proj_scal_litter_num_zcull_banks_v(void)
168{ 168{
169 return 0x00000004; 169 return 0x00000004U;
170} 170}
171static inline u32 proj_scal_litter_num_sm_per_tpc_v(void) 171static inline u32 proj_scal_litter_num_sm_per_tpc_v(void)
172{ 172{
173 return 0x00000002; 173 return 0x00000002U;
174} 174}
175static inline u32 proj_scal_max_gpcs_v(void) 175static inline u32 proj_scal_max_gpcs_v(void)
176{ 176{
177 return 0x00000020; 177 return 0x00000020U;
178} 178}
179static inline u32 proj_scal_max_tpc_per_gpc_v(void) 179static inline u32 proj_scal_max_tpc_per_gpc_v(void)
180{ 180{
181 return 0x00000008; 181 return 0x00000008U;
182} 182}
183static inline u32 proj_sm_stride_v(void) 183static inline u32 proj_sm_stride_v(void)
184{ 184{
185 return 0x00000080; 185 return 0x00000080U;
186} 186}
187#endif 187#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
index 43c0c908..eba6d806 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pwr_gv11b.h
@@ -58,894 +58,894 @@
58 58
59static inline u32 pwr_falcon_irqsset_r(void) 59static inline u32 pwr_falcon_irqsset_r(void)
60{ 60{
61 return 0x0010a000; 61 return 0x0010a000U;
62} 62}
63static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) 63static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
64{ 64{
65 return 0x40; 65 return 0x40U;
66} 66}
67static inline u32 pwr_falcon_irqsclr_r(void) 67static inline u32 pwr_falcon_irqsclr_r(void)
68{ 68{
69 return 0x0010a004; 69 return 0x0010a004U;
70} 70}
71static inline u32 pwr_falcon_irqstat_r(void) 71static inline u32 pwr_falcon_irqstat_r(void)
72{ 72{
73 return 0x0010a008; 73 return 0x0010a008U;
74} 74}
75static inline u32 pwr_falcon_irqstat_halt_true_f(void) 75static inline u32 pwr_falcon_irqstat_halt_true_f(void)
76{ 76{
77 return 0x10; 77 return 0x10U;
78} 78}
79static inline u32 pwr_falcon_irqstat_exterr_true_f(void) 79static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
80{ 80{
81 return 0x20; 81 return 0x20U;
82} 82}
83static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) 83static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
84{ 84{
85 return 0x40; 85 return 0x40U;
86} 86}
87static inline u32 pwr_falcon_irqstat_ext_second_true_f(void) 87static inline u32 pwr_falcon_irqstat_ext_second_true_f(void)
88{ 88{
89 return 0x800; 89 return 0x800U;
90} 90}
91static inline u32 pwr_falcon_irqmode_r(void) 91static inline u32 pwr_falcon_irqmode_r(void)
92{ 92{
93 return 0x0010a00c; 93 return 0x0010a00cU;
94} 94}
95static inline u32 pwr_falcon_irqmset_r(void) 95static inline u32 pwr_falcon_irqmset_r(void)
96{ 96{
97 return 0x0010a010; 97 return 0x0010a010U;
98} 98}
99static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) 99static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
100{ 100{
101 return (v & 0x1) << 0; 101 return (v & 0x1U) << 0U;
102} 102}
103static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) 103static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
104{ 104{
105 return (v & 0x1) << 1; 105 return (v & 0x1U) << 1U;
106} 106}
107static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) 107static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
108{ 108{
109 return (v & 0x1) << 2; 109 return (v & 0x1U) << 2U;
110} 110}
111static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) 111static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
112{ 112{
113 return (v & 0x1) << 3; 113 return (v & 0x1U) << 3U;
114} 114}
115static inline u32 pwr_falcon_irqmset_halt_f(u32 v) 115static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
116{ 116{
117 return (v & 0x1) << 4; 117 return (v & 0x1U) << 4U;
118} 118}
119static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) 119static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
120{ 120{
121 return (v & 0x1) << 5; 121 return (v & 0x1U) << 5U;
122} 122}
123static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) 123static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
124{ 124{
125 return (v & 0x1) << 6; 125 return (v & 0x1U) << 6U;
126} 126}
127static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) 127static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
128{ 128{
129 return (v & 0x1) << 7; 129 return (v & 0x1U) << 7U;
130} 130}
131static inline u32 pwr_falcon_irqmset_ext_f(u32 v) 131static inline u32 pwr_falcon_irqmset_ext_f(u32 v)
132{ 132{
133 return (v & 0xff) << 8; 133 return (v & 0xffU) << 8U;
134} 134}
135static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v) 135static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v)
136{ 136{
137 return (v & 0x1) << 8; 137 return (v & 0x1U) << 8U;
138} 138}
139static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v) 139static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v)
140{ 140{
141 return (v & 0x1) << 9; 141 return (v & 0x1U) << 9U;
142} 142}
143static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v) 143static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v)
144{ 144{
145 return (v & 0x1) << 11; 145 return (v & 0x1U) << 11U;
146} 146}
147static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v) 147static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v)
148{ 148{
149 return (v & 0x1) << 12; 149 return (v & 0x1U) << 12U;
150} 150}
151static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v) 151static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v)
152{ 152{
153 return (v & 0x1) << 13; 153 return (v & 0x1U) << 13U;
154} 154}
155static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v) 155static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v)
156{ 156{
157 return (v & 0x1) << 14; 157 return (v & 0x1U) << 14U;
158} 158}
159static inline u32 pwr_falcon_irqmset_ext_rsvd8_f(u32 v) 159static inline u32 pwr_falcon_irqmset_ext_rsvd8_f(u32 v)
160{ 160{
161 return (v & 0x1) << 15; 161 return (v & 0x1U) << 15U;
162} 162}
163static inline u32 pwr_falcon_irqmclr_r(void) 163static inline u32 pwr_falcon_irqmclr_r(void)
164{ 164{
165 return 0x0010a014; 165 return 0x0010a014U;
166} 166}
167static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) 167static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
168{ 168{
169 return (v & 0x1) << 0; 169 return (v & 0x1U) << 0U;
170} 170}
171static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) 171static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
172{ 172{
173 return (v & 0x1) << 1; 173 return (v & 0x1U) << 1U;
174} 174}
175static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) 175static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
176{ 176{
177 return (v & 0x1) << 2; 177 return (v & 0x1U) << 2U;
178} 178}
179static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) 179static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
180{ 180{
181 return (v & 0x1) << 3; 181 return (v & 0x1U) << 3U;
182} 182}
183static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) 183static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
184{ 184{
185 return (v & 0x1) << 4; 185 return (v & 0x1U) << 4U;
186} 186}
187static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) 187static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
188{ 188{
189 return (v & 0x1) << 5; 189 return (v & 0x1U) << 5U;
190} 190}
191static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) 191static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
192{ 192{
193 return (v & 0x1) << 6; 193 return (v & 0x1U) << 6U;
194} 194}
195static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) 195static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
196{ 196{
197 return (v & 0x1) << 7; 197 return (v & 0x1U) << 7U;
198} 198}
199static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) 199static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
200{ 200{
201 return (v & 0xff) << 8; 201 return (v & 0xffU) << 8U;
202} 202}
203static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v) 203static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v)
204{ 204{
205 return (v & 0x1) << 8; 205 return (v & 0x1U) << 8U;
206} 206}
207static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v) 207static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v)
208{ 208{
209 return (v & 0x1) << 9; 209 return (v & 0x1U) << 9U;
210} 210}
211static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v) 211static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v)
212{ 212{
213 return (v & 0x1) << 11; 213 return (v & 0x1U) << 11U;
214} 214}
215static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v) 215static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v)
216{ 216{
217 return (v & 0x1) << 12; 217 return (v & 0x1U) << 12U;
218} 218}
219static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v) 219static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v)
220{ 220{
221 return (v & 0x1) << 13; 221 return (v & 0x1U) << 13U;
222} 222}
223static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v) 223static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v)
224{ 224{
225 return (v & 0x1) << 14; 225 return (v & 0x1U) << 14U;
226} 226}
227static inline u32 pwr_falcon_irqmclr_ext_rsvd8_f(u32 v) 227static inline u32 pwr_falcon_irqmclr_ext_rsvd8_f(u32 v)
228{ 228{
229 return (v & 0x1) << 15; 229 return (v & 0x1U) << 15U;
230} 230}
231static inline u32 pwr_falcon_irqmask_r(void) 231static inline u32 pwr_falcon_irqmask_r(void)
232{ 232{
233 return 0x0010a018; 233 return 0x0010a018U;
234} 234}
235static inline u32 pwr_falcon_irqdest_r(void) 235static inline u32 pwr_falcon_irqdest_r(void)
236{ 236{
237 return 0x0010a01c; 237 return 0x0010a01cU;
238} 238}
239static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) 239static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
240{ 240{
241 return (v & 0x1) << 0; 241 return (v & 0x1U) << 0U;
242} 242}
243static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) 243static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
244{ 244{
245 return (v & 0x1) << 1; 245 return (v & 0x1U) << 1U;
246} 246}
247static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) 247static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
248{ 248{
249 return (v & 0x1) << 2; 249 return (v & 0x1U) << 2U;
250} 250}
251static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) 251static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
252{ 252{
253 return (v & 0x1) << 3; 253 return (v & 0x1U) << 3U;
254} 254}
255static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) 255static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
256{ 256{
257 return (v & 0x1) << 4; 257 return (v & 0x1U) << 4U;
258} 258}
259static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) 259static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
260{ 260{
261 return (v & 0x1) << 5; 261 return (v & 0x1U) << 5U;
262} 262}
263static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) 263static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
264{ 264{
265 return (v & 0x1) << 6; 265 return (v & 0x1U) << 6U;
266} 266}
267static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) 267static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
268{ 268{
269 return (v & 0x1) << 7; 269 return (v & 0x1U) << 7U;
270} 270}
271static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) 271static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
272{ 272{
273 return (v & 0xff) << 8; 273 return (v & 0xffU) << 8U;
274} 274}
275static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v) 275static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v)
276{ 276{
277 return (v & 0x1) << 8; 277 return (v & 0x1U) << 8U;
278} 278}
279static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v) 279static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v)
280{ 280{
281 return (v & 0x1) << 9; 281 return (v & 0x1U) << 9U;
282} 282}
283static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v) 283static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v)
284{ 284{
285 return (v & 0x1) << 11; 285 return (v & 0x1U) << 11U;
286} 286}
287static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v) 287static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v)
288{ 288{
289 return (v & 0x1) << 12; 289 return (v & 0x1U) << 12U;
290} 290}
291static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v) 291static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v)
292{ 292{
293 return (v & 0x1) << 13; 293 return (v & 0x1U) << 13U;
294} 294}
295static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v) 295static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v)
296{ 296{
297 return (v & 0x1) << 14; 297 return (v & 0x1U) << 14U;
298} 298}
299static inline u32 pwr_falcon_irqdest_host_ext_rsvd8_f(u32 v) 299static inline u32 pwr_falcon_irqdest_host_ext_rsvd8_f(u32 v)
300{ 300{
301 return (v & 0x1) << 15; 301 return (v & 0x1U) << 15U;
302} 302}
303static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) 303static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
304{ 304{
305 return (v & 0x1) << 16; 305 return (v & 0x1U) << 16U;
306} 306}
307static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) 307static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
308{ 308{
309 return (v & 0x1) << 17; 309 return (v & 0x1U) << 17U;
310} 310}
311static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) 311static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
312{ 312{
313 return (v & 0x1) << 18; 313 return (v & 0x1U) << 18U;
314} 314}
315static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) 315static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
316{ 316{
317 return (v & 0x1) << 19; 317 return (v & 0x1U) << 19U;
318} 318}
319static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) 319static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
320{ 320{
321 return (v & 0x1) << 20; 321 return (v & 0x1U) << 20U;
322} 322}
323static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) 323static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
324{ 324{
325 return (v & 0x1) << 21; 325 return (v & 0x1U) << 21U;
326} 326}
327static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) 327static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
328{ 328{
329 return (v & 0x1) << 22; 329 return (v & 0x1U) << 22U;
330} 330}
331static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) 331static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
332{ 332{
333 return (v & 0x1) << 23; 333 return (v & 0x1U) << 23U;
334} 334}
335static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) 335static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
336{ 336{
337 return (v & 0xff) << 24; 337 return (v & 0xffU) << 24U;
338} 338}
339static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v) 339static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v)
340{ 340{
341 return (v & 0x1) << 24; 341 return (v & 0x1U) << 24U;
342} 342}
343static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v) 343static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v)
344{ 344{
345 return (v & 0x1) << 25; 345 return (v & 0x1U) << 25U;
346} 346}
347static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v) 347static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v)
348{ 348{
349 return (v & 0x1) << 27; 349 return (v & 0x1U) << 27U;
350} 350}
351static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v) 351static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v)
352{ 352{
353 return (v & 0x1) << 28; 353 return (v & 0x1U) << 28U;
354} 354}
355static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v) 355static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v)
356{ 356{
357 return (v & 0x1) << 29; 357 return (v & 0x1U) << 29U;
358} 358}
359static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v) 359static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v)
360{ 360{
361 return (v & 0x1) << 30; 361 return (v & 0x1U) << 30U;
362} 362}
363static inline u32 pwr_falcon_irqdest_target_ext_rsvd8_f(u32 v) 363static inline u32 pwr_falcon_irqdest_target_ext_rsvd8_f(u32 v)
364{ 364{
365 return (v & 0x1) << 31; 365 return (v & 0x1U) << 31U;
366} 366}
367static inline u32 pwr_falcon_curctx_r(void) 367static inline u32 pwr_falcon_curctx_r(void)
368{ 368{
369 return 0x0010a050; 369 return 0x0010a050U;
370} 370}
371static inline u32 pwr_falcon_nxtctx_r(void) 371static inline u32 pwr_falcon_nxtctx_r(void)
372{ 372{
373 return 0x0010a054; 373 return 0x0010a054U;
374} 374}
375static inline u32 pwr_falcon_mailbox0_r(void) 375static inline u32 pwr_falcon_mailbox0_r(void)
376{ 376{
377 return 0x0010a040; 377 return 0x0010a040U;
378} 378}
379static inline u32 pwr_falcon_mailbox1_r(void) 379static inline u32 pwr_falcon_mailbox1_r(void)
380{ 380{
381 return 0x0010a044; 381 return 0x0010a044U;
382} 382}
383static inline u32 pwr_falcon_itfen_r(void) 383static inline u32 pwr_falcon_itfen_r(void)
384{ 384{
385 return 0x0010a048; 385 return 0x0010a048U;
386} 386}
387static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) 387static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
388{ 388{
389 return 0x1; 389 return 0x1U;
390} 390}
391static inline u32 pwr_falcon_idlestate_r(void) 391static inline u32 pwr_falcon_idlestate_r(void)
392{ 392{
393 return 0x0010a04c; 393 return 0x0010a04cU;
394} 394}
395static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) 395static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
396{ 396{
397 return (r >> 0) & 0x1; 397 return (r >> 0U) & 0x1U;
398} 398}
399static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) 399static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
400{ 400{
401 return (r >> 1) & 0x7fff; 401 return (r >> 1U) & 0x7fffU;
402} 402}
403static inline u32 pwr_falcon_os_r(void) 403static inline u32 pwr_falcon_os_r(void)
404{ 404{
405 return 0x0010a080; 405 return 0x0010a080U;
406} 406}
407static inline u32 pwr_falcon_engctl_r(void) 407static inline u32 pwr_falcon_engctl_r(void)
408{ 408{
409 return 0x0010a0a4; 409 return 0x0010a0a4U;
410} 410}
411static inline u32 pwr_falcon_cpuctl_r(void) 411static inline u32 pwr_falcon_cpuctl_r(void)
412{ 412{
413 return 0x0010a100; 413 return 0x0010a100U;
414} 414}
415static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) 415static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
416{ 416{
417 return (v & 0x1) << 1; 417 return (v & 0x1U) << 1U;
418} 418}
419static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) 419static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
420{ 420{
421 return (v & 0x1) << 4; 421 return (v & 0x1U) << 4U;
422} 422}
423static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) 423static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
424{ 424{
425 return 0x1 << 4; 425 return 0x1U << 4U;
426} 426}
427static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) 427static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
428{ 428{
429 return (r >> 4) & 0x1; 429 return (r >> 4U) & 0x1U;
430} 430}
431static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) 431static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
432{ 432{
433 return (v & 0x1) << 6; 433 return (v & 0x1U) << 6U;
434} 434}
435static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) 435static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
436{ 436{
437 return 0x1 << 6; 437 return 0x1U << 6U;
438} 438}
439static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) 439static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
440{ 440{
441 return (r >> 6) & 0x1; 441 return (r >> 6U) & 0x1U;
442} 442}
443static inline u32 pwr_falcon_cpuctl_alias_r(void) 443static inline u32 pwr_falcon_cpuctl_alias_r(void)
444{ 444{
445 return 0x0010a130; 445 return 0x0010a130U;
446} 446}
447static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) 447static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v)
448{ 448{
449 return (v & 0x1) << 1; 449 return (v & 0x1U) << 1U;
450} 450}
451static inline u32 pwr_pmu_scpctl_stat_r(void) 451static inline u32 pwr_pmu_scpctl_stat_r(void)
452{ 452{
453 return 0x0010ac08; 453 return 0x0010ac08U;
454} 454}
455static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) 455static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
456{ 456{
457 return (v & 0x1) << 20; 457 return (v & 0x1U) << 20U;
458} 458}
459static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) 459static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
460{ 460{
461 return 0x1 << 20; 461 return 0x1U << 20U;
462} 462}
463static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) 463static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
464{ 464{
465 return (r >> 20) & 0x1; 465 return (r >> 20U) & 0x1U;
466} 466}
467static inline u32 pwr_falcon_imemc_r(u32 i) 467static inline u32 pwr_falcon_imemc_r(u32 i)
468{ 468{
469 return 0x0010a180 + i*16; 469 return 0x0010a180U + i*16U;
470} 470}
471static inline u32 pwr_falcon_imemc_offs_f(u32 v) 471static inline u32 pwr_falcon_imemc_offs_f(u32 v)
472{ 472{
473 return (v & 0x3f) << 2; 473 return (v & 0x3fU) << 2U;
474} 474}
475static inline u32 pwr_falcon_imemc_blk_f(u32 v) 475static inline u32 pwr_falcon_imemc_blk_f(u32 v)
476{ 476{
477 return (v & 0xff) << 8; 477 return (v & 0xffU) << 8U;
478} 478}
479static inline u32 pwr_falcon_imemc_aincw_f(u32 v) 479static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
480{ 480{
481 return (v & 0x1) << 24; 481 return (v & 0x1U) << 24U;
482} 482}
483static inline u32 pwr_falcon_imemd_r(u32 i) 483static inline u32 pwr_falcon_imemd_r(u32 i)
484{ 484{
485 return 0x0010a184 + i*16; 485 return 0x0010a184U + i*16U;
486} 486}
487static inline u32 pwr_falcon_imemt_r(u32 i) 487static inline u32 pwr_falcon_imemt_r(u32 i)
488{ 488{
489 return 0x0010a188 + i*16; 489 return 0x0010a188U + i*16U;
490} 490}
491static inline u32 pwr_falcon_sctl_r(void) 491static inline u32 pwr_falcon_sctl_r(void)
492{ 492{
493 return 0x0010a240; 493 return 0x0010a240U;
494} 494}
495static inline u32 pwr_falcon_mmu_phys_sec_r(void) 495static inline u32 pwr_falcon_mmu_phys_sec_r(void)
496{ 496{
497 return 0x00100ce4; 497 return 0x00100ce4U;
498} 498}
499static inline u32 pwr_falcon_bootvec_r(void) 499static inline u32 pwr_falcon_bootvec_r(void)
500{ 500{
501 return 0x0010a104; 501 return 0x0010a104U;
502} 502}
503static inline u32 pwr_falcon_bootvec_vec_f(u32 v) 503static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
504{ 504{
505 return (v & 0xffffffff) << 0; 505 return (v & 0xffffffffU) << 0U;
506} 506}
507static inline u32 pwr_falcon_dmactl_r(void) 507static inline u32 pwr_falcon_dmactl_r(void)
508{ 508{
509 return 0x0010a10c; 509 return 0x0010a10cU;
510} 510}
511static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) 511static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
512{ 512{
513 return 0x1 << 1; 513 return 0x1U << 1U;
514} 514}
515static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) 515static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
516{ 516{
517 return 0x1 << 2; 517 return 0x1U << 2U;
518} 518}
519static inline u32 pwr_falcon_hwcfg_r(void) 519static inline u32 pwr_falcon_hwcfg_r(void)
520{ 520{
521 return 0x0010a108; 521 return 0x0010a108U;
522} 522}
523static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) 523static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
524{ 524{
525 return (r >> 0) & 0x1ff; 525 return (r >> 0U) & 0x1ffU;
526} 526}
527static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) 527static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
528{ 528{
529 return (r >> 9) & 0x1ff; 529 return (r >> 9U) & 0x1ffU;
530} 530}
531static inline u32 pwr_falcon_dmatrfbase_r(void) 531static inline u32 pwr_falcon_dmatrfbase_r(void)
532{ 532{
533 return 0x0010a110; 533 return 0x0010a110U;
534} 534}
535static inline u32 pwr_falcon_dmatrfbase1_r(void) 535static inline u32 pwr_falcon_dmatrfbase1_r(void)
536{ 536{
537 return 0x0010a128; 537 return 0x0010a128U;
538} 538}
539static inline u32 pwr_falcon_dmatrfmoffs_r(void) 539static inline u32 pwr_falcon_dmatrfmoffs_r(void)
540{ 540{
541 return 0x0010a114; 541 return 0x0010a114U;
542} 542}
543static inline u32 pwr_falcon_dmatrfcmd_r(void) 543static inline u32 pwr_falcon_dmatrfcmd_r(void)
544{ 544{
545 return 0x0010a118; 545 return 0x0010a118U;
546} 546}
547static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) 547static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
548{ 548{
549 return (v & 0x1) << 4; 549 return (v & 0x1U) << 4U;
550} 550}
551static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) 551static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
552{ 552{
553 return (v & 0x1) << 5; 553 return (v & 0x1U) << 5U;
554} 554}
555static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) 555static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
556{ 556{
557 return (v & 0x7) << 8; 557 return (v & 0x7U) << 8U;
558} 558}
559static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) 559static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
560{ 560{
561 return (v & 0x7) << 12; 561 return (v & 0x7U) << 12U;
562} 562}
563static inline u32 pwr_falcon_dmatrffboffs_r(void) 563static inline u32 pwr_falcon_dmatrffboffs_r(void)
564{ 564{
565 return 0x0010a11c; 565 return 0x0010a11cU;
566} 566}
567static inline u32 pwr_falcon_exterraddr_r(void) 567static inline u32 pwr_falcon_exterraddr_r(void)
568{ 568{
569 return 0x0010a168; 569 return 0x0010a168U;
570} 570}
571static inline u32 pwr_falcon_exterrstat_r(void) 571static inline u32 pwr_falcon_exterrstat_r(void)
572{ 572{
573 return 0x0010a16c; 573 return 0x0010a16cU;
574} 574}
575static inline u32 pwr_falcon_exterrstat_valid_m(void) 575static inline u32 pwr_falcon_exterrstat_valid_m(void)
576{ 576{
577 return 0x1 << 31; 577 return 0x1U << 31U;
578} 578}
579static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) 579static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
580{ 580{
581 return (r >> 31) & 0x1; 581 return (r >> 31U) & 0x1U;
582} 582}
583static inline u32 pwr_falcon_exterrstat_valid_true_v(void) 583static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
584{ 584{
585 return 0x00000001; 585 return 0x00000001U;
586} 586}
587static inline u32 pwr_pmu_falcon_icd_cmd_r(void) 587static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
588{ 588{
589 return 0x0010a200; 589 return 0x0010a200U;
590} 590}
591static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) 591static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
592{ 592{
593 return 4; 593 return 4U;
594} 594}
595static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) 595static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
596{ 596{
597 return (v & 0xf) << 0; 597 return (v & 0xfU) << 0U;
598} 598}
599static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) 599static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
600{ 600{
601 return 0xf << 0; 601 return 0xfU << 0U;
602} 602}
603static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) 603static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
604{ 604{
605 return (r >> 0) & 0xf; 605 return (r >> 0U) & 0xfU;
606} 606}
607static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) 607static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
608{ 608{
609 return 0x8; 609 return 0x8U;
610} 610}
611static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) 611static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
612{ 612{
613 return 0xe; 613 return 0xeU;
614} 614}
615static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) 615static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
616{ 616{
617 return (v & 0x1f) << 8; 617 return (v & 0x1fU) << 8U;
618} 618}
619static inline u32 pwr_pmu_falcon_icd_rdata_r(void) 619static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
620{ 620{
621 return 0x0010a20c; 621 return 0x0010a20cU;
622} 622}
623static inline u32 pwr_falcon_dmemc_r(u32 i) 623static inline u32 pwr_falcon_dmemc_r(u32 i)
624{ 624{
625 return 0x0010a1c0 + i*8; 625 return 0x0010a1c0U + i*8U;
626} 626}
627static inline u32 pwr_falcon_dmemc_offs_f(u32 v) 627static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
628{ 628{
629 return (v & 0x3f) << 2; 629 return (v & 0x3fU) << 2U;
630} 630}
631static inline u32 pwr_falcon_dmemc_offs_m(void) 631static inline u32 pwr_falcon_dmemc_offs_m(void)
632{ 632{
633 return 0x3f << 2; 633 return 0x3fU << 2U;
634} 634}
635static inline u32 pwr_falcon_dmemc_blk_f(u32 v) 635static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
636{ 636{
637 return (v & 0xff) << 8; 637 return (v & 0xffU) << 8U;
638} 638}
639static inline u32 pwr_falcon_dmemc_blk_m(void) 639static inline u32 pwr_falcon_dmemc_blk_m(void)
640{ 640{
641 return 0xff << 8; 641 return 0xffU << 8U;
642} 642}
643static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) 643static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
644{ 644{
645 return (v & 0x1) << 24; 645 return (v & 0x1U) << 24U;
646} 646}
647static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) 647static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
648{ 648{
649 return (v & 0x1) << 25; 649 return (v & 0x1U) << 25U;
650} 650}
651static inline u32 pwr_falcon_dmemd_r(u32 i) 651static inline u32 pwr_falcon_dmemd_r(u32 i)
652{ 652{
653 return 0x0010a1c4 + i*8; 653 return 0x0010a1c4U + i*8U;
654} 654}
655static inline u32 pwr_pmu_new_instblk_r(void) 655static inline u32 pwr_pmu_new_instblk_r(void)
656{ 656{
657 return 0x0010a480; 657 return 0x0010a480U;
658} 658}
659static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) 659static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
660{ 660{
661 return (v & 0xfffffff) << 0; 661 return (v & 0xfffffffU) << 0U;
662} 662}
663static inline u32 pwr_pmu_new_instblk_target_fb_f(void) 663static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
664{ 664{
665 return 0x0; 665 return 0x0U;
666} 666}
667static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) 667static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
668{ 668{
669 return 0x20000000; 669 return 0x20000000U;
670} 670}
671static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void) 671static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
672{ 672{
673 return 0x30000000; 673 return 0x30000000U;
674} 674}
675static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) 675static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
676{ 676{
677 return (v & 0x1) << 30; 677 return (v & 0x1U) << 30U;
678} 678}
679static inline u32 pwr_pmu_mutex_id_r(void) 679static inline u32 pwr_pmu_mutex_id_r(void)
680{ 680{
681 return 0x0010a488; 681 return 0x0010a488U;
682} 682}
683static inline u32 pwr_pmu_mutex_id_value_v(u32 r) 683static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
684{ 684{
685 return (r >> 0) & 0xff; 685 return (r >> 0U) & 0xffU;
686} 686}
687static inline u32 pwr_pmu_mutex_id_value_init_v(void) 687static inline u32 pwr_pmu_mutex_id_value_init_v(void)
688{ 688{
689 return 0x00000000; 689 return 0x00000000U;
690} 690}
691static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) 691static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
692{ 692{
693 return 0x000000ff; 693 return 0x000000ffU;
694} 694}
695static inline u32 pwr_pmu_mutex_id_release_r(void) 695static inline u32 pwr_pmu_mutex_id_release_r(void)
696{ 696{
697 return 0x0010a48c; 697 return 0x0010a48cU;
698} 698}
699static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) 699static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
700{ 700{
701 return (v & 0xff) << 0; 701 return (v & 0xffU) << 0U;
702} 702}
703static inline u32 pwr_pmu_mutex_id_release_value_m(void) 703static inline u32 pwr_pmu_mutex_id_release_value_m(void)
704{ 704{
705 return 0xff << 0; 705 return 0xffU << 0U;
706} 706}
707static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) 707static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
708{ 708{
709 return 0x00000000; 709 return 0x00000000U;
710} 710}
711static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) 711static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
712{ 712{
713 return 0x0; 713 return 0x0U;
714} 714}
715static inline u32 pwr_pmu_mutex_r(u32 i) 715static inline u32 pwr_pmu_mutex_r(u32 i)
716{ 716{
717 return 0x0010a580 + i*4; 717 return 0x0010a580U + i*4U;
718} 718}
719static inline u32 pwr_pmu_mutex__size_1_v(void) 719static inline u32 pwr_pmu_mutex__size_1_v(void)
720{ 720{
721 return 0x00000010; 721 return 0x00000010U;
722} 722}
723static inline u32 pwr_pmu_mutex_value_f(u32 v) 723static inline u32 pwr_pmu_mutex_value_f(u32 v)
724{ 724{
725 return (v & 0xff) << 0; 725 return (v & 0xffU) << 0U;
726} 726}
727static inline u32 pwr_pmu_mutex_value_v(u32 r) 727static inline u32 pwr_pmu_mutex_value_v(u32 r)
728{ 728{
729 return (r >> 0) & 0xff; 729 return (r >> 0U) & 0xffU;
730} 730}
731static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) 731static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
732{ 732{
733 return 0x0; 733 return 0x0U;
734} 734}
735static inline u32 pwr_pmu_queue_head_r(u32 i) 735static inline u32 pwr_pmu_queue_head_r(u32 i)
736{ 736{
737 return 0x0010a800 + i*4; 737 return 0x0010a800U + i*4U;
738} 738}
739static inline u32 pwr_pmu_queue_head__size_1_v(void) 739static inline u32 pwr_pmu_queue_head__size_1_v(void)
740{ 740{
741 return 0x00000008; 741 return 0x00000008U;
742} 742}
743static inline u32 pwr_pmu_queue_head_address_f(u32 v) 743static inline u32 pwr_pmu_queue_head_address_f(u32 v)
744{ 744{
745 return (v & 0xffffffff) << 0; 745 return (v & 0xffffffffU) << 0U;
746} 746}
747static inline u32 pwr_pmu_queue_head_address_v(u32 r) 747static inline u32 pwr_pmu_queue_head_address_v(u32 r)
748{ 748{
749 return (r >> 0) & 0xffffffff; 749 return (r >> 0U) & 0xffffffffU;
750} 750}
751static inline u32 pwr_pmu_queue_tail_r(u32 i) 751static inline u32 pwr_pmu_queue_tail_r(u32 i)
752{ 752{
753 return 0x0010a820 + i*4; 753 return 0x0010a820U + i*4U;
754} 754}
755static inline u32 pwr_pmu_queue_tail__size_1_v(void) 755static inline u32 pwr_pmu_queue_tail__size_1_v(void)
756{ 756{
757 return 0x00000008; 757 return 0x00000008U;
758} 758}
759static inline u32 pwr_pmu_queue_tail_address_f(u32 v) 759static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
760{ 760{
761 return (v & 0xffffffff) << 0; 761 return (v & 0xffffffffU) << 0U;
762} 762}
763static inline u32 pwr_pmu_queue_tail_address_v(u32 r) 763static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
764{ 764{
765 return (r >> 0) & 0xffffffff; 765 return (r >> 0U) & 0xffffffffU;
766} 766}
767static inline u32 pwr_pmu_msgq_head_r(void) 767static inline u32 pwr_pmu_msgq_head_r(void)
768{ 768{
769 return 0x0010a4c8; 769 return 0x0010a4c8U;
770} 770}
771static inline u32 pwr_pmu_msgq_head_val_f(u32 v) 771static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
772{ 772{
773 return (v & 0xffffffff) << 0; 773 return (v & 0xffffffffU) << 0U;
774} 774}
775static inline u32 pwr_pmu_msgq_head_val_v(u32 r) 775static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
776{ 776{
777 return (r >> 0) & 0xffffffff; 777 return (r >> 0U) & 0xffffffffU;
778} 778}
779static inline u32 pwr_pmu_msgq_tail_r(void) 779static inline u32 pwr_pmu_msgq_tail_r(void)
780{ 780{
781 return 0x0010a4cc; 781 return 0x0010a4ccU;
782} 782}
783static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) 783static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
784{ 784{
785 return (v & 0xffffffff) << 0; 785 return (v & 0xffffffffU) << 0U;
786} 786}
787static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) 787static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
788{ 788{
789 return (r >> 0) & 0xffffffff; 789 return (r >> 0U) & 0xffffffffU;
790} 790}
791static inline u32 pwr_pmu_idle_mask_r(u32 i) 791static inline u32 pwr_pmu_idle_mask_r(u32 i)
792{ 792{
793 return 0x0010a504 + i*16; 793 return 0x0010a504U + i*16U;
794} 794}
795static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) 795static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
796{ 796{
797 return 0x1; 797 return 0x1U;
798} 798}
799static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) 799static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
800{ 800{
801 return 0x200000; 801 return 0x200000U;
802} 802}
803static inline u32 pwr_pmu_idle_count_r(u32 i) 803static inline u32 pwr_pmu_idle_count_r(u32 i)
804{ 804{
805 return 0x0010a508 + i*16; 805 return 0x0010a508U + i*16U;
806} 806}
807static inline u32 pwr_pmu_idle_count_value_f(u32 v) 807static inline u32 pwr_pmu_idle_count_value_f(u32 v)
808{ 808{
809 return (v & 0x7fffffff) << 0; 809 return (v & 0x7fffffffU) << 0U;
810} 810}
811static inline u32 pwr_pmu_idle_count_value_v(u32 r) 811static inline u32 pwr_pmu_idle_count_value_v(u32 r)
812{ 812{
813 return (r >> 0) & 0x7fffffff; 813 return (r >> 0U) & 0x7fffffffU;
814} 814}
815static inline u32 pwr_pmu_idle_count_reset_f(u32 v) 815static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
816{ 816{
817 return (v & 0x1) << 31; 817 return (v & 0x1U) << 31U;
818} 818}
819static inline u32 pwr_pmu_idle_ctrl_r(u32 i) 819static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
820{ 820{
821 return 0x0010a50c + i*16; 821 return 0x0010a50cU + i*16U;
822} 822}
823static inline u32 pwr_pmu_idle_ctrl_value_m(void) 823static inline u32 pwr_pmu_idle_ctrl_value_m(void)
824{ 824{
825 return 0x3 << 0; 825 return 0x3U << 0U;
826} 826}
827static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) 827static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
828{ 828{
829 return 0x2; 829 return 0x2U;
830} 830}
831static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) 831static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
832{ 832{
833 return 0x3; 833 return 0x3U;
834} 834}
835static inline u32 pwr_pmu_idle_ctrl_filter_m(void) 835static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
836{ 836{
837 return 0x1 << 2; 837 return 0x1U << 2U;
838} 838}
839static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) 839static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
840{ 840{
841 return 0x0; 841 return 0x0U;
842} 842}
843static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) 843static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
844{ 844{
845 return 0x0010a9f0 + i*8; 845 return 0x0010a9f0U + i*8U;
846} 846}
847static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) 847static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
848{ 848{
849 return 0x0010a9f4 + i*8; 849 return 0x0010a9f4U + i*8U;
850} 850}
851static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) 851static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
852{ 852{
853 return 0x0010aa30 + i*8; 853 return 0x0010aa30U + i*8U;
854} 854}
855static inline u32 pwr_pmu_debug_r(u32 i) 855static inline u32 pwr_pmu_debug_r(u32 i)
856{ 856{
857 return 0x0010a5c0 + i*4; 857 return 0x0010a5c0U + i*4U;
858} 858}
859static inline u32 pwr_pmu_debug__size_1_v(void) 859static inline u32 pwr_pmu_debug__size_1_v(void)
860{ 860{
861 return 0x00000004; 861 return 0x00000004U;
862} 862}
863static inline u32 pwr_pmu_mailbox_r(u32 i) 863static inline u32 pwr_pmu_mailbox_r(u32 i)
864{ 864{
865 return 0x0010a450 + i*4; 865 return 0x0010a450U + i*4U;
866} 866}
867static inline u32 pwr_pmu_mailbox__size_1_v(void) 867static inline u32 pwr_pmu_mailbox__size_1_v(void)
868{ 868{
869 return 0x0000000c; 869 return 0x0000000cU;
870} 870}
871static inline u32 pwr_pmu_bar0_addr_r(void) 871static inline u32 pwr_pmu_bar0_addr_r(void)
872{ 872{
873 return 0x0010a7a0; 873 return 0x0010a7a0U;
874} 874}
875static inline u32 pwr_pmu_bar0_data_r(void) 875static inline u32 pwr_pmu_bar0_data_r(void)
876{ 876{
877 return 0x0010a7a4; 877 return 0x0010a7a4U;
878} 878}
879static inline u32 pwr_pmu_bar0_ctl_r(void) 879static inline u32 pwr_pmu_bar0_ctl_r(void)
880{ 880{
881 return 0x0010a7ac; 881 return 0x0010a7acU;
882} 882}
883static inline u32 pwr_pmu_bar0_timeout_r(void) 883static inline u32 pwr_pmu_bar0_timeout_r(void)
884{ 884{
885 return 0x0010a7a8; 885 return 0x0010a7a8U;
886} 886}
887static inline u32 pwr_pmu_bar0_fecs_error_r(void) 887static inline u32 pwr_pmu_bar0_fecs_error_r(void)
888{ 888{
889 return 0x0010a988; 889 return 0x0010a988U;
890} 890}
891static inline u32 pwr_pmu_bar0_error_status_r(void) 891static inline u32 pwr_pmu_bar0_error_status_r(void)
892{ 892{
893 return 0x0010a7b0; 893 return 0x0010a7b0U;
894} 894}
895static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) 895static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
896{ 896{
897 return 0x0010a6c0 + i*4; 897 return 0x0010a6c0U + i*4U;
898} 898}
899static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) 899static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
900{ 900{
901 return 0x0010a6e8 + i*4; 901 return 0x0010a6e8U + i*4U;
902} 902}
903static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) 903static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
904{ 904{
905 return 0x0010a710 + i*4; 905 return 0x0010a710U + i*4U;
906} 906}
907static inline u32 pwr_pmu_pg_intren_r(u32 i) 907static inline u32 pwr_pmu_pg_intren_r(u32 i)
908{ 908{
909 return 0x0010a760 + i*4; 909 return 0x0010a760U + i*4U;
910} 910}
911static inline u32 pwr_fbif_transcfg_r(u32 i) 911static inline u32 pwr_fbif_transcfg_r(u32 i)
912{ 912{
913 return 0x0010ae00 + i*4; 913 return 0x0010ae00U + i*4U;
914} 914}
915static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) 915static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
916{ 916{
917 return 0x0; 917 return 0x0U;
918} 918}
919static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) 919static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
920{ 920{
921 return 0x1; 921 return 0x1U;
922} 922}
923static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) 923static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
924{ 924{
925 return 0x2; 925 return 0x2U;
926} 926}
927static inline u32 pwr_fbif_transcfg_mem_type_s(void) 927static inline u32 pwr_fbif_transcfg_mem_type_s(void)
928{ 928{
929 return 1; 929 return 1U;
930} 930}
931static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) 931static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
932{ 932{
933 return (v & 0x1) << 2; 933 return (v & 0x1U) << 2U;
934} 934}
935static inline u32 pwr_fbif_transcfg_mem_type_m(void) 935static inline u32 pwr_fbif_transcfg_mem_type_m(void)
936{ 936{
937 return 0x1 << 2; 937 return 0x1U << 2U;
938} 938}
939static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) 939static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
940{ 940{
941 return (r >> 2) & 0x1; 941 return (r >> 2U) & 0x1U;
942} 942}
943static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) 943static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
944{ 944{
945 return 0x0; 945 return 0x0U;
946} 946}
947static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) 947static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
948{ 948{
949 return 0x4; 949 return 0x4U;
950} 950}
951#endif 951#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h
index fe8bcd6b..1191e580 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ram_gv11b.h
@@ -58,619 +58,619 @@
58 58
59static inline u32 ram_in_ramfc_s(void) 59static inline u32 ram_in_ramfc_s(void)
60{ 60{
61 return 4096; 61 return 4096U;
62} 62}
63static inline u32 ram_in_ramfc_w(void) 63static inline u32 ram_in_ramfc_w(void)
64{ 64{
65 return 0; 65 return 0U;
66} 66}
67static inline u32 ram_in_page_dir_base_target_f(u32 v) 67static inline u32 ram_in_page_dir_base_target_f(u32 v)
68{ 68{
69 return (v & 0x3) << 0; 69 return (v & 0x3U) << 0U;
70} 70}
71static inline u32 ram_in_page_dir_base_target_w(void) 71static inline u32 ram_in_page_dir_base_target_w(void)
72{ 72{
73 return 128; 73 return 128U;
74} 74}
75static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) 75static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
76{ 76{
77 return 0x0; 77 return 0x0U;
78} 78}
79static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void) 79static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
80{ 80{
81 return 0x2; 81 return 0x2U;
82} 82}
83static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void) 83static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
84{ 84{
85 return 0x3; 85 return 0x3U;
86} 86}
87static inline u32 ram_in_page_dir_base_vol_w(void) 87static inline u32 ram_in_page_dir_base_vol_w(void)
88{ 88{
89 return 128; 89 return 128U;
90} 90}
91static inline u32 ram_in_page_dir_base_vol_true_f(void) 91static inline u32 ram_in_page_dir_base_vol_true_f(void)
92{ 92{
93 return 0x4; 93 return 0x4U;
94} 94}
95static inline u32 ram_in_page_dir_base_vol_false_f(void) 95static inline u32 ram_in_page_dir_base_vol_false_f(void)
96{ 96{
97 return 0x0; 97 return 0x0U;
98} 98}
99static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) 99static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v)
100{ 100{
101 return (v & 0x1) << 4; 101 return (v & 0x1U) << 4U;
102} 102}
103static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) 103static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void)
104{ 104{
105 return 0x1 << 4; 105 return 0x1U << 4U;
106} 106}
107static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) 107static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void)
108{ 108{
109 return 128; 109 return 128U;
110} 110}
111static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) 111static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void)
112{ 112{
113 return 0x10; 113 return 0x10U;
114} 114}
115static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) 115static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v)
116{ 116{
117 return (v & 0x1) << 5; 117 return (v & 0x1U) << 5U;
118} 118}
119static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) 119static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void)
120{ 120{
121 return 0x1 << 5; 121 return 0x1U << 5U;
122} 122}
123static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) 123static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void)
124{ 124{
125 return 128; 125 return 128U;
126} 126}
127static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) 127static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void)
128{ 128{
129 return 0x20; 129 return 0x20U;
130} 130}
131static inline u32 ram_in_big_page_size_f(u32 v) 131static inline u32 ram_in_big_page_size_f(u32 v)
132{ 132{
133 return (v & 0x1) << 11; 133 return (v & 0x1U) << 11U;
134} 134}
135static inline u32 ram_in_big_page_size_m(void) 135static inline u32 ram_in_big_page_size_m(void)
136{ 136{
137 return 0x1 << 11; 137 return 0x1U << 11U;
138} 138}
139static inline u32 ram_in_big_page_size_w(void) 139static inline u32 ram_in_big_page_size_w(void)
140{ 140{
141 return 128; 141 return 128U;
142} 142}
143static inline u32 ram_in_big_page_size_128kb_f(void) 143static inline u32 ram_in_big_page_size_128kb_f(void)
144{ 144{
145 return 0x0; 145 return 0x0U;
146} 146}
147static inline u32 ram_in_big_page_size_64kb_f(void) 147static inline u32 ram_in_big_page_size_64kb_f(void)
148{ 148{
149 return 0x800; 149 return 0x800U;
150} 150}
151static inline u32 ram_in_page_dir_base_lo_f(u32 v) 151static inline u32 ram_in_page_dir_base_lo_f(u32 v)
152{ 152{
153 return (v & 0xfffff) << 12; 153 return (v & 0xfffffU) << 12U;
154} 154}
155static inline u32 ram_in_page_dir_base_lo_w(void) 155static inline u32 ram_in_page_dir_base_lo_w(void)
156{ 156{
157 return 128; 157 return 128U;
158} 158}
159static inline u32 ram_in_page_dir_base_hi_f(u32 v) 159static inline u32 ram_in_page_dir_base_hi_f(u32 v)
160{ 160{
161 return (v & 0xffffffff) << 0; 161 return (v & 0xffffffffU) << 0U;
162} 162}
163static inline u32 ram_in_page_dir_base_hi_w(void) 163static inline u32 ram_in_page_dir_base_hi_w(void)
164{ 164{
165 return 129; 165 return 129U;
166} 166}
167static inline u32 ram_in_engine_cs_w(void) 167static inline u32 ram_in_engine_cs_w(void)
168{ 168{
169 return 132; 169 return 132U;
170} 170}
171static inline u32 ram_in_engine_cs_wfi_v(void) 171static inline u32 ram_in_engine_cs_wfi_v(void)
172{ 172{
173 return 0x00000000; 173 return 0x00000000U;
174} 174}
175static inline u32 ram_in_engine_cs_wfi_f(void) 175static inline u32 ram_in_engine_cs_wfi_f(void)
176{ 176{
177 return 0x0; 177 return 0x0U;
178} 178}
179static inline u32 ram_in_engine_cs_fg_v(void) 179static inline u32 ram_in_engine_cs_fg_v(void)
180{ 180{
181 return 0x00000001; 181 return 0x00000001U;
182} 182}
183static inline u32 ram_in_engine_cs_fg_f(void) 183static inline u32 ram_in_engine_cs_fg_f(void)
184{ 184{
185 return 0x8; 185 return 0x8U;
186} 186}
187static inline u32 ram_in_engine_wfi_mode_f(u32 v) 187static inline u32 ram_in_engine_wfi_mode_f(u32 v)
188{ 188{
189 return (v & 0x1) << 2; 189 return (v & 0x1U) << 2U;
190} 190}
191static inline u32 ram_in_engine_wfi_mode_w(void) 191static inline u32 ram_in_engine_wfi_mode_w(void)
192{ 192{
193 return 132; 193 return 132U;
194} 194}
195static inline u32 ram_in_engine_wfi_mode_physical_v(void) 195static inline u32 ram_in_engine_wfi_mode_physical_v(void)
196{ 196{
197 return 0x00000000; 197 return 0x00000000U;
198} 198}
199static inline u32 ram_in_engine_wfi_mode_virtual_v(void) 199static inline u32 ram_in_engine_wfi_mode_virtual_v(void)
200{ 200{
201 return 0x00000001; 201 return 0x00000001U;
202} 202}
203static inline u32 ram_in_engine_wfi_target_f(u32 v) 203static inline u32 ram_in_engine_wfi_target_f(u32 v)
204{ 204{
205 return (v & 0x3) << 0; 205 return (v & 0x3U) << 0U;
206} 206}
207static inline u32 ram_in_engine_wfi_target_w(void) 207static inline u32 ram_in_engine_wfi_target_w(void)
208{ 208{
209 return 132; 209 return 132U;
210} 210}
211static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) 211static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void)
212{ 212{
213 return 0x00000002; 213 return 0x00000002U;
214} 214}
215static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void) 215static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void)
216{ 216{
217 return 0x00000003; 217 return 0x00000003U;
218} 218}
219static inline u32 ram_in_engine_wfi_target_local_mem_v(void) 219static inline u32 ram_in_engine_wfi_target_local_mem_v(void)
220{ 220{
221 return 0x00000000; 221 return 0x00000000U;
222} 222}
223static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) 223static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v)
224{ 224{
225 return (v & 0xfffff) << 12; 225 return (v & 0xfffffU) << 12U;
226} 226}
227static inline u32 ram_in_engine_wfi_ptr_lo_w(void) 227static inline u32 ram_in_engine_wfi_ptr_lo_w(void)
228{ 228{
229 return 132; 229 return 132U;
230} 230}
231static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) 231static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v)
232{ 232{
233 return (v & 0xff) << 0; 233 return (v & 0xffU) << 0U;
234} 234}
235static inline u32 ram_in_engine_wfi_ptr_hi_w(void) 235static inline u32 ram_in_engine_wfi_ptr_hi_w(void)
236{ 236{
237 return 133; 237 return 133U;
238} 238}
239static inline u32 ram_in_engine_wfi_veid_f(u32 v) 239static inline u32 ram_in_engine_wfi_veid_f(u32 v)
240{ 240{
241 return (v & 0x3f) << 0; 241 return (v & 0x3fU) << 0U;
242} 242}
243static inline u32 ram_in_engine_wfi_veid_w(void) 243static inline u32 ram_in_engine_wfi_veid_w(void)
244{ 244{
245 return 134; 245 return 134U;
246} 246}
247static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) 247static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v)
248{ 248{
249 return (v & 0xffffffff) << 0; 249 return (v & 0xffffffffU) << 0U;
250} 250}
251static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) 251static inline u32 ram_in_eng_method_buffer_addr_lo_w(void)
252{ 252{
253 return 136; 253 return 136U;
254} 254}
255static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) 255static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v)
256{ 256{
257 return (v & 0x1ffff) << 0; 257 return (v & 0x1ffffU) << 0U;
258} 258}
259static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) 259static inline u32 ram_in_eng_method_buffer_addr_hi_w(void)
260{ 260{
261 return 137; 261 return 137U;
262} 262}
263static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) 263static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i)
264{ 264{
265 return (v & 0x3) << (0 + i*0); 265 return (v & 0x3U) << (0U + i*0U);
266} 266}
267static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) 267static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void)
268{ 268{
269 return 0x00000040; 269 return 0x00000040U;
270} 270}
271static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) 271static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void)
272{ 272{
273 return 0x00000000; 273 return 0x00000000U;
274} 274}
275static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) 275static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void)
276{ 276{
277 return 0x00000001; 277 return 0x00000001U;
278} 278}
279static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) 279static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void)
280{ 280{
281 return 0x00000002; 281 return 0x00000002U;
282} 282}
283static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) 283static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void)
284{ 284{
285 return 0x00000003; 285 return 0x00000003U;
286} 286}
287static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) 287static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i)
288{ 288{
289 return (v & 0x1) << (2 + i*0); 289 return (v & 0x1U) << (2U + i*0U);
290} 290}
291static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) 291static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void)
292{ 292{
293 return 0x00000040; 293 return 0x00000040U;
294} 294}
295static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) 295static inline u32 ram_in_sc_page_dir_base_vol_true_v(void)
296{ 296{
297 return 0x00000001; 297 return 0x00000001U;
298} 298}
299static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) 299static inline u32 ram_in_sc_page_dir_base_vol_false_v(void)
300{ 300{
301 return 0x00000000; 301 return 0x00000000U;
302} 302}
303static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) 303static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i)
304{ 304{
305 return (v & 0x1) << (4 + i*0); 305 return (v & 0x1U) << (4U + i*0U);
306} 306}
307static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) 307static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void)
308{ 308{
309 return 0x00000040; 309 return 0x00000040U;
310} 310}
311static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) 311static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void)
312{ 312{
313 return 0x00000001; 313 return 0x00000001U;
314} 314}
315static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) 315static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void)
316{ 316{
317 return 0x00000000; 317 return 0x00000000U;
318} 318}
319static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) 319static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i)
320{ 320{
321 return (v & 0x1) << (5 + i*0); 321 return (v & 0x1U) << (5U + i*0U);
322} 322}
323static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) 323static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void)
324{ 324{
325 return 0x00000040; 325 return 0x00000040U;
326} 326}
327static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) 327static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void)
328{ 328{
329 return 0x00000001; 329 return 0x00000001U;
330} 330}
331static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) 331static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void)
332{ 332{
333 return 0x00000000; 333 return 0x00000000U;
334} 334}
335static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) 335static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i)
336{ 336{
337 return (v & 0x1) << (10 + i*0); 337 return (v & 0x1U) << (10U + i*0U);
338} 338}
339static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) 339static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void)
340{ 340{
341 return 0x00000040; 341 return 0x00000040U;
342} 342}
343static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) 343static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void)
344{ 344{
345 return 0x00000000; 345 return 0x00000000U;
346} 346}
347static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) 347static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void)
348{ 348{
349 return 0x00000001; 349 return 0x00000001U;
350} 350}
351static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) 351static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i)
352{ 352{
353 return (v & 0x1) << (11 + i*0); 353 return (v & 0x1U) << (11U + i*0U);
354} 354}
355static inline u32 ram_in_sc_big_page_size__size_1_v(void) 355static inline u32 ram_in_sc_big_page_size__size_1_v(void)
356{ 356{
357 return 0x00000040; 357 return 0x00000040U;
358} 358}
359static inline u32 ram_in_sc_big_page_size_64kb_v(void) 359static inline u32 ram_in_sc_big_page_size_64kb_v(void)
360{ 360{
361 return 0x00000001; 361 return 0x00000001U;
362} 362}
363static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) 363static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i)
364{ 364{
365 return (v & 0xfffff) << (12 + i*0); 365 return (v & 0xfffffU) << (12U + i*0U);
366} 366}
367static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) 367static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void)
368{ 368{
369 return 0x00000040; 369 return 0x00000040U;
370} 370}
371static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) 371static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i)
372{ 372{
373 return (v & 0xffffffff) << (0 + i*0); 373 return (v & 0xffffffffU) << (0U + i*0U);
374} 374}
375static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) 375static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void)
376{ 376{
377 return 0x00000040; 377 return 0x00000040U;
378} 378}
379static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) 379static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v)
380{ 380{
381 return (v & 0x3) << 0; 381 return (v & 0x3U) << 0U;
382} 382}
383static inline u32 ram_in_sc_page_dir_base_target_0_w(void) 383static inline u32 ram_in_sc_page_dir_base_target_0_w(void)
384{ 384{
385 return 168; 385 return 168U;
386} 386}
387static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) 387static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v)
388{ 388{
389 return (v & 0x1) << 2; 389 return (v & 0x1U) << 2U;
390} 390}
391static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) 391static inline u32 ram_in_sc_page_dir_base_vol_0_w(void)
392{ 392{
393 return 168; 393 return 168U;
394} 394}
395static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) 395static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v)
396{ 396{
397 return (v & 0x1) << 4; 397 return (v & 0x1U) << 4U;
398} 398}
399static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) 399static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void)
400{ 400{
401 return 168; 401 return 168U;
402} 402}
403static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) 403static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v)
404{ 404{
405 return (v & 0x1) << 5; 405 return (v & 0x1U) << 5U;
406} 406}
407static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) 407static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void)
408{ 408{
409 return 168; 409 return 168U;
410} 410}
411static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) 411static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v)
412{ 412{
413 return (v & 0x1) << 10; 413 return (v & 0x1U) << 10U;
414} 414}
415static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) 415static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void)
416{ 416{
417 return 168; 417 return 168U;
418} 418}
419static inline u32 ram_in_sc_big_page_size_0_f(u32 v) 419static inline u32 ram_in_sc_big_page_size_0_f(u32 v)
420{ 420{
421 return (v & 0x1) << 11; 421 return (v & 0x1U) << 11U;
422} 422}
423static inline u32 ram_in_sc_big_page_size_0_w(void) 423static inline u32 ram_in_sc_big_page_size_0_w(void)
424{ 424{
425 return 168; 425 return 168U;
426} 426}
427static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) 427static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v)
428{ 428{
429 return (v & 0xfffff) << 12; 429 return (v & 0xfffffU) << 12U;
430} 430}
431static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) 431static inline u32 ram_in_sc_page_dir_base_lo_0_w(void)
432{ 432{
433 return 168; 433 return 168U;
434} 434}
435static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) 435static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v)
436{ 436{
437 return (v & 0xffffffff) << 0; 437 return (v & 0xffffffffU) << 0U;
438} 438}
439static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) 439static inline u32 ram_in_sc_page_dir_base_hi_0_w(void)
440{ 440{
441 return 169; 441 return 169U;
442} 442}
443static inline u32 ram_in_base_shift_v(void) 443static inline u32 ram_in_base_shift_v(void)
444{ 444{
445 return 0x0000000c; 445 return 0x0000000cU;
446} 446}
447static inline u32 ram_in_alloc_size_v(void) 447static inline u32 ram_in_alloc_size_v(void)
448{ 448{
449 return 0x00001000; 449 return 0x00001000U;
450} 450}
451static inline u32 ram_fc_size_val_v(void) 451static inline u32 ram_fc_size_val_v(void)
452{ 452{
453 return 0x00000200; 453 return 0x00000200U;
454} 454}
455static inline u32 ram_fc_gp_put_w(void) 455static inline u32 ram_fc_gp_put_w(void)
456{ 456{
457 return 0; 457 return 0U;
458} 458}
459static inline u32 ram_fc_userd_w(void) 459static inline u32 ram_fc_userd_w(void)
460{ 460{
461 return 2; 461 return 2U;
462} 462}
463static inline u32 ram_fc_userd_hi_w(void) 463static inline u32 ram_fc_userd_hi_w(void)
464{ 464{
465 return 3; 465 return 3U;
466} 466}
467static inline u32 ram_fc_signature_w(void) 467static inline u32 ram_fc_signature_w(void)
468{ 468{
469 return 4; 469 return 4U;
470} 470}
471static inline u32 ram_fc_gp_get_w(void) 471static inline u32 ram_fc_gp_get_w(void)
472{ 472{
473 return 5; 473 return 5U;
474} 474}
475static inline u32 ram_fc_pb_get_w(void) 475static inline u32 ram_fc_pb_get_w(void)
476{ 476{
477 return 6; 477 return 6U;
478} 478}
479static inline u32 ram_fc_pb_get_hi_w(void) 479static inline u32 ram_fc_pb_get_hi_w(void)
480{ 480{
481 return 7; 481 return 7U;
482} 482}
483static inline u32 ram_fc_pb_top_level_get_w(void) 483static inline u32 ram_fc_pb_top_level_get_w(void)
484{ 484{
485 return 8; 485 return 8U;
486} 486}
487static inline u32 ram_fc_pb_top_level_get_hi_w(void) 487static inline u32 ram_fc_pb_top_level_get_hi_w(void)
488{ 488{
489 return 9; 489 return 9U;
490} 490}
491static inline u32 ram_fc_acquire_w(void) 491static inline u32 ram_fc_acquire_w(void)
492{ 492{
493 return 12; 493 return 12U;
494} 494}
495static inline u32 ram_fc_sem_addr_hi_w(void) 495static inline u32 ram_fc_sem_addr_hi_w(void)
496{ 496{
497 return 14; 497 return 14U;
498} 498}
499static inline u32 ram_fc_sem_addr_lo_w(void) 499static inline u32 ram_fc_sem_addr_lo_w(void)
500{ 500{
501 return 15; 501 return 15U;
502} 502}
503static inline u32 ram_fc_sem_payload_lo_w(void) 503static inline u32 ram_fc_sem_payload_lo_w(void)
504{ 504{
505 return 16; 505 return 16U;
506} 506}
507static inline u32 ram_fc_sem_payload_hi_w(void) 507static inline u32 ram_fc_sem_payload_hi_w(void)
508{ 508{
509 return 39; 509 return 39U;
510} 510}
511static inline u32 ram_fc_sem_execute_w(void) 511static inline u32 ram_fc_sem_execute_w(void)
512{ 512{
513 return 17; 513 return 17U;
514} 514}
515static inline u32 ram_fc_gp_base_w(void) 515static inline u32 ram_fc_gp_base_w(void)
516{ 516{
517 return 18; 517 return 18U;
518} 518}
519static inline u32 ram_fc_gp_base_hi_w(void) 519static inline u32 ram_fc_gp_base_hi_w(void)
520{ 520{
521 return 19; 521 return 19U;
522} 522}
523static inline u32 ram_fc_gp_fetch_w(void) 523static inline u32 ram_fc_gp_fetch_w(void)
524{ 524{
525 return 20; 525 return 20U;
526} 526}
527static inline u32 ram_fc_pb_fetch_w(void) 527static inline u32 ram_fc_pb_fetch_w(void)
528{ 528{
529 return 21; 529 return 21U;
530} 530}
531static inline u32 ram_fc_pb_fetch_hi_w(void) 531static inline u32 ram_fc_pb_fetch_hi_w(void)
532{ 532{
533 return 22; 533 return 22U;
534} 534}
535static inline u32 ram_fc_pb_put_w(void) 535static inline u32 ram_fc_pb_put_w(void)
536{ 536{
537 return 23; 537 return 23U;
538} 538}
539static inline u32 ram_fc_pb_put_hi_w(void) 539static inline u32 ram_fc_pb_put_hi_w(void)
540{ 540{
541 return 24; 541 return 24U;
542} 542}
543static inline u32 ram_fc_pb_header_w(void) 543static inline u32 ram_fc_pb_header_w(void)
544{ 544{
545 return 33; 545 return 33U;
546} 546}
547static inline u32 ram_fc_pb_count_w(void) 547static inline u32 ram_fc_pb_count_w(void)
548{ 548{
549 return 34; 549 return 34U;
550} 550}
551static inline u32 ram_fc_subdevice_w(void) 551static inline u32 ram_fc_subdevice_w(void)
552{ 552{
553 return 37; 553 return 37U;
554} 554}
555static inline u32 ram_fc_target_w(void) 555static inline u32 ram_fc_target_w(void)
556{ 556{
557 return 43; 557 return 43U;
558} 558}
559static inline u32 ram_fc_hce_ctrl_w(void) 559static inline u32 ram_fc_hce_ctrl_w(void)
560{ 560{
561 return 57; 561 return 57U;
562} 562}
563static inline u32 ram_fc_chid_w(void) 563static inline u32 ram_fc_chid_w(void)
564{ 564{
565 return 58; 565 return 58U;
566} 566}
567static inline u32 ram_fc_chid_id_f(u32 v) 567static inline u32 ram_fc_chid_id_f(u32 v)
568{ 568{
569 return (v & 0xfff) << 0; 569 return (v & 0xfffU) << 0U;
570} 570}
571static inline u32 ram_fc_chid_id_w(void) 571static inline u32 ram_fc_chid_id_w(void)
572{ 572{
573 return 0; 573 return 0U;
574} 574}
575static inline u32 ram_fc_config_w(void) 575static inline u32 ram_fc_config_w(void)
576{ 576{
577 return 61; 577 return 61U;
578} 578}
579static inline u32 ram_fc_runlist_timeslice_w(void) 579static inline u32 ram_fc_runlist_timeslice_w(void)
580{ 580{
581 return 62; 581 return 62U;
582} 582}
583static inline u32 ram_fc_set_channel_info_w(void) 583static inline u32 ram_fc_set_channel_info_w(void)
584{ 584{
585 return 63; 585 return 63U;
586} 586}
587static inline u32 ram_userd_base_shift_v(void) 587static inline u32 ram_userd_base_shift_v(void)
588{ 588{
589 return 0x00000009; 589 return 0x00000009U;
590} 590}
591static inline u32 ram_userd_chan_size_v(void) 591static inline u32 ram_userd_chan_size_v(void)
592{ 592{
593 return 0x00000200; 593 return 0x00000200U;
594} 594}
595static inline u32 ram_userd_put_w(void) 595static inline u32 ram_userd_put_w(void)
596{ 596{
597 return 16; 597 return 16U;
598} 598}
599static inline u32 ram_userd_get_w(void) 599static inline u32 ram_userd_get_w(void)
600{ 600{
601 return 17; 601 return 17U;
602} 602}
603static inline u32 ram_userd_ref_w(void) 603static inline u32 ram_userd_ref_w(void)
604{ 604{
605 return 18; 605 return 18U;
606} 606}
607static inline u32 ram_userd_put_hi_w(void) 607static inline u32 ram_userd_put_hi_w(void)
608{ 608{
609 return 19; 609 return 19U;
610} 610}
611static inline u32 ram_userd_ref_threshold_w(void) 611static inline u32 ram_userd_ref_threshold_w(void)
612{ 612{
613 return 20; 613 return 20U;
614} 614}
615static inline u32 ram_userd_top_level_get_w(void) 615static inline u32 ram_userd_top_level_get_w(void)
616{ 616{
617 return 22; 617 return 22U;
618} 618}
619static inline u32 ram_userd_top_level_get_hi_w(void) 619static inline u32 ram_userd_top_level_get_hi_w(void)
620{ 620{
621 return 23; 621 return 23U;
622} 622}
623static inline u32 ram_userd_get_hi_w(void) 623static inline u32 ram_userd_get_hi_w(void)
624{ 624{
625 return 24; 625 return 24U;
626} 626}
627static inline u32 ram_userd_gp_get_w(void) 627static inline u32 ram_userd_gp_get_w(void)
628{ 628{
629 return 34; 629 return 34U;
630} 630}
631static inline u32 ram_userd_gp_put_w(void) 631static inline u32 ram_userd_gp_put_w(void)
632{ 632{
633 return 35; 633 return 35U;
634} 634}
635static inline u32 ram_userd_gp_top_level_get_w(void) 635static inline u32 ram_userd_gp_top_level_get_w(void)
636{ 636{
637 return 22; 637 return 22U;
638} 638}
639static inline u32 ram_userd_gp_top_level_get_hi_w(void) 639static inline u32 ram_userd_gp_top_level_get_hi_w(void)
640{ 640{
641 return 23; 641 return 23U;
642} 642}
643static inline u32 ram_rl_entry_size_v(void) 643static inline u32 ram_rl_entry_size_v(void)
644{ 644{
645 return 0x00000010; 645 return 0x00000010U;
646} 646}
647static inline u32 ram_rl_entry_type_f(u32 v) 647static inline u32 ram_rl_entry_type_f(u32 v)
648{ 648{
649 return (v & 0x1) << 0; 649 return (v & 0x1U) << 0U;
650} 650}
651static inline u32 ram_rl_entry_type_channel_v(void) 651static inline u32 ram_rl_entry_type_channel_v(void)
652{ 652{
653 return 0x00000000; 653 return 0x00000000U;
654} 654}
655static inline u32 ram_rl_entry_type_tsg_v(void) 655static inline u32 ram_rl_entry_type_tsg_v(void)
656{ 656{
657 return 0x00000001; 657 return 0x00000001U;
658} 658}
659static inline u32 ram_rl_entry_id_f(u32 v) 659static inline u32 ram_rl_entry_id_f(u32 v)
660{ 660{
661 return (v & 0xfff) << 0; 661 return (v & 0xfffU) << 0U;
662} 662}
663static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) 663static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v)
664{ 664{
665 return (v & 0x1) << 1; 665 return (v & 0x1U) << 1U;
666} 666}
667static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) 667static inline u32 ram_rl_entry_chan_inst_target_f(u32 v)
668{ 668{
669 return (v & 0x3) << 4; 669 return (v & 0x3U) << 4U;
670} 670}
671static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) 671static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void)
672{ 672{
673 return 0x00000003; 673 return 0x00000003U;
674} 674}
675static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void) 675static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void)
676{ 676{
@@ -682,94 +682,94 @@ static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void)
682} 682}
683static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) 683static inline u32 ram_rl_entry_chan_userd_target_f(u32 v)
684{ 684{
685 return (v & 0x3) << 6; 685 return (v & 0x3U) << 6U;
686} 686}
687static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) 687static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void)
688{ 688{
689 return 0x00000000; 689 return 0x00000000U;
690} 690}
691static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) 691static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void)
692{ 692{
693 return 0x00000001; 693 return 0x00000001U;
694} 694}
695static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) 695static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void)
696{ 696{
697 return 0x00000002; 697 return 0x00000002U;
698} 698}
699static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) 699static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void)
700{ 700{
701 return 0x00000003; 701 return 0x00000003U;
702} 702}
703static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) 703static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v)
704{ 704{
705 return (v & 0xffffff) << 8; 705 return (v & 0xffffffU) << 8U;
706} 706}
707static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) 707static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v)
708{ 708{
709 return (v & 0xffffffff) << 0; 709 return (v & 0xffffffffU) << 0U;
710} 710}
711static inline u32 ram_rl_entry_chid_f(u32 v) 711static inline u32 ram_rl_entry_chid_f(u32 v)
712{ 712{
713 return (v & 0xfff) << 0; 713 return (v & 0xfffU) << 0U;
714} 714}
715static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) 715static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v)
716{ 716{
717 return (v & 0xfffff) << 12; 717 return (v & 0xfffffU) << 12U;
718} 718}
719static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) 719static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v)
720{ 720{
721 return (v & 0xffffffff) << 0; 721 return (v & 0xffffffffU) << 0U;
722} 722}
723static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) 723static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v)
724{ 724{
725 return (v & 0xf) << 16; 725 return (v & 0xfU) << 16U;
726} 726}
727static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) 727static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void)
728{ 728{
729 return 0x00000003; 729 return 0x00000003U;
730} 730}
731static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) 731static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v)
732{ 732{
733 return (v & 0xff) << 24; 733 return (v & 0xffU) << 24U;
734} 734}
735static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) 735static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void)
736{ 736{
737 return 0x00000080; 737 return 0x00000080U;
738} 738}
739static inline u32 ram_rl_entry_tsg_timeslice_timeout_disable_v(void) 739static inline u32 ram_rl_entry_tsg_timeslice_timeout_disable_v(void)
740{ 740{
741 return 0x00000000; 741 return 0x00000000U;
742} 742}
743static inline u32 ram_rl_entry_tsg_length_f(u32 v) 743static inline u32 ram_rl_entry_tsg_length_f(u32 v)
744{ 744{
745 return (v & 0xff) << 0; 745 return (v & 0xffU) << 0U;
746} 746}
747static inline u32 ram_rl_entry_tsg_length_init_v(void) 747static inline u32 ram_rl_entry_tsg_length_init_v(void)
748{ 748{
749 return 0x00000000; 749 return 0x00000000U;
750} 750}
751static inline u32 ram_rl_entry_tsg_length_min_v(void) 751static inline u32 ram_rl_entry_tsg_length_min_v(void)
752{ 752{
753 return 0x00000001; 753 return 0x00000001U;
754} 754}
755static inline u32 ram_rl_entry_tsg_length_max_v(void) 755static inline u32 ram_rl_entry_tsg_length_max_v(void)
756{ 756{
757 return 0x00000080; 757 return 0x00000080U;
758} 758}
759static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) 759static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v)
760{ 760{
761 return (v & 0xfff) << 0; 761 return (v & 0xfffU) << 0U;
762} 762}
763static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) 763static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void)
764{ 764{
765 return 0x00000008; 765 return 0x00000008U;
766} 766}
767static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) 767static inline u32 ram_rl_entry_chan_userd_align_shift_v(void)
768{ 768{
769 return 0x00000008; 769 return 0x00000008U;
770} 770}
771static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) 771static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void)
772{ 772{
773 return 0x0000000c; 773 return 0x0000000cU;
774} 774}
775#endif 775#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h
index b47e37f4..ce265901 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h
@@ -58,187 +58,187 @@
58 58
59static inline u32 therm_use_a_r(void) 59static inline u32 therm_use_a_r(void)
60{ 60{
61 return 0x00020798; 61 return 0x00020798U;
62} 62}
63static inline u32 therm_use_a_ext_therm_0_enable_f(void) 63static inline u32 therm_use_a_ext_therm_0_enable_f(void)
64{ 64{
65 return 0x1; 65 return 0x1U;
66} 66}
67static inline u32 therm_use_a_ext_therm_1_enable_f(void) 67static inline u32 therm_use_a_ext_therm_1_enable_f(void)
68{ 68{
69 return 0x2; 69 return 0x2U;
70} 70}
71static inline u32 therm_use_a_ext_therm_2_enable_f(void) 71static inline u32 therm_use_a_ext_therm_2_enable_f(void)
72{ 72{
73 return 0x4; 73 return 0x4U;
74} 74}
75static inline u32 therm_evt_ext_therm_0_r(void) 75static inline u32 therm_evt_ext_therm_0_r(void)
76{ 76{
77 return 0x00020700; 77 return 0x00020700U;
78} 78}
79static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) 79static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v)
80{ 80{
81 return (v & 0x3f) << 24; 81 return (v & 0x3fU) << 24U;
82} 82}
83static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) 83static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void)
84{ 84{
85 return 0x00000001; 85 return 0x00000001U;
86} 86}
87static inline u32 therm_evt_ext_therm_0_mode_f(u32 v) 87static inline u32 therm_evt_ext_therm_0_mode_f(u32 v)
88{ 88{
89 return (v & 0x3) << 30; 89 return (v & 0x3U) << 30U;
90} 90}
91static inline u32 therm_evt_ext_therm_0_mode_normal_v(void) 91static inline u32 therm_evt_ext_therm_0_mode_normal_v(void)
92{ 92{
93 return 0x00000000; 93 return 0x00000000U;
94} 94}
95static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void) 95static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void)
96{ 96{
97 return 0x00000001; 97 return 0x00000001U;
98} 98}
99static inline u32 therm_evt_ext_therm_0_mode_forced_v(void) 99static inline u32 therm_evt_ext_therm_0_mode_forced_v(void)
100{ 100{
101 return 0x00000002; 101 return 0x00000002U;
102} 102}
103static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void) 103static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void)
104{ 104{
105 return 0x00000003; 105 return 0x00000003U;
106} 106}
107static inline u32 therm_evt_ext_therm_1_r(void) 107static inline u32 therm_evt_ext_therm_1_r(void)
108{ 108{
109 return 0x00020704; 109 return 0x00020704U;
110} 110}
111static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) 111static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v)
112{ 112{
113 return (v & 0x3f) << 24; 113 return (v & 0x3fU) << 24U;
114} 114}
115static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) 115static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void)
116{ 116{
117 return 0x00000002; 117 return 0x00000002U;
118} 118}
119static inline u32 therm_evt_ext_therm_1_mode_f(u32 v) 119static inline u32 therm_evt_ext_therm_1_mode_f(u32 v)
120{ 120{
121 return (v & 0x3) << 30; 121 return (v & 0x3U) << 30U;
122} 122}
123static inline u32 therm_evt_ext_therm_1_mode_normal_v(void) 123static inline u32 therm_evt_ext_therm_1_mode_normal_v(void)
124{ 124{
125 return 0x00000000; 125 return 0x00000000U;
126} 126}
127static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void) 127static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void)
128{ 128{
129 return 0x00000001; 129 return 0x00000001U;
130} 130}
131static inline u32 therm_evt_ext_therm_1_mode_forced_v(void) 131static inline u32 therm_evt_ext_therm_1_mode_forced_v(void)
132{ 132{
133 return 0x00000002; 133 return 0x00000002U;
134} 134}
135static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void) 135static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void)
136{ 136{
137 return 0x00000003; 137 return 0x00000003U;
138} 138}
139static inline u32 therm_evt_ext_therm_2_r(void) 139static inline u32 therm_evt_ext_therm_2_r(void)
140{ 140{
141 return 0x00020708; 141 return 0x00020708U;
142} 142}
143static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) 143static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v)
144{ 144{
145 return (v & 0x3f) << 24; 145 return (v & 0x3fU) << 24U;
146} 146}
147static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) 147static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void)
148{ 148{
149 return 0x00000003; 149 return 0x00000003U;
150} 150}
151static inline u32 therm_evt_ext_therm_2_mode_f(u32 v) 151static inline u32 therm_evt_ext_therm_2_mode_f(u32 v)
152{ 152{
153 return (v & 0x3) << 30; 153 return (v & 0x3U) << 30U;
154} 154}
155static inline u32 therm_evt_ext_therm_2_mode_normal_v(void) 155static inline u32 therm_evt_ext_therm_2_mode_normal_v(void)
156{ 156{
157 return 0x00000000; 157 return 0x00000000U;
158} 158}
159static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void) 159static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void)
160{ 160{
161 return 0x00000001; 161 return 0x00000001U;
162} 162}
163static inline u32 therm_evt_ext_therm_2_mode_forced_v(void) 163static inline u32 therm_evt_ext_therm_2_mode_forced_v(void)
164{ 164{
165 return 0x00000002; 165 return 0x00000002U;
166} 166}
167static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void) 167static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void)
168{ 168{
169 return 0x00000003; 169 return 0x00000003U;
170} 170}
171static inline u32 therm_weight_1_r(void) 171static inline u32 therm_weight_1_r(void)
172{ 172{
173 return 0x00020024; 173 return 0x00020024U;
174} 174}
175static inline u32 therm_config1_r(void) 175static inline u32 therm_config1_r(void)
176{ 176{
177 return 0x00020050; 177 return 0x00020050U;
178} 178}
179static inline u32 therm_config2_r(void) 179static inline u32 therm_config2_r(void)
180{ 180{
181 return 0x00020130; 181 return 0x00020130U;
182} 182}
183static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) 183static inline u32 therm_config2_slowdown_factor_extended_f(u32 v)
184{ 184{
185 return (v & 0x1) << 24; 185 return (v & 0x1U) << 24U;
186} 186}
187static inline u32 therm_config2_grad_enable_f(u32 v) 187static inline u32 therm_config2_grad_enable_f(u32 v)
188{ 188{
189 return (v & 0x1) << 31; 189 return (v & 0x1U) << 31U;
190} 190}
191static inline u32 therm_gate_ctrl_r(u32 i) 191static inline u32 therm_gate_ctrl_r(u32 i)
192{ 192{
193 return 0x00020200 + i*4; 193 return 0x00020200U + i*4U;
194} 194}
195static inline u32 therm_gate_ctrl_eng_clk_m(void) 195static inline u32 therm_gate_ctrl_eng_clk_m(void)
196{ 196{
197 return 0x3 << 0; 197 return 0x3U << 0U;
198} 198}
199static inline u32 therm_gate_ctrl_eng_clk_run_f(void) 199static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
200{ 200{
201 return 0x0; 201 return 0x0U;
202} 202}
203static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) 203static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
204{ 204{
205 return 0x1; 205 return 0x1U;
206} 206}
207static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) 207static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
208{ 208{
209 return 0x2; 209 return 0x2U;
210} 210}
211static inline u32 therm_gate_ctrl_blk_clk_m(void) 211static inline u32 therm_gate_ctrl_blk_clk_m(void)
212{ 212{
213 return 0x3 << 2; 213 return 0x3U << 2U;
214} 214}
215static inline u32 therm_gate_ctrl_blk_clk_run_f(void) 215static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
216{ 216{
217 return 0x0; 217 return 0x0U;
218} 218}
219static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) 219static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
220{ 220{
221 return 0x4; 221 return 0x4U;
222} 222}
223static inline u32 therm_gate_ctrl_idle_holdoff_m(void) 223static inline u32 therm_gate_ctrl_idle_holdoff_m(void)
224{ 224{
225 return 0x1 << 4; 225 return 0x1U << 4U;
226} 226}
227static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void) 227static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void)
228{ 228{
229 return 0x0; 229 return 0x0U;
230} 230}
231static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void) 231static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void)
232{ 232{
233 return 0x10; 233 return 0x10U;
234} 234}
235static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) 235static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
236{ 236{
237 return (v & 0x1f) << 8; 237 return (v & 0x1fU) << 8U;
238} 238}
239static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) 239static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
240{ 240{
241 return 0x1f << 8; 241 return 0x1fU << 8U;
242} 242}
243static inline u32 therm_gate_ctrl_eng_idle_filt_exp__prod_f(void) 243static inline u32 therm_gate_ctrl_eng_idle_filt_exp__prod_f(void)
244{ 244{
@@ -246,11 +246,11 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_exp__prod_f(void)
246} 246}
247static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) 247static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
248{ 248{
249 return (v & 0x7) << 13; 249 return (v & 0x7U) << 13U;
250} 250}
251static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) 251static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
252{ 252{
253 return 0x7 << 13; 253 return 0x7U << 13U;
254} 254}
255static inline u32 therm_gate_ctrl_eng_idle_filt_mant__prod_f(void) 255static inline u32 therm_gate_ctrl_eng_idle_filt_mant__prod_f(void)
256{ 256{
@@ -258,11 +258,11 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_mant__prod_f(void)
258} 258}
259static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) 259static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
260{ 260{
261 return (v & 0xf) << 16; 261 return (v & 0xfU) << 16U;
262} 262}
263static inline u32 therm_gate_ctrl_eng_delay_before_m(void) 263static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
264{ 264{
265 return 0xf << 16; 265 return 0xfU << 16U;
266} 266}
267static inline u32 therm_gate_ctrl_eng_delay_before__prod_f(void) 267static inline u32 therm_gate_ctrl_eng_delay_before__prod_f(void)
268{ 268{
@@ -270,11 +270,11 @@ static inline u32 therm_gate_ctrl_eng_delay_before__prod_f(void)
270} 270}
271static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) 271static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
272{ 272{
273 return (v & 0xf) << 20; 273 return (v & 0xfU) << 20U;
274} 274}
275static inline u32 therm_gate_ctrl_eng_delay_after_m(void) 275static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
276{ 276{
277 return 0xf << 20; 277 return 0xfU << 20U;
278} 278}
279static inline u32 therm_gate_ctrl_eng_delay_after__prod_f(void) 279static inline u32 therm_gate_ctrl_eng_delay_after__prod_f(void)
280{ 280{
@@ -282,11 +282,11 @@ static inline u32 therm_gate_ctrl_eng_delay_after__prod_f(void)
282} 282}
283static inline u32 therm_fecs_idle_filter_r(void) 283static inline u32 therm_fecs_idle_filter_r(void)
284{ 284{
285 return 0x00020288; 285 return 0x00020288U;
286} 286}
287static inline u32 therm_fecs_idle_filter_value_m(void) 287static inline u32 therm_fecs_idle_filter_value_m(void)
288{ 288{
289 return 0xffffffff << 0; 289 return 0xffffffffU << 0U;
290} 290}
291static inline u32 therm_fecs_idle_filter_value__prod_f(void) 291static inline u32 therm_fecs_idle_filter_value__prod_f(void)
292{ 292{
@@ -294,11 +294,11 @@ static inline u32 therm_fecs_idle_filter_value__prod_f(void)
294} 294}
295static inline u32 therm_hubmmu_idle_filter_r(void) 295static inline u32 therm_hubmmu_idle_filter_r(void)
296{ 296{
297 return 0x0002028c; 297 return 0x0002028cU;
298} 298}
299static inline u32 therm_hubmmu_idle_filter_value_m(void) 299static inline u32 therm_hubmmu_idle_filter_value_m(void)
300{ 300{
301 return 0xffffffff << 0; 301 return 0xffffffffU << 0U;
302} 302}
303static inline u32 therm_hubmmu_idle_filter_value__prod_f(void) 303static inline u32 therm_hubmmu_idle_filter_value__prod_f(void)
304{ 304{
@@ -306,130 +306,130 @@ static inline u32 therm_hubmmu_idle_filter_value__prod_f(void)
306} 306}
307static inline u32 therm_clk_slowdown_r(u32 i) 307static inline u32 therm_clk_slowdown_r(u32 i)
308{ 308{
309 return 0x00020160 + i*4; 309 return 0x00020160U + i*4U;
310} 310}
311static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) 311static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
312{ 312{
313 return (v & 0x3f) << 16; 313 return (v & 0x3fU) << 16U;
314} 314}
315static inline u32 therm_clk_slowdown_idle_factor_m(void) 315static inline u32 therm_clk_slowdown_idle_factor_m(void)
316{ 316{
317 return 0x3f << 16; 317 return 0x3fU << 16U;
318} 318}
319static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) 319static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
320{ 320{
321 return (r >> 16) & 0x3f; 321 return (r >> 16U) & 0x3fU;
322} 322}
323static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) 323static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void)
324{ 324{
325 return 0x0; 325 return 0x0U;
326} 326}
327static inline u32 therm_grad_stepping_table_r(u32 i) 327static inline u32 therm_grad_stepping_table_r(u32 i)
328{ 328{
329 return 0x000202c8 + i*4; 329 return 0x000202c8U + i*4U;
330} 330}
331static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) 331static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
332{ 332{
333 return (v & 0x3f) << 0; 333 return (v & 0x3fU) << 0U;
334} 334}
335static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) 335static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
336{ 336{
337 return 0x3f << 0; 337 return 0x3fU << 0U;
338} 338}
339static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) 339static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
340{ 340{
341 return 0x1; 341 return 0x1U;
342} 342}
343static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) 343static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void)
344{ 344{
345 return 0x2; 345 return 0x2U;
346} 346}
347static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) 347static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void)
348{ 348{
349 return 0x6; 349 return 0x6U;
350} 350}
351static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) 351static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void)
352{ 352{
353 return 0xe; 353 return 0xeU;
354} 354}
355static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) 355static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
356{ 356{
357 return (v & 0x3f) << 6; 357 return (v & 0x3fU) << 6U;
358} 358}
359static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) 359static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
360{ 360{
361 return 0x3f << 6; 361 return 0x3fU << 6U;
362} 362}
363static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) 363static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
364{ 364{
365 return (v & 0x3f) << 12; 365 return (v & 0x3fU) << 12U;
366} 366}
367static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) 367static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
368{ 368{
369 return 0x3f << 12; 369 return 0x3fU << 12U;
370} 370}
371static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) 371static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
372{ 372{
373 return (v & 0x3f) << 18; 373 return (v & 0x3fU) << 18U;
374} 374}
375static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) 375static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
376{ 376{
377 return 0x3f << 18; 377 return 0x3fU << 18U;
378} 378}
379static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) 379static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
380{ 380{
381 return (v & 0x3f) << 24; 381 return (v & 0x3fU) << 24U;
382} 382}
383static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) 383static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
384{ 384{
385 return 0x3f << 24; 385 return 0x3fU << 24U;
386} 386}
387static inline u32 therm_grad_stepping0_r(void) 387static inline u32 therm_grad_stepping0_r(void)
388{ 388{
389 return 0x000202c0; 389 return 0x000202c0U;
390} 390}
391static inline u32 therm_grad_stepping0_feature_s(void) 391static inline u32 therm_grad_stepping0_feature_s(void)
392{ 392{
393 return 1; 393 return 1U;
394} 394}
395static inline u32 therm_grad_stepping0_feature_f(u32 v) 395static inline u32 therm_grad_stepping0_feature_f(u32 v)
396{ 396{
397 return (v & 0x1) << 0; 397 return (v & 0x1U) << 0U;
398} 398}
399static inline u32 therm_grad_stepping0_feature_m(void) 399static inline u32 therm_grad_stepping0_feature_m(void)
400{ 400{
401 return 0x1 << 0; 401 return 0x1U << 0U;
402} 402}
403static inline u32 therm_grad_stepping0_feature_v(u32 r) 403static inline u32 therm_grad_stepping0_feature_v(u32 r)
404{ 404{
405 return (r >> 0) & 0x1; 405 return (r >> 0U) & 0x1U;
406} 406}
407static inline u32 therm_grad_stepping0_feature_enable_f(void) 407static inline u32 therm_grad_stepping0_feature_enable_f(void)
408{ 408{
409 return 0x1; 409 return 0x1U;
410} 410}
411static inline u32 therm_grad_stepping1_r(void) 411static inline u32 therm_grad_stepping1_r(void)
412{ 412{
413 return 0x000202c4; 413 return 0x000202c4U;
414} 414}
415static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) 415static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v)
416{ 416{
417 return (v & 0x1ffff) << 0; 417 return (v & 0x1ffffU) << 0U;
418} 418}
419static inline u32 therm_clk_timing_r(u32 i) 419static inline u32 therm_clk_timing_r(u32 i)
420{ 420{
421 return 0x000203c0 + i*4; 421 return 0x000203c0U + i*4U;
422} 422}
423static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) 423static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
424{ 424{
425 return (v & 0x1) << 16; 425 return (v & 0x1U) << 16U;
426} 426}
427static inline u32 therm_clk_timing_grad_slowdown_m(void) 427static inline u32 therm_clk_timing_grad_slowdown_m(void)
428{ 428{
429 return 0x1 << 16; 429 return 0x1U << 16U;
430} 430}
431static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) 431static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
432{ 432{
433 return 0x10000; 433 return 0x10000U;
434} 434}
435#endif 435#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h
index 1181f177..61440213 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_timer_gv11b.h
@@ -58,58 +58,58 @@
58 58
59static inline u32 timer_pri_timeout_r(void) 59static inline u32 timer_pri_timeout_r(void)
60{ 60{
61 return 0x00009080; 61 return 0x00009080U;
62} 62}
63static inline u32 timer_pri_timeout_period_f(u32 v) 63static inline u32 timer_pri_timeout_period_f(u32 v)
64{ 64{
65 return (v & 0xffffff) << 0; 65 return (v & 0xffffffU) << 0U;
66} 66}
67static inline u32 timer_pri_timeout_period_m(void) 67static inline u32 timer_pri_timeout_period_m(void)
68{ 68{
69 return 0xffffff << 0; 69 return 0xffffffU << 0U;
70} 70}
71static inline u32 timer_pri_timeout_period_v(u32 r) 71static inline u32 timer_pri_timeout_period_v(u32 r)
72{ 72{
73 return (r >> 0) & 0xffffff; 73 return (r >> 0U) & 0xffffffU;
74} 74}
75static inline u32 timer_pri_timeout_en_f(u32 v) 75static inline u32 timer_pri_timeout_en_f(u32 v)
76{ 76{
77 return (v & 0x1) << 31; 77 return (v & 0x1U) << 31U;
78} 78}
79static inline u32 timer_pri_timeout_en_m(void) 79static inline u32 timer_pri_timeout_en_m(void)
80{ 80{
81 return 0x1 << 31; 81 return 0x1U << 31U;
82} 82}
83static inline u32 timer_pri_timeout_en_v(u32 r) 83static inline u32 timer_pri_timeout_en_v(u32 r)
84{ 84{
85 return (r >> 31) & 0x1; 85 return (r >> 31U) & 0x1U;
86} 86}
87static inline u32 timer_pri_timeout_en_en_enabled_f(void) 87static inline u32 timer_pri_timeout_en_en_enabled_f(void)
88{ 88{
89 return 0x80000000; 89 return 0x80000000U;
90} 90}
91static inline u32 timer_pri_timeout_en_en_disabled_f(void) 91static inline u32 timer_pri_timeout_en_en_disabled_f(void)
92{ 92{
93 return 0x0; 93 return 0x0U;
94} 94}
95static inline u32 timer_pri_timeout_save_0_r(void) 95static inline u32 timer_pri_timeout_save_0_r(void)
96{ 96{
97 return 0x00009084; 97 return 0x00009084U;
98} 98}
99static inline u32 timer_pri_timeout_save_1_r(void) 99static inline u32 timer_pri_timeout_save_1_r(void)
100{ 100{
101 return 0x00009088; 101 return 0x00009088U;
102} 102}
103static inline u32 timer_pri_timeout_fecs_errcode_r(void) 103static inline u32 timer_pri_timeout_fecs_errcode_r(void)
104{ 104{
105 return 0x0000908c; 105 return 0x0000908cU;
106} 106}
107static inline u32 timer_time_0_r(void) 107static inline u32 timer_time_0_r(void)
108{ 108{
109 return 0x00009400; 109 return 0x00009400U;
110} 110}
111static inline u32 timer_time_1_r(void) 111static inline u32 timer_time_1_r(void)
112{ 112{
113 return 0x00009410; 113 return 0x00009410U;
114} 114}
115#endif 115#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h
index 694257ed..89e4aebb 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_top_gv11b.h
@@ -58,178 +58,178 @@
58 58
59static inline u32 top_num_gpcs_r(void) 59static inline u32 top_num_gpcs_r(void)
60{ 60{
61 return 0x00022430; 61 return 0x00022430U;
62} 62}
63static inline u32 top_num_gpcs_value_v(u32 r) 63static inline u32 top_num_gpcs_value_v(u32 r)
64{ 64{
65 return (r >> 0) & 0x1f; 65 return (r >> 0U) & 0x1fU;
66} 66}
67static inline u32 top_tpc_per_gpc_r(void) 67static inline u32 top_tpc_per_gpc_r(void)
68{ 68{
69 return 0x00022434; 69 return 0x00022434U;
70} 70}
71static inline u32 top_tpc_per_gpc_value_v(u32 r) 71static inline u32 top_tpc_per_gpc_value_v(u32 r)
72{ 72{
73 return (r >> 0) & 0x1f; 73 return (r >> 0U) & 0x1fU;
74} 74}
75static inline u32 top_num_fbps_r(void) 75static inline u32 top_num_fbps_r(void)
76{ 76{
77 return 0x00022438; 77 return 0x00022438U;
78} 78}
79static inline u32 top_num_fbps_value_v(u32 r) 79static inline u32 top_num_fbps_value_v(u32 r)
80{ 80{
81 return (r >> 0) & 0x1f; 81 return (r >> 0U) & 0x1fU;
82} 82}
83static inline u32 top_ltc_per_fbp_r(void) 83static inline u32 top_ltc_per_fbp_r(void)
84{ 84{
85 return 0x00022450; 85 return 0x00022450U;
86} 86}
87static inline u32 top_ltc_per_fbp_value_v(u32 r) 87static inline u32 top_ltc_per_fbp_value_v(u32 r)
88{ 88{
89 return (r >> 0) & 0x1f; 89 return (r >> 0U) & 0x1fU;
90} 90}
91static inline u32 top_slices_per_ltc_r(void) 91static inline u32 top_slices_per_ltc_r(void)
92{ 92{
93 return 0x0002245c; 93 return 0x0002245cU;
94} 94}
95static inline u32 top_slices_per_ltc_value_v(u32 r) 95static inline u32 top_slices_per_ltc_value_v(u32 r)
96{ 96{
97 return (r >> 0) & 0x1f; 97 return (r >> 0U) & 0x1fU;
98} 98}
99static inline u32 top_num_ltcs_r(void) 99static inline u32 top_num_ltcs_r(void)
100{ 100{
101 return 0x00022454; 101 return 0x00022454U;
102} 102}
103static inline u32 top_num_ces_r(void) 103static inline u32 top_num_ces_r(void)
104{ 104{
105 return 0x00022444; 105 return 0x00022444U;
106} 106}
107static inline u32 top_num_ces_value_v(u32 r) 107static inline u32 top_num_ces_value_v(u32 r)
108{ 108{
109 return (r >> 0) & 0x1f; 109 return (r >> 0U) & 0x1fU;
110} 110}
111static inline u32 top_device_info_r(u32 i) 111static inline u32 top_device_info_r(u32 i)
112{ 112{
113 return 0x00022700 + i*4; 113 return 0x00022700U + i*4U;
114} 114}
115static inline u32 top_device_info__size_1_v(void) 115static inline u32 top_device_info__size_1_v(void)
116{ 116{
117 return 0x00000040; 117 return 0x00000040U;
118} 118}
119static inline u32 top_device_info_chain_v(u32 r) 119static inline u32 top_device_info_chain_v(u32 r)
120{ 120{
121 return (r >> 31) & 0x1; 121 return (r >> 31U) & 0x1U;
122} 122}
123static inline u32 top_device_info_chain_enable_v(void) 123static inline u32 top_device_info_chain_enable_v(void)
124{ 124{
125 return 0x00000001; 125 return 0x00000001U;
126} 126}
127static inline u32 top_device_info_engine_enum_v(u32 r) 127static inline u32 top_device_info_engine_enum_v(u32 r)
128{ 128{
129 return (r >> 26) & 0xf; 129 return (r >> 26U) & 0xfU;
130} 130}
131static inline u32 top_device_info_runlist_enum_v(u32 r) 131static inline u32 top_device_info_runlist_enum_v(u32 r)
132{ 132{
133 return (r >> 21) & 0xf; 133 return (r >> 21U) & 0xfU;
134} 134}
135static inline u32 top_device_info_intr_enum_v(u32 r) 135static inline u32 top_device_info_intr_enum_v(u32 r)
136{ 136{
137 return (r >> 15) & 0x1f; 137 return (r >> 15U) & 0x1fU;
138} 138}
139static inline u32 top_device_info_reset_enum_v(u32 r) 139static inline u32 top_device_info_reset_enum_v(u32 r)
140{ 140{
141 return (r >> 9) & 0x1f; 141 return (r >> 9U) & 0x1fU;
142} 142}
143static inline u32 top_device_info_type_enum_v(u32 r) 143static inline u32 top_device_info_type_enum_v(u32 r)
144{ 144{
145 return (r >> 2) & 0x1fffffff; 145 return (r >> 2U) & 0x1fffffffU;
146} 146}
147static inline u32 top_device_info_type_enum_graphics_v(void) 147static inline u32 top_device_info_type_enum_graphics_v(void)
148{ 148{
149 return 0x00000000; 149 return 0x00000000U;
150} 150}
151static inline u32 top_device_info_type_enum_graphics_f(void) 151static inline u32 top_device_info_type_enum_graphics_f(void)
152{ 152{
153 return 0x0; 153 return 0x0U;
154} 154}
155static inline u32 top_device_info_type_enum_copy2_v(void) 155static inline u32 top_device_info_type_enum_copy2_v(void)
156{ 156{
157 return 0x00000003; 157 return 0x00000003U;
158} 158}
159static inline u32 top_device_info_type_enum_copy2_f(void) 159static inline u32 top_device_info_type_enum_copy2_f(void)
160{ 160{
161 return 0xc; 161 return 0xcU;
162} 162}
163static inline u32 top_device_info_type_enum_lce_v(void) 163static inline u32 top_device_info_type_enum_lce_v(void)
164{ 164{
165 return 0x00000013; 165 return 0x00000013U;
166} 166}
167static inline u32 top_device_info_type_enum_lce_f(void) 167static inline u32 top_device_info_type_enum_lce_f(void)
168{ 168{
169 return 0x4c; 169 return 0x4cU;
170} 170}
171static inline u32 top_device_info_engine_v(u32 r) 171static inline u32 top_device_info_engine_v(u32 r)
172{ 172{
173 return (r >> 5) & 0x1; 173 return (r >> 5U) & 0x1U;
174} 174}
175static inline u32 top_device_info_runlist_v(u32 r) 175static inline u32 top_device_info_runlist_v(u32 r)
176{ 176{
177 return (r >> 4) & 0x1; 177 return (r >> 4U) & 0x1U;
178} 178}
179static inline u32 top_device_info_intr_v(u32 r) 179static inline u32 top_device_info_intr_v(u32 r)
180{ 180{
181 return (r >> 3) & 0x1; 181 return (r >> 3U) & 0x1U;
182} 182}
183static inline u32 top_device_info_reset_v(u32 r) 183static inline u32 top_device_info_reset_v(u32 r)
184{ 184{
185 return (r >> 2) & 0x1; 185 return (r >> 2U) & 0x1U;
186} 186}
187static inline u32 top_device_info_entry_v(u32 r) 187static inline u32 top_device_info_entry_v(u32 r)
188{ 188{
189 return (r >> 0) & 0x3; 189 return (r >> 0U) & 0x3U;
190} 190}
191static inline u32 top_device_info_entry_not_valid_v(void) 191static inline u32 top_device_info_entry_not_valid_v(void)
192{ 192{
193 return 0x00000000; 193 return 0x00000000U;
194} 194}
195static inline u32 top_device_info_entry_enum_v(void) 195static inline u32 top_device_info_entry_enum_v(void)
196{ 196{
197 return 0x00000002; 197 return 0x00000002U;
198} 198}
199static inline u32 top_device_info_entry_data_v(void) 199static inline u32 top_device_info_entry_data_v(void)
200{ 200{
201 return 0x00000001; 201 return 0x00000001U;
202} 202}
203static inline u32 top_device_info_data_type_v(u32 r) 203static inline u32 top_device_info_data_type_v(u32 r)
204{ 204{
205 return (r >> 30) & 0x1; 205 return (r >> 30U) & 0x1U;
206} 206}
207static inline u32 top_device_info_data_type_enum2_v(void) 207static inline u32 top_device_info_data_type_enum2_v(void)
208{ 208{
209 return 0x00000000; 209 return 0x00000000U;
210} 210}
211static inline u32 top_device_info_data_inst_id_v(u32 r) 211static inline u32 top_device_info_data_inst_id_v(u32 r)
212{ 212{
213 return (r >> 26) & 0xf; 213 return (r >> 26U) & 0xfU;
214} 214}
215static inline u32 top_device_info_data_pri_base_v(u32 r) 215static inline u32 top_device_info_data_pri_base_v(u32 r)
216{ 216{
217 return (r >> 12) & 0xfff; 217 return (r >> 12U) & 0xfffU;
218} 218}
219static inline u32 top_device_info_data_pri_base_align_v(void) 219static inline u32 top_device_info_data_pri_base_align_v(void)
220{ 220{
221 return 0x0000000c; 221 return 0x0000000cU;
222} 222}
223static inline u32 top_device_info_data_fault_id_enum_v(u32 r) 223static inline u32 top_device_info_data_fault_id_enum_v(u32 r)
224{ 224{
225 return (r >> 3) & 0x7f; 225 return (r >> 3U) & 0x7fU;
226} 226}
227static inline u32 top_device_info_data_fault_id_v(u32 r) 227static inline u32 top_device_info_data_fault_id_v(u32 r)
228{ 228{
229 return (r >> 2) & 0x1; 229 return (r >> 2U) & 0x1U;
230} 230}
231static inline u32 top_device_info_data_fault_id_valid_v(void) 231static inline u32 top_device_info_data_fault_id_valid_v(void)
232{ 232{
233 return 0x00000001; 233 return 0x00000001U;
234} 234}
235#endif 235#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-09 20:05:28 -0500