diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 74 |
2 files changed, 76 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c index 1d77ad65..515ba630 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c | |||
@@ -3,7 +3,7 @@ | |||
3 | * | 3 | * |
4 | * GM20B Graphics Context | 4 | * GM20B Graphics Context |
5 | * | 5 | * |
6 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 6 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. |
7 | * | 7 | * |
8 | * This program is free software; you can redistribute it and/or modify it | 8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms and conditions of the GNU General Public License, | 9 | * under the terms and conditions of the GNU General Public License, |
@@ -69,4 +69,5 @@ static bool gr_gp10b_is_firmware_defined(void) | |||
69 | void gp10b_init_gr_ctx(struct gpu_ops *gops) { | 69 | void gp10b_init_gr_ctx(struct gpu_ops *gops) { |
70 | gops->gr_ctx.get_netlist_name = gr_gp10b_get_netlist_name; | 70 | gops->gr_ctx.get_netlist_name = gr_gp10b_get_netlist_name; |
71 | gops->gr_ctx.is_fw_defined = gr_gp10b_is_firmware_defined; | 71 | gops->gr_ctx.is_fw_defined = gr_gp10b_is_firmware_defined; |
72 | gops->gr_ctx.use_dma_for_fw_bootstrap = false; | ||
72 | } | 73 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index b8b985b3..7b806026 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -21,6 +21,8 @@ | |||
21 | 21 | ||
22 | #include "pmu_gp10b.h" | 22 | #include "pmu_gp10b.h" |
23 | 23 | ||
24 | #define gp10b_dbg_pmu(fmt, arg...) \ | ||
25 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) | ||
24 | /*! | 26 | /*! |
25 | * Structure/object which single register write need to be done during PG init | 27 | * Structure/object which single register write need to be done during PG init |
26 | * sequence to set PROD values. | 28 | * sequence to set PROD values. |
@@ -130,6 +132,76 @@ static struct pg_init_sequence_list _pginitseq_gp10b[] = { | |||
130 | {0x0010e004, 0x0000008E}, | 132 | {0x0010e004, 0x0000008E}, |
131 | }; | 133 | }; |
132 | 134 | ||
135 | void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, | ||
136 | u32 flags) | ||
137 | { | ||
138 | struct pmu_gk20a *pmu = &g->pmu; | ||
139 | struct pmu_cmd cmd; | ||
140 | u32 seq; | ||
141 | |||
142 | gk20a_dbg_fn(""); | ||
143 | |||
144 | gp10b_dbg_pmu("wprinit status = %x\n", g->ops.pmu.lspmuwprinitdone); | ||
145 | if (g->ops.pmu.lspmuwprinitdone) { | ||
146 | /* send message to load FECS falcon */ | ||
147 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
148 | cmd.hdr.unit_id = PMU_UNIT_ACR; | ||
149 | cmd.hdr.size = PMU_CMD_HDR_SIZE + | ||
150 | sizeof(struct pmu_acr_cmd_bootstrap_multiple_falcons); | ||
151 | cmd.cmd.acr.boot_falcons.cmd_type = | ||
152 | PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS; | ||
153 | cmd.cmd.acr.boot_falcons.flags = flags; | ||
154 | cmd.cmd.acr.boot_falcons.falconidmask = | ||
155 | falconidmask; | ||
156 | cmd.cmd.acr.boot_falcons.usevamask = | ||
157 | 1 << LSF_FALCON_ID_GPCCS; | ||
158 | cmd.cmd.acr.boot_falcons.wprvirtualbase.lo = | ||
159 | u64_lo32(g->pmu.wpr_buf.gpu_va); | ||
160 | cmd.cmd.acr.boot_falcons.wprvirtualbase.hi = | ||
161 | u64_hi32(g->pmu.wpr_buf.gpu_va); | ||
162 | gp10b_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n", | ||
163 | falconidmask); | ||
164 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | ||
165 | pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0); | ||
166 | } | ||
167 | |||
168 | gk20a_dbg_fn("done"); | ||
169 | return; | ||
170 | } | ||
171 | |||
172 | int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) | ||
173 | { | ||
174 | u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; | ||
175 | |||
176 | /* GM20B PMU supports loading FECS and GPCCS only */ | ||
177 | if (falconidmask == 0) | ||
178 | return -EINVAL; | ||
179 | if (falconidmask & ~((1 << LSF_FALCON_ID_FECS) | | ||
180 | (1 << LSF_FALCON_ID_GPCCS))) | ||
181 | return -EINVAL; | ||
182 | g->ops.pmu.lsfloadedfalconid = 0; | ||
183 | /* check whether pmu is ready to bootstrap lsf if not wait for it */ | ||
184 | if (!g->ops.pmu.lspmuwprinitdone) { | ||
185 | pmu_wait_message_cond(&g->pmu, | ||
186 | gk20a_get_gr_idle_timeout(g), | ||
187 | &g->ops.pmu.lspmuwprinitdone, 1); | ||
188 | /* check again if it still not ready indicate an error */ | ||
189 | if (!g->ops.pmu.lspmuwprinitdone) { | ||
190 | gk20a_err(dev_from_gk20a(g), | ||
191 | "PMU not ready to load LSF"); | ||
192 | return -ETIMEDOUT; | ||
193 | } | ||
194 | } | ||
195 | /* load falcon(s) */ | ||
196 | gp10b_pmu_load_multiple_falcons(g, falconidmask, flags); | ||
197 | pmu_wait_message_cond(&g->pmu, | ||
198 | gk20a_get_gr_idle_timeout(g), | ||
199 | &g->ops.pmu.lsfloadedfalconid, falconidmask); | ||
200 | if (g->ops.pmu.lsfloadedfalconid != falconidmask) | ||
201 | return -ETIMEDOUT; | ||
202 | return 0; | ||
203 | } | ||
204 | |||
133 | static int gp10b_pmu_setup_elpg(struct gk20a *g) | 205 | static int gp10b_pmu_setup_elpg(struct gk20a *g) |
134 | { | 206 | { |
135 | int ret = 0; | 207 | int ret = 0; |
@@ -157,8 +229,10 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) | |||
157 | if (gops->privsecurity) { | 229 | if (gops->privsecurity) { |
158 | gm20b_init_secure_pmu(gops); | 230 | gm20b_init_secure_pmu(gops); |
159 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | 231 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; |
232 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; | ||
160 | } else { | 233 | } else { |
161 | gk20a_init_pmu_ops(gops); | 234 | gk20a_init_pmu_ops(gops); |
235 | gops->pmu.load_lsfalcon_ucode = NULL; | ||
162 | gops->pmu.init_wpr_region = NULL; | 236 | gops->pmu.init_wpr_region = NULL; |
163 | } | 237 | } |
164 | gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg; | 238 | gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg; |