diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hw_therm_gp106.h | 80 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/therm_gp106.c | 45 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/therm_gp10b.c | 33 |
3 files changed, 154 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gp106/hw_therm_gp106.h b/drivers/gpu/nvgpu/gp106/hw_therm_gp106.h index ecc50980..36ffcc7a 100644 --- a/drivers/gpu/nvgpu/gp106/hw_therm_gp106.h +++ b/drivers/gpu/nvgpu/gp106/hw_therm_gp106.h | |||
@@ -94,4 +94,84 @@ static inline u32 therm_temp_sensor_tsense_state_shadow_v(void) | |||
94 | { | 94 | { |
95 | return 0x00000002; | 95 | return 0x00000002; |
96 | } | 96 | } |
97 | static inline u32 therm_gate_ctrl_r(u32 i) | ||
98 | { | ||
99 | return 0x00020200 + i*4; | ||
100 | } | ||
101 | static inline u32 therm_gate_ctrl_eng_clk_m(void) | ||
102 | { | ||
103 | return 0x3 << 0; | ||
104 | } | ||
105 | static inline u32 therm_gate_ctrl_eng_clk_run_f(void) | ||
106 | { | ||
107 | return 0x0; | ||
108 | } | ||
109 | static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) | ||
110 | { | ||
111 | return 0x1; | ||
112 | } | ||
113 | static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) | ||
114 | { | ||
115 | return 0x2; | ||
116 | } | ||
117 | static inline u32 therm_gate_ctrl_blk_clk_m(void) | ||
118 | { | ||
119 | return 0x3 << 2; | ||
120 | } | ||
121 | static inline u32 therm_gate_ctrl_blk_clk_run_f(void) | ||
122 | { | ||
123 | return 0x0; | ||
124 | } | ||
125 | static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) | ||
126 | { | ||
127 | return 0x4; | ||
128 | } | ||
129 | static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) | ||
130 | { | ||
131 | return (v & 0x1f) << 8; | ||
132 | } | ||
133 | static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) | ||
134 | { | ||
135 | return 0x1f << 8; | ||
136 | } | ||
137 | static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) | ||
138 | { | ||
139 | return (v & 0x7) << 13; | ||
140 | } | ||
141 | static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) | ||
142 | { | ||
143 | return 0x7 << 13; | ||
144 | } | ||
145 | static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) | ||
146 | { | ||
147 | return (v & 0xf) << 16; | ||
148 | } | ||
149 | static inline u32 therm_gate_ctrl_eng_delay_before_m(void) | ||
150 | { | ||
151 | return 0xf << 16; | ||
152 | } | ||
153 | static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) | ||
154 | { | ||
155 | return (v & 0xf) << 20; | ||
156 | } | ||
157 | static inline u32 therm_gate_ctrl_eng_delay_after_m(void) | ||
158 | { | ||
159 | return 0xf << 20; | ||
160 | } | ||
161 | static inline u32 therm_fecs_idle_filter_r(void) | ||
162 | { | ||
163 | return 0x00020288; | ||
164 | } | ||
165 | static inline u32 therm_fecs_idle_filter_value_m(void) | ||
166 | { | ||
167 | return 0xffffffff << 0; | ||
168 | } | ||
169 | static inline u32 therm_hubmmu_idle_filter_r(void) | ||
170 | { | ||
171 | return 0x0002028c; | ||
172 | } | ||
173 | static inline u32 therm_hubmmu_idle_filter_value_m(void) | ||
174 | { | ||
175 | return 0xffffffff << 0; | ||
176 | } | ||
97 | #endif | 177 | #endif |
diff --git a/drivers/gpu/nvgpu/gp106/therm_gp106.c b/drivers/gpu/nvgpu/gp106/therm_gp106.c index 153e953d..a3aa3636 100644 --- a/drivers/gpu/nvgpu/gp106/therm_gp106.c +++ b/drivers/gpu/nvgpu/gp106/therm_gp106.c | |||
@@ -55,8 +55,53 @@ static void gp106_therm_debugfs_init(struct gk20a *g) { | |||
55 | } | 55 | } |
56 | #endif | 56 | #endif |
57 | 57 | ||
58 | static int gp106_elcg_init_idle_filters(struct gk20a *g) | ||
59 | { | ||
60 | u32 gate_ctrl, idle_filter; | ||
61 | u32 engine_id; | ||
62 | u32 active_engine_id = 0; | ||
63 | struct fifo_gk20a *f = &g->fifo; | ||
64 | |||
65 | gk20a_dbg_fn(""); | ||
66 | |||
67 | for (engine_id = 0; engine_id < f->num_engines; engine_id++) { | ||
68 | active_engine_id = f->active_engines_list[engine_id]; | ||
69 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id)); | ||
70 | |||
71 | if (tegra_platform_is_linsim()) { | ||
72 | gate_ctrl = set_field(gate_ctrl, | ||
73 | therm_gate_ctrl_eng_delay_after_m(), | ||
74 | therm_gate_ctrl_eng_delay_after_f(4)); | ||
75 | } | ||
76 | |||
77 | gate_ctrl = set_field(gate_ctrl, | ||
78 | therm_gate_ctrl_eng_idle_filt_exp_m(), | ||
79 | therm_gate_ctrl_eng_idle_filt_exp_f(2)); | ||
80 | gate_ctrl = set_field(gate_ctrl, | ||
81 | therm_gate_ctrl_eng_idle_filt_mant_m(), | ||
82 | therm_gate_ctrl_eng_idle_filt_mant_f(1)); | ||
83 | gate_ctrl = set_field(gate_ctrl, | ||
84 | therm_gate_ctrl_eng_delay_before_m(), | ||
85 | therm_gate_ctrl_eng_delay_before_f(0)); | ||
86 | gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl); | ||
87 | } | ||
88 | |||
89 | /* default fecs_idle_filter to 0 */ | ||
90 | idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r()); | ||
91 | idle_filter &= ~therm_fecs_idle_filter_value_m(); | ||
92 | gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter); | ||
93 | /* default hubmmu_idle_filter to 0 */ | ||
94 | idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r()); | ||
95 | idle_filter &= ~therm_hubmmu_idle_filter_value_m(); | ||
96 | gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter); | ||
97 | |||
98 | gk20a_dbg_fn("done"); | ||
99 | return 0; | ||
100 | } | ||
101 | |||
58 | void gp106_init_therm_ops(struct gpu_ops *gops) { | 102 | void gp106_init_therm_ops(struct gpu_ops *gops) { |
59 | #ifdef CONFIG_DEBUG_FS | 103 | #ifdef CONFIG_DEBUG_FS |
60 | gops->therm.therm_debugfs_init = gp106_therm_debugfs_init; | 104 | gops->therm.therm_debugfs_init = gp106_therm_debugfs_init; |
61 | #endif | 105 | #endif |
106 | gops->therm.elcg_init_idle_filters = gp106_elcg_init_idle_filters; | ||
62 | } | 107 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c index 63efc945..7f43cb56 100644 --- a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c | |||
@@ -78,28 +78,53 @@ static int gp10b_init_therm_setup_hw(struct gk20a *g) | |||
78 | return 0; | 78 | return 0; |
79 | } | 79 | } |
80 | 80 | ||
81 | static int gp10b_update_therm_gate_ctrl(struct gk20a *g) | 81 | static int gp10b_elcg_init_idle_filters(struct gk20a *g) |
82 | { | 82 | { |
83 | u32 gate_ctrl; | 83 | u32 gate_ctrl, idle_filter; |
84 | u32 engine_id; | 84 | u32 engine_id; |
85 | u32 active_engine_id = 0; | 85 | u32 active_engine_id = 0; |
86 | struct fifo_gk20a *f = &g->fifo; | 86 | struct fifo_gk20a *f = &g->fifo; |
87 | 87 | ||
88 | gk20a_dbg_fn(""); | ||
89 | |||
88 | for (engine_id = 0; engine_id < f->num_engines; engine_id++) { | 90 | for (engine_id = 0; engine_id < f->num_engines; engine_id++) { |
89 | active_engine_id = f->active_engines_list[engine_id]; | 91 | active_engine_id = f->active_engines_list[engine_id]; |
90 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id)); | 92 | gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id)); |
93 | |||
94 | if (tegra_platform_is_linsim()) { | ||
95 | gate_ctrl = set_field(gate_ctrl, | ||
96 | therm_gate_ctrl_eng_delay_after_m(), | ||
97 | therm_gate_ctrl_eng_delay_after_f(4)); | ||
98 | } | ||
99 | |||
100 | /* 2 * (1 << 9) = 1024 clks */ | ||
101 | gate_ctrl = set_field(gate_ctrl, | ||
102 | therm_gate_ctrl_eng_idle_filt_exp_m(), | ||
103 | therm_gate_ctrl_eng_idle_filt_exp_f(9)); | ||
104 | gate_ctrl = set_field(gate_ctrl, | ||
105 | therm_gate_ctrl_eng_idle_filt_mant_m(), | ||
106 | therm_gate_ctrl_eng_idle_filt_mant_f(2)); | ||
91 | gate_ctrl = set_field(gate_ctrl, | 107 | gate_ctrl = set_field(gate_ctrl, |
92 | therm_gate_ctrl_eng_delay_before_m(), | 108 | therm_gate_ctrl_eng_delay_before_m(), |
93 | therm_gate_ctrl_eng_delay_before_f(4)); | 109 | therm_gate_ctrl_eng_delay_before_f(4)); |
94 | gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl); | 110 | gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl); |
95 | } | 111 | } |
96 | 112 | ||
113 | /* default fecs_idle_filter to 0 */ | ||
114 | idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r()); | ||
115 | idle_filter &= ~therm_fecs_idle_filter_value_m(); | ||
116 | gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter); | ||
117 | /* default hubmmu_idle_filter to 0 */ | ||
118 | idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r()); | ||
119 | idle_filter &= ~therm_hubmmu_idle_filter_value_m(); | ||
120 | gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter); | ||
121 | |||
122 | gk20a_dbg_fn("done"); | ||
97 | return 0; | 123 | return 0; |
98 | } | 124 | } |
99 | 125 | ||
100 | void gp10b_init_therm_ops(struct gpu_ops *gops) | 126 | void gp10b_init_therm_ops(struct gpu_ops *gops) |
101 | { | 127 | { |
102 | gops->therm.init_therm_setup_hw = gp10b_init_therm_setup_hw; | 128 | gops->therm.init_therm_setup_hw = gp10b_init_therm_setup_hw; |
103 | gops->therm.update_therm_gate_ctrl = gp10b_update_therm_gate_ctrl; | 129 | gops->therm.elcg_init_idle_filters = gp10b_elcg_init_idle_filters; |
104 | |||
105 | } | 130 | } |