diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 9 |
3 files changed, 18 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index eb6ee70f..0705d8b6 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1924,10 +1924,13 @@ static u32 gp10b_mask_hww_warp_esr(u32 hww_warp_esr) | |||
1924 | 1924 | ||
1925 | static u32 get_ecc_override_val(struct gk20a *g) | 1925 | static u32 get_ecc_override_val(struct gk20a *g) |
1926 | { | 1926 | { |
1927 | if (tegra_fuse_readl(FUSE_OPT_ECC_EN)) | 1927 | u32 val; |
1928 | |||
1929 | tegra_fuse_readl(FUSE_OPT_ECC_EN, &val); | ||
1930 | if (val) | ||
1928 | return gk20a_readl(g, gr_fecs_feature_override_ecc_r()); | 1931 | return gk20a_readl(g, gr_fecs_feature_override_ecc_r()); |
1929 | else | 1932 | |
1930 | return 0; | 1933 | return 0; |
1931 | } | 1934 | } |
1932 | 1935 | ||
1933 | static bool gr_gp10b_suspend_context(struct channel_gk20a *ch, | 1936 | static bool gr_gp10b_suspend_context(struct channel_gk20a *ch, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index ec81cf35..c4e44483 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -190,6 +190,7 @@ int gp10b_init_hal(struct gk20a *g) | |||
190 | struct gpu_ops *gops = &g->ops; | 190 | struct gpu_ops *gops = &g->ops; |
191 | struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; | 191 | struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; |
192 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | 192 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); |
193 | u32 val; | ||
193 | 194 | ||
194 | *gops = gp10b_ops; | 195 | *gops = gp10b_ops; |
195 | 196 | ||
@@ -198,8 +199,8 @@ int gp10b_init_hal(struct gk20a *g) | |||
198 | gops->privsecurity = 0; | 199 | gops->privsecurity = 0; |
199 | gops->securegpccs = 0; | 200 | gops->securegpccs = 0; |
200 | } else { | 201 | } else { |
201 | if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) & | 202 | tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0, &val); |
202 | PRIV_SECURITY_ENABLED) { | 203 | if (val & PRIV_SECURITY_ENABLED) { |
203 | gops->privsecurity = 1; | 204 | gops->privsecurity = 1; |
204 | gops->securegpccs =1; | 205 | gops->securegpccs =1; |
205 | } else { | 206 | } else { |
@@ -214,8 +215,8 @@ int gp10b_init_hal(struct gk20a *g) | |||
214 | gops->privsecurity = 0; | 215 | gops->privsecurity = 0; |
215 | gops->securegpccs = 0; | 216 | gops->securegpccs = 0; |
216 | } else { | 217 | } else { |
217 | if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) & | 218 | tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0, &val); |
218 | PRIV_SECURITY_ENABLED) { | 219 | if (val & PRIV_SECURITY_ENABLED) { |
219 | gk20a_dbg_info("priv security is not supported but enabled"); | 220 | gk20a_dbg_info("priv security is not supported but enabled"); |
220 | gops->privsecurity = 1; | 221 | gops->privsecurity = 1; |
221 | gops->securegpccs =1; | 222 | gops->securegpccs =1; |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index f40c1b7b..762e2af7 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -365,9 +365,11 @@ static int send_ecc_overide_en_dis_cmd(struct gk20a *g, u32 bitmask) | |||
365 | struct pmu_cmd cmd; | 365 | struct pmu_cmd cmd; |
366 | u32 seq; | 366 | u32 seq; |
367 | int status; | 367 | int status; |
368 | u32 val; | ||
368 | gk20a_dbg_fn(""); | 369 | gk20a_dbg_fn(""); |
369 | 370 | ||
370 | if (!tegra_fuse_readl(FUSE_OPT_ECC_EN)) { | 371 | tegra_fuse_readl(FUSE_OPT_ECC_EN, &val); |
372 | if (!val) { | ||
371 | gk20a_err(dev_from_gk20a(g), "Board not ECC capable"); | 373 | gk20a_err(dev_from_gk20a(g), "Board not ECC capable"); |
372 | return -1; | 374 | return -1; |
373 | } | 375 | } |
@@ -436,12 +438,15 @@ static bool gp10b_is_priv_load(u32 falcon_id) | |||
436 | /*Dump Security related fuses*/ | 438 | /*Dump Security related fuses*/ |
437 | static void pmu_dump_security_fuses_gp10b(struct gk20a *g) | 439 | static void pmu_dump_security_fuses_gp10b(struct gk20a *g) |
438 | { | 440 | { |
441 | u32 val; | ||
442 | |||
439 | gk20a_err(dev_from_gk20a(g), "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", | 443 | gk20a_err(dev_from_gk20a(g), "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", |
440 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); | 444 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); |
441 | gk20a_err(dev_from_gk20a(g), "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", | 445 | gk20a_err(dev_from_gk20a(g), "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", |
442 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); | 446 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); |
447 | tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val); | ||
443 | gk20a_err(dev_from_gk20a(g), "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", | 448 | gk20a_err(dev_from_gk20a(g), "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", |
444 | tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0)); | 449 | val); |
445 | } | 450 | } |
446 | 451 | ||
447 | void gp10b_init_pmu_ops(struct gpu_ops *gops) | 452 | void gp10b_init_pmu_ops(struct gpu_ops *gops) |