diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile.nvgpu-t18x | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c | 649 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/gp106_gating_reglist.h | 87 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 49 |
4 files changed, 785 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu-t18x b/drivers/gpu/nvgpu/Makefile.nvgpu-t18x index 167a0ae2..aaf02931 100644 --- a/drivers/gpu/nvgpu/Makefile.nvgpu-t18x +++ b/drivers/gpu/nvgpu/Makefile.nvgpu-t18x | |||
@@ -40,7 +40,8 @@ nvgpu-y += \ | |||
40 | $(nvgpu-t18x)/perf/vfe_equ.o \ | 40 | $(nvgpu-t18x)/perf/vfe_equ.o \ |
41 | $(nvgpu-t18x)/perf/perf.o \ | 41 | $(nvgpu-t18x)/perf/perf.o \ |
42 | $(nvgpu-t18x)/clk/clk.o \ | 42 | $(nvgpu-t18x)/clk/clk.o \ |
43 | $(nvgpu-t18x)/gp106/clk_gp106.o | 43 | $(nvgpu-t18x)/gp106/clk_gp106.o \ |
44 | $(nvgpu-t18x)/gp106/gp106_gating_reglist.o | ||
44 | 45 | ||
45 | nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o | 46 | nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o |
46 | 47 | ||
diff --git a/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c b/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c new file mode 100644 index 00000000..29870d60 --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c | |||
@@ -0,0 +1,649 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * This file is autogenerated. Do not edit. | ||
14 | */ | ||
15 | |||
16 | #ifndef __gp106_gating_reglist_h__ | ||
17 | #define __gp106_gating_reglist_h__ | ||
18 | |||
19 | #include <linux/types.h> | ||
20 | #include "gp106_gating_reglist.h" | ||
21 | |||
22 | struct gating_desc { | ||
23 | u32 addr; | ||
24 | u32 prod; | ||
25 | u32 disable; | ||
26 | }; | ||
27 | /* slcg bus */ | ||
28 | static const struct gating_desc gp106_slcg_bus[] = { | ||
29 | {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, | ||
30 | }; | ||
31 | |||
32 | /* slcg ce2 */ | ||
33 | static const struct gating_desc gp106_slcg_ce2[] = { | ||
34 | {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe}, | ||
35 | }; | ||
36 | |||
37 | /* slcg chiplet */ | ||
38 | static const struct gating_desc gp106_slcg_chiplet[] = { | ||
39 | {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
40 | {.addr = 0x0010c0fc, .prod = 0x00000000, .disable = 0x00000007}, | ||
41 | {.addr = 0x0010c17c, .prod = 0x00000000, .disable = 0x00000007}, | ||
42 | {.addr = 0x0010c1fc, .prod = 0x00000000, .disable = 0x00000007}, | ||
43 | {.addr = 0x0010c27c, .prod = 0x00000000, .disable = 0x00000007}, | ||
44 | {.addr = 0x0010c2fc, .prod = 0x00000000, .disable = 0x00000007}, | ||
45 | {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
46 | {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, | ||
47 | {.addr = 0x0010d0fc, .prod = 0x00000000, .disable = 0x00000007}, | ||
48 | {.addr = 0x0010d17c, .prod = 0x00000000, .disable = 0x00000007}, | ||
49 | {.addr = 0x0010d1fc, .prod = 0x00000000, .disable = 0x00000007}, | ||
50 | {.addr = 0x0010d27c, .prod = 0x00000000, .disable = 0x00000007}, | ||
51 | {.addr = 0x0010d2fc, .prod = 0x00000000, .disable = 0x00000007}, | ||
52 | {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, | ||
53 | }; | ||
54 | |||
55 | /* slcg fb */ | ||
56 | static const struct gating_desc gp106_slcg_fb[] = { | ||
57 | {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
58 | {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
59 | }; | ||
60 | |||
61 | /* slcg fifo */ | ||
62 | static const struct gating_desc gp106_slcg_fifo[] = { | ||
63 | {.addr = 0x000026ac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
64 | }; | ||
65 | |||
66 | /* slcg gr */ | ||
67 | static const struct gating_desc gp106_slcg_gr[] = { | ||
68 | {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe}, | ||
69 | {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
70 | {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe}, | ||
71 | {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, | ||
72 | {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
73 | {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, | ||
74 | {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
75 | {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, | ||
76 | {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, | ||
77 | {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
78 | {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe}, | ||
79 | {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, | ||
80 | {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
81 | {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, | ||
82 | {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe}, | ||
83 | {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, | ||
84 | {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
85 | {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, | ||
86 | {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
87 | {.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe}, | ||
88 | {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | ||
89 | {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
90 | {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
91 | {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, | ||
92 | {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, | ||
93 | {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
94 | {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff}, | ||
95 | {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, | ||
96 | {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
97 | {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, | ||
98 | {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, | ||
99 | {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, | ||
100 | {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, | ||
101 | {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, | ||
102 | {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, | ||
103 | {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, | ||
104 | {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, | ||
105 | {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, | ||
106 | {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, | ||
107 | {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, | ||
108 | {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, | ||
109 | {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, | ||
110 | {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, | ||
111 | {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, | ||
112 | {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
113 | {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, | ||
114 | {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
115 | {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | ||
116 | {.addr = 0x00412814, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
117 | {.addr = 0x00412a84, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
118 | {.addr = 0x004129ac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
119 | {.addr = 0x00412a24, .prod = 0x00000000, .disable = 0x0000ffff}, | ||
120 | {.addr = 0x00412c14, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
121 | {.addr = 0x00412e84, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
122 | {.addr = 0x00412dac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
123 | {.addr = 0x00412e24, .prod = 0x00000000, .disable = 0x0000ffff}, | ||
124 | {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
125 | {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
126 | {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
127 | {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff}, | ||
128 | }; | ||
129 | |||
130 | /* slcg ltc */ | ||
131 | static const struct gating_desc gp106_slcg_ltc[] = { | ||
132 | {.addr = 0x00154050, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
133 | {.addr = 0x0015455c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
134 | {.addr = 0x0015475c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
135 | {.addr = 0x0015435c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
136 | {.addr = 0x00156050, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
137 | {.addr = 0x0015655c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
138 | {.addr = 0x0015675c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
139 | {.addr = 0x0015635c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
140 | {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
141 | {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
142 | }; | ||
143 | |||
144 | /* slcg perf */ | ||
145 | static const struct gating_desc gp106_slcg_perf[] = { | ||
146 | {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
147 | {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
148 | {.addr = 0x001bc218, .prod = 0x000001ff, .disable = 0x00000000}, | ||
149 | {.addr = 0x001bc418, .prod = 0x000001ff, .disable = 0x00000000}, | ||
150 | {.addr = 0x001bc618, .prod = 0x000001ff, .disable = 0x00000000}, | ||
151 | {.addr = 0x001bc818, .prod = 0x000001ff, .disable = 0x00000000}, | ||
152 | {.addr = 0x001bca18, .prod = 0x000001ff, .disable = 0x00000000}, | ||
153 | {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
154 | {.addr = 0x001b8218, .prod = 0x000001ff, .disable = 0x00000000}, | ||
155 | {.addr = 0x001b8418, .prod = 0x000001ff, .disable = 0x00000000}, | ||
156 | {.addr = 0x001b8618, .prod = 0x000001ff, .disable = 0x00000000}, | ||
157 | {.addr = 0x001b8818, .prod = 0x000001ff, .disable = 0x00000000}, | ||
158 | {.addr = 0x001b8a18, .prod = 0x000001ff, .disable = 0x00000000}, | ||
159 | {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, | ||
160 | }; | ||
161 | |||
162 | /* slcg PriRing */ | ||
163 | static const struct gating_desc gp106_slcg_priring[] = { | ||
164 | {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, | ||
165 | }; | ||
166 | |||
167 | /* slcg pmu */ | ||
168 | static const struct gating_desc gp106_slcg_pmu[] = { | ||
169 | {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
170 | {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, | ||
171 | {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, | ||
172 | }; | ||
173 | |||
174 | /* therm gr */ | ||
175 | static const struct gating_desc gp106_slcg_therm[] = { | ||
176 | {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, | ||
177 | }; | ||
178 | |||
179 | /* slcg Xbar */ | ||
180 | static const struct gating_desc gp106_slcg_xbar[] = { | ||
181 | {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe}, | ||
182 | {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe}, | ||
183 | {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe}, | ||
184 | {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
185 | {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
186 | {.addr = 0x0013cc24, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
187 | {.addr = 0x0013cc44, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
188 | {.addr = 0x0013cc64, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
189 | {.addr = 0x0013cc84, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
190 | {.addr = 0x0013cca4, .prod = 0x00000000, .disable = 0x1ffffffe}, | ||
191 | }; | ||
192 | |||
193 | /* blcg bus */ | ||
194 | static const struct gating_desc gp106_blcg_bus[] = { | ||
195 | {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, | ||
196 | }; | ||
197 | |||
198 | /* blcg ce */ | ||
199 | static const struct gating_desc gp106_blcg_ce[] = { | ||
200 | {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000}, | ||
201 | }; | ||
202 | |||
203 | /* blcg fb */ | ||
204 | static const struct gating_desc gp106_blcg_fb[] = { | ||
205 | {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, | ||
206 | {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, | ||
207 | {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, | ||
208 | {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, | ||
209 | {.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000}, | ||
210 | {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, | ||
211 | }; | ||
212 | |||
213 | /* blcg fifo */ | ||
214 | static const struct gating_desc gp106_blcg_fifo[] = { | ||
215 | {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, | ||
216 | }; | ||
217 | |||
218 | /* blcg gr */ | ||
219 | static const struct gating_desc gp106_blcg_gr[] = { | ||
220 | {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, | ||
221 | {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, | ||
222 | {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
223 | {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, | ||
224 | {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, | ||
225 | {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, | ||
226 | {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
227 | {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, | ||
228 | {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, | ||
229 | {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
230 | {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, | ||
231 | {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
232 | {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, | ||
233 | {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, | ||
234 | {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, | ||
235 | {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, | ||
236 | {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, | ||
237 | {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, | ||
238 | {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, | ||
239 | {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
240 | {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
241 | {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
242 | {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, | ||
243 | {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000}, | ||
244 | {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, | ||
245 | {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, | ||
246 | {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, | ||
247 | {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000}, | ||
248 | {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000}, | ||
249 | {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000}, | ||
250 | {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000}, | ||
251 | {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000}, | ||
252 | {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000}, | ||
253 | {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000}, | ||
254 | {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000}, | ||
255 | {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
256 | {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, | ||
257 | {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, | ||
258 | {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, | ||
259 | {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, | ||
260 | {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000}, | ||
261 | {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000}, | ||
262 | {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000}, | ||
263 | {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000}, | ||
264 | {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000}, | ||
265 | {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, | ||
266 | {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, | ||
267 | {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, | ||
268 | {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, | ||
269 | {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, | ||
270 | {.addr = 0x00412810, .prod = 0x0000c242, .disable = 0x00000000}, | ||
271 | {.addr = 0x00412a80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
272 | {.addr = 0x004129a8, .prod = 0x0000c242, .disable = 0x00000000}, | ||
273 | {.addr = 0x00412c10, .prod = 0x0000c242, .disable = 0x00000000}, | ||
274 | {.addr = 0x00412e80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
275 | {.addr = 0x00412da8, .prod = 0x0000c242, .disable = 0x00000000}, | ||
276 | {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, | ||
277 | {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, | ||
278 | {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, | ||
279 | }; | ||
280 | |||
281 | /* blcg ltc */ | ||
282 | static const struct gating_desc gp106_blcg_ltc[] = { | ||
283 | {.addr = 0x00154030, .prod = 0x00000044, .disable = 0x00000000}, | ||
284 | {.addr = 0x00154040, .prod = 0x00000044, .disable = 0x00000000}, | ||
285 | {.addr = 0x001545e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
286 | {.addr = 0x001545c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
287 | {.addr = 0x001547e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
288 | {.addr = 0x001547c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
289 | {.addr = 0x001543e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
290 | {.addr = 0x001543c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
291 | {.addr = 0x00156030, .prod = 0x00000044, .disable = 0x00000000}, | ||
292 | {.addr = 0x00156040, .prod = 0x00000044, .disable = 0x00000000}, | ||
293 | {.addr = 0x001565e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
294 | {.addr = 0x001565c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
295 | {.addr = 0x001567e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
296 | {.addr = 0x001567c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
297 | {.addr = 0x001563e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
298 | {.addr = 0x001563c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
299 | {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, | ||
300 | {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, | ||
301 | {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, | ||
302 | {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, | ||
303 | }; | ||
304 | |||
305 | /* blcg pmu */ | ||
306 | static const struct gating_desc gp106_blcg_pmu[] = { | ||
307 | {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, | ||
308 | }; | ||
309 | |||
310 | /* blcg Xbar */ | ||
311 | static const struct gating_desc gp106_blcg_xbar[] = { | ||
312 | {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000}, | ||
313 | {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000}, | ||
314 | {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000}, | ||
315 | {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, | ||
316 | {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, | ||
317 | {.addr = 0x0013cc20, .prod = 0x00000042, .disable = 0x00000000}, | ||
318 | {.addr = 0x0013cc40, .prod = 0x00000042, .disable = 0x00000000}, | ||
319 | {.addr = 0x0013cc60, .prod = 0x00000042, .disable = 0x00000000}, | ||
320 | {.addr = 0x0013cc80, .prod = 0x00000042, .disable = 0x00000000}, | ||
321 | {.addr = 0x0013cca0, .prod = 0x00000042, .disable = 0x00000000}, | ||
322 | }; | ||
323 | |||
324 | /* pg gr */ | ||
325 | static const struct gating_desc gp106_pg_gr[] = { | ||
326 | }; | ||
327 | |||
328 | /* inline functions */ | ||
329 | void gp106_slcg_bus_load_gating_prod(struct gk20a *g, | ||
330 | bool prod) | ||
331 | { | ||
332 | u32 i; | ||
333 | u32 size = sizeof(gp106_slcg_bus) / sizeof(struct gating_desc); | ||
334 | for (i = 0; i < size; i++) { | ||
335 | if (prod) | ||
336 | gk20a_writel(g, gp106_slcg_bus[i].addr, | ||
337 | gp106_slcg_bus[i].prod); | ||
338 | else | ||
339 | gk20a_writel(g, gp106_slcg_bus[i].addr, | ||
340 | gp106_slcg_bus[i].disable); | ||
341 | } | ||
342 | } | ||
343 | |||
344 | void gp106_slcg_ce2_load_gating_prod(struct gk20a *g, | ||
345 | bool prod) | ||
346 | { | ||
347 | u32 i; | ||
348 | u32 size = sizeof(gp106_slcg_ce2) / sizeof(struct gating_desc); | ||
349 | for (i = 0; i < size; i++) { | ||
350 | if (prod) | ||
351 | gk20a_writel(g, gp106_slcg_ce2[i].addr, | ||
352 | gp106_slcg_ce2[i].prod); | ||
353 | else | ||
354 | gk20a_writel(g, gp106_slcg_ce2[i].addr, | ||
355 | gp106_slcg_ce2[i].disable); | ||
356 | } | ||
357 | } | ||
358 | |||
359 | void gp106_slcg_chiplet_load_gating_prod(struct gk20a *g, | ||
360 | bool prod) | ||
361 | { | ||
362 | u32 i; | ||
363 | u32 size = sizeof(gp106_slcg_chiplet) / sizeof(struct gating_desc); | ||
364 | for (i = 0; i < size; i++) { | ||
365 | if (prod) | ||
366 | gk20a_writel(g, gp106_slcg_chiplet[i].addr, | ||
367 | gp106_slcg_chiplet[i].prod); | ||
368 | else | ||
369 | gk20a_writel(g, gp106_slcg_chiplet[i].addr, | ||
370 | gp106_slcg_chiplet[i].disable); | ||
371 | } | ||
372 | } | ||
373 | |||
374 | void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
375 | bool prod) | ||
376 | { | ||
377 | } | ||
378 | |||
379 | void gp106_slcg_fb_load_gating_prod(struct gk20a *g, | ||
380 | bool prod) | ||
381 | { | ||
382 | u32 i; | ||
383 | u32 size = sizeof(gp106_slcg_fb) / sizeof(struct gating_desc); | ||
384 | for (i = 0; i < size; i++) { | ||
385 | if (prod) | ||
386 | gk20a_writel(g, gp106_slcg_fb[i].addr, | ||
387 | gp106_slcg_fb[i].prod); | ||
388 | else | ||
389 | gk20a_writel(g, gp106_slcg_fb[i].addr, | ||
390 | gp106_slcg_fb[i].disable); | ||
391 | } | ||
392 | } | ||
393 | |||
394 | void gp106_slcg_fifo_load_gating_prod(struct gk20a *g, | ||
395 | bool prod) | ||
396 | { | ||
397 | u32 i; | ||
398 | u32 size = sizeof(gp106_slcg_fifo) / sizeof(struct gating_desc); | ||
399 | for (i = 0; i < size; i++) { | ||
400 | if (prod) | ||
401 | gk20a_writel(g, gp106_slcg_fifo[i].addr, | ||
402 | gp106_slcg_fifo[i].prod); | ||
403 | else | ||
404 | gk20a_writel(g, gp106_slcg_fifo[i].addr, | ||
405 | gp106_slcg_fifo[i].disable); | ||
406 | } | ||
407 | } | ||
408 | |||
409 | void gr_gp106_slcg_gr_load_gating_prod(struct gk20a *g, | ||
410 | bool prod) | ||
411 | { | ||
412 | u32 i; | ||
413 | u32 size = sizeof(gp106_slcg_gr) / sizeof(struct gating_desc); | ||
414 | for (i = 0; i < size; i++) { | ||
415 | if (prod) | ||
416 | gk20a_writel(g, gp106_slcg_gr[i].addr, | ||
417 | gp106_slcg_gr[i].prod); | ||
418 | else | ||
419 | gk20a_writel(g, gp106_slcg_gr[i].addr, | ||
420 | gp106_slcg_gr[i].disable); | ||
421 | } | ||
422 | } | ||
423 | |||
424 | void ltc_gp106_slcg_ltc_load_gating_prod(struct gk20a *g, | ||
425 | bool prod) | ||
426 | { | ||
427 | u32 i; | ||
428 | u32 size = sizeof(gp106_slcg_ltc) / sizeof(struct gating_desc); | ||
429 | for (i = 0; i < size; i++) { | ||
430 | if (prod) | ||
431 | gk20a_writel(g, gp106_slcg_ltc[i].addr, | ||
432 | gp106_slcg_ltc[i].prod); | ||
433 | else | ||
434 | gk20a_writel(g, gp106_slcg_ltc[i].addr, | ||
435 | gp106_slcg_ltc[i].disable); | ||
436 | } | ||
437 | } | ||
438 | |||
439 | void gp106_slcg_perf_load_gating_prod(struct gk20a *g, | ||
440 | bool prod) | ||
441 | { | ||
442 | u32 i; | ||
443 | u32 size = sizeof(gp106_slcg_perf) / sizeof(struct gating_desc); | ||
444 | for (i = 0; i < size; i++) { | ||
445 | if (prod) | ||
446 | gk20a_writel(g, gp106_slcg_perf[i].addr, | ||
447 | gp106_slcg_perf[i].prod); | ||
448 | else | ||
449 | gk20a_writel(g, gp106_slcg_perf[i].addr, | ||
450 | gp106_slcg_perf[i].disable); | ||
451 | } | ||
452 | } | ||
453 | |||
454 | void gp106_slcg_priring_load_gating_prod(struct gk20a *g, | ||
455 | bool prod) | ||
456 | { | ||
457 | u32 i; | ||
458 | u32 size = sizeof(gp106_slcg_priring) / sizeof(struct gating_desc); | ||
459 | for (i = 0; i < size; i++) { | ||
460 | if (prod) | ||
461 | gk20a_writel(g, gp106_slcg_priring[i].addr, | ||
462 | gp106_slcg_priring[i].prod); | ||
463 | else | ||
464 | gk20a_writel(g, gp106_slcg_priring[i].addr, | ||
465 | gp106_slcg_priring[i].disable); | ||
466 | } | ||
467 | } | ||
468 | |||
469 | void gp106_slcg_pmu_load_gating_prod(struct gk20a *g, | ||
470 | bool prod) | ||
471 | { | ||
472 | u32 i; | ||
473 | u32 size = sizeof(gp106_slcg_pmu) / sizeof(struct gating_desc); | ||
474 | for (i = 0; i < size; i++) { | ||
475 | if (prod) | ||
476 | gk20a_writel(g, gp106_slcg_pmu[i].addr, | ||
477 | gp106_slcg_pmu[i].prod); | ||
478 | else | ||
479 | gk20a_writel(g, gp106_slcg_pmu[i].addr, | ||
480 | gp106_slcg_pmu[i].disable); | ||
481 | } | ||
482 | } | ||
483 | |||
484 | void gp106_slcg_therm_load_gating_prod(struct gk20a *g, | ||
485 | bool prod) | ||
486 | { | ||
487 | u32 i; | ||
488 | u32 size = sizeof(gp106_slcg_therm) / sizeof(struct gating_desc); | ||
489 | for (i = 0; i < size; i++) { | ||
490 | if (prod) | ||
491 | gk20a_writel(g, gp106_slcg_therm[i].addr, | ||
492 | gp106_slcg_therm[i].prod); | ||
493 | else | ||
494 | gk20a_writel(g, gp106_slcg_therm[i].addr, | ||
495 | gp106_slcg_therm[i].disable); | ||
496 | } | ||
497 | } | ||
498 | |||
499 | void gp106_slcg_xbar_load_gating_prod(struct gk20a *g, | ||
500 | bool prod) | ||
501 | { | ||
502 | u32 i; | ||
503 | u32 size = sizeof(gp106_slcg_xbar) / sizeof(struct gating_desc); | ||
504 | for (i = 0; i < size; i++) { | ||
505 | if (prod) | ||
506 | gk20a_writel(g, gp106_slcg_xbar[i].addr, | ||
507 | gp106_slcg_xbar[i].prod); | ||
508 | else | ||
509 | gk20a_writel(g, gp106_slcg_xbar[i].addr, | ||
510 | gp106_slcg_xbar[i].disable); | ||
511 | } | ||
512 | } | ||
513 | |||
514 | void gp106_blcg_bus_load_gating_prod(struct gk20a *g, | ||
515 | bool prod) | ||
516 | { | ||
517 | u32 i; | ||
518 | u32 size = sizeof(gp106_blcg_bus) / sizeof(struct gating_desc); | ||
519 | for (i = 0; i < size; i++) { | ||
520 | if (prod) | ||
521 | gk20a_writel(g, gp106_blcg_bus[i].addr, | ||
522 | gp106_blcg_bus[i].prod); | ||
523 | else | ||
524 | gk20a_writel(g, gp106_blcg_bus[i].addr, | ||
525 | gp106_blcg_bus[i].disable); | ||
526 | } | ||
527 | } | ||
528 | |||
529 | void gp106_blcg_ce_load_gating_prod(struct gk20a *g, | ||
530 | bool prod) | ||
531 | { | ||
532 | u32 i; | ||
533 | u32 size = sizeof(gp106_blcg_ce) / sizeof(struct gating_desc); | ||
534 | for (i = 0; i < size; i++) { | ||
535 | if (prod) | ||
536 | gk20a_writel(g, gp106_blcg_ce[i].addr, | ||
537 | gp106_blcg_ce[i].prod); | ||
538 | else | ||
539 | gk20a_writel(g, gp106_blcg_ce[i].addr, | ||
540 | gp106_blcg_ce[i].disable); | ||
541 | } | ||
542 | } | ||
543 | |||
544 | void gp106_blcg_fb_load_gating_prod(struct gk20a *g, | ||
545 | bool prod) | ||
546 | { | ||
547 | u32 i; | ||
548 | u32 size = sizeof(gp106_blcg_fb) / sizeof(struct gating_desc); | ||
549 | for (i = 0; i < size; i++) { | ||
550 | if (prod) | ||
551 | gk20a_writel(g, gp106_blcg_fb[i].addr, | ||
552 | gp106_blcg_fb[i].prod); | ||
553 | else | ||
554 | gk20a_writel(g, gp106_blcg_fb[i].addr, | ||
555 | gp106_blcg_fb[i].disable); | ||
556 | } | ||
557 | } | ||
558 | |||
559 | void gp106_blcg_fifo_load_gating_prod(struct gk20a *g, | ||
560 | bool prod) | ||
561 | { | ||
562 | u32 i; | ||
563 | u32 size = sizeof(gp106_blcg_fifo) / sizeof(struct gating_desc); | ||
564 | for (i = 0; i < size; i++) { | ||
565 | if (prod) | ||
566 | gk20a_writel(g, gp106_blcg_fifo[i].addr, | ||
567 | gp106_blcg_fifo[i].prod); | ||
568 | else | ||
569 | gk20a_writel(g, gp106_blcg_fifo[i].addr, | ||
570 | gp106_blcg_fifo[i].disable); | ||
571 | } | ||
572 | } | ||
573 | |||
574 | void gp106_blcg_gr_load_gating_prod(struct gk20a *g, | ||
575 | bool prod) | ||
576 | { | ||
577 | u32 i; | ||
578 | u32 size = sizeof(gp106_blcg_gr) / sizeof(struct gating_desc); | ||
579 | for (i = 0; i < size; i++) { | ||
580 | if (prod) | ||
581 | gk20a_writel(g, gp106_blcg_gr[i].addr, | ||
582 | gp106_blcg_gr[i].prod); | ||
583 | else | ||
584 | gk20a_writel(g, gp106_blcg_gr[i].addr, | ||
585 | gp106_blcg_gr[i].disable); | ||
586 | } | ||
587 | } | ||
588 | |||
589 | void gp106_blcg_ltc_load_gating_prod(struct gk20a *g, | ||
590 | bool prod) | ||
591 | { | ||
592 | u32 i; | ||
593 | u32 size = sizeof(gp106_blcg_ltc) / sizeof(struct gating_desc); | ||
594 | for (i = 0; i < size; i++) { | ||
595 | if (prod) | ||
596 | gk20a_writel(g, gp106_blcg_ltc[i].addr, | ||
597 | gp106_blcg_ltc[i].prod); | ||
598 | else | ||
599 | gk20a_writel(g, gp106_blcg_ltc[i].addr, | ||
600 | gp106_blcg_ltc[i].disable); | ||
601 | } | ||
602 | } | ||
603 | |||
604 | void gp106_blcg_pmu_load_gating_prod(struct gk20a *g, | ||
605 | bool prod) | ||
606 | { | ||
607 | u32 i; | ||
608 | u32 size = sizeof(gp106_blcg_pmu) / sizeof(struct gating_desc); | ||
609 | for (i = 0; i < size; i++) { | ||
610 | if (prod) | ||
611 | gk20a_writel(g, gp106_blcg_pmu[i].addr, | ||
612 | gp106_blcg_pmu[i].prod); | ||
613 | else | ||
614 | gk20a_writel(g, gp106_blcg_pmu[i].addr, | ||
615 | gp106_blcg_pmu[i].disable); | ||
616 | } | ||
617 | } | ||
618 | |||
619 | void gp106_blcg_xbar_load_gating_prod(struct gk20a *g, | ||
620 | bool prod) | ||
621 | { | ||
622 | u32 i; | ||
623 | u32 size = sizeof(gp106_blcg_xbar) / sizeof(struct gating_desc); | ||
624 | for (i = 0; i < size; i++) { | ||
625 | if (prod) | ||
626 | gk20a_writel(g, gp106_blcg_xbar[i].addr, | ||
627 | gp106_blcg_xbar[i].prod); | ||
628 | else | ||
629 | gk20a_writel(g, gp106_blcg_xbar[i].addr, | ||
630 | gp106_blcg_xbar[i].disable); | ||
631 | } | ||
632 | } | ||
633 | |||
634 | void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g, | ||
635 | bool prod) | ||
636 | { | ||
637 | u32 i; | ||
638 | u32 size = sizeof(gp106_pg_gr) / sizeof(struct gating_desc); | ||
639 | for (i = 0; i < size; i++) { | ||
640 | if (prod) | ||
641 | gk20a_writel(g, gp106_pg_gr[i].addr, | ||
642 | gp106_pg_gr[i].prod); | ||
643 | else | ||
644 | gk20a_writel(g, gp106_pg_gr[i].addr, | ||
645 | gp106_pg_gr[i].disable); | ||
646 | } | ||
647 | } | ||
648 | |||
649 | #endif /* __gp106_gating_reglist_h__ */ | ||
diff --git a/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.h b/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.h new file mode 100644 index 00000000..423ccf54 --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.h | |||
@@ -0,0 +1,87 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include "gk20a/gk20a.h" | ||
18 | |||
19 | void gp106_slcg_bus_load_gating_prod(struct gk20a *g, | ||
20 | bool prod); | ||
21 | |||
22 | void gp106_slcg_ce2_load_gating_prod(struct gk20a *g, | ||
23 | bool prod); | ||
24 | |||
25 | void gp106_slcg_chiplet_load_gating_prod(struct gk20a *g, | ||
26 | bool prod); | ||
27 | |||
28 | void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
29 | bool prod); | ||
30 | |||
31 | void gp106_slcg_fb_load_gating_prod(struct gk20a *g, | ||
32 | bool prod); | ||
33 | |||
34 | void gp106_slcg_fifo_load_gating_prod(struct gk20a *g, | ||
35 | bool prod); | ||
36 | |||
37 | void gr_gp106_slcg_gr_load_gating_prod(struct gk20a *g, | ||
38 | bool prod); | ||
39 | |||
40 | void ltc_gp106_slcg_ltc_load_gating_prod(struct gk20a *g, | ||
41 | bool prod); | ||
42 | |||
43 | void gp106_slcg_perf_load_gating_prod(struct gk20a *g, | ||
44 | bool prod); | ||
45 | |||
46 | void gp106_slcg_priring_load_gating_prod(struct gk20a *g, | ||
47 | bool prod); | ||
48 | |||
49 | void gp106_slcg_pmu_load_gating_prod(struct gk20a *g, | ||
50 | bool prod); | ||
51 | |||
52 | void gp106_slcg_therm_load_gating_prod(struct gk20a *g, | ||
53 | bool prod); | ||
54 | |||
55 | void gp106_slcg_xbar_load_gating_prod(struct gk20a *g, | ||
56 | bool prod); | ||
57 | |||
58 | void gp106_blcg_bus_load_gating_prod(struct gk20a *g, | ||
59 | bool prod); | ||
60 | |||
61 | void gp106_blcg_ce_load_gating_prod(struct gk20a *g, | ||
62 | bool prod); | ||
63 | |||
64 | void gp106_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | ||
65 | bool prod); | ||
66 | |||
67 | void gp106_blcg_fb_load_gating_prod(struct gk20a *g, | ||
68 | bool prod); | ||
69 | |||
70 | void gp106_blcg_fifo_load_gating_prod(struct gk20a *g, | ||
71 | bool prod); | ||
72 | |||
73 | void gp106_blcg_gr_load_gating_prod(struct gk20a *g, | ||
74 | bool prod); | ||
75 | |||
76 | void gp106_blcg_ltc_load_gating_prod(struct gk20a *g, | ||
77 | bool prod); | ||
78 | |||
79 | void gp106_blcg_pmu_load_gating_prod(struct gk20a *g, | ||
80 | bool prod); | ||
81 | |||
82 | void gp106_blcg_xbar_load_gating_prod(struct gk20a *g, | ||
83 | bool prod); | ||
84 | |||
85 | void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g, | ||
86 | bool prod); | ||
87 | |||
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 5f15a2c8..eb5c4eba 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -26,7 +26,6 @@ | |||
26 | #include "gp10b/mm_gp10b.h" | 26 | #include "gp10b/mm_gp10b.h" |
27 | #include "gp10b/ce_gp10b.h" | 27 | #include "gp10b/ce_gp10b.h" |
28 | #include "gp106/fifo_gp106.h" | 28 | #include "gp106/fifo_gp106.h" |
29 | #include "gp10b/gp10b_gating_reglist.h" | ||
30 | #include "gp10b/regops_gp10b.h" | 29 | #include "gp10b/regops_gp10b.h" |
31 | #include "gp10b/cde_gp10b.h" | 30 | #include "gp10b/cde_gp10b.h" |
32 | #include "gp10b/therm_gp10b.h" | 31 | #include "gp10b/therm_gp10b.h" |
@@ -43,13 +42,59 @@ | |||
43 | #include "gp106/gr_ctx_gp106.h" | 42 | #include "gp106/gr_ctx_gp106.h" |
44 | #include "gp106/gr_gp106.h" | 43 | #include "gp106/gr_gp106.h" |
45 | #include "gp106/fb_gp106.h" | 44 | #include "gp106/fb_gp106.h" |
45 | #include "gp106/gp106_gating_reglist.h" | ||
46 | #include "nvgpu_gpuid_t18x.h" | 46 | #include "nvgpu_gpuid_t18x.h" |
47 | #include "hw_proj_gp106.h" | 47 | #include "hw_proj_gp106.h" |
48 | #include "gk20a/dbg_gpu_gk20a.h" | 48 | #include "gk20a/dbg_gpu_gk20a.h" |
49 | #include "gk20a/css_gr_gk20a.h" | 49 | #include "gk20a/css_gr_gk20a.h" |
50 | 50 | ||
51 | static struct gpu_ops gp106_ops = { | 51 | static struct gpu_ops gp106_ops = { |
52 | .clock_gating = { } | 52 | .clock_gating = { |
53 | .slcg_bus_load_gating_prod = | ||
54 | gp106_slcg_bus_load_gating_prod, | ||
55 | .slcg_ce2_load_gating_prod = | ||
56 | gp106_slcg_ce2_load_gating_prod, | ||
57 | .slcg_chiplet_load_gating_prod = | ||
58 | gp106_slcg_chiplet_load_gating_prod, | ||
59 | .slcg_ctxsw_firmware_load_gating_prod = | ||
60 | gp106_slcg_ctxsw_firmware_load_gating_prod, | ||
61 | .slcg_fb_load_gating_prod = | ||
62 | gp106_slcg_fb_load_gating_prod, | ||
63 | .slcg_fifo_load_gating_prod = | ||
64 | gp106_slcg_fifo_load_gating_prod, | ||
65 | .slcg_gr_load_gating_prod = | ||
66 | gr_gp106_slcg_gr_load_gating_prod, | ||
67 | .slcg_ltc_load_gating_prod = | ||
68 | ltc_gp106_slcg_ltc_load_gating_prod, | ||
69 | .slcg_perf_load_gating_prod = | ||
70 | gp106_slcg_perf_load_gating_prod, | ||
71 | .slcg_priring_load_gating_prod = | ||
72 | gp106_slcg_priring_load_gating_prod, | ||
73 | .slcg_pmu_load_gating_prod = | ||
74 | gp106_slcg_pmu_load_gating_prod, | ||
75 | .slcg_therm_load_gating_prod = | ||
76 | gp106_slcg_therm_load_gating_prod, | ||
77 | .slcg_xbar_load_gating_prod = | ||
78 | gp106_slcg_xbar_load_gating_prod, | ||
79 | .blcg_bus_load_gating_prod = | ||
80 | gp106_blcg_bus_load_gating_prod, | ||
81 | .blcg_ce_load_gating_prod = | ||
82 | gp106_blcg_ce_load_gating_prod, | ||
83 | .blcg_fb_load_gating_prod = | ||
84 | gp106_blcg_fb_load_gating_prod, | ||
85 | .blcg_fifo_load_gating_prod = | ||
86 | gp106_blcg_fifo_load_gating_prod, | ||
87 | .blcg_gr_load_gating_prod = | ||
88 | gp106_blcg_gr_load_gating_prod, | ||
89 | .blcg_ltc_load_gating_prod = | ||
90 | gp106_blcg_ltc_load_gating_prod, | ||
91 | .blcg_pmu_load_gating_prod = | ||
92 | gp106_blcg_pmu_load_gating_prod, | ||
93 | .blcg_xbar_load_gating_prod = | ||
94 | gp106_blcg_xbar_load_gating_prod, | ||
95 | .pg_gr_load_gating_prod = | ||
96 | gr_gp106_pg_gr_load_gating_prod, | ||
97 | } | ||
53 | }; | 98 | }; |
54 | 99 | ||
55 | static int gp106_get_litter_value(struct gk20a *g, | 100 | static int gp106_get_litter_value(struct gk20a *g, |