diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index b69618ae..d4b31c86 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -5837,19 +5837,14 @@ static int gk20a_gr_handle_gpc_exception(struct gk20a *g, bool *post_event, | |||
5837 | return ret; | 5837 | return ret; |
5838 | } | 5838 | } |
5839 | 5839 | ||
5840 | static int gk20a_gr_post_bpt_events(struct gk20a *g, struct channel_gk20a *ch, | 5840 | static int gk20a_gr_post_bpt_events(struct gk20a *g, struct tsg_gk20a *tsg, |
5841 | u32 global_esr) | 5841 | u32 global_esr) |
5842 | { | 5842 | { |
5843 | if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()) { | 5843 | if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()) |
5844 | struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; | ||
5845 | |||
5846 | g->ops.fifo.post_event_id(tsg, NVGPU_EVENT_ID_BPT_INT); | 5844 | g->ops.fifo.post_event_id(tsg, NVGPU_EVENT_ID_BPT_INT); |
5847 | } | ||
5848 | if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f()) { | ||
5849 | struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; | ||
5850 | 5845 | ||
5846 | if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f()) | ||
5851 | g->ops.fifo.post_event_id(tsg, NVGPU_EVENT_ID_BPT_PAUSE); | 5847 | g->ops.fifo.post_event_id(tsg, NVGPU_EVENT_ID_BPT_PAUSE); |
5852 | } | ||
5853 | 5848 | ||
5854 | return 0; | 5849 | return 0; |
5855 | } | 5850 | } |
@@ -5864,6 +5859,7 @@ int gk20a_gr_isr(struct gk20a *g) | |||
5864 | struct channel_gk20a *ch = NULL; | 5859 | struct channel_gk20a *ch = NULL; |
5865 | struct channel_gk20a *fault_ch = NULL; | 5860 | struct channel_gk20a *fault_ch = NULL; |
5866 | int tsgid = NVGPU_INVALID_TSG_ID; | 5861 | int tsgid = NVGPU_INVALID_TSG_ID; |
5862 | struct tsg_gk20a *tsg = NULL; | ||
5867 | u32 gr_engine_id; | 5863 | u32 gr_engine_id; |
5868 | u32 global_esr = 0; | 5864 | u32 global_esr = 0; |
5869 | 5865 | ||
@@ -5903,6 +5899,9 @@ int gk20a_gr_isr(struct gk20a *g) | |||
5903 | nvgpu_err(g, "ch id is INVALID 0xffffffff"); | 5899 | nvgpu_err(g, "ch id is INVALID 0xffffffff"); |
5904 | } | 5900 | } |
5905 | 5901 | ||
5902 | if (ch && gk20a_is_channel_marked_as_tsg(ch)) | ||
5903 | tsg = &g->fifo.tsg[ch->tsgid]; | ||
5904 | |||
5906 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, | 5905 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, |
5907 | "channel %d: addr 0x%08x, " | 5906 | "channel %d: addr 0x%08x, " |
5908 | "data 0x%08x 0x%08x," | 5907 | "data 0x%08x 0x%08x," |
@@ -6126,8 +6125,8 @@ int gk20a_gr_isr(struct gk20a *g) | |||
6126 | "unhandled gr interrupt 0x%08x", gr_intr); | 6125 | "unhandled gr interrupt 0x%08x", gr_intr); |
6127 | 6126 | ||
6128 | /* Posting of BPT events should be the last thing in this function */ | 6127 | /* Posting of BPT events should be the last thing in this function */ |
6129 | if (global_esr && fault_ch) | 6128 | if (global_esr && tsg) |
6130 | gk20a_gr_post_bpt_events(g, fault_ch, global_esr); | 6129 | gk20a_gr_post_bpt_events(g, tsg, global_esr); |
6131 | 6130 | ||
6132 | if (ch) | 6131 | if (ch) |
6133 | gk20a_channel_put(ch); | 6132 | gk20a_channel_put(ch); |