diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 106 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 153 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 70 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/mm_gm20b.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 9 |
7 files changed, 233 insertions, 127 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index a9311759..916e7a66 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -238,8 +238,9 @@ static int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) | |||
238 | struct nvgpu_firmware *gpccs_sig; | 238 | struct nvgpu_firmware *gpccs_sig; |
239 | int err; | 239 | int err; |
240 | 240 | ||
241 | if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) | 241 | if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { |
242 | return -ENOENT; | 242 | return -ENOENT; |
243 | } | ||
243 | 244 | ||
244 | gpccs_sig = nvgpu_request_firmware(g, T18x_GPCCS_UCODE_SIG, 0); | 245 | gpccs_sig = nvgpu_request_firmware(g, T18x_GPCCS_UCODE_SIG, 0); |
245 | if (!gpccs_sig) { | 246 | if (!gpccs_sig) { |
@@ -381,20 +382,23 @@ int prepare_ucode_blob(struct gk20a *g) | |||
381 | /* Discover all managed falcons*/ | 382 | /* Discover all managed falcons*/ |
382 | err = lsfm_discover_ucode_images(g, plsfm); | 383 | err = lsfm_discover_ucode_images(g, plsfm); |
383 | gm20b_dbg_pmu(g, " Managed Falcon cnt %d\n", plsfm->managed_flcn_cnt); | 384 | gm20b_dbg_pmu(g, " Managed Falcon cnt %d\n", plsfm->managed_flcn_cnt); |
384 | if (err) | 385 | if (err) { |
385 | goto free_sgt; | 386 | goto free_sgt; |
387 | } | ||
386 | 388 | ||
387 | if (plsfm->managed_flcn_cnt && !g->acr.ucode_blob.cpu_va) { | 389 | if (plsfm->managed_flcn_cnt && !g->acr.ucode_blob.cpu_va) { |
388 | /* Generate WPR requirements*/ | 390 | /* Generate WPR requirements*/ |
389 | err = lsf_gen_wpr_requirements(g, plsfm); | 391 | err = lsf_gen_wpr_requirements(g, plsfm); |
390 | if (err) | 392 | if (err) { |
391 | goto free_sgt; | 393 | goto free_sgt; |
394 | } | ||
392 | 395 | ||
393 | /*Alloc memory to hold ucode blob contents*/ | 396 | /*Alloc memory to hold ucode blob contents*/ |
394 | err = g->ops.pmu.alloc_blob_space(g, plsfm->wpr_size | 397 | err = g->ops.pmu.alloc_blob_space(g, plsfm->wpr_size |
395 | , &g->acr.ucode_blob); | 398 | , &g->acr.ucode_blob); |
396 | if (err) | 399 | if (err) { |
397 | goto free_sgt; | 400 | goto free_sgt; |
401 | } | ||
398 | 402 | ||
399 | gm20b_dbg_pmu(g, "managed LS falcon %d, WPR size %d bytes.\n", | 403 | gm20b_dbg_pmu(g, "managed LS falcon %d, WPR size %d bytes.\n", |
400 | plsfm->managed_flcn_cnt, plsfm->wpr_size); | 404 | plsfm->managed_flcn_cnt, plsfm->wpr_size); |
@@ -428,8 +432,9 @@ static int lsfm_discover_ucode_images(struct gk20a *g, | |||
428 | /* Obtain the PMU ucode image and add it to the list if required*/ | 432 | /* Obtain the PMU ucode image and add it to the list if required*/ |
429 | memset(&ucode_img, 0, sizeof(ucode_img)); | 433 | memset(&ucode_img, 0, sizeof(ucode_img)); |
430 | status = pmu_ucode_details(g, &ucode_img); | 434 | status = pmu_ucode_details(g, &ucode_img); |
431 | if (status) | 435 | if (status) { |
432 | return status; | 436 | return status; |
437 | } | ||
433 | 438 | ||
434 | /* The falon_id is formed by grabbing the static base | 439 | /* The falon_id is formed by grabbing the static base |
435 | * falon_id from the image and adding the | 440 | * falon_id from the image and adding the |
@@ -441,8 +446,9 @@ static int lsfm_discover_ucode_images(struct gk20a *g, | |||
441 | if (!lsfm_falcon_disabled(g, plsfm, falcon_id)) { | 446 | if (!lsfm_falcon_disabled(g, plsfm, falcon_id)) { |
442 | pmu->falcon_id = falcon_id; | 447 | pmu->falcon_id = falcon_id; |
443 | if (lsfm_add_ucode_img(g, plsfm, &ucode_img, | 448 | if (lsfm_add_ucode_img(g, plsfm, &ucode_img, |
444 | pmu->falcon_id) == 0) | 449 | pmu->falcon_id) == 0) { |
445 | pmu->pmu_mode |= PMU_LSFM_MANAGED; | 450 | pmu->pmu_mode |= PMU_LSFM_MANAGED; |
451 | } | ||
446 | 452 | ||
447 | plsfm->managed_flcn_cnt++; | 453 | plsfm->managed_flcn_cnt++; |
448 | } else { | 454 | } else { |
@@ -480,8 +486,9 @@ static int lsfm_discover_ucode_images(struct gk20a *g, | |||
480 | /* Do not manage non-FB ucode*/ | 486 | /* Do not manage non-FB ucode*/ |
481 | if (lsfm_add_ucode_img(g, | 487 | if (lsfm_add_ucode_img(g, |
482 | plsfm, &ucode_img, falcon_id) | 488 | plsfm, &ucode_img, falcon_id) |
483 | == 0) | 489 | == 0) { |
484 | plsfm->managed_flcn_cnt++; | 490 | plsfm->managed_flcn_cnt++; |
491 | } | ||
485 | } else { | 492 | } else { |
486 | gm20b_dbg_pmu(g, "not managed %d\n", | 493 | gm20b_dbg_pmu(g, "not managed %d\n", |
487 | ucode_img.lsf_desc->falcon_id); | 494 | ucode_img.lsf_desc->falcon_id); |
@@ -513,18 +520,22 @@ int gm20b_pmu_populate_loader_cfg(struct gk20a *g, | |||
513 | u64 addr_code, addr_data; | 520 | u64 addr_code, addr_data; |
514 | u32 addr_args; | 521 | u32 addr_args; |
515 | 522 | ||
516 | if (p_img->desc == NULL) /*This means its a header based ucode, | 523 | if (p_img->desc == NULL) { |
517 | and so we do not fill BL gen desc structure*/ | 524 | /* |
525 | * This means its a header based ucode, | ||
526 | * and so we do not fill BL gen desc structure | ||
527 | */ | ||
518 | return -EINVAL; | 528 | return -EINVAL; |
529 | } | ||
519 | desc = p_img->desc; | 530 | desc = p_img->desc; |
520 | /* | 531 | /* |
521 | Calculate physical and virtual addresses for various portions of | 532 | * Calculate physical and virtual addresses for various portions of |
522 | the PMU ucode image | 533 | * the PMU ucode image |
523 | Calculate the 32-bit addresses for the application code, application | 534 | * Calculate the 32-bit addresses for the application code, application |
524 | data, and bootloader code. These values are all based on IM_BASE. | 535 | * data, and bootloader code. These values are all based on IM_BASE. |
525 | The 32-bit addresses will be the upper 32-bits of the virtual or | 536 | * The 32-bit addresses will be the upper 32-bits of the virtual or |
526 | physical addresses of each respective segment. | 537 | * physical addresses of each respective segment. |
527 | */ | 538 | */ |
528 | addr_base = p_lsfm->lsb_header.ucode_off; | 539 | addr_base = p_lsfm->lsb_header.ucode_off; |
529 | g->ops.pmu.get_wpr(g, &wpr_inf); | 540 | g->ops.pmu.get_wpr(g, &wpr_inf); |
530 | addr_base += wpr_inf.wpr_base; | 541 | addr_base += wpr_inf.wpr_base; |
@@ -584,19 +595,23 @@ int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, | |||
584 | struct pmu_ucode_desc *desc; | 595 | struct pmu_ucode_desc *desc; |
585 | u64 addr_code, addr_data; | 596 | u64 addr_code, addr_data; |
586 | 597 | ||
587 | if (p_img->desc == NULL) /*This means its a header based ucode, | 598 | if (p_img->desc == NULL) { |
588 | and so we do not fill BL gen desc structure*/ | 599 | /* |
600 | * This means its a header based ucode, | ||
601 | * and so we do not fill BL gen desc structure | ||
602 | */ | ||
589 | return -EINVAL; | 603 | return -EINVAL; |
604 | } | ||
590 | desc = p_img->desc; | 605 | desc = p_img->desc; |
591 | 606 | ||
592 | /* | 607 | /* |
593 | Calculate physical and virtual addresses for various portions of | 608 | * Calculate physical and virtual addresses for various portions of |
594 | the PMU ucode image | 609 | * the PMU ucode image |
595 | Calculate the 32-bit addresses for the application code, application | 610 | * Calculate the 32-bit addresses for the application code, application |
596 | data, and bootloader code. These values are all based on IM_BASE. | 611 | * data, and bootloader code. These values are all based on IM_BASE. |
597 | The 32-bit addresses will be the upper 32-bits of the virtual or | 612 | * The 32-bit addresses will be the upper 32-bits of the virtual or |
598 | physical addresses of each respective segment. | 613 | * physical addresses of each respective segment. |
599 | */ | 614 | */ |
600 | addr_base = p_lsfm->lsb_header.ucode_off; | 615 | addr_base = p_lsfm->lsb_header.ucode_off; |
601 | g->ops.pmu.get_wpr(g, &wpr_inf); | 616 | g->ops.pmu.get_wpr(g, &wpr_inf); |
602 | addr_base += wpr_inf.wpr_base; | 617 | addr_base += wpr_inf.wpr_base; |
@@ -642,9 +657,10 @@ static int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g, | |||
642 | 657 | ||
643 | if (pmu->pmu_mode & PMU_LSFM_MANAGED) { | 658 | if (pmu->pmu_mode & PMU_LSFM_MANAGED) { |
644 | gm20b_dbg_pmu(g, "pmu write flcn bl gen desc\n"); | 659 | gm20b_dbg_pmu(g, "pmu write flcn bl gen desc\n"); |
645 | if (pnode->wpr_header.falcon_id == pmu->falcon_id) | 660 | if (pnode->wpr_header.falcon_id == pmu->falcon_id) { |
646 | return g->ops.pmu.pmu_populate_loader_cfg(g, pnode, | 661 | return g->ops.pmu.pmu_populate_loader_cfg(g, pnode, |
647 | &pnode->bl_gen_desc_size); | 662 | &pnode->bl_gen_desc_size); |
663 | } | ||
648 | } | 664 | } |
649 | 665 | ||
650 | /* Failed to find the falcon requested. */ | 666 | /* Failed to find the falcon requested. */ |
@@ -795,9 +811,10 @@ static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g, | |||
795 | u32 full_app_size = 0; | 811 | u32 full_app_size = 0; |
796 | u32 data = 0; | 812 | u32 data = 0; |
797 | 813 | ||
798 | if (pnode->ucode_img.lsf_desc) | 814 | if (pnode->ucode_img.lsf_desc) { |
799 | memcpy(&pnode->lsb_header.signature, pnode->ucode_img.lsf_desc, | 815 | memcpy(&pnode->lsb_header.signature, pnode->ucode_img.lsf_desc, |
800 | sizeof(struct lsf_ucode_desc)); | 816 | sizeof(struct lsf_ucode_desc)); |
817 | } | ||
801 | pnode->lsb_header.ucode_size = pnode->ucode_img.data_size; | 818 | pnode->lsb_header.ucode_size = pnode->ucode_img.data_size; |
802 | 819 | ||
803 | /* The remainder of the LSB depends on the loader usage */ | 820 | /* The remainder of the LSB depends on the loader usage */ |
@@ -865,8 +882,9 @@ static int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr *plsfm, | |||
865 | 882 | ||
866 | struct lsfm_managed_ucode_img *pnode; | 883 | struct lsfm_managed_ucode_img *pnode; |
867 | pnode = nvgpu_kzalloc(g, sizeof(struct lsfm_managed_ucode_img)); | 884 | pnode = nvgpu_kzalloc(g, sizeof(struct lsfm_managed_ucode_img)); |
868 | if (pnode == NULL) | 885 | if (pnode == NULL) { |
869 | return -ENOMEM; | 886 | return -ENOMEM; |
887 | } | ||
870 | 888 | ||
871 | /* Keep a copy of the ucode image info locally */ | 889 | /* Keep a copy of the ucode image info locally */ |
872 | memcpy(&pnode->ucode_img, ucode_image, sizeof(struct flcn_ucode_img)); | 890 | memcpy(&pnode->ucode_img, ucode_image, sizeof(struct flcn_ucode_img)); |
@@ -919,11 +937,12 @@ static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr *plsfm) | |||
919 | while (cnt) { | 937 | while (cnt) { |
920 | mg_ucode_img = plsfm->ucode_img_list; | 938 | mg_ucode_img = plsfm->ucode_img_list; |
921 | if (mg_ucode_img->ucode_img.lsf_desc->falcon_id == | 939 | if (mg_ucode_img->ucode_img.lsf_desc->falcon_id == |
922 | LSF_FALCON_ID_PMU) | 940 | LSF_FALCON_ID_PMU) { |
923 | lsfm_free_ucode_img_res(g, &mg_ucode_img->ucode_img); | 941 | lsfm_free_ucode_img_res(g, &mg_ucode_img->ucode_img); |
924 | else | 942 | } else { |
925 | lsfm_free_nonpmu_ucode_img_res(g, | 943 | lsfm_free_nonpmu_ucode_img_res(g, |
926 | &mg_ucode_img->ucode_img); | 944 | &mg_ucode_img->ucode_img); |
945 | } | ||
927 | plsfm->ucode_img_list = mg_ucode_img->next; | 946 | plsfm->ucode_img_list = mg_ucode_img->next; |
928 | nvgpu_kfree(g, mg_ucode_img); | 947 | nvgpu_kfree(g, mg_ucode_img); |
929 | cnt--; | 948 | cnt--; |
@@ -1110,8 +1129,9 @@ int gm20b_bootstrap_hs_flcn(struct gk20a *g) | |||
1110 | ((acr_ucode_header_t210_load[2]) >> 8); | 1129 | ((acr_ucode_header_t210_load[2]) >> 8); |
1111 | bl_dmem_desc->data_dma_base1 = 0x0; | 1130 | bl_dmem_desc->data_dma_base1 = 0x0; |
1112 | bl_dmem_desc->data_size = acr_ucode_header_t210_load[3]; | 1131 | bl_dmem_desc->data_size = acr_ucode_header_t210_load[3]; |
1113 | } else | 1132 | } else { |
1114 | acr->acr_dmem_desc->nonwpr_ucode_blob_size = 0; | 1133 | acr->acr_dmem_desc->nonwpr_ucode_blob_size = 0; |
1134 | } | ||
1115 | status = pmu_exec_gen_bl(g, bl_dmem_desc, 1); | 1135 | status = pmu_exec_gen_bl(g, bl_dmem_desc, 1); |
1116 | if (status != 0) { | 1136 | if (status != 0) { |
1117 | err = status; | 1137 | err = status; |
@@ -1274,10 +1294,12 @@ int gm20b_init_pmu_setup_hw1(struct gk20a *g, | |||
1274 | pmu->isr_enabled = true; | 1294 | pmu->isr_enabled = true; |
1275 | nvgpu_mutex_release(&pmu->isr_mutex); | 1295 | nvgpu_mutex_release(&pmu->isr_mutex); |
1276 | 1296 | ||
1277 | if (g->ops.pmu.setup_apertures) | 1297 | if (g->ops.pmu.setup_apertures) { |
1278 | g->ops.pmu.setup_apertures(g); | 1298 | g->ops.pmu.setup_apertures(g); |
1279 | if (g->ops.pmu.update_lspmu_cmdline_args) | 1299 | } |
1300 | if (g->ops.pmu.update_lspmu_cmdline_args) { | ||
1280 | g->ops.pmu.update_lspmu_cmdline_args(g); | 1301 | g->ops.pmu.update_lspmu_cmdline_args(g); |
1302 | } | ||
1281 | 1303 | ||
1282 | /*disable irqs for hs falcon booting as we will poll for halt*/ | 1304 | /*disable irqs for hs falcon booting as we will poll for halt*/ |
1283 | nvgpu_mutex_acquire(&pmu->isr_mutex); | 1305 | nvgpu_mutex_acquire(&pmu->isr_mutex); |
@@ -1287,8 +1309,9 @@ int gm20b_init_pmu_setup_hw1(struct gk20a *g, | |||
1287 | /*Clearing mailbox register used to reflect capabilities*/ | 1309 | /*Clearing mailbox register used to reflect capabilities*/ |
1288 | gk20a_writel(g, pwr_falcon_mailbox1_r(), 0); | 1310 | gk20a_writel(g, pwr_falcon_mailbox1_r(), 0); |
1289 | err = bl_bootstrap(pmu, desc, bl_sz); | 1311 | err = bl_bootstrap(pmu, desc, bl_sz); |
1290 | if (err) | 1312 | if (err) { |
1291 | return err; | 1313 | return err; |
1314 | } | ||
1292 | return 0; | 1315 | return 0; |
1293 | } | 1316 | } |
1294 | 1317 | ||
@@ -1362,8 +1385,9 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1362 | */ | 1385 | */ |
1363 | 1386 | ||
1364 | if (g->ops.pmu.falcon_clear_halt_interrupt_status(g, | 1387 | if (g->ops.pmu.falcon_clear_halt_interrupt_status(g, |
1365 | gk20a_get_gr_idle_timeout(g))) | 1388 | gk20a_get_gr_idle_timeout(g))) { |
1366 | goto err_unmap_bl; | 1389 | goto err_unmap_bl; |
1390 | } | ||
1367 | 1391 | ||
1368 | gm20b_dbg_pmu(g, "phys sec reg %x\n", gk20a_readl(g, | 1392 | gm20b_dbg_pmu(g, "phys sec reg %x\n", gk20a_readl(g, |
1369 | pwr_falcon_mmu_phys_sec_r())); | 1393 | pwr_falcon_mmu_phys_sec_r())); |
@@ -1377,12 +1401,13 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1377 | ACR_COMPLETION_TIMEOUT_MS); | 1401 | ACR_COMPLETION_TIMEOUT_MS); |
1378 | if (err == 0) { | 1402 | if (err == 0) { |
1379 | /* Clear the HALT interrupt */ | 1403 | /* Clear the HALT interrupt */ |
1380 | if (g->ops.pmu.falcon_clear_halt_interrupt_status(g, | 1404 | if (g->ops.pmu.falcon_clear_halt_interrupt_status(g, |
1381 | gk20a_get_gr_idle_timeout(g))) | 1405 | gk20a_get_gr_idle_timeout(g))) { |
1406 | goto err_unmap_bl; | ||
1407 | } | ||
1408 | } else { | ||
1382 | goto err_unmap_bl; | 1409 | goto err_unmap_bl; |
1383 | } | 1410 | } |
1384 | else | ||
1385 | goto err_unmap_bl; | ||
1386 | } | 1411 | } |
1387 | gm20b_dbg_pmu(g, "after waiting for halt, err %x\n", err); | 1412 | gm20b_dbg_pmu(g, "after waiting for halt, err %x\n", err); |
1388 | gm20b_dbg_pmu(g, "phys sec reg %x\n", gk20a_readl(g, | 1413 | gm20b_dbg_pmu(g, "phys sec reg %x\n", gk20a_readl(g, |
@@ -1447,8 +1472,9 @@ int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout_ms) | |||
1447 | struct nvgpu_pmu *pmu = &g->pmu; | 1472 | struct nvgpu_pmu *pmu = &g->pmu; |
1448 | int status = 0; | 1473 | int status = 0; |
1449 | 1474 | ||
1450 | if (nvgpu_flcn_clear_halt_intr_status(pmu->flcn, timeout_ms)) | 1475 | if (nvgpu_flcn_clear_halt_intr_status(pmu->flcn, timeout_ms)) { |
1451 | status = -EBUSY; | 1476 | status = -EBUSY; |
1477 | } | ||
1452 | 1478 | ||
1453 | return status; | 1479 | return status; |
1454 | } | 1480 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index c9cb353f..93bae921 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -121,8 +121,9 @@ static u32 get_interim_pldiv(struct gk20a *g, u32 old_pl, u32 new_pl) | |||
121 | { | 121 | { |
122 | u32 pl; | 122 | u32 pl; |
123 | 123 | ||
124 | if ((g->clk.gpc_pll.id == GM20B_GPC_PLL_C1) || (old_pl & new_pl)) | 124 | if ((g->clk.gpc_pll.id == GM20B_GPC_PLL_C1) || (old_pl & new_pl)) { |
125 | return 0; | 125 | return 0; |
126 | } | ||
126 | 127 | ||
127 | pl = old_pl | BIT(ffs(new_pl) - 1); /* pl never 0 */ | 128 | pl = old_pl | BIT(ffs(new_pl) - 1); /* pl never 0 */ |
128 | new_pl |= BIT(ffs(old_pl) - 1); | 129 | new_pl |= BIT(ffs(old_pl) - 1); |
@@ -163,8 +164,9 @@ static int clk_config_pll(struct clk_gk20a *clk, struct pll *pll, | |||
163 | best_PL = pll_params->min_PL; | 164 | best_PL = pll_params->min_PL; |
164 | 165 | ||
165 | target_vco_f = target_clk_f + target_clk_f / 50; | 166 | target_vco_f = target_clk_f + target_clk_f / 50; |
166 | if (max_vco_f < target_vco_f) | 167 | if (max_vco_f < target_vco_f) { |
167 | max_vco_f = target_vco_f; | 168 | max_vco_f = target_vco_f; |
169 | } | ||
168 | 170 | ||
169 | /* Set PL search boundaries. */ | 171 | /* Set PL search boundaries. */ |
170 | high_PL = nvgpu_div_to_pl((max_vco_f + target_vco_f - 1) / target_vco_f); | 172 | high_PL = nvgpu_div_to_pl((max_vco_f + target_vco_f - 1) / target_vco_f); |
@@ -184,22 +186,27 @@ static int clk_config_pll(struct clk_gk20a *clk, struct pll *pll, | |||
184 | for (m = pll_params->min_M; m <= pll_params->max_M; m++) { | 186 | for (m = pll_params->min_M; m <= pll_params->max_M; m++) { |
185 | u_f = ref_clk_f / m; | 187 | u_f = ref_clk_f / m; |
186 | 188 | ||
187 | if (u_f < pll_params->min_u) | 189 | if (u_f < pll_params->min_u) { |
188 | break; | 190 | break; |
189 | if (u_f > pll_params->max_u) | 191 | } |
192 | if (u_f > pll_params->max_u) { | ||
190 | continue; | 193 | continue; |
194 | } | ||
191 | 195 | ||
192 | n = (target_vco_f * m) / ref_clk_f; | 196 | n = (target_vco_f * m) / ref_clk_f; |
193 | n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f; | 197 | n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f; |
194 | 198 | ||
195 | if (n > pll_params->max_N) | 199 | if (n > pll_params->max_N) { |
196 | break; | 200 | break; |
201 | } | ||
197 | 202 | ||
198 | for (; n <= n2; n++) { | 203 | for (; n <= n2; n++) { |
199 | if (n < pll_params->min_N) | 204 | if (n < pll_params->min_N) { |
200 | continue; | 205 | continue; |
201 | if (n > pll_params->max_N) | 206 | } |
207 | if (n > pll_params->max_N) { | ||
202 | break; | 208 | break; |
209 | } | ||
203 | 210 | ||
204 | vco_f = ref_clk_f * n / m; | 211 | vco_f = ref_clk_f * n / m; |
205 | 212 | ||
@@ -231,9 +238,10 @@ static int clk_config_pll(struct clk_gk20a *clk, struct pll *pll, | |||
231 | found_match: | 238 | found_match: |
232 | BUG_ON(best_delta == ~0U); | 239 | BUG_ON(best_delta == ~0U); |
233 | 240 | ||
234 | if (best_fit && best_delta != 0) | 241 | if (best_fit && best_delta != 0) { |
235 | gk20a_dbg_clk(g, "no best match for target @ %dMHz on gpc_pll", | 242 | gk20a_dbg_clk(g, "no best match for target @ %dMHz on gpc_pll", |
236 | target_clk_f); | 243 | target_clk_f); |
244 | } | ||
237 | 245 | ||
238 | pll->M = best_M; | 246 | pll->M = best_M; |
239 | pll->N = best_N; | 247 | pll->N = best_N; |
@@ -278,11 +286,13 @@ static int nvgpu_fuse_calib_gpcpll_get_adc(struct gk20a *g, | |||
278 | int ret; | 286 | int ret; |
279 | 287 | ||
280 | ret = nvgpu_tegra_fuse_read_reserved_calib(g, &val); | 288 | ret = nvgpu_tegra_fuse_read_reserved_calib(g, &val); |
281 | if (ret) | 289 | if (ret) { |
282 | return ret; | 290 | return ret; |
291 | } | ||
283 | 292 | ||
284 | if (!fuse_get_gpcpll_adc_rev(val)) | 293 | if (!fuse_get_gpcpll_adc_rev(val)) { |
285 | return -EINVAL; | 294 | return -EINVAL; |
295 | } | ||
286 | 296 | ||
287 | *slope_uv = fuse_get_gpcpll_adc_slope_uv(val); | 297 | *slope_uv = fuse_get_gpcpll_adc_slope_uv(val); |
288 | *intercept_uv = fuse_get_gpcpll_adc_intercept_uv(val); | 298 | *intercept_uv = fuse_get_gpcpll_adc_intercept_uv(val); |
@@ -521,8 +531,9 @@ static int clk_enbale_pll_dvfs(struct gk20a *g) | |||
521 | */ | 531 | */ |
522 | clk_setup_slide(g, g->clk.gpc_pll.clk_in); | 532 | clk_setup_slide(g, g->clk.gpc_pll.clk_in); |
523 | 533 | ||
524 | if (calibrated) | 534 | if (calibrated) { |
525 | return 0; | 535 | return 0; |
536 | } | ||
526 | 537 | ||
527 | /* | 538 | /* |
528 | * If calibration parameters are not fused, start internal calibration, | 539 | * If calibration parameters are not fused, start internal calibration, |
@@ -544,8 +555,9 @@ static int clk_enbale_pll_dvfs(struct gk20a *g) | |||
544 | /* Wait for internal calibration done (spec < 2us). */ | 555 | /* Wait for internal calibration done (spec < 2us). */ |
545 | do { | 556 | do { |
546 | data = gk20a_readl(g, trim_sys_gpcpll_dvfs1_r()); | 557 | data = gk20a_readl(g, trim_sys_gpcpll_dvfs1_r()); |
547 | if (trim_sys_gpcpll_dvfs1_dfs_cal_done_v(data)) | 558 | if (trim_sys_gpcpll_dvfs1_dfs_cal_done_v(data)) { |
548 | break; | 559 | break; |
560 | } | ||
549 | nvgpu_udelay(1); | 561 | nvgpu_udelay(1); |
550 | delay--; | 562 | delay--; |
551 | } while (delay > 0); | 563 | } while (delay > 0); |
@@ -623,11 +635,13 @@ static int clk_slide_gpc_pll(struct gk20a *g, struct pll *gpll) | |||
623 | coeff = gk20a_readl(g, trim_sys_gpcpll_cfg2_r()); | 635 | coeff = gk20a_readl(g, trim_sys_gpcpll_cfg2_r()); |
624 | sdm_old = trim_sys_gpcpll_cfg2_sdm_din_v(coeff); | 636 | sdm_old = trim_sys_gpcpll_cfg2_sdm_din_v(coeff); |
625 | if ((gpll->dvfs.n_int == nold) && | 637 | if ((gpll->dvfs.n_int == nold) && |
626 | (gpll->dvfs.sdm_din == sdm_old)) | 638 | (gpll->dvfs.sdm_din == sdm_old)) { |
627 | return 0; | 639 | return 0; |
640 | } | ||
628 | } else { | 641 | } else { |
629 | if (gpll->N == nold) | 642 | if (gpll->N == nold) { |
630 | return 0; | 643 | return 0; |
644 | } | ||
631 | 645 | ||
632 | /* dynamic ramp setup based on update rate */ | 646 | /* dynamic ramp setup based on update rate */ |
633 | clk_setup_slide(g, gpll->clk_in / gpll->M); | 647 | clk_setup_slide(g, gpll->clk_in / gpll->M); |
@@ -674,8 +688,9 @@ static int clk_slide_gpc_pll(struct gk20a *g, struct pll *gpll) | |||
674 | ramp_timeout--; | 688 | ramp_timeout--; |
675 | data = gk20a_readl( | 689 | data = gk20a_readl( |
676 | g, trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r()); | 690 | g, trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r()); |
677 | if (trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(data)) | 691 | if (trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(data)) { |
678 | break; | 692 | break; |
693 | } | ||
679 | } while (ramp_timeout > 0); | 694 | } while (ramp_timeout > 0); |
680 | 695 | ||
681 | if ((gpll->mode == GPC_PLL_MODE_DVFS) && (ramp_timeout > 0)) { | 696 | if ((gpll->mode == GPC_PLL_MODE_DVFS) && (ramp_timeout > 0)) { |
@@ -836,8 +851,9 @@ static int clk_lock_gpc_pll_under_bypass(struct gk20a *g, struct pll *gpll) | |||
836 | do { | 851 | do { |
837 | nvgpu_udelay(1); | 852 | nvgpu_udelay(1); |
838 | cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); | 853 | cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); |
839 | if (cfg & trim_sys_gpcpll_cfg_pll_lock_true_f()) | 854 | if (cfg & trim_sys_gpcpll_cfg_pll_lock_true_f()) { |
840 | goto pll_locked; | 855 | goto pll_locked; |
856 | } | ||
841 | } while (--timeout > 0); | 857 | } while (--timeout > 0); |
842 | 858 | ||
843 | /* PLL is messed up. What can we do here? */ | 859 | /* PLL is messed up. What can we do here? */ |
@@ -883,8 +899,9 @@ static int clk_program_gpc_pll(struct gk20a *g, struct pll *gpll_new, | |||
883 | 899 | ||
884 | nvgpu_log_fn(g, " "); | 900 | nvgpu_log_fn(g, " "); |
885 | 901 | ||
886 | if (!nvgpu_platform_is_silicon(g)) | 902 | if (!nvgpu_platform_is_silicon(g)) { |
887 | return 0; | 903 | return 0; |
904 | } | ||
888 | 905 | ||
889 | /* get old coefficients */ | 906 | /* get old coefficients */ |
890 | coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r()); | 907 | coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r()); |
@@ -901,19 +918,22 @@ static int clk_program_gpc_pll(struct gk20a *g, struct pll *gpll_new, | |||
901 | cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); | 918 | cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); |
902 | can_slide = allow_slide && trim_sys_gpcpll_cfg_enable_v(cfg); | 919 | can_slide = allow_slide && trim_sys_gpcpll_cfg_enable_v(cfg); |
903 | 920 | ||
904 | if (can_slide && (gpll_new->M == gpll.M) && (gpll_new->PL == gpll.PL)) | 921 | if (can_slide && (gpll_new->M == gpll.M) && (gpll_new->PL == gpll.PL)) { |
905 | return clk_slide_gpc_pll(g, gpll_new); | 922 | return clk_slide_gpc_pll(g, gpll_new); |
923 | } | ||
906 | 924 | ||
907 | /* slide down to NDIV_LO */ | 925 | /* slide down to NDIV_LO */ |
908 | if (can_slide) { | 926 | if (can_slide) { |
909 | int ret; | 927 | int ret; |
910 | gpll.N = DIV_ROUND_UP(gpll.M * gpc_pll_params.min_vco, | 928 | gpll.N = DIV_ROUND_UP(gpll.M * gpc_pll_params.min_vco, |
911 | gpll.clk_in); | 929 | gpll.clk_in); |
912 | if (gpll.mode == GPC_PLL_MODE_DVFS) | 930 | if (gpll.mode == GPC_PLL_MODE_DVFS) { |
913 | clk_config_dvfs_ndiv(gpll.dvfs.mv, gpll.N, &gpll.dvfs); | 931 | clk_config_dvfs_ndiv(gpll.dvfs.mv, gpll.N, &gpll.dvfs); |
932 | } | ||
914 | ret = clk_slide_gpc_pll(g, &gpll); | 933 | ret = clk_slide_gpc_pll(g, &gpll); |
915 | if (ret) | 934 | if (ret) { |
916 | return ret; | 935 | return ret; |
936 | } | ||
917 | } | 937 | } |
918 | pldiv_only = can_slide && (gpll_new->M == gpll.M); | 938 | pldiv_only = can_slide && (gpll_new->M == gpll.M); |
919 | 939 | ||
@@ -962,13 +982,15 @@ static int clk_program_gpc_pll(struct gk20a *g, struct pll *gpll_new, | |||
962 | if (allow_slide) { | 982 | if (allow_slide) { |
963 | gpll.N = DIV_ROUND_UP(gpll_new->M * gpc_pll_params.min_vco, | 983 | gpll.N = DIV_ROUND_UP(gpll_new->M * gpc_pll_params.min_vco, |
964 | gpll_new->clk_in); | 984 | gpll_new->clk_in); |
965 | if (gpll.mode == GPC_PLL_MODE_DVFS) | 985 | if (gpll.mode == GPC_PLL_MODE_DVFS) { |
966 | clk_config_dvfs_ndiv(gpll.dvfs.mv, gpll.N, &gpll.dvfs); | 986 | clk_config_dvfs_ndiv(gpll.dvfs.mv, gpll.N, &gpll.dvfs); |
987 | } | ||
967 | } | 988 | } |
968 | if (pldiv_only) | 989 | if (pldiv_only) { |
969 | clk_change_pldiv_under_bypass(g, &gpll); | 990 | clk_change_pldiv_under_bypass(g, &gpll); |
970 | else | 991 | } else { |
971 | clk_lock_gpc_pll_under_bypass(g, &gpll); | 992 | clk_lock_gpc_pll_under_bypass(g, &gpll); |
993 | } | ||
972 | 994 | ||
973 | #if PLDIV_GLITCHLESS | 995 | #if PLDIV_GLITCHLESS |
974 | coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r()); | 996 | coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r()); |
@@ -1003,8 +1025,9 @@ static void clk_config_pll_safe_dvfs(struct gk20a *g, struct pll *gpll) | |||
1003 | { | 1025 | { |
1004 | u32 nsafe, nmin; | 1026 | u32 nsafe, nmin; |
1005 | 1027 | ||
1006 | if (gpll->freq > g->clk.dvfs_safe_max_freq) | 1028 | if (gpll->freq > g->clk.dvfs_safe_max_freq) { |
1007 | gpll->freq = gpll->freq * (100 - DVFS_SAFE_MARGIN) / 100; | 1029 | gpll->freq = gpll->freq * (100 - DVFS_SAFE_MARGIN) / 100; |
1030 | } | ||
1008 | 1031 | ||
1009 | nmin = DIV_ROUND_UP(gpll->M * gpc_pll_params.min_vco, gpll->clk_in); | 1032 | nmin = DIV_ROUND_UP(gpll->M * gpc_pll_params.min_vco, gpll->clk_in); |
1010 | nsafe = gpll->M * gpll->freq / gpll->clk_in; | 1033 | nsafe = gpll->M * gpll->freq / gpll->clk_in; |
@@ -1054,8 +1077,9 @@ static int clk_program_na_gpc_pll(struct gk20a *g, struct pll *gpll_new, | |||
1054 | * - voltage is not changing, so DVFS detection settings are the same | 1077 | * - voltage is not changing, so DVFS detection settings are the same |
1055 | */ | 1078 | */ |
1056 | if (!allow_slide || !gpll_new->enabled || | 1079 | if (!allow_slide || !gpll_new->enabled || |
1057 | (gpll_old->dvfs.mv == gpll_new->dvfs.mv)) | 1080 | (gpll_old->dvfs.mv == gpll_new->dvfs.mv)) { |
1058 | return clk_program_gpc_pll(g, gpll_new, allow_slide); | 1081 | return clk_program_gpc_pll(g, gpll_new, allow_slide); |
1082 | } | ||
1059 | 1083 | ||
1060 | /* | 1084 | /* |
1061 | * Interim step for changing DVFS detection settings: low enough | 1085 | * Interim step for changing DVFS detection settings: low enough |
@@ -1129,8 +1153,9 @@ static int clk_disable_gpcpll(struct gk20a *g, int allow_slide) | |||
1129 | gpll.M = trim_sys_gpcpll_coeff_mdiv_v(coeff); | 1153 | gpll.M = trim_sys_gpcpll_coeff_mdiv_v(coeff); |
1130 | gpll.N = DIV_ROUND_UP(gpll.M * gpc_pll_params.min_vco, | 1154 | gpll.N = DIV_ROUND_UP(gpll.M * gpc_pll_params.min_vco, |
1131 | gpll.clk_in); | 1155 | gpll.clk_in); |
1132 | if (gpll.mode == GPC_PLL_MODE_DVFS) | 1156 | if (gpll.mode == GPC_PLL_MODE_DVFS) { |
1133 | clk_config_dvfs_ndiv(gpll.dvfs.mv, gpll.N, &gpll.dvfs); | 1157 | clk_config_dvfs_ndiv(gpll.dvfs.mv, gpll.N, &gpll.dvfs); |
1158 | } | ||
1134 | clk_slide_gpc_pll(g, &gpll); | 1159 | clk_slide_gpc_pll(g, &gpll); |
1135 | } | 1160 | } |
1136 | 1161 | ||
@@ -1174,8 +1199,9 @@ int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1174 | nvgpu_log_fn(g, " "); | 1199 | nvgpu_log_fn(g, " "); |
1175 | 1200 | ||
1176 | err = nvgpu_mutex_init(&clk->clk_mutex); | 1201 | err = nvgpu_mutex_init(&clk->clk_mutex); |
1177 | if (err) | 1202 | if (err) { |
1178 | return err; | 1203 | return err; |
1204 | } | ||
1179 | 1205 | ||
1180 | if (clk->sw_ready) { | 1206 | if (clk->sw_ready) { |
1181 | nvgpu_log_fn(g, "skip init"); | 1207 | nvgpu_log_fn(g, "skip init"); |
@@ -1184,12 +1210,14 @@ int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1184 | 1210 | ||
1185 | if (clk->gpc_pll.id == GM20B_GPC_PLL_C1) { | 1211 | if (clk->gpc_pll.id == GM20B_GPC_PLL_C1) { |
1186 | gpc_pll_params = gpc_pll_params_c1; | 1212 | gpc_pll_params = gpc_pll_params_c1; |
1187 | if (!clk->pll_poweron_uv) | 1213 | if (!clk->pll_poweron_uv) { |
1188 | clk->pll_poweron_uv = BOOT_GPU_UV_C1; | 1214 | clk->pll_poweron_uv = BOOT_GPU_UV_C1; |
1215 | } | ||
1189 | } else { | 1216 | } else { |
1190 | gpc_pll_params = gpc_pll_params_b1; | 1217 | gpc_pll_params = gpc_pll_params_b1; |
1191 | if (!clk->pll_poweron_uv) | 1218 | if (!clk->pll_poweron_uv) { |
1192 | clk->pll_poweron_uv = BOOT_GPU_UV_B1; | 1219 | clk->pll_poweron_uv = BOOT_GPU_UV_B1; |
1220 | } | ||
1193 | } | 1221 | } |
1194 | 1222 | ||
1195 | clk->gpc_pll.clk_in = g->ops.clk.get_ref_clock_rate(g) / KHZ; | 1223 | clk->gpc_pll.clk_in = g->ops.clk.get_ref_clock_rate(g) / KHZ; |
@@ -1254,8 +1282,9 @@ int gm20b_clk_prepare(struct clk_gk20a *clk) | |||
1254 | int ret = 0; | 1282 | int ret = 0; |
1255 | 1283 | ||
1256 | nvgpu_mutex_acquire(&clk->clk_mutex); | 1284 | nvgpu_mutex_acquire(&clk->clk_mutex); |
1257 | if (!clk->gpc_pll.enabled && clk->clk_hw_on) | 1285 | if (!clk->gpc_pll.enabled && clk->clk_hw_on) { |
1258 | ret = set_pll_freq(clk->g, 1); | 1286 | ret = set_pll_freq(clk->g, 1); |
1287 | } | ||
1259 | nvgpu_mutex_release(&clk->clk_mutex); | 1288 | nvgpu_mutex_release(&clk->clk_mutex); |
1260 | return ret; | 1289 | return ret; |
1261 | } | 1290 | } |
@@ -1263,8 +1292,9 @@ int gm20b_clk_prepare(struct clk_gk20a *clk) | |||
1263 | void gm20b_clk_unprepare(struct clk_gk20a *clk) | 1292 | void gm20b_clk_unprepare(struct clk_gk20a *clk) |
1264 | { | 1293 | { |
1265 | nvgpu_mutex_acquire(&clk->clk_mutex); | 1294 | nvgpu_mutex_acquire(&clk->clk_mutex); |
1266 | if (clk->gpc_pll.enabled && clk->clk_hw_on) | 1295 | if (clk->gpc_pll.enabled && clk->clk_hw_on) { |
1267 | clk_disable_gpcpll(clk->g, 1); | 1296 | clk_disable_gpcpll(clk->g, 1); |
1297 | } | ||
1268 | nvgpu_mutex_release(&clk->clk_mutex); | 1298 | nvgpu_mutex_release(&clk->clk_mutex); |
1269 | } | 1299 | } |
1270 | 1300 | ||
@@ -1287,8 +1317,9 @@ int gm20b_gpcclk_set_rate(struct clk_gk20a *clk, unsigned long rate, | |||
1287 | nvgpu_mutex_acquire(&clk->clk_mutex); | 1317 | nvgpu_mutex_acquire(&clk->clk_mutex); |
1288 | old_freq = clk->gpc_pll.freq; | 1318 | old_freq = clk->gpc_pll.freq; |
1289 | ret = set_pll_target(clk->g, rate_gpu_to_gpc2clk(rate), old_freq); | 1319 | ret = set_pll_target(clk->g, rate_gpu_to_gpc2clk(rate), old_freq); |
1290 | if (!ret && clk->gpc_pll.enabled && clk->clk_hw_on) | 1320 | if (!ret && clk->gpc_pll.enabled && clk->clk_hw_on) { |
1291 | ret = set_pll_freq(clk->g, 1); | 1321 | ret = set_pll_freq(clk->g, 1); |
1322 | } | ||
1292 | nvgpu_mutex_release(&clk->clk_mutex); | 1323 | nvgpu_mutex_release(&clk->clk_mutex); |
1293 | 1324 | ||
1294 | return ret; | 1325 | return ret; |
@@ -1303,15 +1334,17 @@ long gm20b_round_rate(struct clk_gk20a *clk, unsigned long rate, | |||
1303 | struct gk20a *g = clk->g; | 1334 | struct gk20a *g = clk->g; |
1304 | 1335 | ||
1305 | maxrate = g->ops.clk.get_maxrate(g, CTRL_CLK_DOMAIN_GPCCLK); | 1336 | maxrate = g->ops.clk.get_maxrate(g, CTRL_CLK_DOMAIN_GPCCLK); |
1306 | if (rate > maxrate) | 1337 | if (rate > maxrate) { |
1307 | rate = maxrate; | 1338 | rate = maxrate; |
1339 | } | ||
1308 | 1340 | ||
1309 | nvgpu_mutex_acquire(&clk->clk_mutex); | 1341 | nvgpu_mutex_acquire(&clk->clk_mutex); |
1310 | freq = rate_gpu_to_gpc2clk(rate); | 1342 | freq = rate_gpu_to_gpc2clk(rate); |
1311 | if (freq > gpc_pll_params.max_freq) | 1343 | if (freq > gpc_pll_params.max_freq) { |
1312 | freq = gpc_pll_params.max_freq; | 1344 | freq = gpc_pll_params.max_freq; |
1313 | else if (freq < gpc_pll_params.min_freq) | 1345 | } else if (freq < gpc_pll_params.min_freq) { |
1314 | freq = gpc_pll_params.min_freq; | 1346 | freq = gpc_pll_params.min_freq; |
1347 | } | ||
1315 | 1348 | ||
1316 | tmp_pll = clk->gpc_pll; | 1349 | tmp_pll = clk->gpc_pll; |
1317 | clk_config_pll(clk, &tmp_pll, &gpc_pll_params, &freq, true); | 1350 | clk_config_pll(clk, &tmp_pll, &gpc_pll_params, &freq, true); |
@@ -1366,8 +1399,9 @@ static int gm20b_init_clk_setup_hw(struct gk20a *g) | |||
1366 | gk20a_writel(g, therm_clk_slowdown_r(0), data); | 1399 | gk20a_writel(g, therm_clk_slowdown_r(0), data); |
1367 | gk20a_readl(g, therm_clk_slowdown_r(0)); | 1400 | gk20a_readl(g, therm_clk_slowdown_r(0)); |
1368 | 1401 | ||
1369 | if (g->clk.gpc_pll.mode == GPC_PLL_MODE_DVFS) | 1402 | if (g->clk.gpc_pll.mode == GPC_PLL_MODE_DVFS) { |
1370 | return clk_enbale_pll_dvfs(g); | 1403 | return clk_enbale_pll_dvfs(g); |
1404 | } | ||
1371 | 1405 | ||
1372 | return 0; | 1406 | return 0; |
1373 | } | 1407 | } |
@@ -1376,10 +1410,11 @@ static int set_pll_target(struct gk20a *g, u32 freq, u32 old_freq) | |||
1376 | { | 1410 | { |
1377 | struct clk_gk20a *clk = &g->clk; | 1411 | struct clk_gk20a *clk = &g->clk; |
1378 | 1412 | ||
1379 | if (freq > gpc_pll_params.max_freq) | 1413 | if (freq > gpc_pll_params.max_freq) { |
1380 | freq = gpc_pll_params.max_freq; | 1414 | freq = gpc_pll_params.max_freq; |
1381 | else if (freq < gpc_pll_params.min_freq) | 1415 | } else if (freq < gpc_pll_params.min_freq) { |
1382 | freq = gpc_pll_params.min_freq; | 1416 | freq = gpc_pll_params.min_freq; |
1417 | } | ||
1383 | 1418 | ||
1384 | if (freq != old_freq) { | 1419 | if (freq != old_freq) { |
1385 | /* gpc_pll.freq is changed to new value here */ | 1420 | /* gpc_pll.freq is changed to new value here */ |
@@ -1403,12 +1438,14 @@ static int set_pll_freq(struct gk20a *g, int allow_slide) | |||
1403 | /* If programming with dynamic sliding failed, re-try under bypass */ | 1438 | /* If programming with dynamic sliding failed, re-try under bypass */ |
1404 | if (clk->gpc_pll.mode == GPC_PLL_MODE_DVFS) { | 1439 | if (clk->gpc_pll.mode == GPC_PLL_MODE_DVFS) { |
1405 | err = clk_program_na_gpc_pll(g, &clk->gpc_pll, allow_slide); | 1440 | err = clk_program_na_gpc_pll(g, &clk->gpc_pll, allow_slide); |
1406 | if (err && allow_slide) | 1441 | if (err && allow_slide) { |
1407 | err = clk_program_na_gpc_pll(g, &clk->gpc_pll, 0); | 1442 | err = clk_program_na_gpc_pll(g, &clk->gpc_pll, 0); |
1443 | } | ||
1408 | } else { | 1444 | } else { |
1409 | err = clk_program_gpc_pll(g, &clk->gpc_pll, allow_slide); | 1445 | err = clk_program_gpc_pll(g, &clk->gpc_pll, allow_slide); |
1410 | if (err && allow_slide) | 1446 | if (err && allow_slide) { |
1411 | err = clk_program_gpc_pll(g, &clk->gpc_pll, 0); | 1447 | err = clk_program_gpc_pll(g, &clk->gpc_pll, 0); |
1448 | } | ||
1412 | } | 1449 | } |
1413 | 1450 | ||
1414 | if (!err) { | 1451 | if (!err) { |
@@ -1437,26 +1474,31 @@ int gm20b_init_clk_support(struct gk20a *g) | |||
1437 | 1474 | ||
1438 | err = gm20b_init_clk_setup_hw(g); | 1475 | err = gm20b_init_clk_setup_hw(g); |
1439 | nvgpu_mutex_release(&clk->clk_mutex); | 1476 | nvgpu_mutex_release(&clk->clk_mutex); |
1440 | if (err) | 1477 | if (err) { |
1441 | return err; | 1478 | return err; |
1479 | } | ||
1442 | 1480 | ||
1443 | /* FIXME: this effectively prevents host level clock gating */ | 1481 | /* FIXME: this effectively prevents host level clock gating */ |
1444 | err = g->ops.clk.prepare_enable(&g->clk); | 1482 | err = g->ops.clk.prepare_enable(&g->clk); |
1445 | if (err) | 1483 | if (err) { |
1446 | return err; | 1484 | return err; |
1485 | } | ||
1447 | 1486 | ||
1448 | /* The prev call may not enable PLL if gbus is unbalanced - force it */ | 1487 | /* The prev call may not enable PLL if gbus is unbalanced - force it */ |
1449 | nvgpu_mutex_acquire(&clk->clk_mutex); | 1488 | nvgpu_mutex_acquire(&clk->clk_mutex); |
1450 | if (!clk->gpc_pll.enabled) | 1489 | if (!clk->gpc_pll.enabled) { |
1451 | err = set_pll_freq(g, 1); | 1490 | err = set_pll_freq(g, 1); |
1491 | } | ||
1452 | nvgpu_mutex_release(&clk->clk_mutex); | 1492 | nvgpu_mutex_release(&clk->clk_mutex); |
1453 | if (err) | 1493 | if (err) { |
1454 | return err; | 1494 | return err; |
1495 | } | ||
1455 | 1496 | ||
1456 | if (!clk->debugfs_set && g->ops.clk.init_debugfs) { | 1497 | if (!clk->debugfs_set && g->ops.clk.init_debugfs) { |
1457 | err = g->ops.clk.init_debugfs(g); | 1498 | err = g->ops.clk.init_debugfs(g); |
1458 | if (err) | 1499 | if (err) { |
1459 | return err; | 1500 | return err; |
1501 | } | ||
1460 | clk->debugfs_set = true; | 1502 | clk->debugfs_set = true; |
1461 | } | 1503 | } |
1462 | 1504 | ||
@@ -1471,8 +1513,9 @@ int gm20b_suspend_clk_support(struct gk20a *g) | |||
1471 | 1513 | ||
1472 | /* The prev call may not disable PLL if gbus is unbalanced - force it */ | 1514 | /* The prev call may not disable PLL if gbus is unbalanced - force it */ |
1473 | nvgpu_mutex_acquire(&g->clk.clk_mutex); | 1515 | nvgpu_mutex_acquire(&g->clk.clk_mutex); |
1474 | if (g->clk.gpc_pll.enabled) | 1516 | if (g->clk.gpc_pll.enabled) { |
1475 | ret = clk_disable_gpcpll(g, 1); | 1517 | ret = clk_disable_gpcpll(g, 1); |
1518 | } | ||
1476 | g->clk.clk_hw_on = false; | 1519 | g->clk.clk_hw_on = false; |
1477 | nvgpu_mutex_release(&g->clk.clk_mutex); | 1520 | nvgpu_mutex_release(&g->clk.clk_mutex); |
1478 | 1521 | ||
@@ -1488,12 +1531,14 @@ int gm20b_clk_get_voltage(struct clk_gk20a *clk, u64 *val) | |||
1488 | u32 det_out; | 1531 | u32 det_out; |
1489 | int err; | 1532 | int err; |
1490 | 1533 | ||
1491 | if (clk->gpc_pll.mode != GPC_PLL_MODE_DVFS) | 1534 | if (clk->gpc_pll.mode != GPC_PLL_MODE_DVFS) { |
1492 | return -ENOSYS; | 1535 | return -ENOSYS; |
1536 | } | ||
1493 | 1537 | ||
1494 | err = gk20a_busy(g); | 1538 | err = gk20a_busy(g); |
1495 | if (err) | 1539 | if (err) { |
1496 | return err; | 1540 | return err; |
1541 | } | ||
1497 | 1542 | ||
1498 | nvgpu_mutex_acquire(&g->clk.clk_mutex); | 1543 | nvgpu_mutex_acquire(&g->clk.clk_mutex); |
1499 | 1544 | ||
@@ -1519,8 +1564,9 @@ int gm20b_clk_get_gpcclk_clock_counter(struct clk_gk20a *clk, u64 *val) | |||
1519 | u32 count1, count2; | 1564 | u32 count1, count2; |
1520 | 1565 | ||
1521 | err = gk20a_busy(g); | 1566 | err = gk20a_busy(g); |
1522 | if (err) | 1567 | if (err) { |
1523 | return err; | 1568 | return err; |
1569 | } | ||
1524 | 1570 | ||
1525 | nvgpu_mutex_acquire(&g->clk.clk_mutex); | 1571 | nvgpu_mutex_acquire(&g->clk.clk_mutex); |
1526 | 1572 | ||
@@ -1559,8 +1605,9 @@ int gm20b_clk_get_gpcclk_clock_counter(struct clk_gk20a *clk, u64 *val) | |||
1559 | 1605 | ||
1560 | gk20a_idle(g); | 1606 | gk20a_idle(g); |
1561 | 1607 | ||
1562 | if (count1 != count2) | 1608 | if (count1 != count2) { |
1563 | return -EBUSY; | 1609 | return -EBUSY; |
1610 | } | ||
1564 | 1611 | ||
1565 | return 0; | 1612 | return 0; |
1566 | } | 1613 | } |
@@ -1571,11 +1618,13 @@ int gm20b_clk_pll_reg_write(struct gk20a *g, u32 reg, u32 val) | |||
1571 | (reg > trim_sys_gpcpll_dvfs2_r())) && | 1618 | (reg > trim_sys_gpcpll_dvfs2_r())) && |
1572 | (reg != trim_sys_sel_vco_r()) && | 1619 | (reg != trim_sys_sel_vco_r()) && |
1573 | (reg != trim_sys_gpc2clk_out_r()) && | 1620 | (reg != trim_sys_gpc2clk_out_r()) && |
1574 | (reg != trim_sys_bypassctrl_r())) | 1621 | (reg != trim_sys_bypassctrl_r())) { |
1575 | return -EPERM; | 1622 | return -EPERM; |
1623 | } | ||
1576 | 1624 | ||
1577 | if (reg == trim_sys_gpcpll_dvfs2_r()) | 1625 | if (reg == trim_sys_gpcpll_dvfs2_r()) { |
1578 | reg = trim_gpc_bcast_gpcpll_dvfs2_r(); | 1626 | reg = trim_gpc_bcast_gpcpll_dvfs2_r(); |
1627 | } | ||
1579 | 1628 | ||
1580 | nvgpu_mutex_acquire(&g->clk.clk_mutex); | 1629 | nvgpu_mutex_acquire(&g->clk.clk_mutex); |
1581 | if (!g->clk.clk_hw_on) { | 1630 | if (!g->clk.clk_hw_on) { |
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index f0635b83..dd11d2c7 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | |||
@@ -99,9 +99,10 @@ void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, | |||
99 | } else { | 99 | } else { |
100 | u32 mmu_id = gm20b_engine_id_to_mmu_id(g, | 100 | u32 mmu_id = gm20b_engine_id_to_mmu_id(g, |
101 | engine_id); | 101 | engine_id); |
102 | if (mmu_id != (u32)~0) | 102 | if (mmu_id != (u32)~0) { |
103 | gk20a_writel(g, fifo_trigger_mmu_fault_r(mmu_id), | 103 | gk20a_writel(g, fifo_trigger_mmu_fault_r(mmu_id), |
104 | fifo_trigger_mmu_fault_enable_f(1)); | 104 | fifo_trigger_mmu_fault_enable_f(1)); |
105 | } | ||
105 | } | 106 | } |
106 | } | 107 | } |
107 | 108 | ||
@@ -120,8 +121,9 @@ void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, | |||
120 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); | 121 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); |
121 | } while (!nvgpu_timeout_expired(&timeout)); | 122 | } while (!nvgpu_timeout_expired(&timeout)); |
122 | 123 | ||
123 | if (ret) | 124 | if (ret) { |
124 | nvgpu_err(g, "mmu fault timeout"); | 125 | nvgpu_err(g, "mmu fault timeout"); |
126 | } | ||
125 | 127 | ||
126 | /* release mmu fault trigger */ | 128 | /* release mmu fault trigger */ |
127 | for_each_set_bit(engine_id, &engine_ids, 32) { | 129 | for_each_set_bit(engine_id, &engine_ids, 32) { |
@@ -150,9 +152,10 @@ void gm20b_device_info_data_parse(struct gk20a *g, | |||
150 | *fault_id = | 152 | *fault_id = |
151 | top_device_info_data_fault_id_enum_v(table_entry); | 153 | top_device_info_data_fault_id_enum_v(table_entry); |
152 | } | 154 | } |
153 | } else | 155 | } else { |
154 | nvgpu_err(g, "unknown device_info_data %d", | 156 | nvgpu_err(g, "unknown device_info_data %d", |
155 | top_device_info_data_type_v(table_entry)); | 157 | top_device_info_data_type_v(table_entry)); |
158 | } | ||
156 | } | 159 | } |
157 | 160 | ||
158 | void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) | 161 | void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) |
@@ -250,10 +253,11 @@ static const char * const gm20b_gpc_client_descs[] = { | |||
250 | 253 | ||
251 | void gm20b_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault) | 254 | void gm20b_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault) |
252 | { | 255 | { |
253 | if (mmfault->client_id >= ARRAY_SIZE(gm20b_gpc_client_descs)) | 256 | if (mmfault->client_id >= ARRAY_SIZE(gm20b_gpc_client_descs)) { |
254 | WARN_ON(mmfault->client_id >= | 257 | WARN_ON(mmfault->client_id >= |
255 | ARRAY_SIZE(gm20b_gpc_client_descs)); | 258 | ARRAY_SIZE(gm20b_gpc_client_descs)); |
256 | else | 259 | } else { |
257 | mmfault->client_id_desc = | 260 | mmfault->client_id_desc = |
258 | gm20b_gpc_client_descs[mmfault->client_id]; | 261 | gm20b_gpc_client_descs[mmfault->client_id]; |
262 | } | ||
259 | } | 263 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index fc4ab3dd..7ed36144 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -89,9 +89,10 @@ void gr_gm20b_cb_size_default(struct gk20a *g) | |||
89 | { | 89 | { |
90 | struct gr_gk20a *gr = &g->gr; | 90 | struct gr_gk20a *gr = &g->gr; |
91 | 91 | ||
92 | if (!gr->attrib_cb_default_size) | 92 | if (!gr->attrib_cb_default_size) { |
93 | gr->attrib_cb_default_size = | 93 | gr->attrib_cb_default_size = |
94 | gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(); | 94 | gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(); |
95 | } | ||
95 | gr->alpha_cb_default_size = | 96 | gr->alpha_cb_default_size = |
96 | gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); | 97 | gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); |
97 | } | 98 | } |
@@ -189,8 +190,9 @@ int gr_gm20b_commit_global_cb_manager(struct gk20a *g, | |||
189 | nvgpu_log_fn(g, " "); | 190 | nvgpu_log_fn(g, " "); |
190 | 191 | ||
191 | tsg = tsg_gk20a_from_ch(c); | 192 | tsg = tsg_gk20a_from_ch(c); |
192 | if (!tsg) | 193 | if (!tsg) { |
193 | return -EINVAL; | 194 | return -EINVAL; |
195 | } | ||
194 | 196 | ||
195 | ch_ctx = &tsg->gr_ctx; | 197 | ch_ctx = &tsg->gr_ctx; |
196 | 198 | ||
@@ -338,8 +340,9 @@ void gr_gm20b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) | |||
338 | /* if (NO_ALPHA_BETA_TIMESLICE_SUPPORT_DEF) | 340 | /* if (NO_ALPHA_BETA_TIMESLICE_SUPPORT_DEF) |
339 | return; */ | 341 | return; */ |
340 | 342 | ||
341 | if (alpha_cb_size > gr->alpha_cb_size) | 343 | if (alpha_cb_size > gr->alpha_cb_size) { |
342 | alpha_cb_size = gr->alpha_cb_size; | 344 | alpha_cb_size = gr->alpha_cb_size; |
345 | } | ||
343 | 346 | ||
344 | gk20a_writel(g, gr_ds_tga_constraintlogic_r(), | 347 | gk20a_writel(g, gr_ds_tga_constraintlogic_r(), |
345 | (gk20a_readl(g, gr_ds_tga_constraintlogic_r()) & | 348 | (gk20a_readl(g, gr_ds_tga_constraintlogic_r()) & |
@@ -385,8 +388,9 @@ void gr_gm20b_set_circular_buffer_size(struct gk20a *g, u32 data) | |||
385 | 388 | ||
386 | nvgpu_log_fn(g, " "); | 389 | nvgpu_log_fn(g, " "); |
387 | 390 | ||
388 | if (cb_size > gr->attrib_cb_size) | 391 | if (cb_size > gr->attrib_cb_size) { |
389 | cb_size = gr->attrib_cb_size; | 392 | cb_size = gr->attrib_cb_size; |
393 | } | ||
390 | 394 | ||
391 | gk20a_writel(g, gr_ds_tga_constraintlogic_r(), | 395 | gk20a_writel(g, gr_ds_tga_constraintlogic_r(), |
392 | (gk20a_readl(g, gr_ds_tga_constraintlogic_r()) & | 396 | (gk20a_readl(g, gr_ds_tga_constraintlogic_r()) & |
@@ -485,18 +489,20 @@ bool gr_gm20b_is_valid_class(struct gk20a *g, u32 class_num) | |||
485 | 489 | ||
486 | bool gr_gm20b_is_valid_gfx_class(struct gk20a *g, u32 class_num) | 490 | bool gr_gm20b_is_valid_gfx_class(struct gk20a *g, u32 class_num) |
487 | { | 491 | { |
488 | if (class_num == MAXWELL_B) | 492 | if (class_num == MAXWELL_B) { |
489 | return true; | 493 | return true; |
490 | else | 494 | } else { |
491 | return false; | 495 | return false; |
496 | } | ||
492 | } | 497 | } |
493 | 498 | ||
494 | bool gr_gm20b_is_valid_compute_class(struct gk20a *g, u32 class_num) | 499 | bool gr_gm20b_is_valid_compute_class(struct gk20a *g, u32 class_num) |
495 | { | 500 | { |
496 | if (class_num == MAXWELL_COMPUTE_B) | 501 | if (class_num == MAXWELL_COMPUTE_B) { |
497 | return true; | 502 | return true; |
498 | else | 503 | } else { |
499 | return false; | 504 | return false; |
505 | } | ||
500 | } | 506 | } |
501 | 507 | ||
502 | 508 | ||
@@ -511,8 +517,9 @@ static u32 _sm_dsm_perf_ctrl_regs[2]; | |||
511 | 517 | ||
512 | void gr_gm20b_init_sm_dsm_reg_info(void) | 518 | void gr_gm20b_init_sm_dsm_reg_info(void) |
513 | { | 519 | { |
514 | if (_sm_dsm_perf_ctrl_regs[0] != 0) | 520 | if (_sm_dsm_perf_ctrl_regs[0] != 0) { |
515 | return; | 521 | return; |
522 | } | ||
516 | 523 | ||
517 | _sm_dsm_perf_ctrl_regs[0] = | 524 | _sm_dsm_perf_ctrl_regs[0] = |
518 | gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(); | 525 | gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(); |
@@ -619,8 +626,9 @@ int gr_gm20b_load_smid_config(struct gk20a *g) | |||
619 | u32 tpc_index, gpc_index; | 626 | u32 tpc_index, gpc_index; |
620 | 627 | ||
621 | tpc_sm_id = nvgpu_kcalloc(g, gr_cwd_sm_id__size_1_v(), sizeof(u32)); | 628 | tpc_sm_id = nvgpu_kcalloc(g, gr_cwd_sm_id__size_1_v(), sizeof(u32)); |
622 | if (!tpc_sm_id) | 629 | if (!tpc_sm_id) { |
623 | return -ENOMEM; | 630 | return -ENOMEM; |
631 | } | ||
624 | 632 | ||
625 | /* Each NV_PGRAPH_PRI_CWD_GPC_TPC_ID can store 4 TPCs.*/ | 633 | /* Each NV_PGRAPH_PRI_CWD_GPC_TPC_ID can store 4 TPCs.*/ |
626 | for (i = 0; i <= ((g->gr.tpc_count-1) / 4); i++) { | 634 | for (i = 0; i <= ((g->gr.tpc_count-1) / 4); i++) { |
@@ -632,8 +640,9 @@ int gr_gm20b_load_smid_config(struct gk20a *g) | |||
632 | u32 sm_id = (i * 4) + j; | 640 | u32 sm_id = (i * 4) + j; |
633 | u32 bits; | 641 | u32 bits; |
634 | 642 | ||
635 | if (sm_id >= g->gr.tpc_count) | 643 | if (sm_id >= g->gr.tpc_count) { |
636 | break; | 644 | break; |
645 | } | ||
637 | 646 | ||
638 | gpc_index = g->gr.sm_to_cluster[sm_id].gpc_index; | 647 | gpc_index = g->gr.sm_to_cluster[sm_id].gpc_index; |
639 | tpc_index = g->gr.sm_to_cluster[sm_id].tpc_index; | 648 | tpc_index = g->gr.sm_to_cluster[sm_id].tpc_index; |
@@ -663,8 +672,9 @@ int gr_gm20b_init_fs_state(struct gk20a *g) | |||
663 | nvgpu_log_fn(g, " "); | 672 | nvgpu_log_fn(g, " "); |
664 | 673 | ||
665 | err = gr_gk20a_init_fs_state(g); | 674 | err = gr_gk20a_init_fs_state(g); |
666 | if (err) | 675 | if (err) { |
667 | return err; | 676 | return err; |
677 | } | ||
668 | 678 | ||
669 | g->ops.gr.load_tpc_mask(g); | 679 | g->ops.gr.load_tpc_mask(g); |
670 | 680 | ||
@@ -731,8 +741,9 @@ u32 gr_gm20b_get_tpc_num(struct gk20a *g, u32 addr) | |||
731 | for (i = 0; i < num_tpcs; i++) { | 741 | for (i = 0; i < num_tpcs; i++) { |
732 | start = tpc_in_gpc_base + (i * tpc_in_gpc_stride); | 742 | start = tpc_in_gpc_base + (i * tpc_in_gpc_stride); |
733 | if ((addr >= start) && | 743 | if ((addr >= start) && |
734 | (addr < (start + tpc_in_gpc_stride))) | 744 | (addr < (start + tpc_in_gpc_stride))) { |
735 | return i; | 745 | return i; |
746 | } | ||
736 | } | 747 | } |
737 | return 0; | 748 | return 0; |
738 | } | 749 | } |
@@ -793,10 +804,12 @@ int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
793 | } else { | 804 | } else { |
794 | /* bind WPR VA inst block */ | 805 | /* bind WPR VA inst block */ |
795 | gr_gk20a_load_falcon_bind_instblk(g); | 806 | gr_gk20a_load_falcon_bind_instblk(g); |
796 | if (g->ops.pmu.is_lazy_bootstrap(LSF_FALCON_ID_FECS)) | 807 | if (g->ops.pmu.is_lazy_bootstrap(LSF_FALCON_ID_FECS)) { |
797 | falcon_id_mask |= (1 << LSF_FALCON_ID_FECS); | 808 | falcon_id_mask |= (1 << LSF_FALCON_ID_FECS); |
798 | if (g->ops.pmu.is_lazy_bootstrap(LSF_FALCON_ID_GPCCS)) | 809 | } |
810 | if (g->ops.pmu.is_lazy_bootstrap(LSF_FALCON_ID_GPCCS)) { | ||
799 | falcon_id_mask |= (1 << LSF_FALCON_ID_GPCCS); | 811 | falcon_id_mask |= (1 << LSF_FALCON_ID_GPCCS); |
812 | } | ||
800 | 813 | ||
801 | err = g->ops.pmu.load_lsfalcon_ucode(g, falcon_id_mask); | 814 | err = g->ops.pmu.load_lsfalcon_ucode(g, falcon_id_mask); |
802 | 815 | ||
@@ -856,11 +869,13 @@ int gr_gm20b_alloc_gr_ctx(struct gk20a *g, | |||
856 | nvgpu_log_fn(g, " "); | 869 | nvgpu_log_fn(g, " "); |
857 | 870 | ||
858 | err = gr_gk20a_alloc_gr_ctx(g, gr_ctx, vm, class, flags); | 871 | err = gr_gk20a_alloc_gr_ctx(g, gr_ctx, vm, class, flags); |
859 | if (err) | 872 | if (err) { |
860 | return err; | 873 | return err; |
874 | } | ||
861 | 875 | ||
862 | if (class == MAXWELL_COMPUTE_B) | 876 | if (class == MAXWELL_COMPUTE_B) { |
863 | gr_ctx->compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CTA; | 877 | gr_ctx->compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CTA; |
878 | } | ||
864 | 879 | ||
865 | nvgpu_log_fn(g, "done"); | 880 | nvgpu_log_fn(g, "done"); |
866 | 881 | ||
@@ -879,8 +894,9 @@ void gr_gm20b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
879 | nvgpu_log_fn(g, " "); | 894 | nvgpu_log_fn(g, " "); |
880 | 895 | ||
881 | tsg = tsg_gk20a_from_ch(c); | 896 | tsg = tsg_gk20a_from_ch(c); |
882 | if (!tsg) | 897 | if (!tsg) { |
883 | return; | 898 | return; |
899 | } | ||
884 | 900 | ||
885 | gr_ctx = &tsg->gr_ctx; | 901 | gr_ctx = &tsg->gr_ctx; |
886 | if (gr_ctx->compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CTA) { | 902 | if (gr_ctx->compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CTA) { |
@@ -941,9 +957,10 @@ int gr_gm20b_dump_gr_status_regs(struct gk20a *g, | |||
941 | gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r())); | 957 | gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r())); |
942 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", | 958 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", |
943 | gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r())); | 959 | gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r())); |
944 | if (gr->gpc_tpc_count && gr->gpc_tpc_count[0] == 2) | 960 | if (gr->gpc_tpc_count && gr->gpc_tpc_count[0] == 2) { |
945 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", | 961 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", |
946 | gk20a_readl(g, gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r())); | 962 | gk20a_readl(g, gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r())); |
963 | } | ||
947 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", | 964 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", |
948 | gk20a_readl(g, gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r())); | 965 | gk20a_readl(g, gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r())); |
949 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0: 0x%x\n", | 966 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0: 0x%x\n", |
@@ -956,9 +973,10 @@ int gr_gm20b_dump_gr_status_regs(struct gk20a *g, | |||
956 | gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_3_r())); | 973 | gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_3_r())); |
957 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", | 974 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", |
958 | gk20a_readl(g, gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r())); | 975 | gk20a_readl(g, gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r())); |
959 | if (gr->gpc_tpc_count && gr->gpc_tpc_count[0] == 2) | 976 | if (gr->gpc_tpc_count && gr->gpc_tpc_count[0] == 2) { |
960 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", | 977 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", |
961 | gk20a_readl(g, gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r())); | 978 | gk20a_readl(g, gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r())); |
979 | } | ||
962 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", | 980 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", |
963 | gk20a_readl(g, gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r())); | 981 | gk20a_readl(g, gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r())); |
964 | gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0: 0x%x\n", | 982 | gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0: 0x%x\n", |
@@ -1042,13 +1060,15 @@ int gr_gm20b_update_pc_sampling(struct channel_gk20a *c, | |||
1042 | nvgpu_log_fn(c->g, " "); | 1060 | nvgpu_log_fn(c->g, " "); |
1043 | 1061 | ||
1044 | tsg = tsg_gk20a_from_ch(c); | 1062 | tsg = tsg_gk20a_from_ch(c); |
1045 | if (!tsg) | 1063 | if (!tsg) { |
1046 | return -EINVAL; | 1064 | return -EINVAL; |
1065 | } | ||
1047 | 1066 | ||
1048 | gr_ctx = &tsg->gr_ctx; | 1067 | gr_ctx = &tsg->gr_ctx; |
1049 | mem = &gr_ctx->mem; | 1068 | mem = &gr_ctx->mem; |
1050 | if (!nvgpu_mem_is_valid(mem) || c->vpr) | 1069 | if (!nvgpu_mem_is_valid(mem) || c->vpr) { |
1051 | return -EINVAL; | 1070 | return -EINVAL; |
1071 | } | ||
1052 | 1072 | ||
1053 | 1073 | ||
1054 | v = nvgpu_mem_rd(c->g, mem, ctxsw_prog_main_image_pm_o()); | 1074 | v = nvgpu_mem_rd(c->g, mem, ctxsw_prog_main_image_pm_o()); |
@@ -1349,8 +1369,9 @@ int gm20b_gr_update_sm_error_state(struct gk20a *g, | |||
1349 | int err = 0; | 1369 | int err = 0; |
1350 | 1370 | ||
1351 | tsg = tsg_gk20a_from_ch(ch); | 1371 | tsg = tsg_gk20a_from_ch(ch); |
1352 | if (!tsg) | 1372 | if (!tsg) { |
1353 | return -EINVAL; | 1373 | return -EINVAL; |
1374 | } | ||
1354 | 1375 | ||
1355 | ch_ctx = &tsg->gr_ctx; | 1376 | ch_ctx = &tsg->gr_ctx; |
1356 | 1377 | ||
@@ -1374,8 +1395,9 @@ int gm20b_gr_update_sm_error_state(struct gk20a *g, | |||
1374 | gm20b_gr_write_sm_error_state(g, offset, tsg_sm_error_states); | 1395 | gm20b_gr_write_sm_error_state(g, offset, tsg_sm_error_states); |
1375 | } else { | 1396 | } else { |
1376 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, false); | 1397 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, false); |
1377 | if (err) | 1398 | if (err) { |
1378 | goto enable_ctxsw; | 1399 | goto enable_ctxsw; |
1400 | } | ||
1379 | 1401 | ||
1380 | gr_gk20a_ctx_patch_write(g, ch_ctx, | 1402 | gr_gk20a_ctx_patch_write(g, ch_ctx, |
1381 | gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r() + offset, | 1403 | gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r() + offset, |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index acdf4591..27daccb6 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -716,8 +716,9 @@ int gm20b_init_hal(struct gk20a *g) | |||
716 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 716 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
717 | 717 | ||
718 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ | 718 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ |
719 | if (gops->fuse.check_priv_security(g)) | 719 | if (gops->fuse.check_priv_security(g)) { |
720 | return -EINVAL; /* Do not boot gpu */ | 720 | return -EINVAL; /* Do not boot gpu */ |
721 | } | ||
721 | 722 | ||
722 | /* priv security dependent ops */ | 723 | /* priv security dependent ops */ |
723 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | 724 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c index 9be3180c..dbaaacc5 100644 --- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c | |||
@@ -42,10 +42,11 @@ void gm20b_mm_set_big_page_size(struct gk20a *g, | |||
42 | val = nvgpu_mem_rd32(g, mem, ram_in_big_page_size_w()); | 42 | val = nvgpu_mem_rd32(g, mem, ram_in_big_page_size_w()); |
43 | val &= ~ram_in_big_page_size_m(); | 43 | val &= ~ram_in_big_page_size_m(); |
44 | 44 | ||
45 | if (size == SZ_64K) | 45 | if (size == SZ_64K) { |
46 | val |= ram_in_big_page_size_64kb_f(); | 46 | val |= ram_in_big_page_size_64kb_f(); |
47 | else | 47 | } else { |
48 | val |= ram_in_big_page_size_128kb_f(); | 48 | val |= ram_in_big_page_size_128kb_f(); |
49 | } | ||
49 | 50 | ||
50 | nvgpu_mem_wr32(g, mem, ram_in_big_page_size_w(), val); | 51 | nvgpu_mem_wr32(g, mem, ram_in_big_page_size_w(), val); |
51 | nvgpu_log_fn(g, "done"); | 52 | nvgpu_log_fn(g, "done"); |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 53bec96f..286a1979 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -131,8 +131,9 @@ static void pmu_handle_acr_init_wpr_msg(struct gk20a *g, struct pmu_msg *msg, | |||
131 | 131 | ||
132 | gm20b_dbg_pmu(g, "reply PMU_ACR_CMD_ID_INIT_WPR_REGION"); | 132 | gm20b_dbg_pmu(g, "reply PMU_ACR_CMD_ID_INIT_WPR_REGION"); |
133 | 133 | ||
134 | if (msg->msg.acr.acrmsg.errorcode == PMU_ACR_SUCCESS) | 134 | if (msg->msg.acr.acrmsg.errorcode == PMU_ACR_SUCCESS) { |
135 | g->pmu_lsf_pmu_wpr_init_done = 1; | 135 | g->pmu_lsf_pmu_wpr_init_done = 1; |
136 | } | ||
136 | nvgpu_log_fn(g, "done"); | 137 | nvgpu_log_fn(g, "done"); |
137 | } | 138 | } |
138 | 139 | ||
@@ -189,8 +190,9 @@ static int pmu_gm20b_ctx_wait_lsf_ready(struct gk20a *g, u32 timeout_ms, | |||
189 | 190 | ||
190 | do { | 191 | do { |
191 | reg = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0)); | 192 | reg = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0)); |
192 | if (reg == val) | 193 | if (reg == val) { |
193 | return 0; | 194 | return 0; |
195 | } | ||
194 | nvgpu_udelay(delay); | 196 | nvgpu_udelay(delay); |
195 | } while (!nvgpu_timeout_expired(&timeout)); | 197 | } while (!nvgpu_timeout_expired(&timeout)); |
196 | 198 | ||
@@ -233,8 +235,9 @@ int gm20b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) | |||
233 | unsigned long timeout = gk20a_get_gr_idle_timeout(g); | 235 | unsigned long timeout = gk20a_get_gr_idle_timeout(g); |
234 | 236 | ||
235 | /* GM20B PMU supports loading FECS only */ | 237 | /* GM20B PMU supports loading FECS only */ |
236 | if (!(falconidmask == (1 << LSF_FALCON_ID_FECS))) | 238 | if (!(falconidmask == (1 << LSF_FALCON_ID_FECS))) { |
237 | return -EINVAL; | 239 | return -EINVAL; |
240 | } | ||
238 | /* check whether pmu is ready to bootstrap lsf if not wait for it */ | 241 | /* check whether pmu is ready to bootstrap lsf if not wait for it */ |
239 | if (!g->pmu_lsf_pmu_wpr_init_done) { | 242 | if (!g->pmu_lsf_pmu_wpr_init_done) { |
240 | pmu_wait_message_cond(&g->pmu, | 243 | pmu_wait_message_cond(&g->pmu, |