diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 56 |
2 files changed, 44 insertions, 22 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index ed730174..6e05d645 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -973,8 +973,16 @@ static bool gk20a_fifo_handle_mmu_fault(struct gk20a *g) | |||
973 | 973 | ||
974 | g->fifo.deferred_reset_pending = false; | 974 | g->fifo.deferred_reset_pending = false; |
975 | 975 | ||
976 | /* Disable ELPG */ | 976 | /* Disable power management */ |
977 | gk20a_pmu_disable_elpg(g); | 977 | gk20a_pmu_disable_elpg(g); |
978 | g->ops.clock_gating.slcg_gr_load_gating_prod(g, | ||
979 | false); | ||
980 | g->ops.clock_gating.slcg_perf_load_gating_prod(g, | ||
981 | false); | ||
982 | g->ops.clock_gating.slcg_ltc_load_gating_prod(g, | ||
983 | false); | ||
984 | gr_gk20a_init_elcg_mode(g, ELCG_RUN, ENGINE_GR_GK20A); | ||
985 | gr_gk20a_init_elcg_mode(g, ELCG_RUN, ENGINE_CE2_GK20A); | ||
978 | 986 | ||
979 | /* Disable fifo access */ | 987 | /* Disable fifo access */ |
980 | grfifo_ctl = gk20a_readl(g, gr_gpfifo_ctl_r()); | 988 | grfifo_ctl = gk20a_readl(g, gr_gpfifo_ctl_r()); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index b3fc8ae1..47f11a1f 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -78,6 +78,8 @@ static void gr_gk20a_free_channel_patch_ctx(struct channel_gk20a *c); | |||
78 | /* golden ctx image */ | 78 | /* golden ctx image */ |
79 | static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | 79 | static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, |
80 | struct channel_gk20a *c); | 80 | struct channel_gk20a *c); |
81 | /*elcg init */ | ||
82 | static void gr_gk20a_enable_elcg(struct gk20a *g); | ||
81 | 83 | ||
82 | /* sm lock down */ | 84 | /* sm lock down */ |
83 | static int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, | 85 | static int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, |
@@ -4256,14 +4258,6 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4256 | 4258 | ||
4257 | gr_gk20a_zcull_init_hw(g, gr); | 4259 | gr_gk20a_zcull_init_hw(g, gr); |
4258 | 4260 | ||
4259 | if (g->elcg_enabled) { | ||
4260 | gr_gk20a_init_elcg_mode(g, ELCG_AUTO, ENGINE_GR_GK20A); | ||
4261 | gr_gk20a_init_elcg_mode(g, ELCG_AUTO, ENGINE_CE2_GK20A); | ||
4262 | } else { | ||
4263 | gr_gk20a_init_elcg_mode(g, ELCG_RUN, ENGINE_GR_GK20A); | ||
4264 | gr_gk20a_init_elcg_mode(g, ELCG_RUN, ENGINE_CE2_GK20A); | ||
4265 | } | ||
4266 | |||
4267 | /* Bug 1340570: increase the clock timeout to avoid potential | 4261 | /* Bug 1340570: increase the clock timeout to avoid potential |
4268 | * operation failure at high gpcclk rate. Default values are 0x400. | 4262 | * operation failure at high gpcclk rate. Default values are 0x400. |
4269 | */ | 4263 | */ |
@@ -4380,6 +4374,22 @@ out: | |||
4380 | return 0; | 4374 | return 0; |
4381 | } | 4375 | } |
4382 | 4376 | ||
4377 | static void gr_gk20a_load_gating_prod(struct gk20a *g) | ||
4378 | { | ||
4379 | /* slcg prod values */ | ||
4380 | g->ops.clock_gating.slcg_gr_load_gating_prod(g, g->slcg_enabled); | ||
4381 | if (g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod) | ||
4382 | g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod(g, | ||
4383 | g->slcg_enabled); | ||
4384 | g->ops.clock_gating.slcg_perf_load_gating_prod(g, g->slcg_enabled); | ||
4385 | |||
4386 | g->ops.clock_gating.blcg_gr_load_gating_prod(g, g->blcg_enabled); | ||
4387 | if (g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod) | ||
4388 | g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod(g, | ||
4389 | g->blcg_enabled); | ||
4390 | g->ops.clock_gating.pg_gr_load_gating_prod(g, true); | ||
4391 | } | ||
4392 | |||
4383 | static int gk20a_init_gr_prepare(struct gk20a *g) | 4393 | static int gk20a_init_gr_prepare(struct gk20a *g) |
4384 | { | 4394 | { |
4385 | u32 gpfifo_ctrl, pmc_en; | 4395 | u32 gpfifo_ctrl, pmc_en; |
@@ -4398,18 +4408,7 @@ static int gk20a_init_gr_prepare(struct gk20a *g) | |||
4398 | | mc_enable_blg_enabled_f() | 4408 | | mc_enable_blg_enabled_f() |
4399 | | mc_enable_perfmon_enabled_f()); | 4409 | | mc_enable_perfmon_enabled_f()); |
4400 | 4410 | ||
4401 | /* slcg prod values */ | 4411 | gr_gk20a_load_gating_prod(g); |
4402 | g->ops.clock_gating.slcg_gr_load_gating_prod(g, g->slcg_enabled); | ||
4403 | if (g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod) | ||
4404 | g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod(g, | ||
4405 | g->slcg_enabled); | ||
4406 | g->ops.clock_gating.slcg_perf_load_gating_prod(g, g->slcg_enabled); | ||
4407 | |||
4408 | g->ops.clock_gating.blcg_gr_load_gating_prod(g, g->blcg_enabled); | ||
4409 | if (g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod) | ||
4410 | g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod(g, | ||
4411 | g->blcg_enabled); | ||
4412 | g->ops.clock_gating.pg_gr_load_gating_prod(g, true); | ||
4413 | 4412 | ||
4414 | /* enable fifo access */ | 4413 | /* enable fifo access */ |
4415 | gk20a_writel(g, gr_gpfifo_ctl_r(), | 4414 | gk20a_writel(g, gr_gpfifo_ctl_r(), |
@@ -4742,6 +4741,7 @@ int gk20a_init_gr_support(struct gk20a *g) | |||
4742 | if (err) | 4741 | if (err) |
4743 | return err; | 4742 | return err; |
4744 | 4743 | ||
4744 | gr_gk20a_enable_elcg(g); | ||
4745 | /* GR is inialized, signal possible waiters */ | 4745 | /* GR is inialized, signal possible waiters */ |
4746 | g->gr.initialized = true; | 4746 | g->gr.initialized = true; |
4747 | wake_up(&g->gr.init_wq); | 4747 | wake_up(&g->gr.init_wq); |
@@ -4935,6 +4935,17 @@ int gk20a_enable_gr_hw(struct gk20a *g) | |||
4935 | return 0; | 4935 | return 0; |
4936 | } | 4936 | } |
4937 | 4937 | ||
4938 | static void gr_gk20a_enable_elcg(struct gk20a *g) | ||
4939 | { | ||
4940 | if (g->elcg_enabled) { | ||
4941 | gr_gk20a_init_elcg_mode(g, ELCG_AUTO, ENGINE_GR_GK20A); | ||
4942 | gr_gk20a_init_elcg_mode(g, ELCG_AUTO, ENGINE_CE2_GK20A); | ||
4943 | } else { | ||
4944 | gr_gk20a_init_elcg_mode(g, ELCG_RUN, ENGINE_GR_GK20A); | ||
4945 | gr_gk20a_init_elcg_mode(g, ELCG_RUN, ENGINE_CE2_GK20A); | ||
4946 | } | ||
4947 | } | ||
4948 | |||
4938 | int gk20a_gr_reset(struct gk20a *g) | 4949 | int gk20a_gr_reset(struct gk20a *g) |
4939 | { | 4950 | { |
4940 | int err; | 4951 | int err; |
@@ -4975,7 +4986,10 @@ int gk20a_gr_reset(struct gk20a *g) | |||
4975 | return err; | 4986 | return err; |
4976 | } | 4987 | } |
4977 | 4988 | ||
4978 | return 0; | 4989 | gr_gk20a_load_gating_prod(g); |
4990 | gr_gk20a_enable_elcg(g); | ||
4991 | |||
4992 | return err; | ||
4979 | } | 4993 | } |
4980 | 4994 | ||
4981 | static int gr_gk20a_handle_sw_method(struct gk20a *g, u32 addr, | 4995 | static int gr_gk20a_handle_sw_method(struct gk20a *g, u32 addr, |