diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/clk_gk20a.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/clk_gk20a.h | 1 |
2 files changed, 7 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c index 3fd25afa..44f8fb64 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c | |||
@@ -39,6 +39,10 @@ static struct pll_parms gpc_pll_params = { | |||
39 | 1, 255, /* M */ | 39 | 1, 255, /* M */ |
40 | 8, 255, /* N */ | 40 | 8, 255, /* N */ |
41 | 1, 32, /* PL */ | 41 | 1, 32, /* PL */ |
42 | 0, 0, 0, 0, 0, /* NA mode parameters: not supported on GK20A */ | ||
43 | 500, /* Locking and ramping timeout */ | ||
44 | 0, /* NA mode lock delay: not supported on GK20A */ | ||
45 | 2, /* IDDQ mode exit delay */ | ||
42 | }; | 46 | }; |
43 | 47 | ||
44 | #ifdef CONFIG_DEBUG_FS | 48 | #ifdef CONFIG_DEBUG_FS |
@@ -185,7 +189,7 @@ static int clk_slide_gpc_pll(struct gk20a *g, u32 n) | |||
185 | { | 189 | { |
186 | u32 data, coeff; | 190 | u32 data, coeff; |
187 | u32 nold; | 191 | u32 nold; |
188 | int ramp_timeout = 500; | 192 | int ramp_timeout = gpc_pll_params.lock_timeout; |
189 | 193 | ||
190 | /* get old coefficients */ | 194 | /* get old coefficients */ |
191 | coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r()); | 195 | coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r()); |
@@ -307,7 +311,7 @@ static int clk_program_gpc_pll(struct gk20a *g, struct clk_gk20a *clk, | |||
307 | trim_sys_gpcpll_cfg_iddq_power_on_v()); | 311 | trim_sys_gpcpll_cfg_iddq_power_on_v()); |
308 | gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg); | 312 | gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg); |
309 | gk20a_readl(g, trim_sys_gpcpll_cfg_r()); | 313 | gk20a_readl(g, trim_sys_gpcpll_cfg_r()); |
310 | udelay(2); | 314 | udelay(gpc_pll_params.iddq_exit_delay); |
311 | } | 315 | } |
312 | 316 | ||
313 | /* disable PLL before changing coefficients */ | 317 | /* disable PLL before changing coefficients */ |
@@ -341,7 +345,7 @@ static int clk_program_gpc_pll(struct gk20a *g, struct clk_gk20a *clk, | |||
341 | } | 345 | } |
342 | 346 | ||
343 | /* wait pll lock */ | 347 | /* wait pll lock */ |
344 | timeout = clk->pll_delay / 2 + 1; | 348 | timeout = gpc_pll_params.lock_timeout / 2 + 1; |
345 | do { | 349 | do { |
346 | cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); | 350 | cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); |
347 | if (cfg & trim_sys_gpcpll_cfg_pll_lock_true_f()) | 351 | if (cfg & trim_sys_gpcpll_cfg_pll_lock_true_f()) |
@@ -456,8 +460,6 @@ static int gk20a_init_clk_setup_sw(struct gk20a *g) | |||
456 | } | 460 | } |
457 | ref_rate = clk_get_rate(ref); | 461 | ref_rate = clk_get_rate(ref); |
458 | 462 | ||
459 | clk->pll_delay = 300; /* usec */ | ||
460 | |||
461 | clk->gpc_pll.id = GK20A_GPC_PLL; | 463 | clk->gpc_pll.id = GK20A_GPC_PLL; |
462 | clk->gpc_pll.clk_in = ref_rate / KHZ; | 464 | clk->gpc_pll.clk_in = ref_rate / KHZ; |
463 | 465 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h index 9f5ea39e..8408f460 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h | |||
@@ -79,7 +79,6 @@ struct clk_gk20a { | |||
79 | struct clk *tegra_clk; | 79 | struct clk *tegra_clk; |
80 | struct pll gpc_pll; | 80 | struct pll gpc_pll; |
81 | struct pll gpc_pll_last; | 81 | struct pll gpc_pll_last; |
82 | u32 pll_delay; /* default PLL settle time */ | ||
83 | struct mutex clk_mutex; | 82 | struct mutex clk_mutex; |
84 | bool sw_ready; | 83 | bool sw_ready; |
85 | bool clk_hw_on; | 84 | bool clk_hw_on; |