17 files changed, 130 insertions, 31 deletions

diff --git a/drivers/gpu/nvgpu/Kconfig b/drivers/gpu/nvgpu/Kconfig
index e0b433c1..00fd3b08 100644
--- a/drivers/gpu/nvgpu/Kconfig
+++ b/drivers/gpu/nvgpu/Kconfig
@@ -8,7 +8,7 @@ config GK20A
 config GK20A_DEFAULT_TIMEOUT
         depends on GK20A
         int "Default timeout for submits"
-        default 5000
+        default 3000
         help
           Default timeout for jobs in milliseconds. Set to zero for no timeout.
 
diff --git a/drivers/gpu/nvgpu/gk20a/cde_gk20a.c b/drivers/gpu/nvgpu/gk20a/cde_gk20a.c
index cd4e71bf..6d8633a7 100644
--- a/drivers/gpu/nvgpu/gk20a/cde_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/cde_gk20a.c
@@ -1035,6 +1035,7 @@ __releases(&cde_app->mutex)
                                 goto exit_unlock;
                 }
 
+                __cpuc_flush_dcache_area(scatter_buffer, scatterbuffer_size);
                 dma_buf_vunmap(compbits_scatter_buf, surface);
                 surface = NULL;
         }
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 2dc8e9a0..92b4b3de 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -136,8 +136,10 @@ static int channel_gk20a_set_schedule_params(struct channel_gk20a *c,
                                 u32 timeslice_timeout)
 {
         void *inst_ptr;
+        struct gk20a_platform *platform = platform_get_drvdata(c->g->dev);
         int shift = 3;
-        int value = timeslice_timeout;
+        int value = scale_ptimer(timeslice_timeout,
+                        platform->ptimerscaling10x);
 
         inst_ptr = c->inst_block.cpu_va;
         if (!inst_ptr)
@@ -1474,8 +1476,11 @@ bool gk20a_channel_update_and_check_timeout(struct channel_gk20a *ch,
 
 static u32 gk20a_get_channel_watchdog_timeout(struct channel_gk20a *ch)
 {
-        if (ch->g->timeouts_enabled && ch->g->ch_wdt_enabled)
-                return NVGPU_CHANNEL_WATCHDOG_DEFAULT_TIMEOUT_MS;
+        struct gk20a_platform *platform = gk20a_get_platform(ch->g->dev);
+
+        if (ch->g->timeouts_enabled && ch->g->ch_wdt_enabled &&
+                                platform->ch_wdt_timeout_ms)
+                return platform->ch_wdt_timeout_ms;
         else
                 return (u32)MAX_SCHEDULE_TIMEOUT;
 }
@@ -1568,6 +1573,21 @@ static void gk20a_channel_timeout_stop(struct channel_gk20a *ch)
         mutex_unlock(&ch->timeout.lock);
 }
 
+void gk20a_channel_timeout_stop_all_channels(struct gk20a *g)
+{
+        u32 chid;
+        struct fifo_gk20a *f = &g->fifo;
+
+        for (chid = 0; chid < f->num_channels; chid++) {
+                struct channel_gk20a *ch = &f->channel[chid];
+
+                if (gk20a_channel_get(ch)) {
+                        gk20a_channel_timeout_stop(ch);
+                        gk20a_channel_put(ch);
+                }
+        }
+}
+
 static void gk20a_channel_timeout_handler(struct work_struct *work)
 {
         struct channel_gk20a_job *job;
@@ -2339,16 +2359,13 @@ static int gk20a_channel_set_priority(struct channel_gk20a *ch,
         /* set priority of graphics channel */
         switch (priority) {
         case NVGPU_PRIORITY_LOW:
-                /* 64 << 3 = 512us */
-                timeslice_timeout = 64;
+                timeslice_timeout = ch->g->timeslice_low_priority_us;
                 break;
         case NVGPU_PRIORITY_MEDIUM:
-                /* 128 << 3 = 1024us */
-                timeslice_timeout = 128;
+                timeslice_timeout = ch->g->timeslice_medium_priority_us;
                 break;
         case NVGPU_PRIORITY_HIGH:
-                /* 255 << 3 = 2048us */
-                timeslice_timeout = 255;
+                timeslice_timeout = ch->g->timeslice_high_priority_us;
                 break;
         default:
                 pr_err("Unsupported priority");
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
index 9d74b412..280c50b1 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
@@ -38,8 +38,6 @@ struct gk20a_fence;
 #include "gr_gk20a.h"
 #include "fence_gk20a.h"
 
-#define NVGPU_CHANNEL_WATCHDOG_DEFAULT_TIMEOUT_MS       5000
-
 struct gpfifo {
         u32 entry0;
         u32 entry1;
@@ -258,4 +256,5 @@ void channel_gk20a_free_inst(struct gk20a *g, struct channel_gk20a *ch);
 int channel_gk20a_setup_ramfc(struct channel_gk20a *c,
                         u64 gpfifo_base, u32 gpfifo_entries, u32 flags);
 void channel_gk20a_enable(struct channel_gk20a *ch);
+void gk20a_channel_timeout_stop_all_channels(struct gk20a *g);
 #endif /* CHANNEL_GK20A_H */
diff --git a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
index bda0dab0..1cac683d 100644
--- a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
@@ -418,6 +418,9 @@ void gk20a_debug_init(struct platform_device *pdev)
         debugfs_create_u32("trace_cmdbuf", S_IRUGO|S_IWUSR, platform->debugfs,
                         &gk20a_debug_trace_cmdbuf);
 
+        debugfs_create_u32("ch_wdt_timeout_ms", S_IRUGO|S_IWUSR,
+                        platform->debugfs, &platform->ch_wdt_timeout_ms);
+
 #if defined(GK20A_DEBUG)
         debugfs_create_u32("dbg_mask", S_IRUGO|S_IWUSR, platform->debugfs,
                         &gk20a_dbg_mask);
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index f736fe8c..4f3363f2 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -344,6 +344,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
         u32 mask;
         u32 timeout;
         int i;
+        struct gk20a_platform *platform = platform_get_drvdata(g->dev);
 
         gk20a_dbg_fn("");
         /* enable pmc pfifo */
@@ -408,8 +409,9 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
         if (g->ops.fifo.apply_pb_timeout)
                 g->ops.fifo.apply_pb_timeout(g);
 
-        timeout = GRFIFO_TIMEOUT_CHECK_PERIOD_US |
-                        fifo_eng_timeout_detection_enabled_f();
+        timeout = GRFIFO_TIMEOUT_CHECK_PERIOD_US;
+        timeout = scale_ptimer(timeout, platform->ptimerscaling10x);
+        timeout |= fifo_eng_timeout_detection_enabled_f();
         gk20a_writel(g, fifo_eng_timeout_r(), timeout);
 
         gk20a_dbg_fn("done");
@@ -1448,6 +1450,7 @@ static bool gk20a_fifo_handle_sched_error(struct gk20a *g)
                 struct channel_gk20a *ch = &f->channel[id];
 
                 if (is_tsg) {
+                        gk20a_channel_timeout_stop_all_channels(g);
                         gk20a_fifo_recover(g, BIT(engine_id), id, true,
                                         true, true);
                         ret = true;
@@ -1465,6 +1468,11 @@ static bool gk20a_fifo_handle_sched_error(struct gk20a *g)
                                 "fifo sched ctxsw timeout error:"
                                 "engine = %u, ch = %d", engine_id, id);
                         gk20a_gr_debug_dump(g->dev);
+                        /*
+                         * Cancel all channels' timeout since SCHED error might
+                         * trigger multiple watchdogs at a time
+                         */
+                        gk20a_channel_timeout_stop_all_channels(g);
                         gk20a_fifo_recover(g, BIT(engine_id), id, false,
                                 true, ch->timeout_debug_dump);
                         ret = true;
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index c606e027..0cc29026 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -40,6 +40,7 @@
 #include <linux/clk/tegra.h>
 #include <linux/kthread.h>
 #include <linux/platform/tegra/common.h>
+#include <linux/reset.h>
 
 #include <linux/sched.h>
 
@@ -1166,7 +1167,10 @@ static void gk20a_pm_shutdown(struct platform_device *pdev)
 #endif
 
         /* Be ready for rail-gate after this point */
-        gk20a_pm_prepare_poweroff(&pdev->dev);
+        if (gk20a_gpu_is_virtual(pdev))
+                vgpu_pm_prepare_poweroff(&pdev->dev);
+        else
+                gk20a_pm_prepare_poweroff(&pdev->dev);
 }
 
 #ifdef CONFIG_PM
@@ -1295,6 +1299,10 @@ static int gk20a_pm_init(struct platform_device *dev)
         if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
                 err = gk20a_pm_initialise_domain(dev);
 
+        platform->reset_control = devm_reset_control_get(&dev->dev, NULL);
+        if (IS_ERR(platform->reset_control))
+                platform->reset_control = NULL;
+
         return err;
 }
 
@@ -1452,6 +1460,10 @@ static int gk20a_probe(struct platform_device *dev)
                 gk20a->timeouts_enabled = true;
         gk20a->ch_wdt_enabled = true;
 
+        gk20a->timeslice_low_priority_us = 1300;
+        gk20a->timeslice_medium_priority_us = 2600;
+        gk20a->timeslice_high_priority_us = 5200;
+
         /* Set up initial power settings. For non-slicon platforms, disable *
          * power features and for silicon platforms, read from platform data */
         gk20a->slcg_enabled =
@@ -1504,6 +1516,25 @@ static int gk20a_probe(struct platform_device *dev)
                                         S_IRUGO|S_IWUSR,
                                         platform->debugfs,
                                         &gk20a->mm.disable_bigpage);
+
+        gk20a->debugfs_timeslice_low_priority_us =
+                        debugfs_create_u32("timeslice_low_priority_us",
+                                        S_IRUGO|S_IWUSR,
+                                        platform->debugfs,
+                                        &gk20a->timeslice_low_priority_us);
+
+        gk20a->debugfs_timeslice_medium_priority_us =
+                        debugfs_create_u32("timeslice_medium_priority_us",
+                                        S_IRUGO|S_IWUSR,
+                                        platform->debugfs,
+                                        &gk20a->timeslice_medium_priority_us);
+
+        gk20a->debugfs_timeslice_high_priority_us =
+                        debugfs_create_u32("timeslice_high_priority_us",
+                                        S_IRUGO|S_IWUSR,
+                                        platform->debugfs,
+                                        &gk20a->timeslice_high_priority_us);
+
         gr_gk20a_debugfs_init(gk20a);
         gk20a_pmu_debugfs_init(dev);
         gk20a_cde_debugfs_init(dev);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index a5e130cb..bec2d2a0 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -215,6 +215,7 @@ struct gpu_ops {
                 void (*blcg_ltc_load_gating_prod)(struct gk20a *g, bool prod);
                 void (*blcg_pwr_csb_load_gating_prod)(struct gk20a *g, bool prod);
                 void (*blcg_pmu_load_gating_prod)(struct gk20a *g, bool prod);
+                void (*blcg_xbar_load_gating_prod)(struct gk20a *g, bool prod);
                 void (*pg_gr_load_gating_prod)(struct gk20a *g, bool prod);
         } clock_gating;
         struct {
@@ -490,6 +491,11 @@ struct gk20a {
         u32 ch_wdt_enabled;
         struct mutex ch_wdt_lock;
 
+        /* Channel priorities */
+        u32 timeslice_low_priority_us;
+        u32 timeslice_medium_priority_us;
+        u32 timeslice_high_priority_us;
+
         bool slcg_enabled;
         bool blcg_enabled;
         bool elcg_enabled;
@@ -509,6 +515,10 @@ struct gk20a {
         struct dentry *debugfs_bypass_smmu;
         struct dentry *debugfs_disable_bigpage;
         struct dentry *debugfs_gr_default_attrib_cb_size;
+
+        struct dentry * debugfs_timeslice_low_priority_us;
+        struct dentry * debugfs_timeslice_medium_priority_us;
+        struct dentry * debugfs_timeslice_high_priority_us;
 #endif
         struct gk20a_ctxsw_ucode_info ctxsw_ucode_info;
 
@@ -885,4 +895,11 @@ void gk20a_user_deinit(struct platform_device *dev);
 
 extern void gk20a_debug_dump_device(struct platform_device *pdev);
 
+static inline u32 scale_ptimer(u32 timeout , u32 scale10x)
+{
+        if (((timeout*10) % scale10x) >= (scale10x/2))
+                return ((timeout * 10) / scale10x) + 1;
+        else
+                return (timeout * 10) / scale10x;
+}
 #endif /* GK20A_H */
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c b/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c
index 96a945f8..996fe221 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a_sysfs.c
@@ -115,6 +115,9 @@ static ssize_t blcg_enable_store(struct device *device,
                 g->ops.clock_gating.blcg_ltc_load_gating_prod(g, g->blcg_enabled);
         if (g->ops.clock_gating.blcg_pmu_load_gating_prod)
                 g->ops.clock_gating.blcg_pmu_load_gating_prod(g, g->blcg_enabled);
+        if (g->ops.clock_gating.blcg_xbar_load_gating_prod)
+                g->ops.clock_gating.blcg_xbar_load_gating_prod(g,
+                        g->blcg_enabled);
         gk20a_idle(g->dev);
 
         dev_info(device, "BLCG is %s.\n", g->blcg_enabled ? "enabled" :
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 19d9cffc..ea06bd20 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -1622,12 +1622,12 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g,
         if (!ctx_ptr)
                 return -ENOMEM;
 
-        if (g->ops.gr.enable_cde_in_fecs && c->cde)
-                g->ops.gr.enable_cde_in_fecs(ctx_ptr);
-
         for (i = 0; i < gr->ctx_vars.golden_image_size / 4; i++)
                 gk20a_mem_wr32(ctx_ptr, i, gr->ctx_vars.local_golden_image[i]);
 
+        if (g->ops.gr.enable_cde_in_fecs && c->cde)
+                g->ops.gr.enable_cde_in_fecs(ctx_ptr);
+
         gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_num_save_ops_o(), 0, 0);
         gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_num_restore_ops_o(), 0, 0);
 
@@ -4227,11 +4227,18 @@ static void gr_gk20a_load_gating_prod(struct gk20a *g)
                 g->ops.clock_gating.slcg_ctxsw_firmware_load_gating_prod(g,
                                 g->slcg_enabled);
         g->ops.clock_gating.slcg_perf_load_gating_prod(g, g->slcg_enabled);
+        if (g->ops.clock_gating.slcg_xbar_load_gating_prod)
+                g->ops.clock_gating.slcg_xbar_load_gating_prod(g,
+                                g->slcg_enabled);
 
+        /* blcg prod values */
         g->ops.clock_gating.blcg_gr_load_gating_prod(g, g->blcg_enabled);
         if (g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod)
                 g->ops.clock_gating.blcg_ctxsw_firmware_load_gating_prod(g,
                                 g->blcg_enabled);
+        if (g->ops.clock_gating.blcg_xbar_load_gating_prod)
+                g->ops.clock_gating.blcg_xbar_load_gating_prod(g,
+                                g->blcg_enabled);
         g->ops.clock_gating.pg_gr_load_gating_prod(g, true);
 }
 
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index b0c864d4..334f251c 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -2144,7 +2144,7 @@ static int update_gmmu_pde_locked(struct vm_gk20a *vm,
                            struct scatterlist **sgl,
                            u64 *offset,
                            u64 *iova,
-                           u32 kind_v, u32 *ctag,
+                           u32 kind_v, u64 *ctag,
                            bool cacheable, bool unammped_pte,
                            int rw_flag, bool sparse, bool priv)
 {
@@ -2194,12 +2194,12 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm,
                            struct scatterlist **sgl,
                            u64 *offset,
                            u64 *iova,
-                           u32 kind_v, u32 *ctag,
+                           u32 kind_v, u64 *ctag,
                            bool cacheable, bool unmapped_pte,
                            int rw_flag, bool sparse, bool priv)
 {
         struct gk20a *g = gk20a_from_vm(vm);
-        u32 ctag_granularity = g->ops.fb.compression_page_size(g);
+        u64 ctag_granularity = g->ops.fb.compression_page_size(g);
         u32 page_size  = vm->gmmu_page_sizes[gmmu_pgsz_idx];
         u32 pte_w[2] = {0, 0}; /* invalid pte */
 
@@ -2218,7 +2218,7 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm,
 
                 pte_w[1] = gmmu_pte_aperture_video_memory_f() |
                         gmmu_pte_kind_f(kind_v) |
-                        gmmu_pte_comptagline_f(*ctag / ctag_granularity);
+                        gmmu_pte_comptagline_f((u32)(*ctag / ctag_granularity));
 
                 if (rw_flag == gk20a_mem_flag_read_only) {
                         pte_w[0] |= gmmu_pte_read_only_true_f();
@@ -2244,7 +2244,7 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm,
                 gk20a_dbg(gpu_dbg_pte,
                         "pte=%d iova=0x%llx kind=%d ctag=%d vol=%d [0x%08x, 0x%08x]",
                            i, *iova,
-                           kind_v, *ctag / ctag_granularity, !cacheable,
+                           kind_v, (u32)(*ctag / ctag_granularity), !cacheable,
                            pte_w[1], pte_w[0]);
 
                 if (*ctag)
@@ -2287,7 +2287,7 @@ static int update_gmmu_level_locked(struct vm_gk20a *vm,
                                     u64 *offset,
                                     u64 *iova,
                                     u64 gpu_va, u64 gpu_end,
-                                    u8 kind_v, u32 *ctag,
+                                    u8 kind_v, u64 *ctag,
                                     bool cacheable, bool unmapped_pte,
                                     int rw_flag,
                                     bool sparse,
@@ -2390,7 +2390,7 @@ static int update_gmmu_ptes_locked(struct vm_gk20a *vm,
 {
         struct gk20a *g = gk20a_from_vm(vm);
         int ctag_granularity = g->ops.fb.compression_page_size(g);
-        u32 ctag = ctag_offset * ctag_granularity;
+        u64 ctag = (u64)ctag_offset * (u64)ctag_granularity;
         u64 iova = 0;
         u64 space_to_skip = buffer_offset;
         u32 page_size  = vm->gmmu_page_sizes[pgsz_idx];
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
index 6786e3c2..c60f1bb7 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
@@ -220,7 +220,7 @@ struct gk20a_mmu_level {
                            struct scatterlist **sgl,
                            u64 *offset,
                            u64 *iova,
-                           u32 kind_v, u32 *ctag,
+                           u32 kind_v, u64 *ctag,
                            bool cacheable, bool unmapped_pte,
                            int rw_flag, bool sparse, bool priv);
         size_t entry_size;
diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h
index 29c88f44..0c3c6ff3 100644
--- a/drivers/gpu/nvgpu/gk20a/platform_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a.h
@@ -3,7 +3,7 @@
  *
  * GK20A Platform (SoC) Interface
  *
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -55,6 +55,9 @@ struct gk20a_platform {
         struct clk *clk[3];
         int num_clks;
 
+        /* Reset control for device */
+        struct reset_control *reset_control;
+
         /* Delay before rail gated */
         int railgate_delay;
 
@@ -76,6 +79,9 @@ struct gk20a_platform {
         /* Adaptative ELPG: true = enable flase = disable */
         bool enable_aelpg;
 
+        /* Timeout for per-channel watchdog (in mS) */
+        u32 ch_wdt_timeout_ms;
+
         /* Enable SMMU bypass by default */
         bool bypass_smmu;
 
@@ -91,6 +97,9 @@ struct gk20a_platform {
         /* Default big page size 64K or 128K */
         u32 default_big_page_size;
 
+        /* scaling factor for ptimer */
+        u32  ptimerscaling10x;
+
         /* Initialize the platform interface of the gk20a driver.
          *
          * The platform implementation of this function must
diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c
index f8e1e3b7..2c9cfb63 100644
--- a/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c
+++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c
@@ -812,11 +812,14 @@ struct gk20a_platform gk20a_tegra_platform = {
         .enable_elcg            = true,
         .enable_elpg            = true,
         .enable_aelpg           = true,
+        .ptimerscaling10x       = 26,
 
         .force_reset_in_do_idle = false,
 
         .default_big_page_size  = SZ_128K,
 
+        .ch_wdt_timeout_ms = 7000,
+
         .probe = gk20a_tegra_probe,
         .late_probe = gk20a_tegra_late_probe,
         .remove = gk20a_tegra_remove,
@@ -858,11 +861,14 @@ struct gk20a_platform gm20b_tegra_platform = {
         .enable_elcg            = true,
         .enable_elpg            = true,
         .enable_aelpg           = true,
+        .ptimerscaling10x       = 26,
 
         .force_reset_in_do_idle = false,
 
         .default_big_page_size  = SZ_128K,
 
+        .ch_wdt_timeout_ms = 5000,
+
         .probe = gk20a_tegra_probe,
         .late_probe = gk20a_tegra_late_probe,
         .remove = gk20a_tegra_remove,
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 4d459ef4..09230437 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -4179,7 +4179,6 @@ int gk20a_pmu_destroy(struct gk20a *g)
         g->pg_gating_cnt += gating_cnt;
 
         mutex_lock(&pmu->isr_mutex);
-        pmu_enable(pmu, false);
         pmu->isr_enabled = false;
         mutex_unlock(&pmu->isr_mutex);
 
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index b8533f46..d590f566 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1041,10 +1041,10 @@ static void gr_gm20b_init_cyclestats(struct gk20a *g)
 #endif
 }
 
-void gr_gm20b_enable_cde_in_fecs(void *ctx_ptr)
+static void gr_gm20b_enable_cde_in_fecs(void *ctx_ptr)
 {
         u32 cde_v;
-        
+
         cde_v = gk20a_mem_rd32(ctx_ptr + ctxsw_prog_main_image_ctl_o(), 0);
         cde_v |=  ctxsw_prog_main_image_ctl_cde_enabled_f();
         gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_ctl_o(), 0, cde_v);
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index e32f8943..edd70f13 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -120,7 +120,6 @@ int gm20b_init_hal(struct gk20a *g)
                 }
         }
 #endif
-
         gm20b_init_mc(gops);
         gm20b_init_ltc(gops);
         gm20b_init_gr(gops);