diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/regops_gm20b.c | 46 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/regops_gp106.c | 40 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/regops_gp10b.c | 40 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/regops_gv100.c | 39 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/regops_gv11b.c | 38 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 8 |
14 files changed, 0 insertions, 268 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index fac7c5df..4d4b4cb1 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1140,15 +1140,8 @@ struct gpu_ops { | |||
1140 | u64 (*get_context_whitelist_ranges_count)(void); | 1140 | u64 (*get_context_whitelist_ranges_count)(void); |
1141 | const u32* (*get_runcontrol_whitelist)(void); | 1141 | const u32* (*get_runcontrol_whitelist)(void); |
1142 | u64 (*get_runcontrol_whitelist_count)(void); | 1142 | u64 (*get_runcontrol_whitelist_count)(void); |
1143 | const struct regop_offset_range* ( | ||
1144 | *get_runcontrol_whitelist_ranges)(void); | ||
1145 | u64 (*get_runcontrol_whitelist_ranges_count)(void); | ||
1146 | const u32* (*get_qctl_whitelist)(void); | 1143 | const u32* (*get_qctl_whitelist)(void); |
1147 | u64 (*get_qctl_whitelist_count)(void); | 1144 | u64 (*get_qctl_whitelist_count)(void); |
1148 | const struct regop_offset_range* ( | ||
1149 | *get_qctl_whitelist_ranges)(void); | ||
1150 | u64 (*get_qctl_whitelist_ranges_count)(void); | ||
1151 | int (*apply_smpc_war)(struct dbg_session_gk20a *dbg_s); | ||
1152 | } regops; | 1145 | } regops; |
1153 | struct { | 1146 | struct { |
1154 | void (*intr_mask)(struct gk20a *g); | 1147 | void (*intr_mask)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 2f90512e..ca7081cf 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -574,16 +574,8 @@ static const struct gpu_ops gm20b_ops = { | |||
574 | .get_runcontrol_whitelist = gm20b_get_runcontrol_whitelist, | 574 | .get_runcontrol_whitelist = gm20b_get_runcontrol_whitelist, |
575 | .get_runcontrol_whitelist_count = | 575 | .get_runcontrol_whitelist_count = |
576 | gm20b_get_runcontrol_whitelist_count, | 576 | gm20b_get_runcontrol_whitelist_count, |
577 | .get_runcontrol_whitelist_ranges = | ||
578 | gm20b_get_runcontrol_whitelist_ranges, | ||
579 | .get_runcontrol_whitelist_ranges_count = | ||
580 | gm20b_get_runcontrol_whitelist_ranges_count, | ||
581 | .get_qctl_whitelist = gm20b_get_qctl_whitelist, | 577 | .get_qctl_whitelist = gm20b_get_qctl_whitelist, |
582 | .get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count, | 578 | .get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count, |
583 | .get_qctl_whitelist_ranges = gm20b_get_qctl_whitelist_ranges, | ||
584 | .get_qctl_whitelist_ranges_count = | ||
585 | gm20b_get_qctl_whitelist_ranges_count, | ||
586 | .apply_smpc_war = gm20b_apply_smpc_war, | ||
587 | }, | 579 | }, |
588 | .mc = { | 580 | .mc = { |
589 | .intr_mask = mc_gk20a_intr_mask, | 581 | .intr_mask = mc_gk20a_intr_mask, |
diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c index e23a0a62..ab865b68 100644 --- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c | |||
@@ -23,12 +23,9 @@ | |||
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include "gk20a/gk20a.h" | 25 | #include "gk20a/gk20a.h" |
26 | #include "gk20a/dbg_gpu_gk20a.h" | ||
27 | #include "gk20a/regops_gk20a.h" | 26 | #include "gk20a/regops_gk20a.h" |
28 | #include "regops_gm20b.h" | 27 | #include "regops_gm20b.h" |
29 | 28 | ||
30 | #include <nvgpu/bsearch.h> | ||
31 | |||
32 | static const struct regop_offset_range gm20b_global_whitelist_ranges[] = { | 29 | static const struct regop_offset_range gm20b_global_whitelist_ranges[] = { |
33 | { 0x00001a00, 3 }, | 30 | { 0x00001a00, 3 }, |
34 | { 0x0000259c, 1 }, | 31 | { 0x0000259c, 1 }, |
@@ -366,29 +363,12 @@ static const u32 gm20b_runcontrol_whitelist[] = { | |||
366 | static const u64 gm20b_runcontrol_whitelist_count = | 363 | static const u64 gm20b_runcontrol_whitelist_count = |
367 | ARRAY_SIZE(gm20b_runcontrol_whitelist); | 364 | ARRAY_SIZE(gm20b_runcontrol_whitelist); |
368 | 365 | ||
369 | static const struct regop_offset_range gm20b_runcontrol_whitelist_ranges[] = { | ||
370 | { 0x00419e10, 1 }, | ||
371 | { 0x0041c610, 1 }, | ||
372 | { 0x0041ce10, 1 }, | ||
373 | { 0x00501e10, 1 }, | ||
374 | { 0x00504610, 1 }, | ||
375 | { 0x00504e10, 1 }, | ||
376 | }; | ||
377 | static const u64 gm20b_runcontrol_whitelist_ranges_count = | ||
378 | ARRAY_SIZE(gm20b_runcontrol_whitelist_ranges); | ||
379 | |||
380 | |||
381 | /* quad ctl */ | 366 | /* quad ctl */ |
382 | static const u32 gm20b_qctl_whitelist[] = { | 367 | static const u32 gm20b_qctl_whitelist[] = { |
383 | }; | 368 | }; |
384 | static const u64 gm20b_qctl_whitelist_count = | 369 | static const u64 gm20b_qctl_whitelist_count = |
385 | ARRAY_SIZE(gm20b_qctl_whitelist); | 370 | ARRAY_SIZE(gm20b_qctl_whitelist); |
386 | 371 | ||
387 | static const struct regop_offset_range gm20b_qctl_whitelist_ranges[] = { | ||
388 | }; | ||
389 | static const u64 gm20b_qctl_whitelist_ranges_count = | ||
390 | ARRAY_SIZE(gm20b_qctl_whitelist_ranges); | ||
391 | |||
392 | const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void) | 372 | const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void) |
393 | { | 373 | { |
394 | return gm20b_global_whitelist_ranges; | 374 | return gm20b_global_whitelist_ranges; |
@@ -419,16 +399,6 @@ u64 gm20b_get_runcontrol_whitelist_count(void) | |||
419 | return gm20b_runcontrol_whitelist_count; | 399 | return gm20b_runcontrol_whitelist_count; |
420 | } | 400 | } |
421 | 401 | ||
422 | const struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void) | ||
423 | { | ||
424 | return gm20b_runcontrol_whitelist_ranges; | ||
425 | } | ||
426 | |||
427 | u64 gm20b_get_runcontrol_whitelist_ranges_count(void) | ||
428 | { | ||
429 | return gm20b_runcontrol_whitelist_ranges_count; | ||
430 | } | ||
431 | |||
432 | const u32 *gm20b_get_qctl_whitelist(void) | 402 | const u32 *gm20b_get_qctl_whitelist(void) |
433 | { | 403 | { |
434 | return gm20b_qctl_whitelist; | 404 | return gm20b_qctl_whitelist; |
@@ -438,19 +408,3 @@ u64 gm20b_get_qctl_whitelist_count(void) | |||
438 | { | 408 | { |
439 | return gm20b_qctl_whitelist_count; | 409 | return gm20b_qctl_whitelist_count; |
440 | } | 410 | } |
441 | |||
442 | const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void) | ||
443 | { | ||
444 | return gm20b_qctl_whitelist_ranges; | ||
445 | } | ||
446 | |||
447 | u64 gm20b_get_qctl_whitelist_ranges_count(void) | ||
448 | { | ||
449 | return gm20b_qctl_whitelist_ranges_count; | ||
450 | } | ||
451 | |||
452 | int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s) | ||
453 | { | ||
454 | /* Not needed on gm20b */ | ||
455 | return 0; | ||
456 | } | ||
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 3408cdfa..da1a44a9 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -701,16 +701,8 @@ static const struct gpu_ops gp106_ops = { | |||
701 | .get_runcontrol_whitelist = gp106_get_runcontrol_whitelist, | 701 | .get_runcontrol_whitelist = gp106_get_runcontrol_whitelist, |
702 | .get_runcontrol_whitelist_count = | 702 | .get_runcontrol_whitelist_count = |
703 | gp106_get_runcontrol_whitelist_count, | 703 | gp106_get_runcontrol_whitelist_count, |
704 | .get_runcontrol_whitelist_ranges = | ||
705 | gp106_get_runcontrol_whitelist_ranges, | ||
706 | .get_runcontrol_whitelist_ranges_count = | ||
707 | gp106_get_runcontrol_whitelist_ranges_count, | ||
708 | .get_qctl_whitelist = gp106_get_qctl_whitelist, | 704 | .get_qctl_whitelist = gp106_get_qctl_whitelist, |
709 | .get_qctl_whitelist_count = gp106_get_qctl_whitelist_count, | 705 | .get_qctl_whitelist_count = gp106_get_qctl_whitelist_count, |
710 | .get_qctl_whitelist_ranges = gp106_get_qctl_whitelist_ranges, | ||
711 | .get_qctl_whitelist_ranges_count = | ||
712 | gp106_get_qctl_whitelist_ranges_count, | ||
713 | .apply_smpc_war = gp106_apply_smpc_war, | ||
714 | }, | 706 | }, |
715 | .mc = { | 707 | .mc = { |
716 | .intr_mask = mc_gp10b_intr_mask, | 708 | .intr_mask = mc_gp10b_intr_mask, |
diff --git a/drivers/gpu/nvgpu/gp106/regops_gp106.c b/drivers/gpu/nvgpu/gp106/regops_gp106.c index 25b88eeb..581b280d 100644 --- a/drivers/gpu/nvgpu/gp106/regops_gp106.c +++ b/drivers/gpu/nvgpu/gp106/regops_gp106.c | |||
@@ -23,12 +23,9 @@ | |||
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include "gk20a/gk20a.h" | 25 | #include "gk20a/gk20a.h" |
26 | #include "gk20a/dbg_gpu_gk20a.h" | ||
27 | #include "gk20a/regops_gk20a.h" | 26 | #include "gk20a/regops_gk20a.h" |
28 | #include "regops_gp106.h" | 27 | #include "regops_gp106.h" |
29 | 28 | ||
30 | #include <nvgpu/bsearch.h> | ||
31 | |||
32 | static const struct regop_offset_range gp106_global_whitelist_ranges[] = { | 29 | static const struct regop_offset_range gp106_global_whitelist_ranges[] = { |
33 | { 0x000004f0, 1}, | 30 | { 0x000004f0, 1}, |
34 | { 0x00001a00, 3}, | 31 | { 0x00001a00, 3}, |
@@ -1697,23 +1694,12 @@ static const u32 gp106_runcontrol_whitelist[] = { | |||
1697 | static const u64 gp106_runcontrol_whitelist_count = | 1694 | static const u64 gp106_runcontrol_whitelist_count = |
1698 | ARRAY_SIZE(gp106_runcontrol_whitelist); | 1695 | ARRAY_SIZE(gp106_runcontrol_whitelist); |
1699 | 1696 | ||
1700 | static const struct regop_offset_range gp106_runcontrol_whitelist_ranges[] = { | ||
1701 | }; | ||
1702 | static const u64 gp106_runcontrol_whitelist_ranges_count = | ||
1703 | ARRAY_SIZE(gp106_runcontrol_whitelist_ranges); | ||
1704 | |||
1705 | |||
1706 | /* quad ctl */ | 1697 | /* quad ctl */ |
1707 | static const u32 gp106_qctl_whitelist[] = { | 1698 | static const u32 gp106_qctl_whitelist[] = { |
1708 | }; | 1699 | }; |
1709 | static const u64 gp106_qctl_whitelist_count = | 1700 | static const u64 gp106_qctl_whitelist_count = |
1710 | ARRAY_SIZE(gp106_qctl_whitelist); | 1701 | ARRAY_SIZE(gp106_qctl_whitelist); |
1711 | 1702 | ||
1712 | static const struct regop_offset_range gp106_qctl_whitelist_ranges[] = { | ||
1713 | }; | ||
1714 | static const u64 gp106_qctl_whitelist_ranges_count = | ||
1715 | ARRAY_SIZE(gp106_qctl_whitelist_ranges); | ||
1716 | |||
1717 | const struct regop_offset_range *gp106_get_global_whitelist_ranges(void) | 1703 | const struct regop_offset_range *gp106_get_global_whitelist_ranges(void) |
1718 | { | 1704 | { |
1719 | return gp106_global_whitelist_ranges; | 1705 | return gp106_global_whitelist_ranges; |
@@ -1744,16 +1730,6 @@ u64 gp106_get_runcontrol_whitelist_count(void) | |||
1744 | return gp106_runcontrol_whitelist_count; | 1730 | return gp106_runcontrol_whitelist_count; |
1745 | } | 1731 | } |
1746 | 1732 | ||
1747 | const struct regop_offset_range *gp106_get_runcontrol_whitelist_ranges(void) | ||
1748 | { | ||
1749 | return gp106_runcontrol_whitelist_ranges; | ||
1750 | } | ||
1751 | |||
1752 | u64 gp106_get_runcontrol_whitelist_ranges_count(void) | ||
1753 | { | ||
1754 | return gp106_runcontrol_whitelist_ranges_count; | ||
1755 | } | ||
1756 | |||
1757 | const u32 *gp106_get_qctl_whitelist(void) | 1733 | const u32 *gp106_get_qctl_whitelist(void) |
1758 | { | 1734 | { |
1759 | return gp106_qctl_whitelist; | 1735 | return gp106_qctl_whitelist; |
@@ -1763,19 +1739,3 @@ u64 gp106_get_qctl_whitelist_count(void) | |||
1763 | { | 1739 | { |
1764 | return gp106_qctl_whitelist_count; | 1740 | return gp106_qctl_whitelist_count; |
1765 | } | 1741 | } |
1766 | |||
1767 | const struct regop_offset_range *gp106_get_qctl_whitelist_ranges(void) | ||
1768 | { | ||
1769 | return gp106_qctl_whitelist_ranges; | ||
1770 | } | ||
1771 | |||
1772 | u64 gp106_get_qctl_whitelist_ranges_count(void) | ||
1773 | { | ||
1774 | return gp106_qctl_whitelist_ranges_count; | ||
1775 | } | ||
1776 | |||
1777 | int gp106_apply_smpc_war(struct dbg_session_gk20a *dbg_s) | ||
1778 | { | ||
1779 | /* Not needed on gp106 */ | ||
1780 | return 0; | ||
1781 | } | ||
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 321a89fd..af64d2a9 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -626,16 +626,8 @@ static const struct gpu_ops gp10b_ops = { | |||
626 | .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist, | 626 | .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist, |
627 | .get_runcontrol_whitelist_count = | 627 | .get_runcontrol_whitelist_count = |
628 | gp10b_get_runcontrol_whitelist_count, | 628 | gp10b_get_runcontrol_whitelist_count, |
629 | .get_runcontrol_whitelist_ranges = | ||
630 | gp10b_get_runcontrol_whitelist_ranges, | ||
631 | .get_runcontrol_whitelist_ranges_count = | ||
632 | gp10b_get_runcontrol_whitelist_ranges_count, | ||
633 | .get_qctl_whitelist = gp10b_get_qctl_whitelist, | 629 | .get_qctl_whitelist = gp10b_get_qctl_whitelist, |
634 | .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count, | 630 | .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count, |
635 | .get_qctl_whitelist_ranges = gp10b_get_qctl_whitelist_ranges, | ||
636 | .get_qctl_whitelist_ranges_count = | ||
637 | gp10b_get_qctl_whitelist_ranges_count, | ||
638 | .apply_smpc_war = gp10b_apply_smpc_war, | ||
639 | }, | 631 | }, |
640 | .mc = { | 632 | .mc = { |
641 | .intr_mask = mc_gp10b_intr_mask, | 633 | .intr_mask = mc_gp10b_intr_mask, |
diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c index 8113f7d5..c61709e0 100644 --- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c | |||
@@ -23,12 +23,9 @@ | |||
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include "gk20a/gk20a.h" | 25 | #include "gk20a/gk20a.h" |
26 | #include "gk20a/dbg_gpu_gk20a.h" | ||
27 | #include "gk20a/regops_gk20a.h" | 26 | #include "gk20a/regops_gk20a.h" |
28 | #include "regops_gp10b.h" | 27 | #include "regops_gp10b.h" |
29 | 28 | ||
30 | #include <nvgpu/bsearch.h> | ||
31 | |||
32 | static const struct regop_offset_range gp10b_global_whitelist_ranges[] = { | 29 | static const struct regop_offset_range gp10b_global_whitelist_ranges[] = { |
33 | { 0x000004f0, 1}, | 30 | { 0x000004f0, 1}, |
34 | { 0x00001a00, 3}, | 31 | { 0x00001a00, 3}, |
@@ -393,23 +390,12 @@ static const u32 gp10b_runcontrol_whitelist[] = { | |||
393 | static const u64 gp10b_runcontrol_whitelist_count = | 390 | static const u64 gp10b_runcontrol_whitelist_count = |
394 | ARRAY_SIZE(gp10b_runcontrol_whitelist); | 391 | ARRAY_SIZE(gp10b_runcontrol_whitelist); |
395 | 392 | ||
396 | static const struct regop_offset_range gp10b_runcontrol_whitelist_ranges[] = { | ||
397 | }; | ||
398 | static const u64 gp10b_runcontrol_whitelist_ranges_count = | ||
399 | ARRAY_SIZE(gp10b_runcontrol_whitelist_ranges); | ||
400 | |||
401 | |||
402 | /* quad ctl */ | 393 | /* quad ctl */ |
403 | static const u32 gp10b_qctl_whitelist[] = { | 394 | static const u32 gp10b_qctl_whitelist[] = { |
404 | }; | 395 | }; |
405 | static const u64 gp10b_qctl_whitelist_count = | 396 | static const u64 gp10b_qctl_whitelist_count = |
406 | ARRAY_SIZE(gp10b_qctl_whitelist); | 397 | ARRAY_SIZE(gp10b_qctl_whitelist); |
407 | 398 | ||
408 | static const struct regop_offset_range gp10b_qctl_whitelist_ranges[] = { | ||
409 | }; | ||
410 | static const u64 gp10b_qctl_whitelist_ranges_count = | ||
411 | ARRAY_SIZE(gp10b_qctl_whitelist_ranges); | ||
412 | |||
413 | const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void) | 399 | const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void) |
414 | { | 400 | { |
415 | return gp10b_global_whitelist_ranges; | 401 | return gp10b_global_whitelist_ranges; |
@@ -440,16 +426,6 @@ u64 gp10b_get_runcontrol_whitelist_count(void) | |||
440 | return gp10b_runcontrol_whitelist_count; | 426 | return gp10b_runcontrol_whitelist_count; |
441 | } | 427 | } |
442 | 428 | ||
443 | const struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void) | ||
444 | { | ||
445 | return gp10b_runcontrol_whitelist_ranges; | ||
446 | } | ||
447 | |||
448 | u64 gp10b_get_runcontrol_whitelist_ranges_count(void) | ||
449 | { | ||
450 | return gp10b_runcontrol_whitelist_ranges_count; | ||
451 | } | ||
452 | |||
453 | const u32 *gp10b_get_qctl_whitelist(void) | 429 | const u32 *gp10b_get_qctl_whitelist(void) |
454 | { | 430 | { |
455 | return gp10b_qctl_whitelist; | 431 | return gp10b_qctl_whitelist; |
@@ -459,19 +435,3 @@ u64 gp10b_get_qctl_whitelist_count(void) | |||
459 | { | 435 | { |
460 | return gp10b_qctl_whitelist_count; | 436 | return gp10b_qctl_whitelist_count; |
461 | } | 437 | } |
462 | |||
463 | const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void) | ||
464 | { | ||
465 | return gp10b_qctl_whitelist_ranges; | ||
466 | } | ||
467 | |||
468 | u64 gp10b_get_qctl_whitelist_ranges_count(void) | ||
469 | { | ||
470 | return gp10b_qctl_whitelist_ranges_count; | ||
471 | } | ||
472 | |||
473 | int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s) | ||
474 | { | ||
475 | /* Not needed on gp10b */ | ||
476 | return 0; | ||
477 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 1bc5d091..9d90d1d4 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -790,16 +790,8 @@ static const struct gpu_ops gv100_ops = { | |||
790 | .get_runcontrol_whitelist = gv100_get_runcontrol_whitelist, | 790 | .get_runcontrol_whitelist = gv100_get_runcontrol_whitelist, |
791 | .get_runcontrol_whitelist_count = | 791 | .get_runcontrol_whitelist_count = |
792 | gv100_get_runcontrol_whitelist_count, | 792 | gv100_get_runcontrol_whitelist_count, |
793 | .get_runcontrol_whitelist_ranges = | ||
794 | gv100_get_runcontrol_whitelist_ranges, | ||
795 | .get_runcontrol_whitelist_ranges_count = | ||
796 | gv100_get_runcontrol_whitelist_ranges_count, | ||
797 | .get_qctl_whitelist = gv100_get_qctl_whitelist, | 793 | .get_qctl_whitelist = gv100_get_qctl_whitelist, |
798 | .get_qctl_whitelist_count = gv100_get_qctl_whitelist_count, | 794 | .get_qctl_whitelist_count = gv100_get_qctl_whitelist_count, |
799 | .get_qctl_whitelist_ranges = gv100_get_qctl_whitelist_ranges, | ||
800 | .get_qctl_whitelist_ranges_count = | ||
801 | gv100_get_qctl_whitelist_ranges_count, | ||
802 | .apply_smpc_war = gv100_apply_smpc_war, | ||
803 | }, | 795 | }, |
804 | .mc = { | 796 | .mc = { |
805 | .intr_mask = mc_gp10b_intr_mask, | 797 | .intr_mask = mc_gp10b_intr_mask, |
diff --git a/drivers/gpu/nvgpu/gv100/regops_gv100.c b/drivers/gpu/nvgpu/gv100/regops_gv100.c index c6ce6b94..baf57c78 100644 --- a/drivers/gpu/nvgpu/gv100/regops_gv100.c +++ b/drivers/gpu/nvgpu/gv100/regops_gv100.c | |||
@@ -23,7 +23,6 @@ | |||
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include "gk20a/gk20a.h" | 25 | #include "gk20a/gk20a.h" |
26 | #include "gk20a/dbg_gpu_gk20a.h" | ||
27 | #include "gk20a/regops_gk20a.h" | 26 | #include "gk20a/regops_gk20a.h" |
28 | #include "regops_gv100.h" | 27 | #include "regops_gv100.h" |
29 | 28 | ||
@@ -5626,19 +5625,12 @@ static const struct regop_offset_range gv100_global_whitelist_ranges[] = { | |||
5626 | static const u64 gv100_global_whitelist_ranges_count = | 5625 | static const u64 gv100_global_whitelist_ranges_count = |
5627 | ARRAY_SIZE(gv100_global_whitelist_ranges); | 5626 | ARRAY_SIZE(gv100_global_whitelist_ranges); |
5628 | 5627 | ||
5629 | /* context */ | ||
5630 | |||
5631 | /* runcontrol */ | 5628 | /* runcontrol */ |
5632 | static const u32 gv100_runcontrol_whitelist[] = { | 5629 | static const u32 gv100_runcontrol_whitelist[] = { |
5633 | }; | 5630 | }; |
5634 | static const u64 gv100_runcontrol_whitelist_count = | 5631 | static const u64 gv100_runcontrol_whitelist_count = |
5635 | ARRAY_SIZE(gv100_runcontrol_whitelist); | 5632 | ARRAY_SIZE(gv100_runcontrol_whitelist); |
5636 | 5633 | ||
5637 | static const struct regop_offset_range gv100_runcontrol_whitelist_ranges[] = { | ||
5638 | }; | ||
5639 | static const u64 gv100_runcontrol_whitelist_ranges_count = | ||
5640 | ARRAY_SIZE(gv100_runcontrol_whitelist_ranges); | ||
5641 | |||
5642 | 5634 | ||
5643 | /* quad ctl */ | 5635 | /* quad ctl */ |
5644 | static const u32 gv100_qctl_whitelist[] = { | 5636 | static const u32 gv100_qctl_whitelist[] = { |
@@ -5646,11 +5638,6 @@ static const u32 gv100_qctl_whitelist[] = { | |||
5646 | static const u64 gv100_qctl_whitelist_count = | 5638 | static const u64 gv100_qctl_whitelist_count = |
5647 | ARRAY_SIZE(gv100_qctl_whitelist); | 5639 | ARRAY_SIZE(gv100_qctl_whitelist); |
5648 | 5640 | ||
5649 | static const struct regop_offset_range gv100_qctl_whitelist_ranges[] = { | ||
5650 | }; | ||
5651 | static const u64 gv100_qctl_whitelist_ranges_count = | ||
5652 | ARRAY_SIZE(gv100_qctl_whitelist_ranges); | ||
5653 | |||
5654 | const struct regop_offset_range *gv100_get_global_whitelist_ranges(void) | 5641 | const struct regop_offset_range *gv100_get_global_whitelist_ranges(void) |
5655 | { | 5642 | { |
5656 | return gv100_global_whitelist_ranges; | 5643 | return gv100_global_whitelist_ranges; |
@@ -5681,16 +5668,6 @@ u64 gv100_get_runcontrol_whitelist_count(void) | |||
5681 | return gv100_runcontrol_whitelist_count; | 5668 | return gv100_runcontrol_whitelist_count; |
5682 | } | 5669 | } |
5683 | 5670 | ||
5684 | const struct regop_offset_range *gv100_get_runcontrol_whitelist_ranges(void) | ||
5685 | { | ||
5686 | return gv100_runcontrol_whitelist_ranges; | ||
5687 | } | ||
5688 | |||
5689 | u64 gv100_get_runcontrol_whitelist_ranges_count(void) | ||
5690 | { | ||
5691 | return gv100_runcontrol_whitelist_ranges_count; | ||
5692 | } | ||
5693 | |||
5694 | const u32 *gv100_get_qctl_whitelist(void) | 5671 | const u32 *gv100_get_qctl_whitelist(void) |
5695 | { | 5672 | { |
5696 | return gv100_qctl_whitelist; | 5673 | return gv100_qctl_whitelist; |
@@ -5700,19 +5677,3 @@ u64 gv100_get_qctl_whitelist_count(void) | |||
5700 | { | 5677 | { |
5701 | return gv100_qctl_whitelist_count; | 5678 | return gv100_qctl_whitelist_count; |
5702 | } | 5679 | } |
5703 | |||
5704 | const struct regop_offset_range *gv100_get_qctl_whitelist_ranges(void) | ||
5705 | { | ||
5706 | return gv100_qctl_whitelist_ranges; | ||
5707 | } | ||
5708 | |||
5709 | u64 gv100_get_qctl_whitelist_ranges_count(void) | ||
5710 | { | ||
5711 | return gv100_qctl_whitelist_ranges_count; | ||
5712 | } | ||
5713 | |||
5714 | int gv100_apply_smpc_war(struct dbg_session_gk20a *dbg_s) | ||
5715 | { | ||
5716 | /* Not needed on gv100 */ | ||
5717 | return 0; | ||
5718 | } | ||
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index e5d7e632..a27d9ab5 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -722,16 +722,8 @@ static const struct gpu_ops gv11b_ops = { | |||
722 | .get_runcontrol_whitelist = gv11b_get_runcontrol_whitelist, | 722 | .get_runcontrol_whitelist = gv11b_get_runcontrol_whitelist, |
723 | .get_runcontrol_whitelist_count = | 723 | .get_runcontrol_whitelist_count = |
724 | gv11b_get_runcontrol_whitelist_count, | 724 | gv11b_get_runcontrol_whitelist_count, |
725 | .get_runcontrol_whitelist_ranges = | ||
726 | gv11b_get_runcontrol_whitelist_ranges, | ||
727 | .get_runcontrol_whitelist_ranges_count = | ||
728 | gv11b_get_runcontrol_whitelist_ranges_count, | ||
729 | .get_qctl_whitelist = gv11b_get_qctl_whitelist, | 725 | .get_qctl_whitelist = gv11b_get_qctl_whitelist, |
730 | .get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count, | 726 | .get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count, |
731 | .get_qctl_whitelist_ranges = gv11b_get_qctl_whitelist_ranges, | ||
732 | .get_qctl_whitelist_ranges_count = | ||
733 | gv11b_get_qctl_whitelist_ranges_count, | ||
734 | .apply_smpc_war = gv11b_apply_smpc_war, | ||
735 | }, | 727 | }, |
736 | .mc = { | 728 | .mc = { |
737 | .intr_mask = mc_gp10b_intr_mask, | 729 | .intr_mask = mc_gp10b_intr_mask, |
diff --git a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c index 768674fe..0bc8ab05 100644 --- a/drivers/gpu/nvgpu/gv11b/regops_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/regops_gv11b.c | |||
@@ -23,7 +23,6 @@ | |||
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include "gk20a/gk20a.h" | 25 | #include "gk20a/gk20a.h" |
26 | #include "gk20a/dbg_gpu_gk20a.h" | ||
27 | #include "gk20a/regops_gk20a.h" | 26 | #include "gk20a/regops_gk20a.h" |
28 | #include "regops_gv11b.h" | 27 | #include "regops_gv11b.h" |
29 | 28 | ||
@@ -1452,23 +1451,12 @@ static const u32 gv11b_runcontrol_whitelist[] = { | |||
1452 | static const u64 gv11b_runcontrol_whitelist_count = | 1451 | static const u64 gv11b_runcontrol_whitelist_count = |
1453 | ARRAY_SIZE(gv11b_runcontrol_whitelist); | 1452 | ARRAY_SIZE(gv11b_runcontrol_whitelist); |
1454 | 1453 | ||
1455 | static const struct regop_offset_range gv11b_runcontrol_whitelist_ranges[] = { | ||
1456 | }; | ||
1457 | static const u64 gv11b_runcontrol_whitelist_ranges_count = | ||
1458 | ARRAY_SIZE(gv11b_runcontrol_whitelist_ranges); | ||
1459 | |||
1460 | |||
1461 | /* quad ctl */ | 1454 | /* quad ctl */ |
1462 | static const u32 gv11b_qctl_whitelist[] = { | 1455 | static const u32 gv11b_qctl_whitelist[] = { |
1463 | }; | 1456 | }; |
1464 | static const u64 gv11b_qctl_whitelist_count = | 1457 | static const u64 gv11b_qctl_whitelist_count = |
1465 | ARRAY_SIZE(gv11b_qctl_whitelist); | 1458 | ARRAY_SIZE(gv11b_qctl_whitelist); |
1466 | 1459 | ||
1467 | static const struct regop_offset_range gv11b_qctl_whitelist_ranges[] = { | ||
1468 | }; | ||
1469 | static const u64 gv11b_qctl_whitelist_ranges_count = | ||
1470 | ARRAY_SIZE(gv11b_qctl_whitelist_ranges); | ||
1471 | |||
1472 | const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void) | 1460 | const struct regop_offset_range *gv11b_get_global_whitelist_ranges(void) |
1473 | { | 1461 | { |
1474 | return gv11b_global_whitelist_ranges; | 1462 | return gv11b_global_whitelist_ranges; |
@@ -1499,16 +1487,6 @@ u64 gv11b_get_runcontrol_whitelist_count(void) | |||
1499 | return gv11b_runcontrol_whitelist_count; | 1487 | return gv11b_runcontrol_whitelist_count; |
1500 | } | 1488 | } |
1501 | 1489 | ||
1502 | const struct regop_offset_range *gv11b_get_runcontrol_whitelist_ranges(void) | ||
1503 | { | ||
1504 | return gv11b_runcontrol_whitelist_ranges; | ||
1505 | } | ||
1506 | |||
1507 | u64 gv11b_get_runcontrol_whitelist_ranges_count(void) | ||
1508 | { | ||
1509 | return gv11b_runcontrol_whitelist_ranges_count; | ||
1510 | } | ||
1511 | |||
1512 | const u32 *gv11b_get_qctl_whitelist(void) | 1490 | const u32 *gv11b_get_qctl_whitelist(void) |
1513 | { | 1491 | { |
1514 | return gv11b_qctl_whitelist; | 1492 | return gv11b_qctl_whitelist; |
@@ -1518,19 +1496,3 @@ u64 gv11b_get_qctl_whitelist_count(void) | |||
1518 | { | 1496 | { |
1519 | return gv11b_qctl_whitelist_count; | 1497 | return gv11b_qctl_whitelist_count; |
1520 | } | 1498 | } |
1521 | |||
1522 | const struct regop_offset_range *gv11b_get_qctl_whitelist_ranges(void) | ||
1523 | { | ||
1524 | return gv11b_qctl_whitelist_ranges; | ||
1525 | } | ||
1526 | |||
1527 | u64 gv11b_get_qctl_whitelist_ranges_count(void) | ||
1528 | { | ||
1529 | return gv11b_qctl_whitelist_ranges_count; | ||
1530 | } | ||
1531 | |||
1532 | int gv11b_apply_smpc_war(struct dbg_session_gk20a *dbg_s) | ||
1533 | { | ||
1534 | /* Not needed on gv11b */ | ||
1535 | return 0; | ||
1536 | } | ||
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index e4e7394e..9ea681b1 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | |||
@@ -1053,10 +1053,8 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, | |||
1053 | if (err) { | 1053 | if (err) { |
1054 | nvgpu_err(g, | 1054 | nvgpu_err(g, |
1055 | "error (%d) during smpc ctxsw mode update", err); | 1055 | "error (%d) during smpc ctxsw mode update", err); |
1056 | goto clean_up; | ||
1057 | } | 1056 | } |
1058 | 1057 | ||
1059 | err = g->ops.regops.apply_smpc_war(dbg_s); | ||
1060 | clean_up: | 1058 | clean_up: |
1061 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 1059 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
1062 | gk20a_idle(g); | 1060 | gk20a_idle(g); |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 0b6a5cb5..58f595f4 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -466,16 +466,8 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
466 | .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist, | 466 | .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist, |
467 | .get_runcontrol_whitelist_count = | 467 | .get_runcontrol_whitelist_count = |
468 | gp10b_get_runcontrol_whitelist_count, | 468 | gp10b_get_runcontrol_whitelist_count, |
469 | .get_runcontrol_whitelist_ranges = | ||
470 | gp10b_get_runcontrol_whitelist_ranges, | ||
471 | .get_runcontrol_whitelist_ranges_count = | ||
472 | gp10b_get_runcontrol_whitelist_ranges_count, | ||
473 | .get_qctl_whitelist = gp10b_get_qctl_whitelist, | 469 | .get_qctl_whitelist = gp10b_get_qctl_whitelist, |
474 | .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count, | 470 | .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count, |
475 | .get_qctl_whitelist_ranges = gp10b_get_qctl_whitelist_ranges, | ||
476 | .get_qctl_whitelist_ranges_count = | ||
477 | gp10b_get_qctl_whitelist_ranges_count, | ||
478 | .apply_smpc_war = gp10b_apply_smpc_war, | ||
479 | }, | 471 | }, |
480 | .mc = { | 472 | .mc = { |
481 | .intr_mask = NULL, | 473 | .intr_mask = NULL, |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 85835cee..9832a714 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -535,16 +535,8 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
535 | .get_runcontrol_whitelist = gv11b_get_runcontrol_whitelist, | 535 | .get_runcontrol_whitelist = gv11b_get_runcontrol_whitelist, |
536 | .get_runcontrol_whitelist_count = | 536 | .get_runcontrol_whitelist_count = |
537 | gv11b_get_runcontrol_whitelist_count, | 537 | gv11b_get_runcontrol_whitelist_count, |
538 | .get_runcontrol_whitelist_ranges = | ||
539 | gv11b_get_runcontrol_whitelist_ranges, | ||
540 | .get_runcontrol_whitelist_ranges_count = | ||
541 | gv11b_get_runcontrol_whitelist_ranges_count, | ||
542 | .get_qctl_whitelist = gv11b_get_qctl_whitelist, | 538 | .get_qctl_whitelist = gv11b_get_qctl_whitelist, |
543 | .get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count, | 539 | .get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count, |
544 | .get_qctl_whitelist_ranges = gv11b_get_qctl_whitelist_ranges, | ||
545 | .get_qctl_whitelist_ranges_count = | ||
546 | gv11b_get_qctl_whitelist_ranges_count, | ||
547 | .apply_smpc_war = gv11b_apply_smpc_war, | ||
548 | }, | 540 | }, |
549 | .mc = { | 541 | .mc = { |
550 | .intr_mask = NULL, | 542 | .intr_mask = NULL, |