diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/Makefile | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ce2_gp10b.c | 83 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ce2_gp10b.h | 29 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h | 81 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 8 |
6 files changed, 206 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index e14cd0ee..421e50f6 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile | |||
@@ -12,6 +12,7 @@ ccflags-y += -Werror | |||
12 | obj-$(CONFIG_GK20A) += \ | 12 | obj-$(CONFIG_GK20A) += \ |
13 | gr_gp10b.o \ | 13 | gr_gp10b.o \ |
14 | gr_ctx_gp10b.o \ | 14 | gr_ctx_gp10b.o \ |
15 | ce2_gp10b.o \ | ||
15 | mc_gp10b.o \ | 16 | mc_gp10b.o \ |
16 | ltc_gp10b.o \ | 17 | ltc_gp10b.o \ |
17 | mm_gp10b.o \ | 18 | mm_gp10b.o \ |
diff --git a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c new file mode 100644 index 00000000..d76b97a5 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c | |||
@@ -0,0 +1,83 @@ | |||
1 | /* | ||
2 | * GK20A Graphics Copy Engine (gr host) | ||
3 | * | ||
4 | * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License along with | ||
16 | * this program; if not, write to the Free Software Foundation, Inc., | ||
17 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
18 | */ | ||
19 | |||
20 | #include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ | ||
21 | #include "hw_ce2_gp10b.h" | ||
22 | #include "ce2_gp10b.h" | ||
23 | |||
24 | static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr) | ||
25 | { | ||
26 | gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n"); | ||
27 | |||
28 | /* wake theads waiting in this channel */ | ||
29 | gk20a_channel_semaphore_wakeup(g); | ||
30 | return ce2_intr_status_nonblockpipe_pending_f(); | ||
31 | } | ||
32 | |||
33 | static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr) | ||
34 | { | ||
35 | gk20a_dbg(gpu_dbg_intr, "ce2 blocking pipe interrupt\n"); | ||
36 | |||
37 | return ce2_intr_status_blockpipe_pending_f(); | ||
38 | } | ||
39 | |||
40 | static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr) | ||
41 | { | ||
42 | gk20a_dbg(gpu_dbg_intr, "ce2 launch error interrupt\n"); | ||
43 | |||
44 | return ce2_intr_status_launcherr_pending_f(); | ||
45 | } | ||
46 | |||
47 | void gp10b_ce2_isr(struct gk20a *g) | ||
48 | { | ||
49 | u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0)); | ||
50 | u32 clear_intr = 0; | ||
51 | |||
52 | gk20a_dbg(gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr); | ||
53 | |||
54 | /* clear blocking interrupts: they exibit broken behavior */ | ||
55 | if (ce2_intr & ce2_intr_status_blockpipe_pending_f()) | ||
56 | clear_intr |= ce2_blockpipe_isr(g, ce2_intr); | ||
57 | |||
58 | if (ce2_intr & ce2_intr_status_launcherr_pending_f()) | ||
59 | clear_intr |= ce2_launcherr_isr(g, ce2_intr); | ||
60 | |||
61 | gk20a_writel(g, ce2_intr_status_r(0), clear_intr); | ||
62 | return; | ||
63 | } | ||
64 | |||
65 | void gp10b_ce2_nonstall_isr(struct gk20a *g) | ||
66 | { | ||
67 | u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0)); | ||
68 | u32 clear_intr = 0; | ||
69 | |||
70 | gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); | ||
71 | |||
72 | if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) | ||
73 | clear_intr |= ce2_nonblockpipe_isr(g, ce2_intr); | ||
74 | |||
75 | gk20a_writel(g, ce2_intr_status_r(0), clear_intr); | ||
76 | |||
77 | return; | ||
78 | } | ||
79 | void gp10b_init_ce2(struct gpu_ops *gops) | ||
80 | { | ||
81 | gops->ce2.isr_stall = gp10b_ce2_isr; | ||
82 | gops->ce2.isr_nonstall = gp10b_ce2_nonstall_isr; | ||
83 | } | ||
diff --git a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.h b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.h new file mode 100644 index 00000000..d432d1e0 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* | ||
2 | * drivers/video/tegra/host/gk20a/fifo_gk20a.h | ||
3 | * | ||
4 | * GK20A graphics copy engine (gr host) | ||
5 | * | ||
6 | * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms and conditions of the GNU General Public License, | ||
10 | * version 2, as published by the Free Software Foundation. | ||
11 | * | ||
12 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
15 | * more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License along with | ||
18 | * this program; if not, write to the Free Software Foundation, Inc., | ||
19 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
20 | */ | ||
21 | #ifndef __CE2_GP10B_H__ | ||
22 | #define __CE2_GP10B_H__ | ||
23 | |||
24 | #include "gk20a/channel_gk20a.h" | ||
25 | #include "gk20a/tsg_gk20a.h" | ||
26 | |||
27 | void gp10b_init_ce2(struct gpu_ops *gops); | ||
28 | |||
29 | #endif /*__CE2_GP10B_H__*/ | ||
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 30b56a5c..c23c0f17 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B Tegra HAL interface | 2 | * GP10B Tegra HAL interface |
3 | * | 3 | * |
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -24,6 +24,7 @@ | |||
24 | #include "gp10b/mc_gp10b.h" | 24 | #include "gp10b/mc_gp10b.h" |
25 | #include "gp10b/ltc_gp10b.h" | 25 | #include "gp10b/ltc_gp10b.h" |
26 | #include "gp10b/mm_gp10b.h" | 26 | #include "gp10b/mm_gp10b.h" |
27 | #include "gp10b/ce2_gp10b.h" | ||
27 | #include "gp10b/fb_gp10b.h" | 28 | #include "gp10b/fb_gp10b.h" |
28 | #include "gp10b/pmu_gp10b.h" | 29 | #include "gp10b/pmu_gp10b.h" |
29 | #include "gp10b/gr_ctx_gp10b.h" | 30 | #include "gp10b/gr_ctx_gp10b.h" |
@@ -94,7 +95,8 @@ int gp10b_init_hal(struct gk20a *g) | |||
94 | gp10b_init_gr(gops); | 95 | gp10b_init_gr(gops); |
95 | gp10b_init_ltc(gops); | 96 | gp10b_init_ltc(gops); |
96 | gp10b_init_fb(gops); | 97 | gp10b_init_fb(gops); |
97 | gp10b_init_fifo(gops); | 98 | gm20b_init_fifo(gops); |
99 | gp10b_init_ce2(gops); | ||
98 | gp10b_init_gr_ctx(gops); | 100 | gp10b_init_gr_ctx(gops); |
99 | gp10b_init_mm(gops); | 101 | gp10b_init_mm(gops); |
100 | gp10b_init_pmu_ops(gops); | 102 | gp10b_init_pmu_ops(gops); |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h new file mode 100644 index 00000000..b0c35a30 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h | |||
@@ -0,0 +1,81 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_ce2_gp10b_h_ | ||
51 | #define _hw_ce2_gp10b_h_ | ||
52 | |||
53 | static inline u32 ce2_intr_status_r(u32 i) | ||
54 | { | ||
55 | return 0x00104410 + i*128; | ||
56 | } | ||
57 | static inline u32 ce2_intr_status_blockpipe_pending_f(void) | ||
58 | { | ||
59 | return 0x1; | ||
60 | } | ||
61 | static inline u32 ce2_intr_status_blockpipe_reset_f(void) | ||
62 | { | ||
63 | return 0x1; | ||
64 | } | ||
65 | static inline u32 ce2_intr_status_nonblockpipe_pending_f(void) | ||
66 | { | ||
67 | return 0x2; | ||
68 | } | ||
69 | static inline u32 ce2_intr_status_nonblockpipe_reset_f(void) | ||
70 | { | ||
71 | return 0x2; | ||
72 | } | ||
73 | static inline u32 ce2_intr_status_launcherr_pending_f(void) | ||
74 | { | ||
75 | return 0x4; | ||
76 | } | ||
77 | static inline u32 ce2_intr_status_launcherr_reset_f(void) | ||
78 | { | ||
79 | return 0x4; | ||
80 | } | ||
81 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 1760b6ad..47c8fcc6 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c | |||
@@ -110,6 +110,9 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | |||
110 | 110 | ||
111 | if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) | 111 | if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) |
112 | gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); | 112 | gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); |
113 | if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) | ||
114 | && g->ops.ce2.isr_stall) | ||
115 | g->ops.ce2.isr_stall(g); | ||
113 | if (mc_intr_0 & mc_intr_pfifo_pending_f()) | 116 | if (mc_intr_0 & mc_intr_pfifo_pending_f()) |
114 | gk20a_fifo_isr(g); | 117 | gk20a_fifo_isr(g); |
115 | if (mc_intr_0 & mc_intr_pmu_pending_f()) | 118 | if (mc_intr_0 & mc_intr_pmu_pending_f()) |
@@ -141,6 +144,11 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) | |||
141 | gk20a_fifo_nonstall_isr(g); | 144 | gk20a_fifo_nonstall_isr(g); |
142 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) | 145 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) |
143 | gk20a_gr_nonstall_isr(g); | 146 | gk20a_gr_nonstall_isr(g); |
147 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) | ||
148 | && g->ops.ce2.isr_nonstall) | ||
149 | g->ops.ce2.isr_nonstall(g); | ||
150 | |||
151 | |||
144 | 152 | ||
145 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), | 153 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), |
146 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); | 154 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); |