diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 57 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h | 6 |
3 files changed, 82 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 61b23711..98aad4e0 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c | |||
@@ -24,6 +24,61 @@ | |||
24 | 24 | ||
25 | #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h> | 25 | #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h> |
26 | #include <nvgpu/hw/gv11b/hw_fb_gv11b.h> | 26 | #include <nvgpu/hw/gv11b/hw_fb_gv11b.h> |
27 | #include <nvgpu/hw/gv11b/hw_mc_gv11b.h> | ||
28 | #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h> | ||
29 | |||
30 | static void gv11b_init_nvlink_soc_credits(struct gk20a *g) | ||
31 | { | ||
32 | void __iomem *soc1 = ioremap(0x02b10010, 4096); | ||
33 | void __iomem *soc2 = ioremap(0x02b20010, 4096); | ||
34 | void __iomem *soc3 = ioremap(0x02b30010, 4096); | ||
35 | void __iomem *soc4 = ioremap(0x02b40010, 4096); | ||
36 | |||
37 | gk20a_dbg_info("init nvlink soc credits"); | ||
38 | |||
39 | writel_relaxed(0x14050000, soc1); | ||
40 | writel_relaxed(0x08020000, soc1 + 4); | ||
41 | writel_relaxed(0x14050000, soc2); | ||
42 | writel_relaxed(0x08020000, soc2 + 4); | ||
43 | writel_relaxed(0x14050000, soc3); | ||
44 | writel_relaxed(0x08020000, soc3 + 4); | ||
45 | writel_relaxed(0x14050000, soc4); | ||
46 | writel_relaxed(0x08020000, soc4 + 4); | ||
47 | |||
48 | } | ||
49 | |||
50 | static void gv11b_fb_reset(struct gk20a *g) | ||
51 | { | ||
52 | u32 val; | ||
53 | |||
54 | gk20a_dbg_info("reset gv11b fb"); | ||
55 | |||
56 | g->ops.mc.reset(g, mc_enable_pfb_enabled_f() | | ||
57 | mc_enable_l2_enabled_f() | | ||
58 | mc_enable_xbar_enabled_f() | | ||
59 | mc_enable_hub_enabled_f()); | ||
60 | |||
61 | val = gk20a_readl(g, mc_elpg_enable_r()); | ||
62 | val |= mc_elpg_enable_xbar_enabled_f() | | ||
63 | mc_elpg_enable_pfb_enabled_f() | | ||
64 | mc_elpg_enable_l2_enabled_f() | | ||
65 | mc_elpg_enable_hub_enabled_f(); | ||
66 | gk20a_writel(g, mc_elpg_enable_r(), val); | ||
67 | |||
68 | /* fs hub should be out of reset by now */ | ||
69 | gv11b_init_nvlink_soc_credits(g); | ||
70 | |||
71 | val = gk20a_readl(g, fifo_fb_iface_r()); | ||
72 | gk20a_dbg_info("fifo_fb_iface val = 0x%x", val); | ||
73 | if (!(val & fifo_fb_iface_control_enable_f() && | ||
74 | val & fifo_fb_iface_status_enabled_f())) { | ||
75 | gk20a_dbg_info("fifo_fb_iface set control enable"); | ||
76 | gk20a_writel(g, fifo_fb_iface_r(), | ||
77 | fifo_fb_iface_control_enable_f()); | ||
78 | val = gk20a_readl(g, fifo_fb_iface_r()); | ||
79 | gk20a_dbg_info("fifo_fb_iface val = 0x%x", val); | ||
80 | } | ||
81 | } | ||
27 | 82 | ||
28 | static void gv11b_init_uncompressed_kind_map(void) | 83 | static void gv11b_init_uncompressed_kind_map(void) |
29 | { | 84 | { |
@@ -94,6 +149,8 @@ void gv11b_init_fb(struct gpu_ops *gops) | |||
94 | { | 149 | { |
95 | gp10b_init_fb(gops); | 150 | gp10b_init_fb(gops); |
96 | gops->fb.hub_isr = gv11b_fb_hub_isr; | 151 | gops->fb.hub_isr = gv11b_fb_hub_isr; |
152 | gops->fb.reset = gv11b_fb_reset; | ||
153 | |||
97 | gv11b_init_uncompressed_kind_map(); | 154 | gv11b_init_uncompressed_kind_map(); |
98 | gv11b_init_kind_attr(); | 155 | gv11b_init_kind_attr(); |
99 | 156 | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h index dbcb02c8..bd2f628c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fifo_gv11b.h | |||
@@ -630,4 +630,24 @@ static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r) | |||
630 | { | 630 | { |
631 | return (r >> 16) & 0xff; | 631 | return (r >> 16) & 0xff; |
632 | } | 632 | } |
633 | static inline u32 fifo_fb_iface_r(void) | ||
634 | { | ||
635 | return 0x000026f0; | ||
636 | } | ||
637 | static inline u32 fifo_fb_iface_control_v(u32 r) | ||
638 | { | ||
639 | return (r >> 0) & 0x1; | ||
640 | } | ||
641 | static inline u32 fifo_fb_iface_control_enable_f(void) | ||
642 | { | ||
643 | return 0x1; | ||
644 | } | ||
645 | static inline u32 fifo_fb_iface_status_v(u32 r) | ||
646 | { | ||
647 | return (r >> 4) & 0x1; | ||
648 | } | ||
649 | static inline u32 fifo_fb_iface_status_enabled_f(void) | ||
650 | { | ||
651 | return 0x10; | ||
652 | } | ||
633 | #endif | 653 | #endif |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h index 98bec43a..f05910a9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_mc_gv11b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -242,4 +242,8 @@ static inline u32 mc_elpg_enable_hub_enabled_f(void) | |||
242 | { | 242 | { |
243 | return 0x20000000; | 243 | return 0x20000000; |
244 | } | 244 | } |
245 | static inline u32 mc_elpg_enable_l2_enabled_f(void) | ||
246 | { | ||
247 | return 0x8; | ||
248 | } | ||
245 | #endif | 249 | #endif |